Method for calibrating inconsistency of multi-channel voltage sampling applied in battery management chip

Abstract

This invention discloses a method for calibrating multi-channel voltage sampling inconsistency in battery management chips. Using a digital domain approach, it separates the operational amplifier offset voltage and resistor mismatch in an operational amplifier-based voltage sampling structure, calibrating them separately. First, two different battery voltages are given to sample each channel. The offset is obtained by calculating the difference between the actual voltage conversion coefficient and the ideally designed voltage conversion coefficient. The quantization voltage of the ADC is then adjusted to obtain V′. ref Instead of directly adjusting the resistance value, this achieves calibration of the voltage conversion coefficient; based on V′ under each channel. ref The sampling and quantization are performed again to obtain the digital code value of the offset voltage of the operational amplifier in each channel; the offset voltage of each channel at V′ is then calculated. ref The quantized digital code is calculated together with the stored offset voltage digital code K of the channel to complete the calibration of the inconsistent sampling results between different channels in the battery management chip based on the operational amplifier sampling structure.

Description

Technical Field

[0001] This invention belongs to the field of battery management chip technology, specifically relating to a method for calibrating multi-channel voltage sampling inconsistency in battery management chips. Background Technology

[0002] With advancements in technology, an increasing number of intelligent electronic products are opting for lithium batteries, which are low-cost, high-energy-density, environmentally friendly, and lightweight. However, lithium batteries also present some safety hazards during use. Overcharging, over-discharging, overcurrent, and high temperatures can jeopardize battery life and even endanger the personal safety and property of users. The primary function of a lithium battery management chip is to collect information such as voltage, current, and temperature during battery use, monitor the battery's condition, analyze the collected data, implement appropriate safety measures, and assess battery safety.

[0003] A single battery management chip typically monitors the voltage of several to a dozen batteries. In operational amplifier-based battery voltage sampling methods, each battery has a sampling channel. As the number of batteries increases and the sampling accuracy requirements become more stringent, even for the same operational amplifier, manufacturing processes can lead to different offset voltages between the amplifiers. Simultaneously, mismatches can occur in resistors R1 and R2, causing errors in the voltage conversion coefficient compared to the design ideal value. Therefore, for the same battery voltage, the final sampling results from different channels are inconsistent. This is especially problematic when the battery voltage is undervoltage, overvoltage, or near the equalization threshold, potentially triggering a safety event and failing to accurately assess the battery's charge level for timely and accurate protection.

[0004] Currently, the main methods for eliminating offset voltage are offset storage and chopping technology. However, for multi-cell series-connected lithium battery packs, high-voltage transistors will inevitably be introduced. On the one hand, this will introduce noise that affects sampling accuracy and increases design difficulty. On the other hand, it will also consume a lot of area and increase manufacturing costs. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-channel voltage sampling inconsistency calibration method for use in battery management chips, so as to solve the problems of high design difficulty and high cost in voltage sampling offset elimination technology.

[0006] The technical solution adopted in this invention is a multi-channel voltage sampling inconsistency calibration method applied to battery management chips. The specific operation steps are as follows:

[0007] The offset voltage V of the operational amplifier in the operational amplifier-based voltage sampling structure os Based on the voltage conversion coefficient mismatch corresponding to resistors R1 and R2, separate them and calibrate them separately;

[0008] First, two different battery voltages are given, with a voltage difference of 1V. Each channel is sampled and quantized. A numerical subtractor calculates the difference between the actual voltage conversion coefficient and the ideal voltage conversion coefficient, obtaining the offset of the voltage conversion coefficient. The decoder decodes this offset and adjusts the quantization voltage V of the analog-to-digital converter (ADC) based on this offset. ref V was obtained through adjustment. r ′ ef ;

[0009] According to V under each channel r ′ ef Given another battery voltage, sampling and quantization are performed to obtain the voltage at V. r ′ ef The actual value is used to calculate the difference between the actual value containing the offset voltage and the ideal digital code of the given voltage using a numerical subtractor, thus obtaining the digital code value K of the op-amp offset voltage in each channel; after calibration, in the sampling stage, the battery voltage sampled by the analog front end is quantized by the ADC to obtain D. in The final sampled and quantized digital code of the battery voltage is D. out =D in +K.

[0010] The invention is further characterized in that,

[0011] During the calibration phase, the voltage supplied to each battery is V. i After sampling by the analog front end and quantization by the analog-to-digital converter (ADC), the corresponding digital code X is obtained and stored in a register; then, the voltage of each battery is V. i -1, after analog front-end sampling and ADC quantization, the digital code Y is obtained; XY operation is performed in the digital domain; then XYA=Z operation is performed, where A is the ideal digital code of the voltage conversion coefficient in the analog front-end sampling, that is, the ideal digital code corresponding to resistor R2 / R1, and Z is the offset of the voltage conversion coefficient. The offset Z is decoded, and the switch S is controlled by the decoding result. n ~S p Select V ref Select the appropriate reference value in the circuit to obtain V. r ′ ef Complete the V ref The adjustment is made to compensate for the offset of R2 / R1 from the standard value, thereby calibrating the voltage conversion coefficient.

[0012] The voltage of each battery is V. i -1, and the V obtained after adjustment r ′ efNext, the analog front-end sampling voltage is quantized to obtain the digital code M. At this time, the offset voltage V of the operational amplifier in this channel is... os They are quantized together into M; the ML=K operation is performed, and L is (V i -1)*(R2 / R1) voltage corresponds to the ideal digital code, where K is the offset voltage V. os The quantized digital code; in each sampling process after calibration, the battery voltage obtained from the analog front-end sampling is quantized by the ADC to obtain the digital code D. in D in Then, by calculating with the digital code K of the offset voltage, the final sampled, quantized, and calibrated result, D, is obtained. out =D in +K.

[0013] The actual voltage conversion coefficient is calculated using the first numerical subtractor; then, the difference between the actual voltage conversion coefficient and the ideal voltage conversion coefficient is calculated using the second numerical subtractor and decoded. The decoded result is then transmitted to the control switch S. n ~S p For V ref Adjust the value to obtain V. r ′ ef ;

[0014] The first numerical subtractor is used to calculate the voltage of each battery cell, given as V. i and V i -1 is the difference between the digital codes X and Y after ADC quantization;

[0015] The second numerical subtractor calculates the offset between the obtained result and the digital code of the ideal voltage conversion coefficient. The decoder decodes this offset and sends the decoding result to the control switch S. n ~S p Select the appropriate benchmark value V r ′ ef Determine the relationship between V and each channel. ref The adjustment value V r ′ ef And store it.

[0016] For quantization voltage V ref The value is adjusted to obtain V r ′ ef The method is as follows:

[0017] If the obtained offset Z is a negative number, then the initial V needs to be... ref Decrease the value, and use the sign bit of Z to control V. ref To Xiaoxiu, the numerical bits of Z, after being decoded by the decoder, control the selected V. r ′ efThe value of Z; if the obtained offset Z is a non-negative number, then the opposite applies.

[0018] The problem of inconsistent multi-channel voltage sampling is calibrated by using the R1 and R2 mismatch calibration circuit, the op-amp offset voltage calibration circuit, and the final sampling circuit.

[0019] The R1 and R2 mismatch calibration circuit includes a SAR analog-to-digital converter (ADC), a first subtractor, a second subtractor, and a decoder; the quantization reference voltage V... ref Connected to the reference terminal of the SAR analog-to-digital converter (ADC), the analog front-end sampling circuit outputs V. o1 ~V on Connected to the sampling input of the SAR analog-to-digital converter (ADC), the SAR ADC is used to quantize the V obtained by the analog front-end sampling sequentially. i *(R2 / R1) and (V i -1)*(R2 / R1); The ADC output is connected to the input of the first numerical subtractor to calculate the difference between X and Y. The output of the first numerical subtractor is connected to the input of the second numerical subtractor to calculate the difference Z between X, Y, and A. The output of the second numerical subtractor is connected to the input of the decoder to decode Z. The sign bit S of Z... ign Connect to V ref The input of the inverter inv in the selection circuit and the NMOS switch M sn The gate, the output S of inv igp Connected to NMOS tube M sp The gate controls V ref Adjust to increase or decrease; decoder output S n ~S p Connected to switch M, which consists of NMOS transistors n ~M p The gate is used to control the selection of the appropriate ADC quantization reference voltage V. r ′ ef .

[0020] The op-amp offset voltage calibration circuit includes V ref Selection circuit, SAR analog-to-digital converter (ADC), and first numerical subtractor; V ref Select the voltage divider resistor R in the circuit. n The bottom and R p The top end is connected to the lowest calibrated voltage V. refn and the highest voltage V refp Voltage divider resistor R n ~R p The output terminal is connected to the nmos switch M n ~M p The source terminals are connected to generate different quantization reference voltages V.r ′ ef M n The drain of M1 is connected to the NMOS switching transistor M. sn The source pole, M0~M p The drain is connected to the NMOS switch M. sp The source, M sn The drain and M sp The drain of the ADC is connected to the reference terminal of the SAR analog-to-digital converter (ADC) and output to provide the reference value V for ADC quantization in different channels. r ′ ef ; Analog front-end sampling output V o1 ~V on Connected to the sampling input of the SAR analog-to-digital converter (ADC), the ADC will simulate the voltage (V) sampled from the front end. i -1)*(R2 / R1) is used to quantize and obtain the digital code M; the output of the SAR analog-to-digital converter (ADC) is connected to the input of the first numerical subtractor to calculate the difference between the actual value M and the ideal value L, thus obtaining the op-amp offset voltage V for each channel. os The quantized digital code K;

[0021] The final sampling circuit includes V ref Selection circuit, SAR analog-to-digital converter (ADC), and third numerical subtractor; V ref Select the NMOS switch M in the circuit. n ~M p and NMOS switching transistor M sn and M sp Connected to the reference terminal of the SAR analog-to-digital converter (ADC), it is used to output the reference value V for ADC quantization under different channels. r ′ ef ; Analog front-end sampling output V o1 ~V on Connected to the sampling input of the SAR analog-to-digital converter (ADC), the ADC will convert V o1 ~V on After quantization, D is obtained in The output of the SAR analog-to-digital converter (ADC) is connected to the input of the third numerical subtractor, which converts the front-end sampled and quantized D... in Calculate with K to complete the final sampled output D. out .

[0022] The voltage unit used in sampling and calculation is the volt (V).

[0023] The beneficial effects of this invention are: This invention calibrates the operational amplifier offset voltage and voltage conversion coefficient resistor mismatch present in voltage sampling based on the operational amplifier structure using a digital domain method. By separating these two factors for separate calibration, the design difficulty of the analog front-end sampling circuit is reduced. First, the offset of the voltage conversion coefficient from the ideal value obtained from the first and second samplings is calculated. The offset is then automatically decoded to obtain the calibration digital code, which controls V... ref The switch in the selection circuit obtains the reference value V for ADC quantization in each channel. r ′ ef The third time in V r ′ ef The given battery voltage is requantized and the difference is calculated to obtain the offset voltage of each channel. This eliminates the need for external processor calculations, greatly reducing complexity, and ultimately yields the sampled and calibrated digital code D. out =D in +K. A digital method is used to calibrate the inconsistency between different channels of battery voltage sampling based on an operational amplifier structure. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of an operational amplifier-based voltage sampling analog front-end and a SAR analog-to-digital converter (ADC).

[0025] Figure 2 This diagram illustrates the impact of operational amplifier offset and the pairing of resistors R1 and R2 on the sampling results in an operational amplifier-type voltage sampling structure.

[0026] Figure 3 This is a schematic diagram of the calibration circuit of the present invention.

[0027] Figure 4(a) shows the simulation results of the battery voltage before and after calibration at 1.5V.

[0028] Figure 4(b) shows the simulation results of the battery voltage before and after calibration at 3V.

[0029] Figure 4(c) shows the simulation results of the battery voltage before and after calibration at 4.5V. Detailed Implementation

[0030] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0031] Example 1

[0032] The offset voltage V of the operational amplifier in the operational amplifier-based voltage sampling structure os Based on the voltage conversion coefficient mismatch corresponding to resistors R1 and R2, separate them and calibrate them separately;

[0033] First, two different battery voltages are given, with a voltage difference of 1V. Each channel is sampled and quantized. A numerical subtractor calculates the difference between the actual voltage conversion coefficient and the ideal voltage conversion coefficient, obtaining the offset of the voltage conversion coefficient. The decoder decodes this offset and adjusts the quantization voltage V of the analog-to-digital converter (ADC) based on this offset. ref V was obtained through adjustment. r ′ ef ;

[0034] According to V under each channel r ′ ef Given another battery voltage, sampling and quantization are performed to obtain the voltage at V. r ′ ef The actual value is used to calculate the difference between the actual value containing the offset voltage and the ideal digital code of the given voltage using a numerical subtractor, thus obtaining the digital code value K of the op-amp offset voltage in each channel; after calibration, in the sampling stage, the battery voltage sampled by the analog front end is quantized by the ADC to obtain D. in The final sampled and quantized digital code of the battery voltage is D. out =D in +K.

[0035] Example 2

[0036] Based on Example 1,

[0037] During the calibration phase, the voltage supplied to each battery is V. i After sampling by the analog front end and quantization by the analog-to-digital converter (ADC), the corresponding digital code X is obtained and stored in a register; then, the voltage of each battery is V. i -1, after analog front-end sampling and ADC quantization, the digital code Y is obtained; XY operation is performed in the digital domain; then XYA=Z operation is performed, where A is the ideal digital code of the voltage conversion coefficient in the analog front-end sampling, that is, the ideal digital code corresponding to resistor R2 / R1, and Z is the offset of the voltage conversion coefficient. The offset Z is decoded, and the switch S is controlled by the decoding result. n ~S p Select V ref Select the appropriate reference value in the circuit to obtain V. r ′ er Complete the V ref The adjustment is made to compensate for the offset of R2 / R1 from the standard value, thereby calibrating the voltage conversion coefficient.

[0038] The voltage of each battery is V. i -1, and the V obtained after adjustment r ′ efNext, the analog front-end sampling voltage is quantized to obtain the digital code M. At this time, the offset voltage V of the operational amplifier in this channel is... os They are quantized together into M; the ML=K operation is performed, and L is (V i -1)*(R2 / R1) voltage corresponds to the ideal digital code, where K is the offset voltage V. os The quantized digital code; in each sampling process after calibration, the battery voltage obtained from the analog front-end sampling is quantized by the ADC to obtain the digital code D. in D in Then, by calculating with the digital code K of the offset voltage, the final sampled, quantized, and calibrated result, D, is obtained. out =D in +K.

[0039] For quantization voltage V ref The value is adjusted to obtain V r ′ ef The method is as follows:

[0040] If the obtained offset Z is a negative number, then the initial V needs to be... ref Decrease the value, and use the sign bit of Z to control V. ref To Xiaoxiu, the numerical bits of Z, after being decoded by the decoder, control the selected V. r ′ ef The value of Z; if the obtained offset Z is a non-negative number, then the opposite applies.

[0041] Example 3

[0042] This invention applies to a multi-channel voltage sampling inconsistency calibration method in battery management chips. The specific operation steps are as follows:

[0043] Figure 1 This diagram illustrates an operational amplifier-type voltage sampling structure and an SRA ADC structure in a battery management chip. The highest voltage of the first battery is 4.5V, so a 1 / 2 voltage divider through a resistor is sufficient. The highest total voltage of the second battery is 9V, which can be sampled using a subtractor. However, as the number of batteries increases and the total battery voltage rises, the operational amplifier clamps the negative terminal voltage of the battery to the lower end of resistor R1. The voltage generated across R2 by the current flowing through resistor R1 is the converted sampling voltage. However, because each battery has its own sampling channel, and due to manufacturing limitations, even with operational amplifiers of the same structure and resistors of the same value, they cannot be manufactured to be exactly the same.

[0044] Figure 2This diagram illustrates the impact of mismatch between the two components on the sampling results. If only the operational amplifier (op-amp) is mismatched, the final input-output curve will shift upwards or downwards. If only resistors R1 and R2 are mismatched, the slope of the final input-output curve (i.e., the battery voltage conversion factor) will change. If both op-amp mismatch and resistor mismatch exist in the same channel, the final input-output curve will shift upwards or downwards, and the slope will also change. This leads to inconsistencies in the sampling results even when the same battery voltage is sampled in different channels during the actual operation of the battery management chip. This results in inaccurate battery capacity assessment and may even cause false triggering of protection functions.

[0045] Figure 3 This is a circuit diagram illustrating the application of this invention in multi-channel voltage sampling inconsistency calibration within a battery management chip. It includes a SAR analog-to-digital converter (ADC), a numerical subtractor, a decoder, and a V... ref Select circuit.

[0046] The circuit for calibrating the mismatch between R1 and R2 consists of a SAR analog-to-digital converter (ADC), a subtractor 1, a subtractor 2, and a decoder. Subtractor 1 calculates the voltage of each battery cell given as V. i and (V) i -1) The difference between the digital codes X and Y after sampling and ADC quantization is used by the second numerical subtractor to calculate the offset between the obtained difference and the ideal voltage conversion coefficient digital code. The decoder decodes this offset and controls V through a switch to output the decoding result. ref Select the appropriate reference value V for the circuit. r ′ ef .

[0047] The op-amp offset voltage calibration circuit is composed of V r ′ ef The circuit consists of a selection circuit, a SAR analog-to-digital converter (ADC), and a numerical subtractor 1. Given an input voltage of (V... i -1) Under the condition of V, each channel is sampled and the corresponding ADC quantization reference voltage V is applied. r ′ ef The quantization is then performed, and the quantized result is passed through the first numerical subtractor and compared with the ideal (V). i The difference between the digital codes corresponding to -1)*(R2 / R1)V is used to obtain the op-amp offset voltage V for each channel. os The digital code value K.

[0048] The final sampling circuit consists of V ref The circuit consists of a selection circuit, a SAR analog-to-digital converter (ADC), and a numerical subtractor. ref The selection circuit controls the V under this channel. r ′ef The voltage value is passed to the SAR analog-to-digital converter (ADC) as the reference voltage value for quantization. The third numerical subtractor calculates the result of the ADC output with the K value of the corresponding channel to obtain the final digital code output.

[0049] In the actual analog front-end circuit, due to the superposition of op-amp offset and R1 / R2 mismatch, we need to first calibrate the mismatch between R1 and R2. In this stage, the voltage of each battery cell is initially given as V. i (V), after being sampled by the analog front end, yields the analog output V. on1 =(V i +V os The result is )*(R2 / R1), which is then quantized by an ADC to obtain the decimal value V corresponding to the digital code X. on1 / LSB, where LSB is the minimum resolution of the ADC, i.e., V ref / 2 N N is the effective number of bits of the ADC. X is then stored in a register. Then, given the voltage of each battery cell as (V) i -1)V, obtained after sampling by the analog front-end circuit. on2 =(V i -1+V os The result is )*(R2 / R1), which is then quantized by an ADC to obtain the decimal value V corresponding to the digital code Y. on2 / LSB. The XY operation is performed through the first numerical subtractor. Since both samplings are performed on the same channel, V... os The XY result is canceled out after the subtraction operation. The result is then fed into the second numerical subtractor and subtracted from the digital code A corresponding to the ideal R2 / R1 to obtain the offset Z of R2 / R1. This offset is then decoded. If the obtained Z is negative, the initial V needs to be... ref Decrease the value, and use the sign bit of Z to control V. ref To Xiaoxiu, the numerical value of Z is decoded by the decoder and then used to control the selected V via a switch. ref’ The value of V is determined by the decoding process. If the result is a non-negative number, the opposite is true. The decoded result of each channel decoder is stored, and the corresponding result is retrieved to control V during each sampling. ref The output is used to calibrate the mismatch between R1 and R2, that is, to complete the calibration of the voltage conversion coefficient.

[0050] In V ref After adjustment, the quantized result of each voltage sample includes the offset voltage of the operational amplifier in the corresponding channel. Therefore, during the offset voltage calibration stage, the given voltage of each battery cell is (V i -1)V, obtained after sampling by the analog front-end circuit. on3 =(V i -1+Vos The result is )*(R2 / R1), which is then quantized by an ADC to obtain the decimal value V corresponding to the digital code M. on3 / LSB', where LSB' is V r ′ ef / 2 N V os Both are quantized into M. M and (V) i The ideal digital code L corresponding to -1) / 2 is calculated by numerical subtractor 1 to the offset voltage V. os The digital code K is used to store the K value of each channel to complete the calibration.

[0051] After calibration, each voltage sampling is performed, followed by analog front-end sampling and ADC quantization, and finally, a third numerical subtractor is used to obtain the final digital code output D. out =D in +K.

[0052] Figures 4(a)-4(c) The figures show the simulation results before and after calibration for this invention. Taking seven channels as an example, the simulation results are shown when the battery voltage is 1.5V, 3V, and 4.5V. A 12-bit SAR ADC was used in the simulation. The top of the simulation results in Figure 4 is the clock signal CLK. The numbers in the figure are the decimal values ​​corresponding to the digital codes of the battery voltage obtained from the front-end sampling after ADC quantization. The "before" in the figure shows the result of sampling without calibration, and "Dout" is the result of sampling without calibration. <11> ~Dout <0> This is the final output after calibration, a 12-bit parallel result. At 1.5V, the maximum error before calibration was 79 LSBs, and the maximum error after calibration was 2 LSBs; at 3V, the maximum error before calibration was 187 LSBs, and the error after calibration was 0; at 4.5V, the maximum error before calibration was 281 LSBs, and the maximum error after calibration was 2 LSBs.

[0053] This invention, from a digital domain perspective, separates the offset voltage of operational amplifiers in different channels of the analog front-end from the mismatch of voltage conversion coefficients R2 / R1. Firstly, it separates the offset voltage of the ADC quantization reference voltage V... ref After adjusting and calibrating the voltage conversion factor, the V of each channel's operational amplifier is then adjusted. os The data is stored to complete the calibration of inconsistencies between different channels based on operational amplifier-type voltage sampling, such as... Figures 4(a)-4(c) The waveform is shown.

Claims

1. A method for calibrating multi-channel voltage sampling inconsistency in battery management chips, characterized in that, The offset voltage V of the operational amplifier in the operational amplifier-based voltage sampling structure os The mismatch of the voltage conversion coefficients corresponding to resistors R1 and R2 is separated and calibrated separately. First, two different battery voltages are given, with a voltage difference of 1V. Each channel is sampled and quantized. A numerical subtractor calculates the difference between the actual voltage conversion coefficient and the ideal voltage conversion coefficient, obtaining the offset of the voltage conversion coefficient. The decoder decodes this offset, and based on the decoding result, the quantized voltage V of the analog-to-digital converter (ADC) is calculated. ref Adjustments were made to obtain ; According to each channel Given another battery voltage, sampling and quantization are performed to obtain the result. The actual value is calculated using a numerical subtractor. The difference between the actual value containing the offset voltage and the ideal digital code of the given voltage is used to obtain the digital code value K of the op-amp offset voltage in each channel. After calibration, during the sampling phase, the battery voltage obtained from the analog front-end sampling is quantized by the ADC to obtain D. in The final sampled and quantized digital code of the battery voltage is D. out =D in +K; The specific steps are as follows: During the calibration phase, the voltage supplied to each battery is... V i After sampling by the analog front end and quantization by the analog-to-digital converter (ADC), the corresponding digital code X is obtained and stored in a register; then, the voltage of each battery is... V i -1, after analog front-end sampling and ADC quantization, the digital code Y is obtained; XY operation is performed in the digital domain; then XYA=Z operation is performed, where A is the ideal digital code of the voltage conversion coefficient in the analog front-end sampling, that is, the ideal digital code corresponding to resistor R2 / R1, and Z is the offset of the voltage conversion coefficient. The offset Z is decoded, and the switch S is controlled by the decoding result. n ~S p Select V ref By selecting the appropriate reference value in the circuit, we can obtain... Complete the V ref The adjustment is made to compensate for the offset of R2 / R1 from the standard value, thereby calibrating the voltage conversion coefficient. The voltage of each battery is V i -1, and obtained after adjustment Next, the analog front-end sampling voltage is quantized to obtain the digital code M. At this time, the offset voltage V of the operational amplifier in this channel is... os They are quantized together into M; the ML=K operation is performed, and L is ( V i -1)*(R2 / R1) voltage corresponds to the ideal digital code, where K is the offset voltage V. os The quantized digital code; in each sampling process after calibration, the battery voltage obtained from the analog front-end sampling is quantized by the ADC to obtain the digital code D. in D in Then, by calculating with the digital code K of the offset voltage, the final sampled, quantized, and calibrated result, D, is obtained. out =D in +K; The actual voltage conversion coefficient is calculated using the first numerical subtractor; then, the difference between the actual voltage conversion coefficient and the ideal voltage conversion coefficient is calculated using the second numerical subtractor and decoded. The decoded result is then transmitted to the control switch S. n ~S p For V ref Adjust the value to obtain ; The first numerical subtractor is used to calculate the given voltage of each battery cell. V i as well as V i -1 is the difference between the digital codes X and Y after ADC quantization; The second numerical subtractor calculates the offset between the obtained result and the digital code of the ideal voltage conversion coefficient. The decoder decodes this offset and sends the decoding result to the control switch S. n ~S p Select the appropriate benchmark value Determine the relationship between V and each channel. ref adjustment value And store it; For quantization voltage V ref The value was adjusted to obtain The method is as follows: If the obtained offset Z is a negative number, then the initial V needs to be... ref Decrease the value, and use the sign bit of Z to control V. ref To Xiaoxiu, the numerical bits of Z, after being decoded by the decoder, control the selection of... The value of Z; if the obtained offset Z is a non-negative number, then the opposite applies.

2. The method for calibrating multi-channel voltage sampling inconsistency in battery management chips according to claim 1, characterized in that, The problem of inconsistent multi-channel voltage sampling is calibrated by using the R1 and R2 mismatch calibration circuit, the op-amp offset voltage calibration circuit, and the final sampling circuit. The R1 and R2 mismatch calibration circuit includes a SAR analog-to-digital converter (ADC), a first numerical subtractor, a second numerical subtractor, and a decoder; the quantization reference voltage V... ref Connected to the reference terminal of the SAR analog-to-digital converter (ADC), the analog front-end sampling circuit outputs V. o1 ~V on Connected to the sampling input of the SAR analog-to-digital converter (ADC), the SAR ADC is used to quantize the samples obtained from the simulation front end. V i *(R2 / R1) and ( V i -1)*(R2 / R1); The ADC output is connected to the input of the first numerical subtractor to calculate the difference between X and Y. The output of the first numerical subtractor is connected to the input of the second numerical subtractor to calculate the difference Z between XYA. The output of the second numerical subtractor is connected to the input of the decoder to decode Z; the sign bit S of Z... ign Connect to V ref The input of the inverter inv in the selection circuit and the NMOS switch M sn The gate, the output S of inv igp Connected to NMOS tube M sp The gate controls V ref Adjust to increase or decrease; decoder output S n ~S p Connected to switch M, which consists of NMOS transistors n ~M p The gate is used to control the selection of the appropriate ADC quantization reference voltage. ; The operational amplifier offset voltage calibration circuit includes V ref Selection circuit, SAR analog-to-digital converter (ADC), and first numerical subtractor; V ref Select the voltage divider resistor R in the circuit. n The bottom and R p The top end is connected to the lowest calibrated voltage V. refn and the highest voltage V refp Voltage divider resistor R n ~R p The output terminal is connected to the nmos switch M n ~M p The source terminals are connected to generate different quantization reference voltages. M n The drain of M1 is connected to the NMOS switch M. sn The source pole, M0~M p The drain is connected to the NMOS switch M. sp The source, M sn The drain and M sp The drain is connected and the output is connected to the reference terminal of the SAR analog-to-digital converter (ADC) to output the reference value for ADC quantization under different channels. ; Analog front-end sampling output V o1 ~V on Connected to the sampling input of the SAR analog-to-digital converter (ADC), the ADC will simulate the voltage sampled from the front end. V i Quantization of -1)*(R2 / R1) yields the digital code M; The output of the SAR analog-to-digital converter (ADC) is connected to the input of the first numerical subtractor to calculate the difference between the actual value M and the ideal value L, thus obtaining the op-amp offset voltage V for each channel. os The quantized digital code K; The final sampling circuit includes V ref Selection circuit, SAR analog-to-digital converter (ADC), and third numerical subtractor; V ref Select the NMOS switch M in the circuit. n ~M p and NMOS switching transistor M sn and M sp Connected to the reference terminal of the SAR analog-to-digital converter (ADC), it is used to output the reference value for ADC quantization in different channels. ; Analog front-end sampling output V o1 ~V on Connected to the sampling input of the SAR analog-to-digital converter (ADC), the ADC will convert V o1 ~V on After quantization, D is obtained in The output of the SAR analog-to-digital converter (ADC) is connected to the input of the third numerical subtractor, which converts the front-end sampled and quantized D... in Calculate with K to complete the final sampled output D. out .

3. The method for calibrating multi-channel voltage sampling inconsistency in battery management chips according to any one of claims 1-2, characterized in that, The voltage unit used in sampling and calculation is V.

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