Compact aCAM array (tree-type CAM) for decision tree inference

Abstract

This disclosure provides a compact aCAM array (tree-based CAM) for decision tree inference. Examples of the technology disclosed herein provide a "tree-based CAM" specifically constructed to more efficiently implement decision trees—that is, with less hardware (i.e., fewer memristors and transistors), less power consumption, and less memristor programming time compared to existing aCAMs used for implementing decision trees. The tree-based CAM achieves these optimizations by utilizing a shared comparator subcircuit that stores a threshold shared among evaluable conditions for multiple root-to-leaf paths of the decision tree. The threshold can be evaluated based on common features of the feature vectors. The shared comparator subcircuit may consist of only a single memristor programmed to store the threshold. Therefore, the tree-based CAM can represent / implement evaluable conditions (sharing a common threshold and evaluating based on common features) on multiple root-to-leaf paths of the decision tree using only a single memristor—thus reducing the memristors required to implement the decision tree.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 440,014, filed January 19, 2023, which is incorporated herein by reference in its entirety. Background Technology

[0003] Content-addressable memory (“CAM”) is a type of computational memory in which stored data is searched based on its content rather than its location. When a “word” is input into the CAM, the CAM searches for that word in its content. If the CAM finds the word (i.e., “returns a match”), the CAM returns the address of the location of the found word.

[0004] Analog CAM (“aCAM”) is a special type of CAM that can use the programmable conductance of a memristor to store and search a range of values ​​(compared to the more traditional digital-based CAM that can only store / search zeros and ones).

[0005] Individual aCAM cells can be arranged as an aCAM array consisting of rows and columns of aCAM cells. Words can be stored along the rows of the aCAM array (the rows of the aCAM array can be called "matching lines"), where each aCAM cell in a given row stores an entry of the stored word. When the aCAM array receives an input word (e.g., a series of analog voltage signals, each analog voltage signal representing an entry of the input word), the aCAM array is able to search for the input word along the columns of the aCAM array by entries (i.e., the first entry of the input word can be searched down in the first column of the aCAM array, the second entry of the input word can be searched down in the second column of the aCAM array, and so on). If all aCAM cells in a given row return a value that matches the corresponding entry of the input word, then the aCAM array has "found" the input word in the given row. Attached Figure Description

[0006] This disclosure is described in detail with reference to the following figures, based on one or more various examples. The figures provided are for illustrative purposes only and are merely examples.

[0007] Figure 1 An example aCAM unit is described according to the technology disclosed herein.

[0008] Figure 2 An example voltage range diagram is depicted according to an example of the technology disclosed herein.

[0009] Figure 3 Another example voltage range diagram is depicted according to the technology of this disclosure.

[0010] Figure 4An example decision tree is described based on the techniques of this disclosure.

[0011] Figure 5 An example feature chain is described according to an example of the technology disclosed herein.

[0012] Figure 6 An example representation of a decision tree in aCAM, based on the techniques described herein, is presented.

[0013] Figures 7A-7C Example decision trees, example representations of decision trees in aCAM, and example representations of decision trees in tree-type CAMs are described respectively, according to the present disclosure.

[0014] Figures 8A-8B Example representations of decision trees and example decision trees in tree-type CAMs according to the present disclosure are described respectively.

[0015] Figure 9 A block diagram of an example computer system is depicted, in which various examples described herein can be implemented.

[0016] These accompanying drawings are not exhaustive and do not limit this disclosure to the precise form disclosed. Detailed Implementation

[0017] Tree-based models (e.g., random forests, gradient boosting trees, etc.) are popular machine learning models because they are easy to train, perform well on small datasets (especially tabular datasets), and can provide human-interpretable explanations. As used in this paper, tree-based models are often referred to as decision trees.

[0018] A decision tree consists of multiple root-to-leaf paths. Each root-to-leaf path represents a traversal of a series of decision nodes. For example, a root-to-leaf path might begin at the root decision node, traverse one or more intermediate decision nodes, and end at a leaf node. Each decision node traversed in a root-to-leaf path can represent an evaluable condition, according to which features of a feature vector can be evaluated. Therefore, a root-to-leaf path can represent a series of evaluable conditions that represent logical rules, according to which feature vectors can be evaluated.

[0019] The decision tree can be reformulated for aCAM implementation by representing each root-to-leaf path of the decision tree as a “feature chain” comprising a series of feature chain nodes. A feature chain node can represent one or more evaluable conditions of the root-to-leaf path, against which a given feature of the feature vector is evaluated. Decision nodes associated with common features in the root-to-leaf paths can be combined into a single feature chain node, and “wildcard” (i.e., “don’t care” or “always match”) feature chain nodes can be used to indicate features not evaluated in the root-to-leaf path. Such representations can be programmed into rows of aCAM such that each row in aCAM represents a different root-to-leaf path of the decision tree. Individual aCAM units in a row can be programmed to represent a single feature chain node associated with the root-to-leaf path (e.g., a first aCAM unit can be programmed to represent a first feature chain node representing a first feature of the feature vector evaluated according to it, a second aCAM unit can be programmed to represent a second feature chain node representing a second feature of the feature vector evaluated according to it, and so on). Therefore, the columns of an aCAM can be associated with individual features of the feature vector evaluated according to the decision tree (e.g., the aCAM cell in the first column of an aCAM can be evaluated based on the first feature of the feature vector, the aCAM cell in the second column of an aCAM can be evaluated based on the second feature of the feature vector, etc.). As mentioned above, an aCAM cell can be programmed as a wildcard value to represent a wildcard feature chain node that describes a feature that was not evaluated in a given root-to-leaf path. Such an aCAM cell may be referred to as a "non-evaluation cell" in this paper.

[0020] As described above, by applying a series of analog input voltages down to the columns of the aCAM, feature vectors can be applied to root-to-leaf paths stored in the aCAM (e.g., a first analog input voltage representing a first feature can be applied down to the first column of the aCAM, a second analog input voltage representing a second feature can be applied down to the second column of the aCAM, and so on). If the first row of the aCAM returns a match, the match indicates that the feature vector matches the first root-to-leaf path represented by the first row. In some implementations, the leaves of the root-to-leaf paths (e.g., classification results) can be programmed as random access memory (RAM) or resistive RAM (ReRAM) arrays directly connected to the matching lines of the aCAM.

[0021] The representations used for decision trees in aCAM described above can be very sparse because typically, a given root-to-leaf path in a decision tree will only evaluate a subset of features associated with the feature vector. Therefore, memristors associated with “non-evaluation units” (i.e., aCAM unit representing a wildcard feature chain node associated with a feature not evaluated for a given root-to-leaf path) are typically programmed to always return matching “wildcard” values. Correspondingly, for a decision tree of depth D, up to 2^D values ​​may have to be programmed into the aCAM, many of which are wildcards and / or redundant values. This leads to large area and power overhead, as well as low utilization of the aCAM hardware. Relatedly, reliable memristor programming typically requires several iterations, thus an increasing number of memristors leads to an increasing number of programming failures. Therefore, there is a need for aCAM capable of implementing decision trees with greater efficiency.

[0022] In this context, examples of the technology disclosed herein provide an aCAM (referred to herein as a "tree-based CAM") specifically constructed to implement decision trees more efficiently, i.e., with less hardware (i.e., fewer memristors and transistors), less power consumption, and less memristor programming time compared to existing aCAMs used for implementing decision trees. The tree-based CAM achieves these optimizations by utilizing a "shared" comparator subcircuit that stores a threshold shared among evaluable conditions for multiple root-to-leaf paths of the decision tree (here, each root-to-leaf path may be associated with a separate matching line of the tree-based CAM). The threshold can be evaluated based on common features of the feature vectors. The shared comparator subcircuit may consist of only a single memristor programmed to store the threshold. Therefore, the tree-based CAM can represent / implement evaluable conditions across multiple root-to-leaf paths of the decision tree using only a single memristor (sharing a common threshold and evaluating based on common features) – thereby reducing the memristors required to implement the decision tree. Relatedly, tree-based CAMs can eliminate / reduce memristors and other hardware associated with the aforementioned “non-evaluation units,” which proliferate in the existing representation of the decision tree in aCAM (e.g., see...). Figure 7B (Example in the text). Therefore, compared to existing aCAM circuits used to implement decision trees, tree-based CAMs can be more compact, consume less power (a large portion of the power consumption of aCAM circuits is associated with memristor programming and its associated circuitry), and require less memristor programming time.

[0023] In various examples, the tree-based CAM of this disclosure may include: (1) a first matching line associated with a first root-to-leaf path of the decision tree; (2) a second matching line associated with a second root-to-leaf path of the decision tree; and (3) a shared comparator subcircuit including a (single) memristor. The shared comparator subcircuit may operate to: (a) store a boundary voltage threshold based on the memristor's programming conductance, the boundary voltage threshold being associated with one or more evaluable conditions relating to a feature vector; (b) receive an analog input voltage corresponding to the feature; and (c) output a comparison output voltage including a first voltage when the analog input voltage exceeds the stored boundary voltage threshold and a second voltage when the analog input voltage is less than the stored boundary voltage threshold. The tree-based CAM may also include: (1) a first matching line transistor that selectively modifies the voltage of the first matching line based on the comparison output voltage (e.g., modifying only the voltage of the first matching line when the comparator subcircuit includes the second voltage); and (2) a second matching line transistor that selectively modifies the voltage of the second matching line based on the comparison output voltage (e.g., modifying only the voltage of the second matching line when the comparator subcircuit includes the first voltage). Therefore (as described above), tree-based CAM can represent / implement evaluable conditions (sharing a common threshold and evaluating based on common features) using only a (single) memristor across multiple root-to-leaf paths of the decision tree.

[0024] In some examples, a tree-based CAM may include a third matching line associated with the third root-to-leaf path of the decision tree. Here, the first and second root-to-leaf paths may include evaluable conditions involving features, while the third root-to-leaf path does not. Therefore, of the first to third matching lines, only the first and second matching lines can be electrically connected to the shared comparator circuitry via matching line transistors. As described in more detail below, through this ingenious mechanism, tree-based CAMs can further reduce footprint, hardware, power consumption, programming time, and failures.

[0025] For the conceptual explanation (and as will be described in more detail below), the conventional aCAM representation (comprising 6 transistors and 2 memristor aCAM cells) will use: (1) a first aCAM cell electrically connected to a first matching line; (2) a second aCAM cell electrically connected to a second matching line; and (3) a third aCAM cell electrically connected to a third matching line to represent the decision tree segment described above. The first to third aCAM cells are typically located in the same column of the aCAM and will be evaluated based on the features applied to the aCAM. Here, the first aCAM cell will be programmed to store a first feature chain node (i.e., the feature chain node associated with the first root-to-leaf path), the second aCAM cell will be programmed to store a second feature chain node (i.e., the feature chain node associated with the second root-to-leaf path), and the third aCAM cell will be programmed to store a third “wildcard” feature chain node using a wildcard value that always returns a match (as mentioned above, the third aCAM cell may be referred to as a “non-evaluation” cell). Typically, the conductance of one memristor in the first aCAM unit is programmed such that the first aCAM unit stores the boundary voltage threshold stored by the shared comparator circuit of the aforementioned tree-structured CAM (here, the first aCAM unit can store the boundary voltage threshold as either an upper or lower boundary). The conductance of the second memristor in the first aCAM unit is programmed as a wildcard value. Similarly, the conductance of one memristor in the second aCAM unit is programmed such that the second aCAM unit stores the boundary voltage threshold stored by the shared comparator circuit of the aforementioned tree-structured CAM (again, the second aCAM unit can store the boundary voltage threshold as either an upper or lower boundary). The conductance of the second memristor in the first aCAM unit is programmed as a wildcard value. As described above, both memristors in the third aCAM unit are programmed as wildcard values. Therefore, a conventional aCAM representation will utilize 18 transistors and 6 memristors to store the aforementioned decision tree segment (i.e., (6 transistors and 2 memristors) x (3 aCAM units)). In contrast, tree-based CAMs can be implemented using only a single memristor and up to three transistors (e.g., up to one transistor for implementing the shared comparator circuitry, a first matching line transistor, and a second matching line transistor). Therefore, tree-based CAMs can significantly reduce footprint, hardware, power consumption, memristor programming time, and failures.

[0026] An example of this technique will be described in more detail with reference to the following diagram. That is, Figure 1-6 A general background is described, which may help to understand the advantages offered by the tree-based CAM of this disclosure over the traditional representation of decision trees in aCAM. Figures 7A-7C A comparison is shown between the traditional representation of decision trees in aCAM and the decision tree representation of a tree-based CAM using the techniques of this disclosure. Figures 8A-8BAnother representation of a decision tree for a tree-based CAM using the techniques of this disclosure is shown. Figure 9 A block diagram of an example computer system is depicted, in which various examples described herein can be implemented.

[0027] Now for reference Figure 1 , Figure 1 An example conventional aCAM cell 100 is depicted. The aCAM cell 100 may be an example of a 6 transistor-2 memristor (6T2M) aCAM cell commonly used to represent a decision tree in an aCAM.

[0028] aCAM cell 100 is electrically connected to a matching line (i.e., ML 102) that can be precharged to a high voltage. aCAM cell 100 can “return to matching” when the voltage across ML 102 remains high, and “return to mismatch” when the voltage across ML 102 is discharged. As described above, aCAM cell 100 can be an aCAM cell within a row of aCAMs. In some examples, the matching / mismatch results for an entire row (of which aCAM cell 100 is a part) can be output to another circuit (e.g., a resistive random access memory array (reRAM)) for further processing / classification.

[0029] aCAM unit 100 also includes two data lines: DL1 106 and DL2 108 (in Figure 1 In the example, both DL1 106 and DL2 108 are electrically connected to the input data line DL 104. The aCAM unit 100 can receive an analog input voltage signal (V(x)) along DL 104 (here, the analog input voltage (V(x)) can be an analog voltage signal converted from the digital input signal (x)). As shown, both DL1 106 and DL2 108 are electrically connected to DL 104 and are connected in parallel with each other. Therefore, the analog input voltage signal (V(x)) can be applied along DL1 106 and DL2 108 respectively. As described above, if the analog input voltage signal (V(x)) exceeds the analog voltage range programmed in the aCAM unit 100, the analog input voltage (V(x)) will eventually discharge ML102. Here, the analog voltage range stored by aCAM unit 100 is set / defined by the programming conductance of memristors M1 and M2, wherein the programming conductance of memristor M1 sets / defined the lower boundary of the stored analog current range, and the programming conductance of memristor M2 sets or defines the upper boundary of the stored analog voltage range (see, for example, [reference]). Figure 2 ).

[0030] As shown in the figure, the aCAM unit 100 includes a "lower boundary side" 110 and an "upper boundary side" 120. The reason for this designation is that memristors M1 and M2 are programmed to set the lower and upper boundaries of the analog voltage range stored by the aCAM unit 100, respectively.

[0031] The lower boundary side 110 includes a transistor T1 and a memristor M1 connected in series. The memristor M1, together with the transistor T1, defines a voltage divider subcircuit 112. As shown, the voltage divider subcircuit 112 generates a gate voltage (G1) across the pull-down transistor T2. When the gate voltage (G1) across the pull-down transistor T2 exceeds a threshold, the pull-down transistor T2 will turn on / activate and “pull down” (i.e., discharge) the voltage across ML 102, returning to mismatch. As mentioned above, the voltage across the pull-down transistor T2 can be affected by: (1) the programming conductance of the memristor M1; and (2) the analog input voltage signal (V(x)). In particular, when the analog input voltage signal (V(x)) is greater than or equal to the threshold voltage (e.g., (T... L When the transistor T1 becomes more conductive (the programming conductance of memristor M1 remains the same during the search operation), the voltage between SL_hi and SL_lo (typically at ground (GND)) will drop across memristor M1, resulting in a small gate voltage (G1) that does not turn on / on the pull-down transistor T2, producing a matching result at the lower boundary side 110. Here, the conductance of memristor M1 can be programmed (T) L The value of ) (i.e., the threshold voltage that will cause transistor T1 to become more conductive relative to memristor M1). In this way, the programming conductance of memristor M1 can be used to set the lower boundary of the voltage range stored by aCAM unit 100.

[0032] Similar to the lower boundary side 110, the upper boundary side 120 includes a transistor T3 and a memristor M2 connected in series. The memristor M2, together with the transistor T3, defines a voltage divider subcircuit 122. The upper boundary side 120 differs slightly from the lower boundary side 110 because the voltage divider subcircuit 122 is electrically connected to the input of the inverter 124 (here, the series combination of transistors T4 and T5 operates together to form the inverter 124). The inverter 124 operates to invert the voltage output of the voltage divider subcircuit 122. Since the pull-down transistor T6 is electrically connected to the output of the inverter 124, the reverse voltage output by the inverter 124 controls the gate voltage (G2) across the pull-down transistor T6. Similarly, when the gate voltage (G2) across the pull-down transistor T6 exceeds a threshold, the pull-down transistor T6 will turn on / activate and "pull down" (i.e., discharge) the voltage across ML 102, returning to mismatch. As mentioned above, the voltage across the pull-down transistor T6 may be affected by the following factors: (1) the programming conductance of the memristor M2; and (2) the analog input voltage signal (V(x)). Specifically, when the analog input voltage signal (V(x)) is less than or equal to the threshold voltage (e.g., (T...),... HWhen the voltage is high (e.g., about 10 nS conductance compared to a higher conductance state of, for example, 10 mS), the voltage between SL_hi and SL_lo (typically at GND) will remain high across transistor T3, resulting in a high voltage output from the voltage divider subcircuit 122. However, when this high voltage is reversed by inverter 124, the reversed (now low) voltage results in a low gate voltage (G2) that does not turn on / activate pull-down transistor T6, thus producing a matching result on the upper boundary side 120. Here, (T H The value of (i.e., the threshold voltage that would cause transistor T3 to have no high conductivity relative to memristor M2) can be programmed by programming the conductance of memristor M2. In this way, the upper boundary of the voltage range stored by aCAM cell 100 can be set using the programming conductance of memristor M2.

[0033] As described above (and will be combined) Figure 3 (To be described in more detail), one or both of M1 and M2 can be programmed as wildcard values. If both M1 and M2 are programmed as wildcard values, aCAM cell 100 will almost always return a match. If only M1 is programmed as a wildcard value, aCAM cell 100 will essentially / virtually only store the upper boundary voltage threshold. Conversely, if only M2 is programmed as a wildcard value, aCAM cell 100 will essentially / virtually only store the lower boundary voltage threshold.

[0034] Figure 2 An example diagram is depicted illustrating how memristors M1 and M2 from aCAM unit 100 are used to set the lower boundary voltage 202 and upper boundary voltage 204 of the storage voltage range for aCAM unit 100. As shown, when the analog input voltage signal (V(x)) is within the voltage range defined by the lower boundary voltage 202 and upper boundary voltage 204, aCAM unit 100 returns a match for the analog input voltage signal (V(x)). When the analog input voltage signal (V(x)) exceeds the voltage range defined by the lower boundary voltage 202 and upper boundary voltage 204, aCAM unit 100 returns a mismatch. As described above, the conductances of memristors M1 and M2 can be programmed separately to set / define the lower boundary voltage 202 and upper boundary voltage 204.

[0035] Figure 3An example diagram illustrating how memristors M1 and M2 from aCAM unit 100 are programmed to store an open voltage range for aCAM unit 100 (i.e., the stored voltage range has virtually no boundary at at least one end). As shown, aCAM unit 100 returns a match to the analog input voltage (V(x)) whenever the analog input voltage signal (V(x)) is greater than or equal to the lower boundary voltage 302 set by memristor M1. In other words, aCAM unit 100 returns only a mismatch when the analog input voltage signal (V(x)) is less than the lower boundary voltage 302. As described above, the conductance of memristor M1 can be programmed to set the lower boundary voltage 302.

[0036] here, Figure 3 and Figure 2 The difference lies in the fact that the conductance of memristor M2 is programmed as a "wildcard" value (sometimes called a "don't care" value), which in fact always returns a match to the upper boundary side 120 of aCAM cell 100 (i.e., returns a match to the upper boundary 120 of aCAM cell 100 for any value of the analog input voltage signal (V(x)) that will be received by aCAM cell 100 in practice). Typically, deep conductance states of the memristor can be used as wildcard values, which effectively set open upper and lower boundaries for the aCAM cell. These deep conductance states (e.g., deep low conductance states (DLCS) for lower boundary wildcard values ​​and deep high conductance states (DHCS) for upper boundary wildcard values) will be well beyond the reliable programmed conductance range of the memristor. For example, if the memristor of aCAM unit 100 is programmed in the range [1µS, 100µS], then deep conductance states, such as 0.01µS and 1000µS, can be used to effectively set open lower and upper bounds for wildcard values, respectively, for aCAM unit 100. These deep conductance states are generally difficult to program reliably, so they are reserved for wildcard values ​​where errors in programming, such as 10%, are acceptable. By programming the memristor of aCAM unit 100 to wildcard values / deep conductance states, examples can be set to effectively open deep state and upper voltage boundaries. In other words, because in practice, the input / search voltage values ​​received by the aCAM unit / subcircuit are generally always within the deep state and upper voltage boundaries set by programming the memristor of the aCAM unit / subcircuit to wildcard values, it can generally be said that the programmed wildcard value will always return a match.

[0037] Therefore, in Figure 3In this example, memristor M2 effectively sets an open “upper boundary” for the analog voltage range stored by aCAM unit 100. It should be understood that in other examples, the conductance of memristor M2 can be programmed to set a “real” upper boundary voltage (i.e., an upper boundary voltage that actually defines a “less than or equal to” condition at the upper boundary), and the conductance of memristor M1 can be programmed to actually always return a matching “wildcard” value to the lower boundary side 110 of aCAM unit 100 (i.e., such programming can actually store an open voltage range bounded only at the upper end). Similarly, in some examples, the conductances of both memristors M1 and M2 can be programmed as “wildcard” values ​​such that aCAM unit 100 actually always returns a match (i.e., a match for any value of the analog input voltage signal (V(x)) that aCAM unit 10 will receive in practice).

[0038] As described above, aCAM units can be programmed as wildcard values ​​to represent features that are not evaluated in the root-to-leaf path. Such aCAM units may be referred to as "non-evaluation units" in this paper.

[0039] Figure 4-6 This demonstrates how to represent the example decision tree 402 in aCAM. Combined with... Figure 4-6 The method described can be an example of the traditional method / representation of decision trees in aCAM.

[0040] like Figure 4 As shown, decision tree 402 may include a set of decision nodes, including a root decision node 404, various intermediate decision nodes (e.g., intermediate decision node 406), and various leaf nodes (e.g., leaf node 408) representing the endpoints of decision tree 402. It should be understood that decision tree 402 is merely an illustrative implementation of a decision tree.

[0041] Decision tree 402 may include multiple root-to-leaf paths. Each root-to-leaf path represents a traversal of a series of decision nodes. For example, a root-to-leaf path may begin at the root decision node 404, traverse one or more intermediate decision nodes, and end at a leaf node. Each decision node traversed in a root-to-leaf path may represent an evaluable condition by which features of feature vector 400 can be evaluated. Therefore, a root-to-leaf path represents a series of evaluable conditions that represent logical rules by which feature vector 400 can be evaluated.

[0042] exist Figure 4In the illustrated example root-to-leaf path 410, a sequence of evaluable conditions may start with the condition evaluated at the root decision node 404, which is illustrated as involving feature f1 of feature vector 400. In the example decision tree 402, evaluation of the condition represented by any given decision node can result in one of two possible outcomes, labeled outcome "a" and outcome "b". In some examples, outcome "b" indicates that the condition is not satisfied upon evaluation, and outcome "a" indicates that the condition is satisfied upon evaluation. For example, if the evaluable condition at root node 404 is whether f1 is less than value x1, outcome "b" may indicate a negative determination (i.e., f1≥x1), and outcome "a" may indicate a positive determination (i.e., f1<x1). It should be understood that in other implementations, there may be more than two outcomes for an evaluable condition associated with a decision node.

[0043] In the example root-to-leaf path 410, the determined outcome at the root decision node 404 is illustrated as outcome "b", which indicates that the condition involving feature f1 evaluated at the root decision node 404 is not satisfied. Based on this outcome, the root-to-leaf path 410 transitions from the root decision node 404 to the intermediate decision node 406. A transition from a first decision node to a second decision node within a given root-to-leaf path is represented by the combination of the condition evaluated at the first decision node and the outcome of said evaluation. For example, in the example root-to-leaf path 410, the transition from root decision node 404 to intermediate decision node 406 is represented as f1 condition 1b. Using this convention, the example root-to-leaf path 410 can be represented by the following decision node transitions: f1 condition 1b to f3 condition 1b to f2 condition 2a to class 2. Each other root-to-leaf path in decision tree 402 can similarly be represented as a sequence of decision node transitions, indicating the condition evaluated at each decision node in combination with the outcome of that evaluation.

[0044] In various examples, the information contained in decision tree 402 may be converted into an alternative representation, such as a tabular representation. In particular, each root-to-leaf path in decision tree 402 can be represented as a corresponding column in the tabular representation, referred to herein as a "feature chain", and is shown in Figure 5 . For example, a decision tree can be reformulated for an aCAM implementation by: reformulating the decision tree to represent each root-to-leaf path as a feature chain having a sequence of feature chain nodes; combining a plurality of evaluable conditions involving a single feature of the root-to-leaf path into one feature chain node; adding "wildcard" feature chain nodes to account for features not evaluated in the root-to-leaf path; and rotating (i.e., matrix transforming) the representation and mapping each feature chain to each row in the aCAM such that columns of the aCAM correspond to feature vectors.

[0045] For example, Figure 4The example root-to-leaf path 410 shown can be transformed into feature chain 512. Feature chain nodes in feature chain 512 can correspond to one or more decision node transformations in the corresponding root-to-leaf path 410. More specifically, each feature chain node in feature chain 512 corresponds to a corresponding feature in feature vector 400. Since feature vector 400 is illustrated as including four features (f1, f2, f3, f4), each feature chain associated with decision tree 402 can include four feature chain nodes corresponding to these four features, and leaf nodes representing the leaf nodes of the corresponding root-to-leaf path. It should be understood that feature vector 400 can contain any number of features, in which case the corresponding feature chain can include a corresponding number of feature chain nodes and leaf nodes. In some examples, leaf nodes can also correspond to features that form part of feature vector 400 (e.g., optimization parameters).

[0046] As described above, some root-to-leaf paths may not include evaluable conditions for one or more features. For example, root-to-leaf path 410 does not include evaluable conditions for feature f4. Therefore, “wildcard” feature chain nodes (i.e., feature chain nodes that include wildcard values) may be included to indicate features not involved in any evaluable conditions for a given root-to-leaf path. Feature chain 512 includes such wildcard feature chain nodes for feature f4 because root-to-leaf path 410 (corresponding to feature chain 512) does not include evaluable conditions involving feature f4. This means that any value specified for feature f4 in a search query will result in a match relative to feature f4 when feature chain 512 is evaluated after being encoded into aCAM.

[0047] By converting the representation of the domain logic rule set from decision tree 402 to a tabular representation, decision nodes within a given root-to-leaf path can be merged and / or reordered when determining the sequence of corresponding feature chain nodes representing root-to-leaf paths in the feature chains. For example, in a sequence of decision nodes traversed as part of root-to-leaf path 410, evaluable conditions involving feature f3 occur before evaluable conditions involving feature f2. However, before encoding feature chains 512 in aCAM, the sequence of evaluable conditions represented by root-to-leaf path 410 can be reordered to ensure that the sequence of evaluable conditions in the corresponding feature chains 512 matches the feature sequence in feature vector 400. This reordering can occur as needed for each root-to-leaf path in decision tree 402, as part of converting the root-to-leaf path into a tabular representation.

[0048] For example, each feature chain in the table representation (e.g., each column in the table) can start with a feature chain node representing an evaluable condition relating to feature f1 in the corresponding root-to-leaf path, followed by an evaluable condition relating to feature f2, and so on, until the penultimate feature chain node in the feature chain relates to the last feature f of the feature vector n (e.g., an evaluable condition for feature f4 in feature vector 400), and the last node of the feature chain comprises a suitable leaf node (alternatively, each leaf node may correspond to the last feature f in the feature vector n ).

[0049] In some examples, converting a root-to-leaf path to a corresponding feature chain can comprise merging two or more decision node transitions in the root-to-leaf path into a single feature chain node in the feature chain. For example, consider a root-to-leaf path in decision tree 402 that comprises the following decision node transitions: f1 condition 1a to f4 condition 1b to f1 condition 2a to class 2. Two decision node transitions in this example path occur due to evaluation of conditions relating to feature f1. Accordingly, these two decision node transitions may be merged into a single feature chain node associated with feature f1 in the corresponding feature chain 514 (represented as f1 condition 1a+2a). For example, if f1 condition 1a represents f1>x1, and f1 condition 2a represents f1<x2, then the merged result (i.e., x1<f1<x2) may be represented in the first feature chain node of feature chain 514 (i.e., the feature chain node associated with feature f1). Merging multiple decision node transitions relating to a particular feature variable into a single merged feature chain node for that feature variable can increase memory density and reduce the amount of area required when encoding the set of logical rules represented by decision tree 402 into aCAM.

[0050] Conversion of the example root-to-leaf path involving the above-identified sequence of decision node transitions to feature chain 514 involves all types of data operations described above, specifically: merging decision node transitions (combining f1 condition 1a and f1 condition 2a); reordering decision node transitions (moving f4 condition 1b to a position after the nodes corresponding to features f1, f2 and f3 in node chain 514); and including wildcard feature chain node values for particular features that do not have an evaluable condition in the corresponding root-to-leaf path (i.e., including wildcard feature chain nodes for features f2 and f3 in feature chain 514). In accordance with the method described above, the set of all root-to-leaf paths represented in decision tree 402 may be converted into a corresponding set of feature chains.

[0051] Once the conversion process is complete and a tabular representation of domain logic rules is generated, each feature chain in the tabular representation may be rotated and mapped to Figure 6The corresponding rows of aCAM 616 in the table representation. In some examples, the sequence of feature chains in the table representation can be specified by a convention that defines the order in which decision tree 402 is traversed to cover all root-to-leaf paths represented in decision tree 402. Furthermore, in some examples, the sequence of feature chains in the table representation can be mapped and encoded into rows of aCAM 616 in the same sequence. In other examples, the order of the feature chains can be irrelevant, provided that each root-to-leaf node in decision tree 402 is transformed into a corresponding feature chain, and each feature chain is mapped to and encoded into a corresponding row of aCAM 616.

[0052] like Figure 6 As shown, feature chain 512 can be mapped to a specific row of aCAM 616 (e.g., aCAM row N-1) and encoded in that row. More specifically, each value represented in each feature chain node of feature chain 512 can be stored using one or more corresponding aCAM cells in row N-1. For example, each other feature chain such as feature chain 514 can similarly be mapped to and encoded in the corresponding row of aCAM 616 (not shown).

[0053] In some examples, the values ​​represented in the feature chain nodes of feature chain 512 can actually be a range of values. As previously mentioned, aCAM 616 provides the ability to store and encode such a range of values. The number of aCAM units required to encode the value / range of values ​​corresponding to a specific feature (e.g., feature f1) across all feature chains (i.e., the number of aCAM-unit columns corresponding to feature f1) can depend on the level of precision required to encode such a value / range of values. For categorical variables in feature vector 400 that can only take a finite number of discrete values ​​(e.g., the set of all origin or destination airports), a single column of aCAM units may be sufficient to represent all stored values ​​across the set of domain logical rules for that feature. On the other hand, for features corresponding to numerical variables that can tolerate a large number of possible values ​​(e.g., a continuous range of values), multiple columns of aCAM units may be needed to provide the bit precision required to store these values.

[0054] In some examples, the output parameters of each feature chain (domain logic rule) encoded in aCAM 616 can actually be stored in a separate memory array from aCAM 616. For example, as Figure 4As shown, each leaf node of decision tree 402 represents a classification output that can be stored in random access memory (RAM) 618, separate from aCAM 616 (in some examples, RAM 618 may include resistive random access memory (ReRAM)). This can then allow multiple matches to be returned for a search query. In some examples, the search query may conform to the format of feature vector 400, and a discrete value, a range of values, or a "wildcard" value may be specified for each search variable (i.e., each feature in feature vector 400). The search query can then be searched in parallel against each row in aCAM 616 to determine whether the search query matches any of the values ​​stored in such rows. Each row of aCAM 616 may represent a storage word corresponding to a particular feature chain, and therefore a particular root-to-leaf path in decision tree 402. In some examples, the storage word may only include those values ​​stored in a particular row of aCAM 616. In other examples, the storage word may include the value of a particular aCAM row and the corresponding value (e.g., a classification output value) of the output parameter stored in RAM 618.

[0055] In some examples, the output parameter (e.g., the classification output represented by the leaf nodes of decision tree 402) can be a parameter that the user seeks to optimize. For example, the search query can specify a maximum or minimum allowed value for the optimization parameter, in which case any row in aCAM 616 that matches each constraint and / or flexible parameter value specified in the search query and satisfies the value specified for the optimization parameter can be returned as a matching result. More specifically, the address of any such matching row in aCAM 616 can be returned as a search result. Alternatively, the corresponding value of the optimization parameter stored in RAM 618 (or the memory address in RAM 618 for the corresponding value) can also be returned.

[0056] In other examples, instead of searching for stored rows in aCAM 616 corresponding to output parameter values ​​below or above a specified value as part of the optimization process, the search query can specify values ​​for the output parameters that need to be precisely matched among the values ​​of the output parameters stored in RAM 618. For example, in such an example, a search query can result in a match only if (1) all other search parameter values ​​specified in the search query match the corresponding stored value in a given row of aCAM 616, and (2) the output parameter value specified in the search query matches precisely the value stored in RAM 618 corresponding to that row in aCAM 616. Thus, in such an example, a search query that includes the first four feature chain nodes of feature chain 512 but specifies a search variable value of “Category 3” for the output parameter value will not produce a match at storage word N-1.

[0057] In other examples, search queries can specify exclusion values ​​for output parameters. For instance, a search query can specify "Category 2" as... Figure 4 The excluded values ​​of the output parameters in the table. Such an example search query will then produce matching results for any row in aCAM 616, and therefore, any feature chain in the table representation and the corresponding root-to-leaf path in decision tree 402 will match each other constraint parameter in the search query and correspond to the stored output parameter value instead of "Category 2". This can represent a mechanism for optimizing output parameters by specifying values ​​to exclude from the matches rather than by iteratively adjusting optimization parameters.

[0058] Figures 7A-7C A comparison is shown between the traditional representation of a decision tree in aCAM and the decision tree representation of a tree-based CAM using the techniques of this disclosure. That is, Figure 7A Example decision tree 702 is depicted. Figure 7B An example conventional representation of decision tree 702 in aCAM 716 is depicted. Figure 7C An example representation of decision tree 702 in tree-based CAM 720 is depicted.

[0059] like Figure 7A As shown, the decision tree 702 includes a set of decision nodes, including the root decision node 704, intermediate decision nodes 706a and 706b, and leaf nodes 708a-d.

[0060] Decision tree 702 includes four root-to-leaf paths: a first root-to-leaf path terminating at leaf node 708a; a second root-to-leaf path terminating at leaf node 708b; a third root-to-leaf path terminating at leaf node 708c; and a fourth root-to-leaf path terminating at leaf node 708d. As described above, each root-to-leaf path represents a traversal of a series of decision nodes in decision tree 702 that begins at the root decision node 704, passes through intermediate decision nodes, and ends at a leaf node. Each decision node traversed in a given root-to-leaf path can represent a corresponding evaluable condition relating to the corresponding feature of feature vector 700. Therefore, each root-to-leaf path represents a series of evaluable conditions that represent logical rules by which feature vectors can be evaluated.

[0061] exist Figure 7AIn the example of the first root-to-leaf path (i.e., the root-to-leaf path terminating at leaf node 708a), a series of evaluable conditions begin with an evaluable condition at the root decision node 704, which is illustrated as involving feature f1 of feature vector 700. That is, the evaluable condition compares feature f1 of feature vector 700 with a threshold (T1) to determine whether f1 < (T1). As described, such evaluation may result in two possible outcomes: (a) f1 ≥ (T1), which could indicate that the condition is not satisfied at the time of evaluation; and (b) f1 < (T1), which could indicate that the condition is satisfied at the time of evaluation. In the example of the first root-to-leaf path, the evaluation result at the root decision node 704 is f1 ≥ (T1), meaning that the first root-to-leaf path traverses to the intermediate decision node 706a. At the intermediate decision node 706a, the evaluable condition compares feature f2 of feature vector 700 with a threshold (T2) to determine whether f2 < (T2). As shown in the figure, such evaluation may lead to two possible results: (a) f2 ≥ (T2), which could indicate that the condition is not met during evaluation; and (b) f2 < (T2), which could indicate that the condition is met during evaluation. In the example of the first root-to-leaf path, the evaluation result at the intermediate decision node 706a is f2 ≥ (T2). Therefore, the first root-to-leaf path traverses to the leaf node 708a, which can represent classification L1. Here, other root-to-leaf paths of decision tree 702 can be traversed in the same / similar manner.

[0062] Now for reference Figure 7B , Figure 7B The conventional representation of decision tree 702 in aCAM 716 is depicted. As shown, aCAM 716 comprises four rows: row 716a; row 716b; row 716c; and row 716d. Each row of aCAM 716 comprises three aCAM cells (e.g., aCAM cell 716a(1)) electrically connected along a matching line. Figure 1 Like aCAM cell 100, each aCAM cell of aCAM 716 may include a lower boundary side (e.g., lower boundary side 716(1)(i)) including a first memristor (not depicted) programmed to store a lower boundary threshold, and an upper boundary side (e.g., upper boundary side 716(1)(ii)) including a second memristor (not depicted) programmed to store an upper boundary threshold. In various examples, the aCAM cell of aCAM 716 may include... Figure 1 The aCAM unit 100 has the same / similar structure, although this is not necessary.

[0063] As described above, decision tree 702 can be programmed into rows of aCAM 716 such that each row of aCAM 716 represents a different root-to-leaf path of decision tree 702. Specifically, the first root-to-leaf path of decision tree 702 (i.e., the root-to-leaf path terminating at leaf node 708a) is programmed into row 716a, the second root-to-leaf path of decision tree 702 (i.e., the root-to-leaf path terminating at leaf node 708b) is programmed into row 715b, the third root-to-leaf path of decision tree 702 (i.e., the root-to-leaf path terminating at leaf node 708c) is programmed into row 716c, and the fourth root-to-leaf path of decision tree 702 (i.e., the root-to-leaf path terminating at leaf node 708d) is encoded into row 716d. As shown, the leaf nodes of decision tree 702 can be programmed into rows of ReRAM 718 electrically connected to the matching lines of aCAM 716.

[0064] As described above, by applying a series of analog input voltages along the columns of aCAM 716, an eigenvector can be applied to the root-to-leaf path stored in aCAM 716. For example, a first analog input voltage representing feature f1 of eigenvector 700 can be applied along the leftmost column of aCAM 716, a second analog input voltage representing feature f2 of eigenvector 700 can be applied along the middle column of aCAM 716, and a third analog input voltage representing feature f3 of eigenvector 700 can be applied along the rightmost column of aCAM 716. For example, if row 716a returns a match, it can be indicated that eigenvector 700 matches the first root-to-leaf path represented by row 716a.

[0065] As shown in the figure, aCAM unit 716a (1) can be programmed to represent the first feature chain node of the first root-to-leaf path (corresponding to feature f1 of feature vector 700). That is, the lower boundary side 716a (1) (i) of aCAM unit 716a (1) is programmed to store the threshold (T1), while the upper boundary side 716ma (1) (ii) of aCAM unit 716a is programmed to be a wildcard value (represented by "X"). In this way, aCAM unit 716a (1) has been programmed to store the evaluable condition f1≥(T1), which is consistent with the traversal of the first root-to-leaf path from the root decision node to the intermediate decision node 706a. Taking aCAM unit 716 (d) (1) as a comparative example, the lower boundary side 716d (l) (i) of aCAM unit 716d (1) is programmed to be a wildcard value (represented by "X"), while the upper boundary side 716d (1) (ii) of aCAM unit 716d is programmed to store the threshold (T1). Thus, aCAM unit 716d(1) has been programmed to store the evaluable condition f1<(T1), which is consistent with the traversal of the fourth root-to-leaf path from the root decision node to the intermediate decision node 706b. The other aCAM units of aCAM 716 are programmed in a similar manner, such that the row representation of aCAM 716 is the decision tree 702.

[0066] In combination Figure 7CBefore describing the tree-based CAM 720, some things to note about aCAM 716. For example, the traditional representation of the decision tree 702 in aCAM 716 is very sparse. That is, the representation includes four “non-evaluation units” (i.e., aCAM units where the upper and lower boundary thresholds are programmed as wildcard values) to describe features that are not evaluated for certain root-to-leaf paths. Relatedly, even the aCAM units representing “non-wildcard” feature chain nodes (i.e., feature chain nodes representing evaluable conditions involving features evaluated in a given root-to-leaf path) include memristors programmed as wildcard values. It can also be noted that aCAM units in different rows (representing different root-to-leaf paths) are programmed to store the same threshold. For example, the four aCAM units in the leftmost column of aCAM 716 have been programmed to store thresholds (T1). Similarly, the two aCAM units in the middle column are programmed to store thresholds (T2), and the two sub-aCAM units in the rightmost column are programmed to store thresholds (T3). Therefore, the aCAM 716 utilizes 24 memristors: that is, (two memristors per aCAM cell) x (12 aCAM cells) to represent the decision tree 702, which has 3 thresholds. In contrast (described in more detail below), the tree-based CAM 720 can represent the decision tree 702 using only three memristors. Therefore, compared to existing aCAM circuits used to implement decision trees, the tree-based CAM 720 can be more compact, consume less power during operation (a significant portion of the power consumption during aCAM operation is due to the quiescent current flowing through the memristors during the search operation) and programming (a significant portion of the power consumption of the aCAM circuit is associated with memristor programming and its associated circuitry), and requires less memristor programming time.

[0067] Now for reference Figure 7C , Figure 7C An example tree CAM 720, programmed to represent a decision tree 702, is depicted.

[0068] The tree-based CAM 720 is specifically constructed to implement the decision tree 702 more efficiently, requiring less hardware (i.e., fewer memristors and transistors), less power consumption, and less memristor programming time compared to existing aCAMs (e.g., aCAM 716). The tree-based CAM 720 achieves these optimizations by utilizing shared comparator subcircuits (i.e., shared comparator subcircuits 722, 724, and 726), each storing thresholds shared among evaluable conditions for multiple root-to-leaf paths of the decision tree 702. Thresholds associated with a given shared comparator subcircuit (e.g., shared comparator subcircuit 722) can be evaluated based on features of the feature vector 700 (e.g., feature f1). A given shared comparator subcircuit may consist of only a single memristor programmed to store the threshold. Therefore, the tree-based CAM 720 can represent / implement evaluable conditions (sharing a common threshold and evaluating based on common features of the feature vector 700) across multiple root-to-leaf paths of the decision tree 702 using a single memristor – thereby reducing the number of memristors required to implement the decision tree 702. Relatedly, the tree-based CAM 720 can eliminate / reduce the memristors and other hardware associated with the aforementioned “non-evaluation units” that proliferate in the existing representation of the decision tree in the aCAM (e.g., see...). Figure 7B (Example in [reference]). Therefore, the tree-type CAM 720 requires only three memristors (i.e., one memristor associated with each of its three constituent comparator subcircuits) to implement the decision tree 702. Thus, the tree-type CAM 720 can be more compact, consume less power (a large portion of the power consumption of aCAM circuit is associated with memristor programming and its associated circuitry), and require less memristor programming time compared to existing aCAM circuits used to implement the decision tree 702.

[0069] As shown in the figure, the tree-based CAM 720 includes four matching lines. Each matching line of the tree-based CAM 720 is associated with a separate root-to-leaf path of the decision tree 702. Specifically, matching line 720a is associated with the first root-to-leaf path of the decision tree 702 (i.e., the root-to-leaf path terminating at leaf node 708a), matching line 720b is associated with the second root-to-leaf path of the decision tree 702 (i.e., the root-to-leaf path terminating at leaf node 708b), matching line 720c is associated with the third root-to-leaf path of the decision tree 702 (i.e., the root-to-leaf path terminating at leaf node 708c), and matching line 720d is associated with the fourth root-to-leaf path of the decision tree 702 (i.e., the root-to-leaf path terminating at leaf node 708d). As shown in the figure, the leaf nodes of the decision tree 702 can be programmed into the rows of matching lines of the tree-based CAM 720 via electrical connections to the ReRAM 758. For example, the first row of ReRAM 758 is electrically connected to the output of matching line 720a and stores the leaves of the first root-to-leaf path of decision tree 702. Similarly, the second row of ReRAM 758 is electrically connected to the output of matching line 720b and stores the leaves of the second root-to-leaf path of decision tree 702.

[0070] As shown in the figure, the tree-structured CAM 720 includes three shared comparator subcircuits: (1) shared comparator subcircuit 722; (2) shared comparator subcircuit 724; and (3) shared comparator subcircuit 726. As described above, the shared comparator subcircuits of the tree-structured CAM 720 can operate to: (a) store a boundary voltage threshold based on the programming conductance of its constituent memristors, the boundary voltage threshold being associated with one or more evaluable conditions relating to features of feature vector 700; (b) receive an analog input voltage corresponding to the feature; and (c) output a comparison output voltage, the comparison output voltage including a first voltage when the analog input voltage exceeds the stored boundary voltage threshold and a second voltage when the analog input voltage is less than the stored boundary voltage threshold. For example, the shared comparator subcircuit 722 stores the boundary voltage threshold (T1) based on the programming conductance of its constituent memristors. As described above, the boundary voltage threshold (T1) is evaluated according to feature f1 of feature vector 700 in all four root-to-leaf paths of decision tree 702. Therefore, the shared comparator circuit 722 can receive the analog input voltage corresponding to feature f1 and output a comparison output voltage, which includes a first voltage when the analog input voltage corresponding to feature f1 exceeds the stored boundary voltage threshold (T1) and a second voltage when the analog output voltage corresponding to feature f1 is less than the stored boundary voltage threshold (T1). As shown, the shared comparator circuit 724 stores the boundary voltage threshold (T2) based on the programming conductance of its constituent memristor. As described above, the boundary voltage threshold (T2) is evaluated based on feature f2 of the feature vector 700 in the two root-to-leaf paths of the decision tree 702. Therefore, the shared comparator circuit 724 can receive the analog input voltage corresponding to feature f2 and output a comparison output voltage, which includes a first voltage when the analog input voltage corresponding to feature f2 exceeds the stored boundary voltage threshold (T2) and a second voltage when the analog output voltage corresponding to feature f2 is less than the stored boundary voltage threshold (T2). Similarly, the shared comparator circuit 726 stores the boundary voltage threshold (T3) based on the programming conductance of its constituent memristor. As described above, the boundary voltage threshold (T3) is evaluated based on the feature f3 of the feature vector 700 in the two root-to-leaf paths of the decision tree 702. Therefore, the shared comparator circuit 726 can receive the analog input voltage corresponding to feature f3 and output a comparison output voltage, which includes a first voltage when the analog input voltage corresponding to feature f3 exceeds the storage boundary voltage threshold (T3) and a second voltage when the analog input voltage corresponding to feature f3 is less than the storage boundary voltage threshold (T3).

[0071] As described above, each shared comparator subcircuit of the tree-type CAM 720 may include only a single memristor. In various examples, each shared comparator subcircuit may include the same / similar structure as the voltage divider subcircuit 112 of the aCAM unit 100. For example, the shared comparator subcircuit 722 may include a transistor and a memristor electrically connected in series with each other. The memristor and transistor may define a voltage divider subcircuit. The voltage divider subcircuit may receive an analog input voltage corresponding to feature f1 and output a comparison output voltage, which includes a first voltage when the analog input voltage corresponding to feature f1 exceeds a stored boundary voltage threshold (T1) and a second voltage when the analog output voltage corresponding to feature f1 is less than the stored boundary voltage threshold (T1). For example, when the analog input voltage corresponding to feature f1 is greater than or equal to the boundary voltage threshold (T1), the conductance of the transistor may increase, causing the voltage across the memristor to decrease, resulting in a smaller comparison output voltage. As described in more detail below, the small comparator output voltage may be insufficient to turn on / activate the matching line transistors 730a and 730b electrically connected to the shared comparator subcircuit 722. Therefore, matching line transistors 730a and 730b cannot pull down the voltages of matching lines 720a and 720b, respectively, indicating the matching between feature f1 and the first and second root-to-leaf paths of the decision tree 702 associated with matching lines 720a and 720b. Instead, the small comparator output voltage can be inverted by the voltage inverter 740 before being received by matching line transistors 730c and 730d. Therefore, the inverted comparator output voltage received by matching line transistors 730c and 730d can include a (large) voltage sufficient to turn on / activate matching line transistors 760c and 760d. Therefore, the matching line transistors 730c and 730d can pull down the voltages of matching lines 720c and 720d respectively, indicating the mismatch between feature f1 and the third and fourth root-to-leaf paths of decision tree 702 associated with matching lines 720c and 720d respectively.

[0072] As described above, the tree-type CAM 720 includes eight matching line transistors electrically connected between the respective shared comparator subcircuit and the respective matching line of the tree-type CAM 720: (1) a matching line transistor 730a electrically connected between the shared comparator subcircuit 722 and the matching line 720a; (2) a matching line transistor 730b electrically connected between the shared comparator subcircuit 722 and the matching line 720b; (3) a matching line transistor 730c electrically connected between the shared comparator subcircuit 722 and the matching line 720c; (4) a matching line transistor 730c electrically connected between the shared comparator subcircuit 722 and the matching line 720d. The tree-type CAM 720 also includes three voltage inverters (which may include a matching line transistor 730d electrically connected between certain shared comparator subcircuits 724 and matching line 720a); (5) a matching line transistor 732a electrically connected between shared comparator subcircuits 724 and matching line 720a; (6) a matching line transistor 732b electrically connected between shared comparator subcircuits 724 and matching line 720b; (7) a matching line transistor 734c electrically connected between shared comparator subcircuits 726 and matching line 720c; and (8) a matching line transistor 730d electrically connected between shared comparator subcircuits 726 and matching line 720d. Figure 1 (The same / similar structure as inverter 124): (1) a voltage inverter 740 electrically connected between shared comparator circuit 722 and matching line transistors 730c-d; (2) a voltage inverter 742 electrically connected between shared comparator circuit 724 and matching line transistor 732b; and (3) a voltage inverter 744 electrically connected between shared comparator circuit 726 and matching line transistor 734d.

[0073] Here, the combination of the shared comparator circuit 722 and the matching line transistor 730a can implement the evaluable condition f1 ≥ (T1). Similarly, the combination of the shared comparator circuit 722 and the matching line transistor 730b can also implement the evaluable condition f1 ≥ (T1). Therefore, the boundary voltage threshold (T1) can include a lower boundary threshold for the evaluable condition relating to the feature f1 for the first and second root-to-leaf paths. Conversely, since the voltage inverter 740 is electrically connected between the shared comparator circuit 722 and the matching line transistor 730c, the combination of the shared comparator circuit 722, the voltage inverter 740, and the matching line transistor 730c can implement the evaluable condition f1 < (T1). Similarly, the combination of the shared comparator circuit 722, the voltage inverter 740, and the matching line transistor 730d can also implement the evaluable condition f1 < (T1). Therefore, the boundary voltage threshold (T1) can include an upper boundary threshold for the evaluable condition relating to the feature f1 for the third and fourth root-to-leaf paths. Therefore, a first comparator output voltage (e.g., a low voltage) output from the shared comparator circuit 722 can achieve the matching condition at matching lines 720a and 720b (electrically connected to matching line transistors 730a and 730b, respectively) and the mismatch condition at matching lines 720c and 720d (electrically connected to matching line transistors 730c and 730d, respectively). Conversely, a second comparator output voltage (e.g., a high voltage) output from the shared comparator circuit 722 can achieve the matching condition at matching lines 720c and 720d (electrically connected to matching line transistors 730c and 730d, respectively) and the mismatch condition at matching lines 720a and 720b (electrically connected to matching line transistors 730a and 730b, respectively). Similarly, this logic can be implemented using only a single memristor of the shared comparator circuit 722.

[0074] Based on the above principles, the combination of the shared comparator circuit 724 and the matching line transistor 732a can implement the evaluable condition f2 ≥ (T2). Therefore, the boundary voltage threshold (T2) can include the lower boundary threshold of the evaluable condition relating to feature f2 of the first root-to-leaf path. Conversely, since the voltage inverter 742 is electrically connected between the shared comparator circuit 724 and the matching line transistor 732b, the combination of the shared comparator circuit 724, the voltage inverter 742, and the matching line transistor 732b can implement the evaluable condition f2 < (T2). Therefore, the boundary voltage threshold (T2) can include the upper boundary threshold of the evaluable condition relating to feature f2 of the second root-to-leaf path. It is worth noting that there is no electrically connected matching line transistor between the shared comparator circuit 724 and matching line 720c or matching line 720d. As mentioned above, this is because the third and fourth root-to-leaf paths (associated with matching line 720c and matching line 720d, respectively) do not include the evaluable condition relating to feature f2. Figure 7BIn the traditional representation of decision trees in aCAM, non-evaluation is illustrated using "non-evaluation" cells (typically comprising two memristors and up to six transistors) programmed as wildcard values. However, the tree-based CAM 720 is specifically designed to eliminate these "non-evaluation" cells, achieving a further reduction in memristor hardware and associated circuitry. In other words, if a given root-to-leaf path in the decision tree does not include an evaluable condition involving a feature, the tree-based CAM only excludes the matching line transistors electrically connected between the shared comparator subcircuit associated with that feature and the matching line associated with the given root-to-leaf path.

[0075] Based on the above principles, the combination of the shared comparator circuit 726 and the matching line transistor 734c can implement the evaluable condition f3 ≥ (T3). Therefore, the boundary voltage threshold (T3) can include the lower boundary threshold of the evaluable condition relating to the feature f3 of the third root-to-leaf path. Conversely, since the voltage inverter 744 is electrically connected between the shared comparator circuit 726 and the matching line transistor 734d, the combination of the shared comparator circuit 726, the voltage inverter 744, and the matching line transistor 734d can implement the evaluable condition f3 < (T3). Therefore, the boundary voltage threshold (T3) can include the feature f3 relating to the fourth root-to-leaf path. s The upper boundary threshold of the evaluable condition. There is no electrically connected matching line transistor between the shared comparator subcircuit 726 and matching line 720a or matching line 720b. As mentioned above, this is because the first and second root-to-leaf paths (associated with matching line 720a and matching line 720b, respectively) do not include the evaluable condition involving feature f3.

[0076] Figures 8A-8B Examples of decision tree 802 and example representations of decision trees in tree-type CAM 820 are described respectively, based on examples of the technology disclosed herein.

[0077] Here, decision tree 802 can be an example of an "oblivious tree"—a special type of decision tree where each decision node at a given level performs the same comparison. As shown, tree-based CAM 820 (in combination with ReRAM 858) can implement / represent decision tree 802 in an efficient manner. That is, tree-based CAM 820 can implement decision tree 802 using only two memristors (associated with shared comparator subcircuits 822 and 824, respectively).

[0078] Figure 9 A block diagram of an example computer system 900 is depicted, in which various examples described herein can be implemented.

[0079] Computer system 900 includes a bus 912 or other communication mechanism for communicating information, and one or more hardware processors 904 coupled to the bus 912 for processing information. For example, hardware processor 904 may be one or more general-purpose microprocessors.

[0080] Computer system 900 also includes main memory 906, such as random access memory (RAM), cache, and / or other dynamic storage devices, coupled to bus 912, for storing information and instructions to be executed by processor 904. Main memory 906 can also be used to store temporary variables or other intermediate information during the execution of instructions executed by processor 904. When these instructions are stored in storage media accessible to processor 904, computer system 900 is rendered as a dedicated machine customized to execute the operations specified in the instructions.

[0081] The computer system 900 also includes a read-only memory (ROM) 912 or other static storage device coupled to the bus 912 for storing static information and instructions of the processor 904. A storage device 914, such as a disk, optical disk, or USB thumb drive (flash drive), is provided and coupled to the bus 912 for storing information and instructions.

[0082] Computer system 900 also includes hardware accelerator 908. Hardware accelerator 908 may be configured to execute instructions (i.e., programming or software code) stored in main memory 906, read-only memory (ROM) 912, and / or storage device 914 to encode a set of logical rules embodied in a data structure (e.g., a decision tree) into tree-based CAM array 910. In an example implementation, exemplary hardware accelerator 908 may include multiple integrated circuits, which may in turn include application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other very large-scale integrated circuits (VLSIs). The integrated circuits of exemplary hardware accelerator 908 may be specifically optimized to perform a discrete subset of computer processing operations in an accelerated manner, or to execute a discrete subset of computer-executable instructions. For example, hardware accelerator 908 may be configured or manufactured to implement a set of logical rules embodied in a data structure such as a decision tree on tree-based CAM array 910.

[0083] The tree-type CAM array 910 may include non-volatile memory constructed using techniques such as resistive switched memory (i.e., memristors), phase-change memory, magnetoresistive memory, ferroelectric memory, some other resistive random access memory devices (Re-RAM), or combinations of these techniques. More generally, the tree-type CAM array 910 may be implemented using techniques that allow the tree-type CAM array 910 to retain its contents in the event of power failure or otherwise loss of power. Thus, data in the tree-type CAM array 910 is "retained," and the tree-type CAM array 910 can act as a so-called "non-volatile memory."

[0084] Computer system 900 may be coupled to display 916, such as a liquid crystal display (LCD) (or touchscreen), via bus 912 for displaying information to the computer user. Input device 918, including alphanumeric and other keys, is coupled to bus 912 for communicating information and command selections to processor 904. Another type of user input device is cursor control 920, such as a mouse, trackball, or arrow keys, for communicating directional information and command selections to processor 904 and for controlling cursor movement on display 916. In some embodiments, the same directional information and command selections as cursor control may be implemented via receiving touch on a touchscreen without a cursor.

[0085] The computing system 900 may include a user interface module to implement a GUI, which may be stored as executable software code executed by the computing device in a mass storage device. This module and other modules may include, for example, components such as software components, object-oriented software components, class components and task components, procedures, functions, properties, processes, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

[0086] Generally, the terms “component,” “engine,” “system,” “database,” and “data storage” used in this document can refer to logic embodied in hardware or firmware, or to a set of software instructions written in a programming language (such as, for example, Java, C, or C++) that may have entry and exit points. Software components can be compiled and linked into an executable program, installed in a dynamic link library, or written in an interpreted programming language (such as, for example, BASIC, Perl, or Python). It should be understood that software components can be invoked from other components or themselves, and / or can be invoked in response to detected events or interrupts. Software components configured to execute on a computing device can be provided on computer-readable media, such as optical discs, digital video discs, flash drives, disks, or any other tangible media, or as digital downloads (and can be initially stored in a compressed or installable format that needs to be installed, decompressed, or decrypted before execution). Such software code can be stored, in part or in whole, on a storage device executing the computing device for execution by the computing device. Software instructions can be embedded in firmware, such as EPROM. It will be further understood that hardware components can consist of connected logic units (such as gates and flip-flops), and / or can consist of programmable units (such as programmable gate arrays or processors).

[0087] Computer system 900 may implement the techniques described herein using custom hardwired logic, one or more ASICs or FPGAs, firmware, and / or program logic, which, in combination with the computer system, enable or program the computer system 900 into a dedicated machine. According to one embodiment, the techniques herein are executed by computer system 900 in response to processor 904 executing one or more sequences of one or more instructions contained in main memory 906. Such instructions may be read into main memory 906 from another storage medium, such as storage device 914. Execution of the sequence of instructions contained in main memory 906 causes processor 904 to perform the processing steps described herein. In alternative embodiments, hardwired circuitry may be used instead of or in combination with software instructions.

[0088] As used herein, the term "non-transitory medium" and similar terms refer to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Such non-transitory media can include non-volatile media and / or volatile media. Non-volatile media include, for example, optical discs or disks, such as storage device 914. Volatile media include dynamic memory, such as main memory 906. Common forms of non-transitory media include, for example, floppy disks, hard disks, solid-state drives, magnetic tape or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, PROMs and EPROMs, FLASH-EPROMs, NVRAMs, any other memory chips or cassettes and their network versions.

[0089] Non-transitory media differ from transmission media, but can be used in conjunction with them. Transmission media participate in the transfer of information between non-transitory media. For example, transmission media include coaxial cables, copper wires, and optical fibers, including the conductors that make up bus 912. Transmission media can also take the form of sound waves or light waves, such as those generated during radio wave and infrared data communication.

[0090] Computer system 900 also includes a communication / network interface 922 coupled to bus 912. Network interface 922 provides bidirectional data communication coupled to one or more network links connected to one or more local networks. For example, communication interface 922 may be an Integrated Services Digital Network (ISDN) card, cable modem, satellite modem, or modem to provide data communication connectivity to a corresponding type of telephone line. As another example, network interface 922 may be a Local Area Network (LAN) card to provide data communication connectivity to a LAN-compatible network (or a WAN component communicating with a WAN). Wireless links may also be implemented. In any such implementation, network interface 918 transmits and receives electrical, electromagnetic, or optical indicators carrying streams of digital data representing various types of information.

[0091] Network links typically provide data communication to other data devices over one or more networks. For example, a network link can provide a connection to a host or to a data device operated by an Internet Service Provider (ISP) over a local network. ISPs, in turn, provide data communication services over a global packet data communication network now commonly referred to as the “Internet.” Both local area networks (LANs) and the Internet use electrical, electromagnetic, or optical indicators that carry streams of digital data. Indicators over various networks and on network links, as well as indicators through communication interface 922, are example forms of transmission media that carry digital data to or from computer system 900.

[0092] Computer system 900 can send and receive messages, including program code, via a network, network link, and communication interface 918. In the Internet example, the server can transmit application request code via the Internet, ISP, local network, and communication interface 922.

[0093] The received code may be executed by processor 904 upon receipt and / or stored in storage device 914, or stored in other non-volatile memory for later execution.

[0094] Each process, method, and algorithm described in the preceding sections may be embodied in a code component executed by one or more computer systems or computer processors including computer hardware, and may be fully or partially automated by them. One or more computer systems or computer processors may also operate in a “cloud computing” environment or as “Software as a Service” (SaaS) to support the performance of the associated operations. These processes and algorithms may be implemented, partially or wholly, in application-specific circuitry. The various features and processes described above may be used independently of each other or may be combined in various ways. Different combinations and sub-combinations are intended to fall within the scope of this disclosure, and certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular sequence, and the associated blocks or states may be executed in other suitable sequences, or may be executed in parallel, or may be executed in some other manner. Blocks or states may be added or removed in the disclosed example embodiments. The performance of certain operations or processes may be distributed among computer systems or computer processors, residing not only within a single machine but also deployed across multiple machines.

[0095] As used herein, circuits can be implemented using any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FPGAs, logic components, software routines, or other mechanisms can be implemented to constitute the circuit. In implementations, the various circuits described herein can be implemented as discrete circuits, or the described functions and features can be partially or wholly shared among one or more circuits. Even though various features or functional elements can be described or claimed as separate circuits, these features and functions can be shared among one or more common circuits, and such description should not require or imply the need for separate circuits to implement such features or functions. If the circuit is implemented wholly or partially using software, such software can be implemented to operate with a computing or processing system (such as computer system 900) capable of performing the functions described herein.

[0096] As used herein, the term “or” can be interpreted in an inclusive or exclusive sense. Furthermore, singular descriptions of resources, operations, or structures must not be construed as excluding the plural. Unless otherwise specifically stated or otherwise understood in the context in which they are used, conditional language such as “may,” “may,” or “can” is generally intended to convey that certain embodiments include certain features, elements, and / or steps, while other embodiments do not.

[0097] Unless otherwise expressly stated, the terms and phrases used in this document, and their variations thereof, shall be interpreted as open-ended rather than restrictive. Adjectives such as “routine,” “traditional,” “common,” “standard,” “known,” and similar terms shall not be interpreted as limiting the described items to a given time period or to items available up to a given time, but shall be understood to include standard techniques that are routine, traditional, common, or may be available or known at any time now or in the future. In some cases, the presence of broadening words and phrases such as “one or more,” “at least,” “but not limited to,” or other similar phrases shall not be interpreted as an intention or necessity for a narrower scope where such broadening phrases may not exist.

Claims

1. A circuit comprising: The first matching line is associated with the first root-to-leaf path of the decision tree; The second matching line is associated with the second root-to-leaf path of the decision tree; A shared comparator subcircuit includes memristors selectively connected to the first matching line and the second matching line, wherein the shared comparator subcircuit: The memristor is based on a programmable conductance storage boundary voltage threshold, which is associated with one or more evaluable conditions relating to features of the feature vector. Receive an analog input voltage corresponding to the aforementioned feature. The output is a comparison output voltage, which includes a first voltage when the analog input voltage exceeds a stored boundary voltage threshold and a second voltage when the analog input voltage is less than the stored boundary voltage threshold. A first matching line transistor selectively modifies the voltage of the first matching line based on the comparison output voltage; as well as The second matching line transistor selectively modifies the voltage of the second matching line based on the comparison output voltage. The first matching line transistor is connected between the first matching line and the shared comparator circuit, and the second matching line transistor is connected between the second matching line and the shared comparator circuit.

2. The circuit of claim 1, further comprising a third matching line associated with the third root-to-leaf path of the decision tree, wherein: The first root-to-leaf path includes evaluable conditions relating to the aforementioned features; The second root-to-leaf path includes evaluable conditions relating to the aforementioned features; The third root-to-leaf path does not include evaluable conditions related to the aforementioned feature; as well as Of the first matching line to the third matching line, only the first matching line and the second matching line are electrically connected to the shared comparator circuit.

3. The circuit according to claim 2 further includes: The second shared comparator sub-circuit includes a second memristor, wherein the second shared comparator sub-circuit: The second boundary voltage threshold is stored based on the programmable conductance of the second memristor, and the second boundary voltage threshold is associated with one or more evaluable conditions relating to a second feature of the feature vector. Receive a second analog input voltage corresponding to the second feature. Output a second comparison output voltage, wherein the second comparison input voltage includes a first voltage when the second analog input voltage exceeds a second stored boundary voltage threshold and a second voltage when the second analog input voltage is less than the second stored boundary voltage threshold; A third matching line transistor selectively modifies the voltage of the first matching line based on the second comparison output voltage; as well as A fourth matching line transistor that selectively modifies the voltage of the third matching line based on the second comparison output voltage.

4. The circuit according to claim 3, wherein: The first root-to-leaf path includes evaluable conditions relating to the second feature; and The second root-to-leaf path does not include evaluable conditions relating to the second feature; The third root-to-leaf path includes evaluable conditions relating to the second feature; as well as Of the first matching line to the third matching line, only the first matching line and the third matching line are electrically connected to the second shared comparator circuit.

5. The circuit according to claim 1, wherein: The boundary voltage threshold is associated with a lower boundary threshold of an evaluable condition relating to the characteristics of the first root-to-leaf path; and The boundary voltage threshold is associated with the upper boundary threshold of the evaluable condition relating to the feature of the second root-to-leaf path.

6. The circuit of claim 5 further includes a voltage inverter electrically connected between the shared comparator sub-circuit and the second matching line transistor, wherein, The voltage inverter reverses the comparison output voltage, causing the second matching line transistor to receive the reversed comparison output voltage.

7. The circuit of claim 1 further includes a resistive random access memory (ReRAM) for storing the leaves of the decision tree.

8. The circuit according to claim 7, wherein: The first row of the ReRAM is electrically connected to the output of the first matching line and stores the leaves of the first root-to-leaf path; and The second row of the ReRAM is electrically connected to the output of the second matching line and stores the leaves of the second root-to-leaf path.

9. A circuit comprising: The first matching line is associated with the first root-to-leaf path of the decision tree; The second matching line is associated with the second root-to-leaf path of the decision tree; A shared comparator subcircuit includes memristors selectively connected to the first matching line and the second matching line, wherein the shared comparator subcircuit: The memristor is based on a programmable conductance storage boundary voltage threshold, which is associated with one or more evaluable conditions relating to features of the feature vector. Receive an analog input voltage corresponding to the aforementioned feature. The output is a comparison output voltage, which includes a first voltage when the analog input voltage exceeds a stored boundary voltage threshold and a second voltage when the analog input voltage is less than the stored boundary voltage threshold. A first matching line transistor selectively modifies the voltage of the first matching line based on the comparison output voltage; A voltage inverter is electrically connected between the shared comparator circuit and the second matching line transistor, wherein the voltage inverter reverses the comparator output voltage; as well as The second matching line transistor selectively modifies the voltage of the second matching line based on the inverted comparison output voltage. The first matching line transistor is connected between the first matching line and the shared comparator circuit, and the second matching line transistor is connected between the second matching line and the shared comparator circuit.

10. The circuit according to claim 9, wherein: The boundary voltage threshold is associated with a lower boundary threshold of an evaluable condition relating to the characteristics of the first root-to-leaf path; and The boundary voltage threshold is associated with the upper boundary threshold of the evaluable condition relating to the feature of the second root-to-leaf path.

11. The circuit of claim 9, further comprising a third matching line associated with the third root-to-leaf path of the decision tree, wherein: The first root-to-leaf path includes evaluable conditions relating to the aforementioned features; The second root-to-leaf path includes evaluable conditions relating to the aforementioned features; The third root-to-leaf path does not include evaluable conditions related to the aforementioned feature; as well as Of the first matching line to the third matching line, only the first matching line and the second matching line are electrically connected to the shared comparator circuit.

12. The circuit according to claim 11, further comprising: The second shared comparator sub-circuit includes a second memristor, wherein the second shared comparator sub-circuit: The second boundary voltage threshold is stored based on the programmable conductance of the second memristor, and the second boundary voltage threshold is associated with one or more evaluable conditions relating to a second feature of the feature vector. Receive a second analog input voltage corresponding to the second feature. Output a second comparison output voltage, wherein the second comparison input voltage includes a first voltage when the second analog input voltage exceeds a second stored boundary voltage threshold and a second voltage when the second analog input voltage is less than the second stored boundary voltage threshold; A third matching line transistor selectively modifies the voltage of the first matching line based on the second comparison output voltage; as well as A fourth matching line transistor that selectively modifies the voltage of the third matching line based on the second comparison output voltage.

13. The circuit according to claim 12, wherein: The first root-to-leaf path includes evaluable conditions relating to the second feature; and The second root-to-leaf path does not include evaluable conditions relating to the second feature; The third root-to-leaf path includes evaluable conditions relating to the second feature; as well as Of the first matching line to the third matching line, only the first matching line and the third matching line are electrically connected to the second shared comparator circuit.

14. The circuit of claim 9, further comprising a resistive random access memory (ReRAM) storing the leaves of the decision tree, wherein: The first row of the ReRAM is electrically connected to the output of the first matching line and stores the leaves of the first root-to-leaf path; and The second row of the ReRAM is electrically connected to the output of the second matching line and stores the leaves of the second root-to-leaf path.

15. A circuit comprising: The first matching line is associated with the first root-to-leaf path of the decision tree; The second matching line is associated with the second root-to-leaf path of the decision tree; The third matching line is associated with the third root-to-leaf path of the decision tree; A shared comparator subcircuit includes memristors selectively connected to the first matching line and the second matching line, wherein the shared comparator subcircuit: The memristor is based on a programmable conductance storage boundary voltage threshold, which is associated with one or more evaluable conditions relating to features of the feature vector. Receive an analog input voltage corresponding to the aforementioned feature. The output is a comparison output voltage, which includes a first voltage when the analog input voltage exceeds a stored boundary voltage threshold and a second voltage when the analog input voltage is less than the stored boundary voltage threshold. A first matching line transistor selectively modifies the voltage of the first matching line based on the comparison output voltage; as well as A second matching line transistor selectively modifies the voltage of the second matching line based on the comparison output voltage; in: The first root-to-leaf path includes evaluable conditions relating to the aforementioned features; The second root-to-leaf path includes evaluable conditions relating to the aforementioned features; The third root-to-leaf path does not include evaluable conditions related to the aforementioned feature; Of the first to the third matching lines, only the first and second matching lines are electrically connected to the shared comparator circuit; and The first matching line transistor is connected between the first matching line and the shared comparator circuit, and the second matching line transistor is connected between the second matching line and the shared comparator circuit.

16. The circuit according to claim 15, further comprising: The second shared comparator sub-circuit includes a second memristor, wherein the second shared comparator sub-circuit: The second boundary voltage threshold is stored based on the programmable conductance of the second memristor, and the second boundary voltage threshold is associated with one or more evaluable conditions relating to a second feature of the feature vector. Receive a second analog input voltage corresponding to the second feature. Output a second comparison output voltage, wherein the second comparison input voltage includes a first voltage when the second analog input voltage exceeds a second stored boundary voltage threshold and a second voltage when the second analog input voltage is less than the second stored boundary voltage threshold; A third matching line transistor selectively modifies the voltage of the first matching line based on the second comparison output voltage; as well as A fourth matching line transistor that selectively modifies the voltage of the third matching line based on the second comparison output voltage.

17. The circuit according to claim 16, wherein: The first root-to-leaf path includes evaluable conditions relating to the second feature; and The second root-to-leaf path does not include evaluable conditions relating to the second feature; The third root-to-leaf path includes evaluable conditions relating to the second feature; as well as Of the first matching line to the third matching line, only the first matching line and the third matching line are electrically connected to the second shared comparator circuit.

18. The circuit according to claim 15, wherein: The boundary voltage threshold is associated with a lower boundary threshold of an evaluable condition relating to the characteristics of the first root-to-leaf path; and The boundary voltage threshold is associated with the upper boundary threshold of the evaluable condition relating to the feature of the second root-to-leaf path.

19. The circuit of claim 18, further comprising a voltage inverter electrically connected between the shared comparator sub-circuit and the second matching line transistor, wherein, The voltage inverter reverses the comparison output voltage, causing the second matching line transistor to receive the reversed comparison output voltage.

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