A thermionic transistor with high injection energy and a method of making the same

Abstract

The application discloses a hot electron transistor with high injection energy and a preparation method thereof. The hot electron transistor comprises a substrate, an epitaxial structure and a metal electrode. The epitaxial structure comprises, from bottom to top, a buffer layer, an n+ GaN collector ohmic contact layer, a UID-GaN collector layer, a first AlGaN collector barrier layer, a second AlGaN collector barrier layer, an n-type GaN-based region layer, a ScAlN tunnel barrier layer, an AlGaN emitter barrier layer and a GaN emitter cap layer. The collector is stacked on the n+ GaN collector ohmic contact layer. The base is stacked on the ScAlN tunnel barrier layer. The emitter is stacked on the GaN emitter cap layer. The application improves the emitter injection electron energy by designing an emitter-base barrier, reduces the low-energy electron leakage from the emitter to the base, reduces the base region relaxation electron proportion, improves the collector collection efficiency, and improves the current density and current gain of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a hot electron transistor with high injection energy and its fabrication method. Background Technology

[0002] In recent years, gallium nitride (GaN), a third-generation semiconductor material, has attracted widespread attention worldwide due to its advantages such as large bandgap, high breakdown voltage, high electron mobility, and high thermal conductivity. Compared to Si-based and GaAs-based microwave devices, GaN-based HEMT (High Electron Mobility Transistor) devices have higher power density and efficiency, thus exhibiting significant advantages in communication base stations, radar, satellite communications, and electronic warfare. A key goal of GaN microwave power device research is to continuously increase the cutoff frequency of the devices, enabling them to demonstrate their high power and high efficiency advantages at higher frequency bands. GaN HEMT devices mainly reduce transit delay by shrinking the gate length, thereby achieving higher cutoff frequencies. Currently, the GaN HEMT device with the highest cutoff frequency internationally is the AlN / GaN HEMT device with a gate length of 20nm developed by HRL (Hughes Research Laboratory) in the United States, with a cutoff frequency f0. T The maximum oscillation frequency is 454 GHz. max The GHz clock speed is 444 GHz. However, when the gate length is reduced to less than 100 nm, the device encounters severe short-channel effects. The smaller the gate length, the more severe the short-channel effect. Furthermore, limitations in photolithography processes restrict the gate length L... g Further miniaturization faces significant challenges. Under the constraints mentioned above, continuously increasing the cutoff frequency of GaN HEMT devices becomes extremely difficult.

[0003] With the miniaturization and frequency increase of GaN HEMT devices facing significant challenges, and given that the electrical characteristics of p-type GaN are insufficient to meet the requirements for developing high-frequency GaN heterojunction bipolar transistors, there has been considerable interest in GaN HET devices. Theoretically, GaN HET devices can not only overcome the bottleneck in frequency increase of GaN HEMT devices but also offer advantages such as high collector current and high breakdown voltage.

[0004] A HET (hot electron transistor) device is a unipolar semiconductor device with a quasi-vertical structure. Its working principle involves injecting electrons into the n-type doped base region through the emitter (E) barrier. The injected electrons travel through the base region (B) via quasi-ballistic transport and are finally collected through the collector (C) barrier. Figure 1The advantage of HET devices in achieving ultra-high frequencies lies in the significant shift (band order) in the valence band of the heterojunction, which increases the velocity of vertically transported electrons. The near-ballistic transport of charge carriers is achieved by utilizing the base thickness, which is smaller than the electron mean free path. Because the time for hot electrons to transit the base region from the emitter to the collector is extremely short, high f-frequency characteristics can be achieved. T and f max .

[0005] The hot electron transistor (HET) was first proposed in 1961 by a laboratory at Caltech. It consisted of a metal-oxide-metal-oxide-metal (MOMOM) transistor and was implemented using tunneling injection. However, due to the limitations of the technology at the time, achieving a thin metal layer was very difficult, and ballistic transport in the base region was not possible, resulting in poor current gain. Subsequently, Geppert et al. proposed using hot injection to inject electrons into the base region, fabricating a semiconductor-metal-semiconductor (SMS) transistor. However, due to the small mean free path of electrons in the metal base, hot electrons were subject to significant scattering as they passed through the base, resulting in low current gain. Later, Levi et al. first reported a hot electron transistor achievable at room temperature, using the wide-bandgap semiconductor AlSb. 0.92 As 0.08 InAs serves as the emitter barrier, GaSb serves as the collector barrier, but hot electrons are subjected to strong quantum reflection when passing through the base to reach the collector barrier, resulting in a current gain of less than 0.5.

[0006] G. Gupta et al. compared the effects of collector barriers formed by AlGaN layers with a 30% (mass percentage) Al composition and InGaN layers with a 10% (mass percentage) In composition on forward bias current and low reverse leakage current, and discussed the influence of spiral dislocation density of epitaxial structures on leakage current on different substrates. Subsequently, based on this, they used Al... 0.45 Ga 0.55 N serves as the emitter barrier, with In 0.1 Ga 0.9 Using an N-dipole layer as the collector barrier and a 10nm GaN base layer, a low base sheet resistance of 1000Ω / sq was achieved, and the common-emitter current gain of this device was 0.45. (The rest of the text is missing.) Figure 2 As shown, by improving the emitter barrier structure and using AlN as the emitter barrier tunneling layer, the electron energy distribution will approach the gradation energy level of the emitter, thereby generating a quasi-monoenergetic electron beam, reducing the number of electrons relaxing in the base region, and achieving higher collection efficiency. Simultaneously, the base region thickness is reduced to 7 nm, and the current gain measured under common-emitter operation is 1.1. One problem with this approach is that the reduced base region thickness leads to an increase in the sheet resistance of the base region and an increase in the difficulty of etching the base region, resulting in problems such as under-etching or excessive etching depth.

[0007] Zhichao Yang et al. designed a hot electron transistor using 1nm GaN and 3nm AlN materials as emitter materials and 8nm n-type doped gallium nitride as the base, achieving a collector current density of 50kA / cm². 2 The small-signal current gain was 5, and the DC current gain was 1.3. Subsequently, attempts were made to improve the emitter material, replacing 1nm GaN with 111nm UID-GaN (intrinsic gallium nitride), utilizing the higher polarization intensity of AlN to improve the conduction band of GaN, such as... Figure 3 As shown, this method is used to increase the electron energy injected into the emitter, ultimately resulting in a GaN HET device with a common-emitter current gain of 14.5, demonstrating the potential of GaN HET devices to achieve high-frequency characteristics.

[0008] Riccardo Soligo et al. investigated Monte Carlo simulations of HET devices. They discussed the effects of the GaN thickness in the base region and the InGaN thickness at the collector barrier on the current transfer ratio, and calculated the device cutoff frequency using the short-circuit current gain. For a 12nm base gallium nitride HET, the corresponding fi... T Up to 120 GHz. By simulating the hot electron injection energy and momentum distribution in the base region under different Al compositions and thicknesses of the emitter barrier, the electron dynamics characteristics of the peak-valley electron ratio after injected electrons tunnel through the AlN layer, as well as the base region scattering and collector barrier quantum scattering, were investigated. Finally, the optimal barrier structure was obtained, with a current gain of 3 and a current density of 5 × 10⁻⁶. 5 A / cm 2 The measured f T It is approximately 270 GHz.

[0009] In the closest existing technology, based on HET devices using UID-GaN / AlN as the emitter material, by designing UID-GaN to bring in hot electrons with higher injection energy, and utilizing ultrathin barrier AlN to achieve tunneling, a tunneling hot electron transistor can be obtained, thereby increasing the energy of tunneling electrons and improving the current gain of the device. Figure 4 The material parameters of this HET device are shown in the table. However, the base region lateral resistance of this HET device is very large, and the DC gain effect is not ideal. Therefore, the polarization effect of the ultrathin AlN tunneling layer alone is not enough. It is also necessary to further improve the conduction band of the emitter and the energy of the injected electrons, reduce the leakage of low-energy electrons from the emitter to the base, and improve the collector collection efficiency, thereby improving the current density and current gain of the HET device. Summary of the Invention

[0010] To address the aforementioned problems in the prior art, this invention provides a hot electronic transistor with high injection energy and a method for its fabrication.

[0011] The technical problem to be solved by this invention is achieved through the following technical solution:

[0012] A hot electronic transistor with high injection energy includes: a substrate, an epitaxial structure, a base, an emitter, and a collector;

[0013] The epitaxial structure is located on the substrate, and its surrounding area is the device electrical isolation region of the hot electronic transistor; the epitaxial structure includes, from bottom to top, a buffer layer, an n+GaN collector ohmic contact layer, a UID-GaN collector layer, a first AlGaN collector barrier layer, a second AlGaN collector barrier layer, an n-type GaN base layer, a ScAlN tunneling barrier layer, an AlGaN emitter barrier layer, and a GaN emitter cap layer;

[0014] The collector is stacked on the n+GaN collector ohmic contact layer and isolated from the UID-GaN collector layer; the base is stacked on the ScAlN tunneling barrier layer and isolated from the AlGaN emitter barrier layer; the emitter is stacked on the GaN emitter cap layer.

[0015] Optionally, the buffer layer is a GaN buffer layer with a thickness of 300nm to 500nm.

[0016] Optionally, the n+GaN collector ohmic contact layer is made of Si-doped GaN, wherein the Si doping concentration is 5 × 10⁻⁶. -8 cm -3 ~1×10 19 cm -3 The thickness of the n+GaN collector ohmic contact layer is 70nm to 200nm.

[0017] Optionally, the UID-GaN collector layer is made of intrinsic GaN and has a thickness of 20nm to 60nm.

[0018] Optionally, the first AlGaN collector barrier layer is made of Al 0.2 Ga 0.8 N, with a thickness of 15nm to 30nm;

[0019] In the second AlGaN collector barrier layer, the mass percentage of Al component gradually changes from 20% to 15% from bottom to top, and the mass percentage of Ga component gradually changes from 80% to 85% from bottom to top; the thickness of the second AlGaN collector barrier layer is 8nm to 20nm.

[0020] Optionally, the n-type GaN base layer is made of Si-doped GaN, wherein the Si doping concentration is 1×10⁻⁶. 19 cm -3The thickness of the n-type GaN base layer is 5 nm to 8 nm.

[0021] Optionally, the material of the ScAlN tunneling barrier layer is Sc 0.18 Al 0.82 N, with a thickness of 2nm to 6nm.

[0022] Optionally, the material of the AlGaN emitter barrier layer is Al 0.2 Ga 0.8 N, with a thickness of 30nm to 40nm.

[0023] Optionally, the GaN emitter cap layer is made of Si-doped n+GaN, wherein the Si doping concentration is 5 × 10⁻⁶. - 8 cm -3 ~1×10 19 cm -3 The thickness of the GaN emitter cap layer is 10 nm to 40 nm.

[0024] The present invention also provides a method for fabricating a hot electron transistor with high injection energy, comprising:

[0025] Step 1: On the substrate, a buffer layer, an n+GaN collector ohmic contact layer, a UID-GaN collector layer, a first AlGaN collector barrier layer, a second AlGaN collector barrier layer, an n-type GaN base region layer, a ScAlN tunneling barrier layer, an AlGaN emitter barrier layer, and a GaN emitter cap layer are epitaxially grown sequentially to form the initial epitaxial structure.

[0026] Step 2: Etch the epitaxial structure to prepare the device's electrically isolated region;

[0027] Step 3: Define a first region on the surface of the GaN emitter cap layer. Starting from the first region, use Cl-based plasma to etch downwards until the ScAlN tunneling barrier layer directly below the first region is exposed. During the etching process, ScCl3 generated by the reaction of Sc and Cl achieves self-terminating etching on the surface of the ScAlN tunneling barrier layer.

[0028] Step 4: Define a second region on the surface of the ScAlN tunneling barrier layer exposed in Step 3. Etch downwards from the second region until the n+GaN collector ohmic contact layer directly below the second region is exposed.

[0029] Step 5: Fabricate the base on the ScAlN tunneling barrier layer exposed in Step 3, fabricate the collector on the n+GaN collector ohmic contact layer exposed in Step 4, and fabricate the emitter on the GaN emitter cap layer; wherein the base is isolated from the AlGaN emitter barrier layer, and the collector is isolated from the UID-GaN collector layer.

[0030] The hot electron transistor with high injection energy provided by the present invention includes an epitaxial structure comprising, from bottom to top, a buffer layer, an n+GaN collector ohmic contact layer, a UID-GaN collector layer, a first AlGaN collector barrier layer, a second AlGaN collector barrier layer, an n-type GaN base region layer, a ScAlN tunneling barrier layer, an AlGaN emitter barrier layer, and a GaN emitter cap layer. The AlGaN / ScAlN composite emitter barrier consists of a ScAlN tunneling barrier layer and an AlGaN emitter barrier layer. The AlGaN emitter barrier layer raises the emitter bandgap, preventing low-energy electron injection. Under emitter-base forward bias, electrons gain greater injection energy. After tunneling, due to their higher energy, even with partial scattering from the base region, electrons can still be collected by the collector through the base region. ScAlN (with a wurtzite crystal structure) is an ultrawide bandgap metal nitride. Due to its large bandgap, it acts as a tunneling layer, making the incident electron direction more perpendicular, thereby reducing the number of electrons relaxing in the base region and simultaneously blocking low-energy electrons, raising the emitter bandgap and increasing the injected electron energy. Furthermore, ScAlN exhibits significantly enhanced polarization characteristics, with a piezoelectric modulus di. 33 It is 5 times that of AlN, and its spontaneous polarization intensity is 3 times that of AlN. As a result, the emitter-base heterojunction (ScAlN / GaN) in the hot electron transistor can generate a high 2DEG (two-dimensional electron gas) density, which is beneficial to reducing the base resistance.

[0031] In the fabrication method of the hot electron transistor with high injection energy provided by this invention, during the etching of the GaN emitter cap layer and AlGaN emitter barrier layer using Cl-based plasma, a self-terminating etching process based on Cl can be achieved due to the significant difference in etching reaction rates between ScAlN and AlGaN. Specifically, the GaN emitter cap layer and AlGaN emitter barrier layer are first completely etched away using Cl-based plasma. The exposed ScAlN reacts with the Cl-based plasma to generate ScCl3, which has low volatility. This causes the etching byproducts to adhere to the surface, hindering further etching. Consequently, the etching reaction terminates at the ScAlN tunneling barrier layer, achieving a high etching selectivity between the AlGaN emitter barrier layer and the ScAlN tunneling barrier layer. This solves the problem of excessive base resistance caused by over-etching or insufficient etching depth in the base region.

[0032] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the working principle of a thermionic transistor;

[0034] Figure 2 This is a schematic diagram of a hot-electron transistor designed by G. Gupta et al., which uses an AlN emitter barrier and a 7nm GaN base region.

[0035] Figure 3 This is a schematic diagram of the structure of the polarization engineering barrier hot electron transistor designed by Zhichao Yang et al.

[0036] Figure 4 This is a material parameter table for a tunneling hot electron transistor that uses UID-GaN / AlN as the emitter material and utilizes ultrathin barrier AlN to achieve tunneling in the existing technology.

[0037] Figure 5 This is a schematic diagram of a hot electronic transistor with high injection energy provided in an embodiment of the present invention;

[0038] Figure 6 This is a flowchart of a method for fabricating a hot electron transistor with high injection energy according to an embodiment of the present invention;

[0039] Figure 7 yes Figure 6 A schematic diagram of the method for preparing the initial epitaxial structure is shown.

[0040] Figure 8 yes Figure 6 The diagram illustrates the process of fabricating an epitaxial structure using micro / nano fabrication and depositing a metal electrode. Detailed Implementation

[0041] In existing HET devices, current gain and current density remain low, failing to meet the requirements for ultra-high frequency applications. This invention improves the current density and current gain of the HET device by designing an emitter-base barrier, increasing the energy of electrons injected from the emitter, reducing low-energy electron leakage from the emitter to the base, decreasing the proportion of relaxed electrons in the base region, and improving the collector collection efficiency. The following is a detailed description of the high-injection-energy thermionic transistor provided by this invention.

[0042] The hot electronic transistor with high injection energy provided in this embodiment of the invention includes: a substrate, an epitaxial structure, a base, an emitter, and a collector. Here, base, emitter, and collector are used to refer to the metal electrodes of the base, emitter, and collector.

[0043] The substrate can be a Si, SiC, or sapphire substrate, but is not limited to these.

[0044] like Figure 5 As shown, the epitaxial structure is located on the substrate, and its surrounding area is the device electrical isolation region of the hot electron transistor. This epitaxial structure can be grown on the substrate using the MBE (molecular beam epitaxy) process.

[0045] See Figure 5 The epitaxial structure includes, from bottom to top, a buffer layer, an n+GaN collector ohmic contact layer, a UID-GaN collector layer, a first AlGaN collector barrier layer, a second AlGaN collector barrier layer, an n-type GaN base layer, a ScAlN tunneling barrier layer, an AlGaN emitter barrier layer, and a GaN emitter cap layer.

[0046] The buffer layer can be a GaN buffer layer, which is a single-crystal GaN thin film with a thickness preferably of 300 nm to 500 nm. Alternatively, the buffer layer can also be an AlN nucleation layer.

[0047] In this embodiment of the invention, homogeneous gallium nitride is not used as the substrate for growing epitaxial structures. Instead, a buffer layer is grown on a Si, SiC, or sapphire substrate as the substrate for subsequent epitaxial growth. This is done because although homogeneous epitaxial materials have higher quality, there may be leakage in the cross-platform isolation area for the substrate of vertical devices such as HET devices.

[0048] In this embodiment of the invention, the n+GaN collector ohmic contact layer is made of Si-doped GaN, wherein the Si doping concentration is 5 × 10⁻⁶. -8 cm -3 ~1×10 19 cm -3 The thickness of the n+GaN collector ohmic contact layer is preferably 70 nm to 200 nm. The function of the n+GaN collector ohmic contact layer is to cooperate with the metal electrode to form a collector ohmic contact. Generally, it is considered to be heavily doped and have a large thickness.

[0049] In this embodiment of the invention, the UID-GaN collector layer is made of intrinsic GaN, and its thickness is preferably 20 nm to 60 nm. The function of this UID-GaN collector layer is to reduce the collector junction capacitance.

[0050] In this embodiment of the invention, the first AlGaN collector barrier layer is made of Al 0.2 Ga 0.8N, the thickness of which is preferably 15nm to 30nm; in the second AlGaN collector barrier layer, the mass percentage of Al component gradually changes from 20% to 15% from bottom to top, and the mass percentage of Ga component gradually changes from 80% to 85% from bottom to top; the thickness of the second AlGaN collector barrier layer is 8nm to 20nm.

[0051] In this embodiment of the invention, the second AlGaN collector barrier layer, the first AlGaN collector barrier layer, and the UID-GaN collector layer constitute a barrier layer, which serves to reduce collector leakage. Compared to a traditional single AlGaN layer, it can effectively reduce collector leakage. The gradient Al composition of the second AlGaN collector barrier layer helps reduce quantum reflection caused by the sharp barrier. A higher barrier in this second AlGaN collector barrier layer can reduce leakage current, but it should not be too high, otherwise it will block some high-energy electrons in the base region. Therefore, the low leakage of this two AlGaN collector barrier layer can be achieved by appropriately increasing its thickness, or by designing a more complex electrostatic barrier.

[0052] In this embodiment of the invention, the n-type GaN base layer is made of Si-doped GaN, wherein the Si doping concentration is 1×10⁻⁶. 19 cm -3 The thickness of the n-type GaN-based layer is preferably 5 nm to 8 nm.

[0053] In this embodiment of the invention, the material of the ScAlN tunneling barrier layer is Sc 0.18 Al 0.82 N, with a thickness preferably between 2 nm and 6 nm. This ScAlN tunneling barrier layer, in conjunction with a metal electrode, forms a base ohmic contact, which allows injected electrons to tunnel more perpendicularly, thereby reducing the number of electrons relaxing in the base region. At the same time, it blocks low-energy electrons and raises the emitter band to increase the energy of the injected electrons.

[0054] In this embodiment of the invention, the material of the AlGaN emitter barrier layer is Al 0.2 Ga 0.8 The AlGaN emitter barrier layer, with a thickness preferably between 30 nm and 40 nm, raises the emitter band height, making it significantly higher than the collector barrier band, thus preventing low-energy electron injection. Its thickness and band height determine the energy of the injected electrons. Considering that the AlGaN emitter barrier layer is limited by a critical thickness, AlGaN materials with graded Al compositions can be considered.

[0055] In this embodiment of the invention, the GaN emitter cap layer is made of Si-doped n+GaN, wherein the Si doping concentration is 5 × 10⁻⁶. -8 cm -3 ~1×10 19 cm -3The thickness of the GaN emitter cap layer is preferably 10 nm to 40 nm. The function of the GaN emitter cap layer is to form an emitter ohmic contact with the metal electrode, and at the same time, to introduce base charge under EB bias, thereby reducing the base resistance.

[0056] See also Figure 5 The collector (metal electrode) is stacked on the n+GaN collector ohmic contact layer and isolated from the UID-GaN collector layer; the base (metal electrode) is stacked on the ScAlN tunneling barrier layer and isolated from the AlGaN emitter barrier layer; the emitter (metal electrode) is stacked on the GaN emitter cap layer. The base (metal electrode), collector (metal electrode), and emitter (metal electrode) can all be Al / Au stacks, but are not limited to these.

[0057] The hot electron transistor with high injection energy provided in this embodiment of the invention includes an epitaxial structure comprising, from bottom to top, a buffer layer, an n+GaN collector ohmic contact layer, a UID-GaN collector layer, a first AlGaN collector barrier layer, a second AlGaN collector barrier layer, an n-type GaN base region layer, a ScAlN tunneling barrier layer, an AlGaN emitter barrier layer, and a GaN emitter cap layer. The AlGaN / ScAlN composite emitter barrier consists of a ScAlN tunneling barrier layer and an AlGaN emitter barrier layer. The AlGaN emitter barrier layer raises the emitter bandgap, preventing low-energy electron injection. Under emitter-base forward bias, electrons gain greater injection energy. After tunneling, due to their higher energy, even with partial scattering from the base region, electrons can still be collected by the collector through the base region. ScAlN (with a wurtzite crystal structure) is an ultrawide bandgap metal nitride. Due to its large bandgap, it acts as a tunneling layer, making the incident electron direction more perpendicular, thereby reducing the number of electrons relaxing in the base region and simultaneously blocking low-energy electrons, raising the emitter bandgap and increasing the injected electron energy. Furthermore, ScAlN exhibits significantly enhanced polarization characteristics, with a piezoelectric modulus di. 33 It is 5 times that of AlN, and its spontaneous polarization intensity is 3 times that of AlN. As a result, the emitter-base heterojunction (ScAlN / GaN) in the hot electron transistor can generate a high 2DEG (two-dimensional electron gas) density, which is beneficial to reducing the base resistance.

[0058] Based on the aforementioned hot electron transistor with high injection energy, embodiments of the present invention also provide a method for its fabrication, see [link to documentation]. Figure 6 and Figure 7 The preparation method includes the following steps:

[0059] Step 1: On the substrate, a buffer layer, an n+GaN collector ohmic contact layer, a UID-GaN collector layer, a first AlGaN collector barrier layer, a second AlGaN collector barrier layer, an n-type GaN base region layer, a ScAlN tunneling barrier layer, an AlGaN emitter barrier layer, and a GaN emitter cap layer are epitaxially grown sequentially to form the initial epitaxial structure.

[0060] Specifically, the substrate is first pretreated, including: immersing the substrate sequentially in acetone, isopropanol, and deionized water, ultrasonically cleaning for 3 minutes, then treating with a 15%–40% hydrochloric acid solution for 5 minutes, rinsing with deionized water, and drying with a nitrogen gun. The substrate is then placed in a plasma-enhanced molecular beam epitaxy (PBE) apparatus and annealed at 800°C–1000°C for 10–30 minutes.

[0061] Next, using the MBE process, a buffer layer, an n+ GaN collector ohmic contact layer, a UID-GaN collector layer, a first AlGaN collector barrier layer, a second AlGaN collector barrier layer, an n-type GaN base layer, a ScAlN tunneling barrier layer, an AlGaN emitter barrier layer, and a GaN emitter cap layer are sequentially grown on the substrate. The specific epitaxial growth process is illustrated below with an example:

[0062] (1) A buffer layer is grown on the substrate using the MBE process.

[0063] For example, a buffer layer with a thickness of 300 nm to 500 nm is grown on a substrate using the MBE process. Preferred process conditions include: growth temperature 650 °C to 750 °C, plasma power 250 W to 400 W, nitrogen flow rate 2.5 sccm to 3.5 sccm, and Ga beam equilibrium vapor pressure 1 × 10⁻⁶. -7 Torr~2×10 -6 Torr.

[0064] (2) An n+GaN collector ohmic contact layer is grown on the buffer layer using the MBE process.

[0065] For example, a 70 nm thick Si doping concentration of 5 × 10⁻⁶ is grown on a buffer layer using the MBE process. -8 cm -3 ~1×10 19 cm -3 The preferred process conditions for the n+GaN collector ohmic contact layer include: growth temperature 650℃~750℃, plasma power 250W~400W, nitrogen flow rate 2.5sccm~3.5sccm, and Ga beam equilibrium vapor pressure 1×10⁻⁶. -7 Torr~2×10 -6 Torr, Si beam equilibrium vapor pressure 3×10-9 Torr~4×10 -8 Torr.

[0066] (3) UID-GaN collector layer is grown on n+GaN collector ohmic contact layer using MBE process.

[0067] For example, a UID-GaN collector layer with a thickness of 30 nm is formed on an n+GaN collector ohmic contact layer using the MBE process. Preferred process conditions include: growth temperature 650℃~750℃, plasma power 250W~400W, nitrogen flow rate 2.5sccm~3.5sccm, and Ga beam equilibrium vapor pressure 1×10⁻⁶. -7 Torr~2×10 -6 Torr.

[0068] (4) The first AlGaN collector barrier layer is grown on the UID-GaN collector layer using the MBE process.

[0069] For example, an Al layer with a thickness of 15 nm to 30 nm is grown on the UID-GaN collector layer using the MBE process. 0.2 Ga 0.8 Nitrogen (N) serves as the first AlGaN collector barrier layer. Preferred process conditions include: growth temperature 650℃–750℃, plasma power 250W–400W, nitrogen flow rate 2.5 sccm–3.5 sccm, and Al beam equilibrium vapor pressure 1.5 × 10⁻⁶. -8 Torr~7.5×10 -8 Torr, Ga beam equilibrium vapor pressure 6×10 -8 Torr~4.5×10 -7 Torr.

[0070] (5) A second AlGaN collector barrier layer is grown on the first AlGaN collector barrier layer using the MBE process.

[0071] For example, a second AlGaN collector barrier layer with a thickness of 8 nm to 20 nm is grown on the first AlGaN collector barrier layer using the MBE process. The Al composition is 15% to 20% (mass percentage) from bottom to top, and the Ga composition gradually increases from 80% to 85% from bottom to top. Preferred process conditions include: growth temperature 650°C to 750°C, plasma power 250 W to 400 W, nitrogen flow rate 2.5 sccm to 3.5 sccm, and Ga beam equilibrium vapor pressure 6 × 10⁻⁶. -8 Torr~4.5×10 -7 Torr, Al beam equilibrium vapor pressure 1.5 × 10 -8 Torr~7.5×10 -8Torr, and during the growth process, by controlling the specific size of the Al beam, the mass percentage of the Al component in the second AlGaN collector barrier layer gradually changes from 20% to 15% from bottom to top.

[0072] (6) An n-type GaN-based region was grown on the second AlGaN collector barrier layer using the MBE process.

[0073] For example, using the MBE process, a Si doping concentration of 1×10⁻⁶ is grown on the second AlGaN collector barrier layer with a thickness of 5nm to 8nm. 19 cm -3 The preferred process conditions for the n-type GaN-based layer include: growth temperature 650℃~50℃, plasma power 250W~400W, nitrogen flow rate 2.5sccm~3.5sccm, and Ga beam equilibrium vapor pressure 1×10⁻⁶. -7 Torr~2×10 - 6 Torr, Si beam equilibrium vapor pressure 8×10 -9 Torr~4×10 -8 Torr.

[0074] (7) ScAlN tunneling barrier layer is grown on n-type GaN-based layer using MBE process.

[0075] For example, a 2nm thick Sc layer is grown on an n-type GaN-based region using the MBE process. 0.18 Al 0.82 Nitrogen (N) serves as the tunneling barrier layer in ScAlN. Preferred process conditions include: growth temperature 650℃–800℃, plasma power 250W–400W, nitrogen flow rate 2.5 sccm–3.5 sccm, and Al beam equilibrium vapor pressure 1×10⁻⁶. -7 Torr~5×10 -7 Torr, Sc beam equilibrium vapor pressure 5×10 -8 Torr~8×10 -8 Torr.

[0076] (8) An AlGaN emitter barrier layer was grown on the ScAlN tunneling barrier layer using the MBE process.

[0077] For example, Al atoms with a thickness of 30 nm to 40 nm are grown on the ScAlN tunneling barrier layer using the MBE process. 0.2 Ga 0.8 Nitrogen (N) serves as the emitter barrier layer in AlGaN. Preferred process conditions include: growth temperature 650℃–750℃, plasma power 250W–400W, nitrogen flow rate 2.5 sccm–3.5 sccm, and Al beam equilibrium vapor pressure 1.5 × 10⁻⁶.-8 Torr~7.5×10 - 8 Torr, Ga beam equilibrium vapor pressure 6×10 -8 Torr~4.5×10 -7 Torr.

[0078] (9) Using the MBE process, GaN emitter cap layer is grown on AlGaN emitter barrier layer.

[0079] For example, a 30 nm thick AlGaN emitter barrier layer with a Si doping concentration of 5 × 10⁻⁶ was grown using the MBE process. -8 cm -3 ~1×10 19 cm -3 The preferred process conditions for the GaN emitter cap layer include: growth temperature 650℃~750℃, plasma power 250W~400W, nitrogen flow rate 2.5sccm~3.5sccm, and Ga beam equilibrium vapor pressure 1×10⁻⁶. -7 Torr~2×10 -6 Torr, Si beam equilibrium vapor pressure 8×10 -89 Torr~4×10 -8 Torr.

[0080] Thus, by sequentially growing a buffer layer, an n+GaN collector ohmic contact layer, a UID-GaN collector layer, a first AlGaN collector barrier layer, a second AlGaN collector barrier layer, an n-type GaN base region layer, a ScAlN tunneling barrier layer, an AlGaN emitter barrier layer, and a GaN emitter cap layer on the substrate, an initial epitaxial structure is formed, and the subsequent micro-nano fabrication of the structure begins in step two.

[0081] Step 2: Etch the above epitaxial structure to prepare the device's electrical isolation region.

[0082] Specifically, patterns for subsequent etching of the electrical isolation region of the device are photolithographically etched at both ends of the GaN emitter cap layer surface. Then, starting from this pattern, the GaN emitter cap layer, AlGaN emitter barrier layer, ScAlN tunneling barrier layer, n-type GaN base layer, second AlGaN collector barrier layer, first AlGaN collector barrier layer, UID-GaN collector layer, n+GaN collector ohmic contact layer and buffer layer are etched sequentially downwards until the substrate directly below the pattern is exposed.

[0083] The etching process can be inductively coupled plasma (ICP) etching, with BCl3 / Cl2 as the etching gas. The upper / lower electrode power of the ICP etching machine is 51W / 14W, the etching rate is 24nm / min, and the etching depth can reach 50% over-etching. After etching, routine cleaning is performed to remove residual photoresist from the surface.

[0084] Step 3: Define a first region on the surface of the GaN emitter cap layer. Starting from the first region, use Cl-based plasma to etch downwards until the ScAlN tunneling barrier layer directly below the first region is exposed. During the etching process, ScCl3 generated by the reaction of Sc and Cl is used to achieve self-terminating etching on the surface of the ScAlN tunneling barrier layer.

[0085] Specifically, a first region is defined on the surface of the GaN emitter cap layer by photolithography. In this embodiment of the invention, the specific location of the first region on the GaN emitter cap layer is not limited. For example, two regions can be defined as the first region at both ends of the surface of the GaN emitter cap layer.

[0086] After defining the first region, starting from the first region, the GaN emitter cap layer and AlGaN emitter barrier layer are etched sequentially downwards using Cl-based plasma until the ScAlN tunneling barrier layer directly beneath the first region is exposed. The etching process can employ ICP etching, using BCl3 / Cl2 as the etching gas. The upper / lower electrode power of the ICP etching machine is 200W / 30W, the etching rate is 24nm / min, and the etching depth is sufficient to completely remove both the GaN emitter cap layer and the AlGaN emitter barrier layer directly beneath the first region. After etching, routine cleaning is performed to remove residual photoresist from the surface.

[0087] It is worth mentioning that the etching process in step three can achieve a self-terminating etching effect. Specifically, the Cl-based plasma completely etches away the GaN emitter cap layer and AlGaN emitter barrier layer directly below the first region. The exposed ScAlN tunneling barrier layer will react with the Cl-based plasma to generate ScCl3, with a vapor pressure of 3 × 10⁻⁶. - 30 Torr) and AlCl3 vapor pressure (3×10) -3 The difference between the vapor pressures (Torr) and GaCl3 (2Torr) is relatively large, and the latter has lower volatility, causing etching byproducts to adhere to the surface and hinder further etching. This causes the etching reaction to terminate above the ScAlN tunneling barrier layer, achieving a high etching selectivity between the AlGaN and ScAlN layers. This solves the problem of excessive base region resistance caused by over-etching or insufficient etching depth.

[0088] As those skilled in the art know, quasi-vertical devices like HETs require extremely high precision in base region etching. Etching depths that are too deep or too shallow will prevent the achievement of good ohmic contact in the base region, and excessive etching damage will also lead to high contact resistance. In this embodiment of the invention, the etching reaction terminates on the ScAlN tunneling barrier layer, effectively solving the problem of excessive base region resistance caused by over-etching or insufficient etching depth.

[0089] Step 4: Define a second region on the surface of the ScAlN tunneling barrier layer exposed in Step 3. Start etching downwards from the second region until the n+GaN collector ohmic contact layer directly below the second region is exposed.

[0090] Specifically, a second region is defined on the surface of the exposed ScAlN tunneling barrier layer by photolithography. In this embodiment of the invention, the specific location of the second region on the surface of the exposed ScAlN tunneling barrier layer is not limited. For example, two regions can be defined as the second region at both ends of the surface of the ScAlN tunneling barrier layer.

[0091] After defining the second region, starting from the second region, Cl-based plasma is used to sequentially etch the n-type GaN base layer, the second AlGaN collector barrier layer, the first AlGaN collector barrier layer, and the UID-GaN collector layer downwards until the n+GaN collector ohmic contact layer directly beneath the second region is exposed. The etching process can employ ICP etching, using BCl3 / Cl2 as the etching gas. The upper / lower electrode power of the ICP etching machine is 51W / 14W, the etching rate is 24nm / min, and the etching depth reaches the point where the n+GaN collector ohmic contact layer directly beneath the second region is just exposed. After etching, routine cleaning is performed to remove residual photoresist from the surface.

[0092] Step 5: Fabricate the base on the ScAlN tunneling barrier layer exposed in Step 3, fabricate the collector on the n+GaN collector ohmic contact layer exposed in Step 4, and fabricate the emitter on the GaN emitter cap layer; wherein, the base is isolated from the AlGaN emitter barrier layer, and the collector is isolated from the UID-GaN collector layer.

[0093] Specifically, electrode metal marks are fabricated on the ScAlN tunneling barrier layer exposed in step three, the n+GaN collector ohmic contact layer exposed in step four, and the GaN emitter cap layer, respectively. Then, an electron beam evaporation process is used, with a stepper lithography machine aligned with the electrode metal marks. After photolithography, metal evaporation is performed, thereby depositing electrode metal, such as Al / Au, on the ScAlN tunneling barrier layer exposed in step three, the n+GaN collector ohmic contact layer exposed in step four, and the GaN emitter cap layer, respectively. The preferred thickness of Al is... The preferred thickness of Au Then, annealing is performed at a temperature of 700℃~900℃ to complete the fabrication of the hot electron transistor. Specifically, the metal deposited on the ScAlN tunneling barrier layer forms the base of the hot electron transistor, the metal deposited on the n+GaN collector ohmic contact layer forms the collector of the hot electron transistor, and the metal deposited on the GaN emitter cap layer forms the emitter of the hot electron transistor.

[0094] In the fabrication method of the hot electron transistor with high injection energy provided in this embodiment of the invention, during the etching of the GaN emitter cap layer and the AlGaN emitter barrier layer using Cl-based plasma, the GaN emitter cap layer and the AlGaN emitter barrier layer are completely etched away using Cl-based plasma. The exposed ScAlN will react with the Cl-based plasma to generate ScCl3. Due to the large difference in etching reaction rates between ScAlN and AlGaN, and the low volatility of ScCl3, the etching byproducts adhere to the surface, hindering further etching. As a result, the etching reaction terminates on the ScAlN tunneling barrier layer, achieving a high etching selectivity between the AlGaN emitter barrier layer and the ScAlN tunneling barrier layer. This solves the problem of excessive base region resistance caused by over-etching or insufficient etching depth in the base region.

[0095] The hot electron transistors fabricated using the method provided in this embodiment of the invention have an AlGaN / ScAlN composite emitter barrier, which can improve the emitter barrier band, thereby increasing the electron injection energy and reducing the proportion of electrons relaxing to the base region, thus improving the current gain of the device.

[0096] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure.

[0097] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0098] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings and the disclosure, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the description of this invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0099] For the embodiments of the device / electronic device / storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and relevant parts can be referred to in the description of the method embodiments.

[0100] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0101] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0102] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0103] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A hot electron transistor with high injection energy, characterized in that, include: Substrate, epitaxial structure, base, emitter, and collector; The epitaxial structure is located on the substrate, surrounded by the device electrical isolation region of the hot-electron transistor; the epitaxial structure includes, from bottom to top, a buffer layer, an n+GaN collector ohmic contact layer, a UID-GaN collector layer, a first AlGaN collector barrier layer, a second AlGaN collector barrier layer, an n-type GaN base layer, a ScAlN tunneling barrier layer, an AlGaN emitter barrier layer, and a GaN emitter cap layer; the thickness of the n-type GaN base layer is 5 nm to 8 nm. nm; The AlGaN tunneling barrier layer and the AlGaN emitter barrier layer form an AlGaN / ScAlN composite emitter barrier; the AlGaN emitter barrier layer raises the emitter energy band to prevent low-energy electron injection, while the ScAlN tunneling barrier layer makes the incident electron direction more perpendicular, reducing the number of electron relaxations in the base region, and simultaneously blocking low-energy electrons, raising the emitter energy band to increase the injected electron energy; the emitter-base heterojunction (ScAlN / GaN) formed by the ScAlN tunneling barrier layer and the n-type GaN base layer generates a high 2DEG (two-dimensional electron gas) density, reducing the base resistance; the thickness of the second AlGaN collector barrier layer is 8 nm to 20 nm; in the second AlGaN collector barrier layer, the mass percentage of Al component gradually changes from 20% to 15% from bottom to top to reduce quantum reflection caused by the sharp barrier; the mass percentage of Ga component gradually changes from 80% to 85% from bottom to top. The collector is stacked on the n+GaN collector ohmic contact layer and isolated from the UID-GaN collector layer; The base is stacked on the ScAlN tunneling barrier layer and isolated from the AlGaN emitter barrier layer; The emitters are stacked on the GaN emitter cap layer.

2. The hot electron transistor with high injection energy according to claim 1, characterized in that, The buffer layer is a GaN buffer layer with a thickness of 300 nm to 500 nm.

3. The hot electron transistor with high injection energy according to claim 1, characterized in that, The n+GaN collector ohmic contact layer is made of Si-doped GaN, with a Si doping concentration of 5 × 10⁻⁶. -8 cm -3 ~1×10 19 cm -3 The thickness of the n+GaN collector ohmic contact layer is 70 nm to 200 nm.

4. The hot electron transistor with high injection energy according to claim 1, characterized in that, The UID-GaN collector layer is made of intrinsic GaN and has a thickness of 20 nm to 60 nm.

5. The hot electron transistor with high injection energy according to claim 1, characterized in that, The first AlGaN collector barrier layer is made of Al 0.2 Ga 0.8 N, with a thickness of 15 nm to 30 nm.

6. The hot electron transistor with high injection energy according to claim 1, characterized in that, The n-type GaN base layer is made of Si-doped GaN, with a Si doping concentration of 1×10⁻⁶. 19 cm -3 .

7. The hot electron transistor with high injection energy according to claim 1, characterized in that, The material of the ScAlN tunneling barrier layer is Sc 0.18 Al 0.82 N, with a thickness of 2 nm to 6 nm.

8. The hot electron transistor with high injection energy according to claim 1, characterized in that, The material of the AlGaN emitter barrier layer is Al. 0.2 Ga 0.8 N, with a thickness of 30 nm to 40 nm.

9. The hot electron transistor with high injection energy according to claim 1, characterized in that, The GaN emitter cap layer is made of Si-doped n+GaN, with a Si doping concentration of 5 × 10⁻⁶. -8 cm -3 ~1×10 19 cm -3 The thickness of the GaN emitter cap layer is 10 nm to 40 nm.

10. A method for fabricating a hot electron transistor with high injection energy, characterized in that, The method for fabricating a high-injection-energy thermionic transistor according to any one of claims 1-9 comprises: Step 1: On the substrate, a buffer layer, an n+GaN collector ohmic contact layer, a UID-GaN collector layer, a first AlGaN collector barrier layer, a second AlGaN collector barrier layer, an n-type GaN base region layer, a ScAlN tunneling barrier layer, an AlGaN emitter barrier layer, and a GaN emitter cap layer are epitaxially grown sequentially to form the initial epitaxial structure. Step 2: Etch the epitaxial structure to prepare the device's electrically isolated region; Step 3: Define a first region on the surface of the GaN emitter cap layer. Starting from the first region, use Cl-based plasma to etch downwards until the ScAlN tunneling barrier layer directly below the first region is exposed. During the etching process, ScCl3 generated by the reaction of Sc and Cl achieves self-terminating etching on the surface of the ScAlN tunneling barrier layer. Step 4: Define a second region on the surface of the ScAlN tunneling barrier layer exposed in Step 3. Etch downwards from the second region until the n+GaN collector ohmic contact layer directly below the second region is exposed. Step 5: Fabricate the base on the ScAlN tunneling barrier layer exposed in Step 3, fabricate the collector on the n+GaN collector ohmic contact layer exposed in Step 4, and fabricate the emitter on the GaN emitter cap layer; wherein the base is isolated from the AlGaN emitter barrier layer, and the collector is isolated from the UID-GaN collector layer.

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