Device for emitting ultrasonic waves

Abstract

The invention relates to a device for emitting ultrasound waves, the device comprising a microchip (300) for driving a resonant circuit and a resonant circuit being at least one of an LC tank circuit, an antenna and a piezoelectric transducer. The microchip (300) is a single unit comprising a plurality of interconnected embedded components and subsystems, the plurality of interconnected embedded components and subsystems comprising at least an oscillator (315), a pulse width modulation (PWM) signal generator subsystem (329), an analog-to-digital converter (ADC) subsystem (318) and a digital-to-analog converter (DAC) subsystem (327).

Description

Technical Field

[0001] This invention relates to a device for emitting ultrasonic waves. More specifically, this invention relates to a device for emitting ultrasonic waves comprising a microchip driving a resonant circuit in the form of an LC oscillating circuit (tank), an antenna, or a piezoelectric transducer. Background Technology

[0002] Therapeutic aerosol delivery is a primary means of treating asthma, chronic obstructive pulmonary disease (COPD), and cystic fibrosis. Therapeutic aerosols are also used to treat influenza, osteoporosis, and deliver vaccines.

[0003] Lung delivery of therapeutic agents for treating non-respiratory systemic diseases is attractive due to its high pulmonary vascularity, thin blood-alveolar barrier, large surface area, and avoidance of gastric enzymes and first-pass hepatic metabolism. It is also attractive because it improves patient comfort and compliance. The pulmonary system can be utilized to deliver antibodies, proteins, analgesics, and nucleic acids. Effective delivery of nicotine into systemic circulation via the lungs can significantly enhance the treatment of central nervous system disorders such as tobacco dependence.

[0004] The effectiveness of therapeutic aerosols is related to the amount of drug deposited outside the oropharyngeal region. The area where deposition occurs is a function of the inhaled particle size.

[0005] Currently, devices used for administering inhaled medications fall into three categories: nebulizers, metered-dose inhalers, and dry powder inhalers. Nebulizers are generally divided into two types: jet and ultrasonic, but both types have drawbacks and problems in conventional devices.

[0006] Jet nebulizers are based on Bernoulli's principle and produce relatively large droplets that typically deposit in the oropharyngeal region, making them less effective. Ultrasonic nebulizers use piezoelectric crystals that vibrate at frequencies ranging from 1 MHz to 1.7 MHz, projecting vibrational energy into the liquid and converting it into an aerosol. However, ultrasonic nebulizers are known to be ineffective with viscous suspensions or solutions and tend to heat the medication, breaking down its molecules and negating any benefits of inhalation.

[0007] There are other applications that require efficient driving of resonant circuits at or near their resonant frequency in an optimal manner. For example, devices incorporating resonant circuits in the form of antennas typically require a precise AC drive signal to drive the antenna for optimal operation. Additionally, devices incorporating resonant circuits in the form of ultrasonic piezoelectric transducers must generate an AC drive signal to optimally drive the ultrasonic transducer.

[0008] Therefore, there is a need in the art for a device for emitting ultrasonic waves that attempts to solve at least some of the problems described herein. Summary of the Invention

[0009] This invention provides an apparatus for emitting ultrasonic waves. The invention also provides preferred embodiments as claimed in the dependent claims.

[0010] The various examples of this disclosure described below have several advantages over conventional devices. These advantages and benefits are set forth in the description below.

[0011] Because the apparatus of this disclosure achieves more efficient operation than conventional apparatus, the apparatus of this disclosure has environmental benefits due to reduced power requirements. Attached Figure Description

[0012] To facilitate understanding of this disclosure, preferred embodiments will now be described by way of example only with reference to the accompanying drawings, in which: Figure 1 This is a schematic diagram of the apparatus disclosed herein; Figure 2 This is a schematic diagram of the integrated circuit disclosed herein; Figure 3 This is a schematic diagram of the pulse width modulation generator disclosed herein; Figure 4 This is a timing diagram of an example of this disclosure; Figure 5 This is a timing diagram of an example of this disclosure; Figure 6 This is a table illustrating port functions as examples of those in this disclosure; Figure 7 This is a schematic diagram of the integrated circuit disclosed herein; Figure 8 This is a circuit diagram of an example H-bridge of this disclosure; Figure 9 This is a circuit diagram of an example current sensing arrangement of this disclosure; Figure 10 This is a circuit diagram of an example H-bridge of this disclosure; Figure 11 It is shown in Figure 8 A graph showing the voltage during the operation phase of the H-bridge; Figure 12 It is shown in Figure 8 A graph showing the voltage during the operation phase of the H-bridge; Figure 13 This indicates that when the ultrasonic transducer is being powered by... Figure 8 The curves of voltage and current at the terminals of the ultrasonic transducer when the H-bridge is driven; Figure 14 This is a schematic diagram illustrating the connections between integrated circuits of this disclosure; Figure 15 This is a schematic diagram of the integrated circuit disclosed herein; and Figure 16 This is a diagram illustrating the steps of an authentication method as exemplified by this disclosure. Detailed Implementation

[0013] When with attachment Figure 1 When reading this document, it is best to understand all aspects of this disclosure from the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0014] The following disclosure provides numerous different embodiments or examples for achieving various features of the provided subject matter. Specific examples of components, concentrations, applications, and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the attachment of the first and second features in the following description may include embodiments in which the first and second features are in direct contact with each other, and may also include embodiments in which an additional feature may be positioned between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0015] The following disclosure describes representative examples. Each example may be considered an implementation scheme, and any reference to “example” in this disclosure may be changed to “implementation scheme”.

[0016] Now refer to the attached diagram. Figure 1 The driver device 202 includes a microchip, referred to herein as a power management integrated circuit or PMIC 300. The PMIC 300 is a microchip used to drive a resonant circuit. The resonant circuit is an LC oscillating circuit, an antenna, or a piezoelectric transducer. In this example, the resonant circuit is an ultrasonic transducer 215 disposed within the resonant circuit device 201. In this example, the resonant circuit device 201 is a separate device releasably coupled to the driver device 202. In other examples, the components of the resonant circuit device 201 are combined in the same device as the driver device 202.

[0017] In this disclosure, the terms chip, microchip, and integrated circuit are used interchangeably. A microchip or integrated circuit is a single unit comprising multiple interconnected embedded components and subsystems. A microchip is made, for example, at least in part, of a semiconductor such as silicon and is manufactured using semiconductor manufacturing techniques.

[0018] This disclosure describes an exemplary resonant circuit device 201, which is a mist inhaler device including an ultrasonic transducer 215. When the ultrasonic transducer 215 is activated by a driver device 202, the ultrasonic transducer 215 atomizes liquid to produce a mist for inhalation by a user.

[0019] However, it should be understood that the components of the driver device are used differently in other applications involving resonant circuits. In these other examples, the ultrasonic transducer 215 is replaced by another resonant circuit, such as an LC oscillating circuit or an antenna.

[0020] In one example, the resonant circuit device 201 includes a resonant circuit in the form of a piezoelectric ultrasonic transducer that generates ultrasonic waves for wireless power transmission. In this example, the ultrasonic transducer is driven by a driver device 202 to generate ultrasonic waves that can be focused and transmitted to a receiver transducer. The receiver transducer converts the ultrasonic waves back into electrical energy and stores that energy in an energy storage device such as a battery, or uses the electrical energy to power the device. In this way, the device can be remotely charged or powered via electricity transmitted wirelessly via ultrasonic waves without having to tether the device to an electrical outlet.

[0021] As described below, the driver device 202 is configured to modulate the frequency and duty cycle of the AC power signal driving the ultrasonic transducer with high accuracy and efficiency. In the case of a power transmission system, this enables the driver device 202 to encode information for wireless transmission by modulating ultrasonic waves carrying encoded information. In one example, the driver device 202 is configured for use in a wireless power transmission system, such as, but not limited to, the type described in U.S. Patent No. 9,001,622 entitled “receiver communications for wireless power transfer,” the entire contents of which are incorporated herein by reference.

[0022] In another example, driver device 202 drives a resonant circuit in the form of an ultrasound transducer to deliver ultrasound waves at a precise frequency and high intensity to treat tumors. High-intensity focused ultrasound from the ultrasound transducer is used as a non-invasive targeted therapy to raise the temperature within the tumor to above 65°C, killing tumor cells without damaging surrounding tissue.

[0023] In other applications, the driver device 202 is used to drive a resonant circuit in the form of an antenna to precisely control the frequency and power of the wave emitted by the antenna. In this example, the antenna can be used for any purpose. In one example, the driver device 202 drives the antenna to emit waves at a precise frequency for the purpose of searching for materials such as underground minerals or gold.

[0024] The driver device 202 includes a second microchip, referred herein as a bridge integrated circuit or bridge IC 301, which is electrically connected to the PMIC 300. Bridge IC 301 is a microchip used to drive resonant circuits such as LC oscillator circuits, antennas, or piezoelectric transducers. Bridge IC 301 is a single unit comprising multiple interconnected embedded components and subsystems.

[0025] In this example, PMIC 300 and bridge IC 301 are mounted on the same PCB as driver device 202. In this example, the physical dimensions of PMIC 300 are 1mm-3mm wide and 1mm-3mm long, and the physical dimensions of bridge IC 301 are 1mm-3mm wide and 1mm-3mm long.

[0026] In this example, the resonant circuit device 201 includes an optional programmable or one-time programmable integrated circuit or OTP IC 242. When the resonant circuit device 201 is coupled to the driver device 202, the OTP IC is electrically connected to the PMIC 300 to receive power from the PMIC 300, allowing the PMIC 300 to manage the voltage supplied to the OTP IC 242. The OTP IC 242 is also connected to a communication bus 302 in the driver device 202. In this example, the communication bus 302 is an I2C bus, but in other examples, the communication bus 302 is another type of digital serial communication bus.

[0027] OTP IC 242 provides the security functions described below. However, it should be understood that OTP IC 242 is omitted in examples of this disclosure where such security functions are not required.

[0028] The ultrasonic transducer 215 in the resonant circuit device 200 is electrically connected to the bridge IC 301, so that the ultrasonic transducer 215 can be driven by the AC drive signal generated by the bridge IC 301 when the device 201 is in use.

[0029] The driver device 202 includes a processor in the form of a microcontroller 303, which is electrically coupled for communicating with a communication bus 302. In this example, the microcontroller 303 is a Bluetooth device. ™ This is a low-power (BLE) microcontroller, but in other examples, microcontroller 303 is a general-purpose processor. Microcontroller 303 receives power from a low-dropout regulator (LDO) 304 powered by battery 250. LDO 304 provides a stable, regulated voltage to microcontroller 303 so that microcontroller 303 can operate consistently even when the voltage of battery 250 varies.

[0030] Driver device 202 includes a voltage regulator in the form of a DC-DC boost converter 305 powered by battery 250. The boost converter 305 increases the voltage of battery 250 to a programmable voltage VBOOST. The programmable voltage VBOOST is set by the boost converter 305 in response to a voltage control signal VCTL from PMIC 300. As will be described in more detail below, the boost converter 305 outputs the voltage VBOOST to bridge IC 301. In other examples, the voltage regulator is a buck converter or another type of voltage regulator with a selectable output voltage.

[0031] The voltage control signal VCTL is generated by a digital-to-analog converter (DAC), which in this example is implemented within the PMIC300. The DAC is... Figure 1 It is not visible in the PMIC 300 because the DAC is integrated within the PMIC 300. The DAC and the technical benefits of integrating the DAC into the PMIC 300 are described in detail below.

[0032] In this example, the PMIC 300 is connected to a power connector in the form of a Universal Serial Bus (USB) connector 306, so that the PMIC 300 can receive the charging voltage VCHRG when the USB connector 306 is connected to a USB charger.

[0033] In this example, the actuator device 202 includes a first pressure sensor 307, which is a static pressure sensor in this example. The actuator device 202 also includes a second pressure sensor 308, which is a dynamic pressure sensor in this example. However, in other examples, the actuator device 202 includes only one of the two pressure sensors 307, 308, or the pressure sensors 307, 308 are omitted entirely. In this example involving a fog generator device, the pressure sensors 307, 308 sense pressure changes in an aerosol chamber (not shown) to sense when a user inhales fog from the aerosol chamber.

[0034] In this example, the driver device 202 includes a plurality of LEDs 308 controlled by the PMIC 300. In other examples, the LEDs 308 are omitted.

[0035] The microcontroller 303 acts as the master device on the communication bus 302, where the PMIC 300 is the first slave device, the OTP IC 242 is the second slave device, the second pressure sensor 308 is the third slave device, and the first pressure sensor 307 is the fourth slave device. The communication bus 302 enables the microcontroller 303 to control the following functions within the driver device 202: 1. All functions of the PMIC can be highly configurable by the microcontroller 303.

[0036] 2. The current flowing through the resonant circuit (ultrasonic transducer 215) is sensed by a high-bandwidth sensing and rectification circuit at a high common-mode voltage (high side of the bridge). The sensed current is converted into a voltage proportional to the root-mean-square current and provided as a buffered voltage at the current sensing output pin 309 of the bridge IC 301. This voltage is fed to the PMIC 300 and sampled therein, and is available as a digital representation via an I2C request. Sensing the current flowing through the ultrasonic transducer 215 forms part of a resonant frequency tracking function. As described herein, the ability of the device to enable this function within the bridge IC 301 provides significant technical benefits.

[0037] 3. DAC integrated into PMIC 300 ( Figure 1 (Not shown in the image) This allows the DC-DC boost converter voltage VBOOST to be programmed between 10V and 20V.

[0038] 4. The microcontroller 303 enables the charger subsystem of the device 202 to manage the charging of the battery, which in this example is a single cell battery.

[0039] 5. A light-emitting diode (LED) driver module (not shown) is powered by the PMIC 300 to digitally drive and dim the LED 308 in linear mode or gamma correction mode.

[0040] 6. The microcontroller 303 can read the pressure #1 and pressure #2 sensor values ​​from pressure sensors 307 and 308.

[0041] Now refer to the attached diagram. Figure 2 In this example, PMIC 300 is a self-contained chip or integrated circuit that includes an integrated subsystem and multiple pins providing electrical inputs and outputs to PMIC 300. References to integrated circuits or chips are used interchangeably in this disclosure, and any term encompasses, for example, a semiconductor device that may have silicon.

[0042] The PMIC 300 includes an analog core 310, which includes analog components including a reference block (BG) 311, an LDO 312, a current sensor 313, a temperature sensor 314, and an oscillator 315.

[0043] As described in more detail below, oscillator 315 is coupled to a delay-locked loop (DLL) that outputs pulse width modulation (PWM) phases A and B. Oscillator 315 and DLL generate a two-phase center-aligned PWM output for the H-bridge in driver bridge IC 301.

[0044] The DLL comprises multiple delay lines connected end-to-end, where the total delay of the delay lines is equal to the period of the master clock signal clk_m. In this example, the DLL is implemented in the digital processor subsystem of the PMIC 300 (referred to herein as digital core 316), which receives a clock signal from oscillator 315 and an regulated supply voltage from LDO 312. The DLL is implemented in a large number (e.g., approximately millions) of delay gates connected end-to-end in digital core 316.

[0045] Implementing the oscillator 315 and DLL in the same integrated circuit of the PMIC 300 to generate a two-phase center-aligned PWM signal is unique because no signal generator component in the current integrated circuit market includes this implementation.

[0046] As described herein, PWM is part of the functionality that enables the driver device 202 to accurately track the resonant frequency of the ultrasonic transducer 215 in order to maintain efficient transfer of electrical energy to kinetic energy in order to optimize fog formation. Other examples of the same functionality can be achieved by efficiently driving the resonant circuit with high power and high frequency, including different resonant circuits.

[0047] In this example, the PMIC 300 includes a charger circuit 317 that controls the charging of the battery 250, for example, using power from a USB power source. In other examples where a battery is not required, the charger circuit 317 is omitted.

[0048] PMIC 300 includes an integrated power switch VSYS, which configures PMIC 300 to power analog core 310 via power from battery 250 or via power from an external power source while battery 250 is being charged.

[0049] The PMIC 300 includes an embedded analog-to-digital converter (ADC) subsystem 318. The implementation of the ADC 318 and oscillator 315 within the same integrated circuit is unique in itself because no other integrated circuit on the market includes an oscillator and an ADC implemented as a sub-block within the integrated circuit. In conventional devices, the ADC is typically configured as a discrete component separate from the oscillator, with the individual ADC and oscillator mounted on the same PCB. The problem with this conventional arrangement is that the two separate components of the ADC and oscillator unnecessarily occupy space on the PCB. Another problem is that conventional ADCs and oscillators are typically connected to each other via a serial data communication bus, such as the I2C bus, which has a limited communication speed of only 400 kHz. Compared to conventional devices, the PMIC 300 includes the ADC 318 and oscillator 315 integrated within the same integrated circuit, which eliminates any hysteresis in communication between the ADC 318 and oscillator 315. This means that the ADC 318 and oscillator 315 can communicate with each other at high speeds, such as the speed of the oscillator 315 (e.g., 3 MHz to 5 MHz).

[0050] In this example PMIC 300, oscillator 315 is operating at 5MHz and generating the clock signal SYSCLOCK at 5MHz. However, in other examples, oscillator 315 generates the clock signal at a much higher frequency, up to 105MHz. All integrated circuits described herein are configured to operate at the high frequency of oscillator 315.

[0051] The ADC 318 includes multiple feedback input terminals or analog input terminals 319, which include multiple GPIO input terminals (IF_GPIO1-3). At least one of the feedback input terminals or analog input terminals 319 receives a feedback signal from the H-bridge circuit in the bridge IC 301, which indicates the parameters of the operation of the H-bridge circuit or the AC drive signal when the H-bridge circuit drives a resonant circuit (such as the ultrasonic transducer 215) with an AC drive signal. As described below, the GPIO input terminals are used to receive a current sensing signal from the bridge IC 301, which indicates the path mean square (rms) current reported by the bridge IC 301. In this example, one of the GPIO input terminals is the feedback input terminal that receives the feedback signal from the H-bridge in the bridge IC 301.

[0052] The ADC subsystem 318 samples the analog signals received at multiple ADC input terminals 319 at a sampling frequency proportional to the frequency of the master clock signal. The ADC subsystem 318 then uses the sampled analog signals to generate ADC digital signals.

[0053] In this example, the ADC 318 incorporated in the PMIC 300 samples not only the root mean square current flowing through the H-bridge circuit 334 and the ultrasonic transducer 215, but also the voltages available in the system (e.g., VBAT, VCHRG, VBOOST), the temperature of the PMIC 300, the temperature of the battery 250, and the GPIO inputs (IF_GPIO1-3) that allow for future expansion.

[0054] Digital core 316 receives digital signals generated by the ADC from the ADC subsystem and processes the ADC digital signals to generate driver control signals. Digital core 316 transmits the driver control signals to the PWM signal generator subsystem (DLL332) to control the PWM signal generator subsystem.

[0055] Current rectifier circuits on the market have very limited bandwidth (typically less than 1MHz). Since the oscillator 315 of the PMIC 300 operates at up to 5MHz or even up to 105MHz, a high-bandwidth rectifier circuit is implemented in the PMIC 300. As will be described below, the root-mean-square current within the H-bridge of the sensing bridge IC 301 forms part of the feedback loop, which enables the driver device 202 to drive the ultrasonic transducer 215 with high precision. The feedback loop is a game-changer in the ultrasonic transducer industry because it adapts to any process variations (changes in resonant frequency) in piezoelectric transducer production and compensates for temperature effects on the resonant frequency. This is achieved in part through the ingenious implementation of integrating the ADC 318, oscillator 315, and DLL within the same integrated circuit of the PMIC 300. This integration allows these subsystems to communicate with each other at high speeds (e.g., clock frequencies of 5MHz or up to 105MHz). Reducing hysteresis between these subsystems is a game-changer in the ultrasonic industry, particularly in the field of fog generator devices.

[0056] The ADC 318 includes a battery voltage monitoring input VBAT, a charger input voltage monitoring input VCHG, voltage monitoring inputs VMON and VRTH, and a temperature monitoring input TEMP.

[0057] The temperature monitoring input TEMP receives a temperature signal from the temperature sensor 314 embedded within the PMIC 300. This allows the PMIC 300 to accurately sense the actual temperature within the PMIC 300, enabling it to detect any faults within the PMIC 300 and faults in other components on the printed circuit board that affect the temperature of the PMIC 300. If a fault is present, the PMIC 300 can then control the bridge IC 301 to prevent excitation of the ultrasonic transducer 215, thereby maintaining the safety of the resonant circuit device 201.

[0058] The additional temperature sensor input VRTH receives a temperature sensing signal from an external temperature sensor within the driver device 202 that monitors the battery temperature. The PMIC 300 can therefore react by stopping battery charging or otherwise shutting down the driver device 202 in the event of a high battery temperature to reduce the risk of damage caused by excessively high battery temperatures.

[0059] The PMIC 300 includes an LED driver 320, which in this example receives digital drive signals from a digital core 316 and provides LED drive output signals to six LEDs 321 to 326 configured to be connected to the output pins of the PMIC 300. Therefore, the LED driver 320 can drive and dim LEDs 321-326 in up to six independent channels.

[0060] PMIC 300 includes a first digital-to-analog converter (DAC) 327 that converts digital signals within PMIC 300 into analog voltage control signals output from PMIC 300 via output pin VDAC0. The first DAC 327 converts the digital control signals generated by digital core 316 into analog voltage control signals, which are output via output pin VDAC0 to control voltage regulator circuitry, such as boost converter 305. The voltage control signals thus control the voltage regulator circuitry to generate a predetermined voltage modulated by an H-bridge circuit, causing the H-bridge circuit to drive the resonant circuit (such as ultrasonic transducer 215) in response to a feedback signal indicating operation of the resonant circuit (such as ultrasonic transducer 215).

[0061] In this example, PMIC 300 includes a second DAC 328 that converts digital signals within PMIC 300 into analog signals output from PMIC 300 via a second analog output pin VDAC1.

[0062] Embedding DAC 327 or DAC 327, 328 within the same microchip as other subsystems of PMIC 300 allows DAC 327, 328 to communicate with digital core 316 and other components within PMIC 300 at high speed with no or minimal communication lag. DAC 327, 328 provides analog outputs to control external feedback loops. For example, the first DAC 327 provides a control signal VCTL to boost converter 305 to control its operation. In other examples, instead of boost converter 305 or other components, DAC 327, 328 is configured to provide drive signals to a DC-DC buck converter. Integrating two independent DAC channels in PMIC 300 allows PMIC 300 to manipulate the feedback loop of any regulator used in driver device 202 and allows driver device 202 to adjust the acoustic processing power of ultrasonic transducer 215 or set analog thresholds for absolute maximum current and temperature settings for ultrasonic transducer 215.

[0063] The PMIC 300 includes a serial communication interface, which in this example is an I2C interface that combines an external I2C address set with pins.

[0064] The PMIC 300 also includes various function blocks, including digital machine modules (FSMs) to implement the functions of the microchip. These blocks will be described in more detail below.

[0065] Now refer to the attached diagram. Figure 3 A pulse width modulation (PWM) signal generator subsystem 329 is embedded within the PMIC 300. The PWM generator system 329 includes an oscillator 315, a frequency divider 330, a multiplexer 331, and a delay-locked loop (DLL) 332. As will be described below, the PWM generator system 329 is a two-phase center-aligned PWM generator.

[0066] Frequency divider 330, multiplexer 331, and DLL 332 are implemented in digital logic components (e.g., transistors, logic gates, etc.) within digital core 316.

[0067] In embodiments of this disclosure, the frequency range covered by oscillator 315 and PWM generator system 329 is 50 kHz to 5 MHz or up to 105 MHz, respectively. The frequency accuracy of PWM generator system 329 is ±1%, and its temperature range is ±1%. In today's IC market, no IC has an embedded oscillator and a two-phase center-aligned PWM generator capable of providing a frequency range of 50 kHz to 5 MHz or up to 105 MHz.

[0068] Oscillator 315 generates a master clock signal (clk_m) with a frequency ranging from 50 kHz to 5 MHz or up to 105 MHz. The master clock clk_m is input to frequency divider 330, which divides the frequency of the master clock clk_m by one or more predetermined divisors. In this example, frequency divider 330 divides the frequency of the master clock clk_m by 2, 4, 8, and 16, and provides the divided clock as an output to multiplexer 331. Multiplexer 331 multiplexes the divided clock and provides the divided output to DLL 332. This signal passed to DLL 332 is a frequency reference signal that controls DLL 332 to output a signal at the desired frequency. In other examples, frequency divider 330 and multiplexer 331 are omitted.

[0069] Oscillator 315 also generates two phases: a first-phase clock signal (Phase 1) and a second-phase clock signal (Phase 2). The phases of the first-phase clock signal and the second-phase clock signal are center-aligned. For example... Figure 4 As shown: ● The first phase clock signal, Phase 1, is high during the variable time of the positive half-cycle of clk_m and low during the negative half-cycle of clk_m.

[0070] ●The second phase clock signal, Phase 2, is high during the variable time of the negative half-cycle of clk_m and low during the positive half-cycle of clk_m.

[0071] Phase 1 and Phase 2 are then sent to DLL 332, which uses the first phase clock signal Phase 1 and the second phase clock signal Phase 2 to generate a dual-frequency clock signal. The dual-frequency clock signal is twice the frequency of the master clock signal clk_m. In this example, an OR gate within DLL 332 uses the first phase clock signal Phase 1 and the second phase clock signal Phase 2 to generate the dual-frequency clock signal. This dual-frequency clock, or a division from frequency divider 330, is selected based on the chosen target frequency and then used as a reference for DLL 332.

[0072] Within DLL 332, the signal referred to below as "clock" represents the master clock clk_m multiplied by 2, while the signal referred to below as "clock_del" is a copy of the clock delayed by one frequency cycle. clock and clock_del are transmitted via a phase frequency detector. Node Vc is then charged or discharged via a charge pump based on the phase error polarity. A control voltage is directly fed to control the delay of each individual delay unit within DLL 332 until the total delay of DLL 332 is exactly one cycle.

[0073] DLL 332 controls the rising edges of the first phase clock signal Phase 1 and the second phase clock signal Phase 2 to be synchronized with the rising edges of the dual-frequency clock signal. DLL 332 adjusts the frequencies and duty cycles of the first phase clock signal Phase 1 and the second phase clock signal Phase 2 in response to the corresponding frequency reference signal and duty cycle control signal to generate the first phase output signal Phase A and the second phase output signal Phase B to drive the H-bridge or inverter to generate the AC drive signal to drive the ultrasonic transducer.

[0074] PMIC 300 includes a first phase output signal terminal PHASE_A that outputs a first phase output signal Phase A to the H-bridge circuit and a second phase output signal terminal PHASE_B that outputs a second phase output signal Phase B to the H-bridge circuit.

[0075] In this example, DLL 332 adjusts the duty cycle of the first phase clock signal Phase 1 and the second phase clock signal Phase 2 in response to the duty cycle control signal by changing the delay of each delay line in DLL 332 in response to the duty cycle control signal.

[0076] Clocks are used at twice their frequency because this ensures better accuracy. For example... Figure 5 As shown, for illustrative purposes, if the master clock frequency clk_m is used (which is not the case in the example of this disclosure), Phase A is synchronized with the rising edge R of the clock, while Phase B is synchronized with the falling edge F of the clock. The delay line of DLL 332 controls the rising edge R, and therefore for the falling edge F, the PWM generator system 329 will need to rely on a perfect match of the delay unit of DLL 332, which may be imperfect. However, to eliminate this error, the PWM generator system 329 uses a dual-frequency clock, such that both Phase A and Phase B are synchronized with the rising edge R of the dual-frequency clock.

[0077] To execute duty cycles from 20% to 50% in 2% increments, the delay line of the DLL 332 comprises 25 delay units, where the output of each corresponding delay unit represents phase n. Ultimately, the phase of the final delay unit's output will correspond to the input clock. Given that all delays are nearly identical, a specific duty cycle is obtained by utilizing the output of a specific delay unit with simple logic within the digital core 316.

[0078] It is important to note the startup of DLL 332, as DLL 332 may not lock the delay period, but instead lock two or more periods, leading DLL 332 into the non-convergent region. To avoid this problem, a startup circuit is implemented in the PWM generator system 329, which allows DLL 332 to start from known and deterministic conditions. Furthermore, the startup circuit allows DLL 332 to start with minimal delay.

[0079] In the example of this disclosure, the frequency range covered by the PWM generator system 329 is extended, and therefore the delay unit in DLL 332 can provide delays from 4ns (for a 5MHz oscillator frequency) to 400ns (for a 50kHz oscillator frequency). To accommodate these different delays, a capacitor Cb is included in the PWM generator system 329, wherein the capacitor value is selected to provide the desired delay.

[0080] Phase A and Phase B are output from DLL 332 and transmitted to bridge IC 301 via digital I / O, so that Phase A and Phase B can be used to control the operation of bridge IC 301.

[0081] The battery charging function of the driver device 202 will now be described in more detail. The battery charging subsystem includes a charger circuit 317 embedded in the PMIC 300 and controlled by a digital charging controller hosted in the PMIC 300. The charger circuit 317 is controlled by the microcontroller 303 via a communication bus 302. The battery charging subsystem is capable of charging individual lithium polymer (LiPo) or lithium-ion (Li-ion) batteries.

[0082] In this example, the battery charging subsystem is capable of charging one or more batteries using a charging current of up to 1A from a 5V power source (e.g., USB power). The battery charging parameters can be adjusted by programming one or more of the following parameters via the communication bus 302 (I2C interface): ● The charging voltage can be set between 3.9V and 4.3V in 100mV increments.

[0083] ● The charging current can be set in 50mA increments between 150mA and 1000mA.

[0084] ● The pre-charge current is 1 / 10 of the charging current.

[0085] ● The pre-charge and fast charge timeouts can be set between 5 minutes and 85 minutes, and between 20 minutes and 340 minutes, respectively.

[0086] ●Optionally, an external negative temperature coefficient (NTC) thermistor can be used to monitor the battery temperature.

[0087] In some examples, the battery charging subsystem reports one or more of the following events by triggering an interrupt to the host microcontroller 303: ● Battery detected ● The battery is charging. ●Battery fully charged ●Battery not present ● Charging timeout reached ●Charge supply is below undervoltage limit The main advantage of embedding the charger circuit 317 within the PMIC 300 is that it allows all listed programming options and event indications to be implemented within the PMIC 300, ensuring the safe operation of the battery charging subsystem. Furthermore, significant manufacturing cost and PCB space savings are achieved compared to conventional resonant circuit devices (such as mist inhaler devices) that include discrete components of the charging system mounted separately on a PCB. The charger circuit 317 also allows for highly versatile settings of charging current and voltage, various fault timeouts, and a large number of event flags for detailed condition analysis.

[0088] The analog-to-digital converter (ADC) 318 will now be described in more detail. The inventors had to overcome significant technical challenges in integrating the ADC 318 with the high-speed oscillator 315 within the PMIC 300. Furthermore, integrating the ADC 318 within the PMIC 300 deviates from the conventional approach in the art that relies on using one of the many discrete ADC devices available in the IC market.

[0089] In this example, the ADC 318 samples at least one parameter within the ultrasonic transducer driver chip (PMIC 300) at a sampling rate equal to the frequency of the master clock signal clk_m. In this example, the ADC 318 is a 10-bit analog-to-digital converter that can offload digital sampling from the microprocessor 303 to save microprocessor 303 resources. Integrating the ADC 318 within the PMIC 300 also avoids the need for an I2C bus, which would otherwise slow down the ADC's sampling capabilities (conventional devices rely on the I2C bus to transfer data between a dedicated discrete ADC and the microcontroller at a limited clock speed typically up to 400kHz).

[0090] In the examples disclosed herein, the ADC 318 may sample one or more of the following parameters sequentially: i. The root-mean-square (RMS) current signal received at the ultrasonic transducer driver chip (PMIC 300) from the external inverter circuit driving the ultrasonic transducer. In this example, this parameter is the RMS current reported by the bridge IC 301. Sensing the RMS current is important for implementing the feedback loop used to drive the ultrasonic transducer 215. The ADC 318 is able to sense the RMS current directly from the bridge IC 301 via a signal with minimal or no hysteresis because the ADC 318 does not rely on this information transmitted via the I2C bus. This provides significant speed and accuracy benefits compared to conventional devices constrained by the relatively low speed of the I2C bus.

[0091] ii. Voltage of the battery connected to the PMIC 300.

[0092] iii. Voltage of the charger connected to the PMIC 300.

[0093] iv. Temperature signals, such as temperature signals indicating the temperature of the PMIC 300 chip. As described above, since the temperature sensor 314 is embedded in the same IC as the oscillator 315, the temperature can be measured very accurately. For example, if the PMIC 300 temperature rises, the current, frequency, and PWM are regulated by the PMIC 300 to control the transducer oscillation, which in turn controls the temperature.

[0094] v. Two external pins.

[0095] vi. An external NTC temperature sensor for monitoring battery pack temperature.

[0096] In some examples, the ADC 318 samples one or more of the sources described above sequentially, for example, in a cyclic scheme. The ADC 318 samples the sources at high speeds, such as the speed of an oscillator 315 up to 5 MHz or up to 105 MHz.

[0097] In some examples, device 202 is configured such that the user or manufacturer of the device can specify how many samples should be taken from each source for averaging. For example, the user can configure the system to take 512 samples from the RMS current input, 64 samples from the battery voltage, 64 samples from the charger input voltage, 32 samples from the external pin, and 8 samples from the NTC pin. Furthermore, the user can specify whether one of the aforementioned sources should be skipped.

[0098] In some examples, for each source, the user can specify two numerical thresholds that divide the entire range into multiple zones, such as three zones. Subsequently, when a sampled value changes a zone, for example, from zone 2 to zone 3, the user can configure the system to release the interrupt.

[0099] There are currently no commercially available conventional ICs that can perform the aforementioned features of the PMIC 300. Such flexibility and granularity in sampling are extremely important when driving resonant circuits or components, such as ultrasonic transducers.

[0100] In this example, the PMIC 300 includes 8 general purpose digital input / output (GPIO) ports. Each port can be configured as both a digital input and a digital output. Some ports also have analog input functionality, such as... Figure 6 As shown in the table below.

[0101] The GPIO7-GPIO5 ports of the PMIC 300 can be used to set the device address on the I2C communication bus 302. Subsequently, eight identical devices can be used on the same I2C bus. This is a unique feature in the IC industry because it allows eight identical devices to be used on the same I2C bus without any address conflicts. This is achieved by reading the status of GPIO7-GPIO5 for each device during the first 100µs after the PMIC 300 starts up and internally storing that portion of the address in the PMIC 300. After the PMIC 300 has started up, the GPIOs can be used for any other purpose.

[0102] As described above, the PMIC 300 includes a six-channel LED driver 320. In this example, the LED driver 320 includes a 5V-tolerant N-channel metal-oxide-semiconductor (NMOS) current source. The LED driver 320 is configured to set the LED current at four discrete levels: 5mA, 10mA, 15mA, and 20mA. The LED driver 320 is configured to dim each LED channel using a 12-bit PWM signal with or without gamma correction. The LED driver 320 is configured to vary the PWM frequency from 300Hz to 1.5kHz. This feature is unique in the field of resonant circuit devices, such as ultrasonic mist inhaler devices, because this functionality is embedded as a subsystem of the PMIC 300.

[0103] In this example, PMIC 300 includes two independent 6-bit digital-to-analog converters (DACs) 327 and 328 incorporated within PMIC 300. The purpose of DACs 327 and 328 is to output analog voltages to manipulate the feedback path of an external regulator, such as a DC-DC boost converter 305, a buck converter, or an LDO. Furthermore, in some examples, DACs 327 and 328 can also be used to dynamically adjust the overcurrent shutdown level of bridge IC 301, as described below.

[0104] The output voltage of each DAC 327, 328 can be programmed between 0V and 1.5V or between 0V and V_battery (Vbat). In this example, the control of the DAC output voltage is accomplished via I2C commands. Integrating two DACs into the PMIC 300 is unique and will allow for dynamic monitoring and control of the current. If either DAC 327, 328 were an external chip, the speed would fall under the same speed constraints due to the I2C protocol. If all these embedded features are in the PMIC, the active power monitoring arrangement of device 202 operates with optimal efficiency. If they are external components, the active power monitoring arrangement would be completely inefficient.

[0105] Now refer to the attached diagram. Figure 7 Bridge IC 301 is a microchip that includes an embedded power switch circuit 333. In this example, the power switch circuit 333 is an H-bridge circuit 334, which... Figure 8 The following is a detailed description of the H-bridge circuit 334, as shown in the figure. However, it should be understood that other examples of bridge IC 301 may incorporate alternative power switching circuitry into the H-bridge circuit 334, provided that the power switching circuitry performs an equivalent function for generating AC drive signals to drive the ultrasonic transducer 215.

[0106] Bridge IC 301 includes a first phase terminal PHASE A that receives a first phase output signal Phase A from the PWM signal generator subsystem of PMIC 300. Bridge IC 301 also includes a second phase terminal PHASE B that receives a second phase output signal Phase B from the PWM signal generator subsystem of PMIC 300.

[0107] Bridge IC 301 includes a current sensor 335 that directly senses the current flow in the H-bridge circuit 334 and provides a root-mean-square (RMS) current output signal via the RMS_CURR pin of Bridge IC 301. The current sensor 335 is configured for overcurrent monitoring to detect when the current flowing in the H-bridge circuit 334 exceeds a predetermined threshold. The integration of the power switching circuit 333, including the H-bridge circuit 334 and the current sensor 335, into the same embedded circuitry of Bridge IC 301 is a unique combination in the IC market. Currently, no other integrated circuit in the IC market includes an H-bridge with embedded circuitry for sensing the RMS current flowing through the H-bridge.

[0108] Bridge IC 301 includes a temperature sensor 336, which includes over-temperature monitoring. Temperature sensor 336 is configured to shut down or disable at least a portion of bridge IC 301 if it detects that bridge IC 301 is operating at a temperature above a predetermined threshold. Therefore, temperature sensor 336 provides an integrated safety function that prevents damage to bridge IC 301 or other components within driver device 202 in the event of bridge IC 301 operating at excessively high temperatures.

[0109] Bridge IC 301 includes a digital state machine 337, which is integrally connected to power switching circuit 333. Digital state machine 337 receives phase A and phase B signals from PMIC 300 and, for example, an ENABLE signal from microcontroller 303. Digital state machine 337 generates timing signals based on the first phase output signal Phase A and the second phase output signal Phase B.

[0110] Digital state machine 337 outputs timing signals corresponding to phase A and phase B signals, as well as BRIDGE PR and BRIDGE EN signals, to power switching circuit 333 to control power switching circuit 333. Digital state machine 337 then outputs timing signals to switches T1-T4 of H-bridge circuit 334 to control switches T1-T4 to turn on and off sequentially, causing H-bridge circuit to output AC drive signals for driving resonant circuits such as ultrasonic transducers 215.

[0111] As described in more detail below, the switching sequence includes a free-floating period in which the first switch T1 and the second switch T1 are off, and the third switch T3 and the fourth switch T4 are on, in order to dissipate the energy stored by the resonant circuit (ultrasonic transducer 215).

[0112] Bridge IC 301 includes a test controller 338, which enables bridge IC 301 to be tested to determine whether the embedded components within bridge IC 301 are operating correctly. Test controller 338 is coupled to the TEST_DATA, TEST_CLK, and TEST_LOAD pins, allowing bridge IC 301 to be connected to an external control device that feeds data into and out of bridge IC 301 to test its operation. Bridge IC 301 also includes a TEST BUS, which enables the digital communication bus within bridge IC 301 to be tested via the TST_PAD pin.

[0113] Bridge IC 301 includes a power-on reset circuit (POR) 339, which controls the startup operation of Bridge IC 301. POR 339 ensures that Bridge IC 301 starts properly only if the supply voltage is within a predetermined range. If the supply voltage is outside the predetermined range, for example, if the supply voltage is too high, POR 339 delays the startup of Bridge IC 301 until the supply voltage is within the predetermined range.

[0114] Bridge IC 301 includes a reference block (BG) 340, which provides a precise reference voltage used by other subsystems of Bridge IC 301.

[0115] Bridge IC 301 includes a current reference 341 that provides accurate current to power switching circuit 333 and / or other subsystems within bridge IC 301, such as current sensor 335.

[0116] Temperature sensor 336 continuously monitors the temperature of the silicon in bridge IC 301. If the temperature exceeds a predetermined temperature threshold, the power switch circuit 333 is automatically cut off. Additionally, an over-temperature report can be sent to an external host to notify it of the over-temperature event.

[0117] The digital state machine (FSM) 337 generates timing signals for the power switching circuit 333, which in this example are timing signals for controlling the H-bridge circuit 334.

[0118] Bridge IC 301 includes comparators 342 and 343, which compare signals from various subsystems of Bridge IC 301 with voltage and current references 340 and 341, and provide reference output signals via pins of Bridge IC 301.

[0119] See the attached diagram again. Figure 8 The example H-bridge circuit 334 includes four switches in the form of NMOS field-effect transistors (FETs) on both sides of the H-bridge circuit 334. The H-bridge circuit 334 includes four switches or transistors T1-T4 connected in an H-bridge configuration, wherein each transistor T1-T4 is driven by a corresponding logic input AD. Transistors T1-T4 are configured to be driven by a bootstrap voltage, which is utilized using... Figure 8 The two external capacitors Cb shown are generated internally.

[0120] The H-bridge circuit 334 includes various power input and output terminals connected to corresponding pins of the bridge IC 301. The H-bridge circuit 334 receives a programmable voltage VBOOST output from the boost converter 305 via a first power supply terminal. Figure 8 The middle part is marked VBOOST. The H-bridge circuit 334 includes a second power supply terminal, in Figure 8 It is marked as VSS_P.

[0121] The H-bridge circuit 334 includes output terminals OUTP and OUTN, which are configured to be connected to the corresponding terminals of the ultrasonic transducer 215, so that the AC drive signal output from the H-bridge circuit 334 can drive the ultrasonic transducer 215.

[0122] The switching of the four switches or transistors T1-T4 is controlled by switching signals from the digital state machine 337 via the logic input AD. It should be understood that, although... Figure 8 Four transistors T1-T4 are shown, but in other examples, the H-bridge circuit 334 incorporates a larger number of transistors or other switching components to achieve the function of an H-bridge.

[0123] In this example, the H-bridge circuit 334 operates with switching power from 22W to 50W to deliver an AC drive signal with sufficient power to optimally drive the ultrasonic transducer 215 at or near its resonant frequency. The voltage switched by the H-bridge circuit 334 in this example is ±15V. In other examples, the voltage is ±20V.

[0124] In this example, the H-bridge circuit 334 switches at frequencies from 3 MHz to 5 MHz or up to 105 MHz. This is a high switching speed compared to conventional integrated circuit H-bridges available in the IC market. For example, conventional integrated circuit H-bridges available in the IC market today are configured to operate at a maximum frequency of only 2 MHz. Apart from the bridge IC 301 described herein, none of the conventional integrated circuit H-bridges available in the IC market can operate at frequencies up to 5 MHz (let alone up to 105 MHz) with power from 22 V to 50 V.

[0125] Now refer to the attached diagram. Figure 9 The current sensor 335 includes a positive current sensing resistor RshuntP and a negative current sensing resistor RshuntN connected in series with the corresponding high and low sides of the H-bridge circuit 334, such as Figure 8As shown. The current sensing resistors RshuntP and RshuntN are low-value resistors, which are 0.1Ω in this example. The current sensor 335 includes a first voltage sensor in the form of a first operational amplifier 344 and a second voltage sensor in the form of a second operational amplifier 345. The first voltage sensor measures the voltage drop across the first current sensor resistor RshuntP, and the second voltage sensor measures the voltage drop across the second current sensor resistor RshuntN. In this example, the gain of each operational amplifier 344, 345 is 2V / V. In this example, the output of each operational amplifier 344, 345 is 1mA / V. The current sensor 335 includes a pull-down resistor Rcs, which is 2kΩ in this example. The outputs of the operational amplifiers 344, 345 provide an output CSout, which passes through a low-pass filter 346 to remove transients in the signal CSout. The output Vout of the low-pass filter 346 is the output signal of the current sensor 335.

[0126] The current sensor 335 therefore measures the AC current flowing through the H-bridge circuit 334 and the ultrasonic transducer 215, respectively. The current sensor 335 converts the AC current into an equivalent root-mean-square output voltage (Vout) relative to ground. The current sensor 335 has a high bandwidth capability because the H-bridge circuit 334 can operate at frequencies up to 5 MHz, or in some examples up to 105 MHz. The output Vout of the current sensor 335 reports a positive voltage equivalent to the measured AC root-mean-square current flowing through the ultrasonic transducer 215. In this example, the output voltage Vout of the current sensor 335 is fed back to the control circuitry within the bridge IC 301 so that the bridge IC 301 can turn off the H-bridge circuit 334 if the current flowing through the H-bridge circuit 334 and therefore through the transducer 215 exceeds a predetermined threshold. Additionally, an overcurrent threshold event is reported to a first comparator 342 in the bridge IC 301, allowing the bridge IC 301 to report the overcurrent event via its OVC_TRIGG pin.

[0127] Now refer to the attached diagram. Figure 10 The control of the H-bridge circuit 334 will now be described with reference to the equivalent piezoelectric model of the ultrasonic transducer 215.

[0128] To generate a positive voltage across the output terminals OUTP and OUTN of the H-bridge circuit 334, such as Figure 10 As indicated by V_out (note the direction of the arrow), the switching sequence of transistors T1-T4 via the input AD is as follows: 1. Positive output voltages across ultrasonic transducer 215: A-ON, B-OFF, C-OFF, D-ON 2. Transition from positive output voltage to zero: A-OFF, B-OFF, C-OFF, D-ON. During this transition, if there is a switching error or delay in A, C is first disconnected to minimize or avoid power loss by minimizing or avoiding the current flowing through A and C.

[0129] 3. Zero Output Voltage: A-OFF, B-OFF, C-ON, D-ON. During this zero output voltage phase, the output terminals OUTP and OUTN of the H-bridge circuit 334 are grounded through the continuously connected C and D switches. This dissipates the energy stored in the capacitors of the equivalent circuit of the ultrasonic transducer, minimizing voltage overshoot in the switching waveform voltage applied to the ultrasonic transducer.

[0130] 4. Transition from zero to negative output voltage: A-OFF, B-OFF, C-ON, D-OFF.

[0131] 5. Negative output voltages across ultrasonic transducer 215: A-OFF, B-ON, C-ON, D-OFF At high frequencies of up to 5 MHz or even up to 105 MHz, it should be understood that the duration of each part of the switching sequence is extremely short, on the order of nanoseconds or picoseconds. For example, at a switching frequency of 6 MHz, each part of the switching sequence occurs within approximately 80 ns.

[0132] In the attached diagram Figure 11 The diagram shows the output voltages OUTP and OUTN of the H-bridge circuit 334 according to the switching sequence described above. The zero output voltage portion of the switching sequence is included to accommodate the energy stored by the ultrasonic transducer 215 (e.g., energy stored by the capacitor in the equivalent circuit of the ultrasonic transducer). As described above, this minimizes voltage overshoot in the switching waveform voltage applied to the ultrasonic transducer, and thus minimizes unnecessary power dissipation and heating in the ultrasonic transducer.

[0133] By preventing the transistors from being subjected to voltages exceeding their rated voltage, minimizing or eliminating voltage overshoot also reduces the risk of damaging the transistors in bridge IC 301. Furthermore, minimizing or eliminating voltage overshoot allows bridge IC 301 to accurately drive the ultrasonic transducer in a manner that minimizes disruption to the current sensing feedback loop described herein. Therefore, bridge IC 301 can drive the ultrasonic transducer at high power levels of 22W to 50W or even up to 70W at high frequencies up to 5MHz or even up to 105MHz.

[0134] The bridge IC 301 in this example is configured to be controlled by the PMIC 300 to operate in two different modes (referred to herein as forced mode and intrinsic frequency mode). These two operating modes are novel compared to existing bridge ICs. In particular, the intrinsic frequency mode is a major innovation, offering significant benefits in terms of accuracy and efficiency in driving ultrasonic transducers compared to conventional devices.

[0135] Forced Frequency Mode (FFM) In forced frequency mode, the H-bridge circuit 334 is controlled in the aforementioned sequence but at a user-selectable frequency. Therefore, regardless of the inherent resonant frequency of the ultrasonic transducer 215, the H-bridge transistors T1-T4 are controlled in a forced manner to switch the output voltage across the ultrasonic transducer 215. Thus, forced frequency mode allows the H-bridge circuit 334 to drive the ultrasonic transducer 215, which has a resonant frequency f1, at different frequencies f2.

[0136] Driving an ultrasonic transducer at a frequency different from its resonant frequency may be suitable to adapt operation to different applications. For example, driving the ultrasonic transducer at a frequency slightly deviating from its resonant frequency may be appropriate (for mechanical reasons to prevent mechanical damage to the transducer). Alternatively, driving the ultrasonic transducer at a low frequency may be appropriate, but ultrasonic transducers have different inherent resonant frequencies due to their size.

[0137] The driver device 202 controls the bridge IC 301 to drive the ultrasonic transducer 215 in a forced frequency mode in response to the configuration of the driver device 202 for a specific application or a specific ultrasonic transducer. For example, the driver device 202 may be configured to operate in forced frequency mode when the resonant circuit device 201 is used for a specific application, such as generating a mist from a liquid containing a specific viscosity of a drug for delivery to a user.

[0138] Inherent Frequency Mode (NFM) The following inherent frequency operating mode is a significant development and offers improved accuracy and efficiency benefits compared to conventional ultrasonic drivers currently available on the IC market.

[0139] The inherent frequency operating mode follows the same switching sequence as described above, but the timing of the zero-output portion of this sequence is adjusted to minimize or avoid problems that may arise due to current spikes in forced frequency mode operation. These current spikes occur when the voltage across the ultrasonic transducer 215 is switched to its opposite polarity. Ultrasonic transducers including piezoelectric crystals have an equivalent circuit incorporating capacitors connected in parallel (e.g., see...). Figure 10 (referring to the piezoelectric model in the text). If the voltage across the ultrasonic transducer is hard-switched from positive to negative, a large current may flow as the energy stored in the capacitor dissipates due to the high dV / dt.

[0140] The inherent frequency mode avoids a hard switch (and vice versa) of the voltage across the ultrasonic transducer 215 from positive to negative. Instead, the ultrasonic transducer 215 (piezoelectric crystal) is allowed to float freely before the reverse voltage is applied, with zero voltage applied across its terminals during the free-float period. The PMIC 300 sets the drive frequency of the bridge IC 301, causing the bridge 334 to set the free-float period, such that the current flow inside the ultrasonic transducer 215 (due to the energy stored within the piezoelectric crystal) reverses the voltage across the terminals of the ultrasonic transducer 215 during the free-float period.

[0141] Therefore, when the H-bridge circuit 334 applies a negative voltage to the terminals of the ultrasonic transducer 215, the ultrasonic transducer 215 (the capacitor in the equivalent circuit) has been reverse-charged and no current spike occurs because there is no high dV / dt.

[0142] However, it should be understood that when the ultrasonic transducer 215 is first activated, the charge within the ultrasonic transducer 215 (piezoelectric crystal) requires time to accumulate. Therefore, the ideal situation where the energy within the ultrasonic transducer 215 is reversed during the free-floating period only occurs after the oscillation within the ultrasonic transducer 215 has accumulated charge. To accommodate this, when the bridge IC 301 first activates the ultrasonic transducer 215, the PMIC 300 controls the power delivered to the ultrasonic transducer 215 via the H-bridge circuit 334 to a first value (e.g., 5V) that is low. The PMIC 300 then controls the power delivered to the ultrasonic transducer 215 via the H-bridge circuit 334 to increase to a second value (e.g., 15V) above the first value over a certain period of time in order to accumulate the energy stored within the ultrasonic transducer 215. Current spikes still occur during this ramp of oscillation until the current inside the ultrasonic transducer 215 has fully developed. However, by using a low initial voltage at startup, those current spikes are kept low enough to minimize their impact on the operation of the ultrasonic transducer 215.

[0143] To achieve the inherent frequency mode, the driver device 202 precisely controls the frequency of the oscillator 315 and the duty cycle (the ratio of on-time to free-float time) of the AC drive signal output from the H-bridge circuit 334. In this example, the driver device 202 executes three control loops to adjust the oscillator frequency and duty cycle, ensuring that the voltage reversal at the terminals of the ultrasonic transducer 215 is as precise as possible, and that current spikes are minimized or avoided as much as possible. This precise control of the oscillator and duty cycle using control loops represents a significant advancement in the field of IC ultrasonic drivers.

[0144] During the inherent frequency operating mode, the current sensor 335 senses the current flowing through the ultrasonic transducer 215 (resonant circuit) during the free float period. When the current sensor 335 senses that the current flowing through the ultrasonic transducer 215 (resonant circuit) during the free float period is zero, the digital state machine 337 adjusts the timing signal to turn on the first switch T1 or the second switch T2.

[0145] The attached diagram Figure 12 The diagram shows oscillator voltage waveform 347 (V(osc)), switching waveform 348 generated by turning on and off the left-hand high switch T1 of the H-bridge circuit 334, and switching waveform 349 generated by turning on and off the right-hand high switch T2 of the H-bridge circuit 334. During the intermediate free-float period 350, both high switches T1 and T2 of the H-bridge circuit 334 are turned off (free-float phase). The duration of the free-float period 350 is controlled by the magnitude of the free-float control voltage 351 (Vphioff).

[0146] The attached diagram Figure 13 The voltage waveform 352 at the first terminal of the ultrasonic transducer 215 (which is inverted at the second terminal of the ultrasonic transducer 215) and the piezoelectric current 353 flowing through the ultrasonic transducer 215 are shown. The piezoelectric current 353 represents a (nearly) ideal sine wave (which is never possible in forced frequency mode or in any bridge in the IC market).

[0147] Before the sinusoidal wave of the piezoelectric current 353 reaches zero, the high-side switch T1 on the left side of the H-bridge circuit 334 is turned off (here, switch T1 is turned off when the piezoelectric current 353 is approximately 6A). The remaining piezoelectric current 353 flowing within the ultrasonic transducer 215 (the capacitor of the piezoelectric equivalent circuit) due to the energy stored in it is responsible for the voltage reversal during the free-float period 350. The piezoelectric current 353 decays to zero during the free-float period 350 and then enters the negative current flow domain. The terminal voltage at the ultrasonic transducer 215 drops from the supply voltage (19V in this case) to less than 2V, and this drop stops when the piezoelectric current 353 reaches zero. This is the ideal time to turn on the low-side switch T3 of the H-bridge circuit 334 to minimize or avoid current spikes.

[0148] Compared with the forced frequency modes mentioned above, the intrinsic frequency modes have at least three advantages: 1. Current spikes associated with hard switching of packaged capacitors are significantly reduced or completely avoided.

[0149] 2. It almost eliminates power loss caused by hard switching.

[0150] 3. The frequency is regulated by the control loop and will be kept close to the resonance of the piezoelectric crystal (i.e., the inherent resonant frequency of the piezoelectric crystal).

[0151] In the case of frequency regulation via a control loop (advantage 3 above), the PMIC 300 initiates operation by driving the ultrasonic transducer 215 at a frequency higher than the resonant frequency of the piezoelectric crystal via the control bridge IC 301. The PMIC 300 then controls the bridge IC 301 to cause the frequency of the AC drive signal to decay / decrease during startup. Once the frequency approaches the resonant frequency of the piezoelectric crystal, the piezoelectric current will rapidly increase / grow. Once the piezoelectric current is high enough to cause the desired voltage reversal, the frequency decay / decrease is stopped by the PMIC 300. The control loop of the PMIC 300 then takes over the regulation of the frequency and duty cycle of the AC drive signal.

[0152] In the forced frequency mode, the power delivered to the ultrasonic transducer 215 is controlled by the duty cycle and / or frequency shift and / or by changing the supply voltage. However, in this example, in the inherent frequency mode, the power delivered to the ultrasonic transducer 215 is controlled solely by the supply voltage.

[0153] In this example, during the setup phase of the driver device's operation, bridge IC 301 is configured to measure the length of time it takes for the current flowing through ultrasonic transducer 215 (resonant circuit) to drop to zero when the first switch T1 and the second switch T2 are open and the third switch T3 and the fourth switch T4 are closed. Bridge IC 301 then sets the length of the free-float period to be equal to the measured length of time.

[0154] Now refer to the attached diagram. Figure 14 In this example, the PMIC 300 and Bridge IC 301 are designed to work together as a companion chipset. The PMIC 300 and Bridge IC 301 are electrically connected to communicate with each other. In this example, an interconnect exists between the PMIC 300 and Bridge IC 301, which enables the following two categories of communication: 1. Control signals 2. Feedback signal The connection between the PHASE_A and PHASE_B pins of PMIC 300 and bridge IC 301 carries the PWM modulation control signal that drives the H-bridge circuit 334. The connection between the EN_BR pin of PMIC 300 and bridge IC 301 carries the EN_BR control signal that triggers the start of the H-bridge circuit 334. The timing between the PHASE_A, PHASE_B, and EN_BR control signals is critical and is handled by the digital bridge control of PMIC 300.

[0155] The connections between the CS, OC, and OT pins of PMIC 300 and bridge IC 301 carry the CS (current sensing), OC (overcurrent), and OT (overheating) feedback signals back to PMIC 300 from bridge IC 301. Most notably, the CS (current sensing) feedback signal includes a voltage equivalent to the root-mean-square current flowing through ultrasonic transducer 215, which is measured by current sensor 335 of bridge IC 301.

[0156] The OC (overcurrent) and OT (overtemperature) feedback signals are digital signals that indicate to the bridge IC 301 that an overcurrent or overvoltage event has been detected. In this example, external resistors are used to set the overcurrent and overtemperature thresholds. Alternatively, the thresholds can be set dynamically in response to a signal delivered from one of the two DAC channels VDAC0 and VDAC1 from the PMIC 300 to the OC_REF pin of the bridge IC 301.

[0157] In this example, the design of the PMIC 300 and bridge IC 301 allows the pins of these two integrated circuits to be directly connected to each other (e.g., via copper traces on the PCB) to minimize or eliminate hysteresis in signal communication between the PMIC 300 and bridge IC 301. This provides a significant speed advantage over conventional bridges in the IC market, which are typically controlled by signals via digital communication buses. For example, the standard I2C bus is only clocked at 400kHz, which is too slow for transmitting data sampled at high clock speeds of up to 5MHz, as in the example of this disclosure.

[0158] While examples of this disclosure have been described above with respect to microchip hardware, it should be understood that other examples of this disclosure include methods for operating the components and subsystems of each microchip to perform the functions described herein. For example, methods for operating the PMIC 300 and bridge IC 301 in a forced frequency mode or an inherent frequency mode.

[0159] Now refer to the attached diagram. Figure 15 The optional OTP IC 242 includes a power-on reset circuit (POR) 354, a bandgap reference (BG) 355, a capless low-dropout regulator (LDO) 356, a communication (e.g., I2C) interface 357, an eFuse (one-time programmable memory) 358, an oscillator 359, and a general-purpose input / output interface 360. The OTP IC 242 also includes a digital core 361, which includes a cryptographic authenticator. In this example, the cryptographic authenticator uses an elliptic curve digital signature algorithm (ECDSA) to encrypt / decrypt data stored within the OTP IC 242, as well as data transmitted to and from the OTP IC 242.

[0160] The POR 354 ensures that the OTP IC 242 starts up properly only if the supply voltage is within the predetermined range. If the supply voltage is outside the predetermined range, the POR 354 resets the OTP IC 242 and waits until the supply voltage is within the predetermined range.

[0161] The BG 355 provides precise reference voltage and current to the LDO 356 and oscillator 359. The LDO 356 powers the digital core 361, the communication interface 357, and the eFuse memory bank 358.

[0162] The OTP IC 242 is configured to operate in at least the following modes: ● Fuse Programming (Fusing): During eFuse programming (programming of the one-time programmable memory), a high current is required to burn the associated fuses within the eFuse memory bank 358. In this mode, a higher bias current is provided to maintain the gain and bandwidth of the regulation loop.

[0163] ● Fuse Read: In this mode, a moderate current level is required to sustain eFuse reads within the eFuse memory bank 358. This mode is executed during the startup of the OTP IC 242 to transfer the fuse contents to the shadow register. In this mode, the gain and bandwidth of the regulation loop are set to lower values ​​than in fusion mode.

[0164] ●Normal Operation: In this mode, the LDO 356 is driven under very low bias current conditions to operate the OTP IC 242 with low power, so that the OTP IC 242 consumes as little power as possible.

[0165] Oscillator 359 provides the necessary clock for the digital core / engine 361 during testing (SCAN test), during fusion, and during normal operation. Oscillator 359 is tuned to meet the stringent timing requirements during fusion mode.

[0166] In this example, communication interface 357 conforms to the FM+ specification of the I2C standard, but it also supports both slow and fast modes. The OTP IC 242 uses communication interface 357 to communicate with driver device 202 (the host) for data and key exchange.

[0167] Digital core 361 implements the control and communication functions of OTP IC 242. The cryptographic authenticator of digital core 361 enables OTP IC 242 to authenticate itself to drive device 202 (e.g., for a specific application) to ensure that OTP IC 242 is authentic and authorized to connect to drive device 202 (or another product), for example, using ECDSA encrypted messages.

[0168] See attached diagram. Figure 16 The OTP IC 242 performs the following PKI process to authenticate the OTP IC 242 for use with a host (e.g., drive device 202): 1. Verify the signer's public key: The host requests to generate a public key and certificate. The host verifies the certificate using the authorized public key.

[0169] 2. Verify device public key: If verification is successful, the host requests the device public key and certificate. The host verifies the certificate using the manufacturing public key.

[0170] 3. Query-Response: If verification is successful, the host creates a random number query and sends it to the device. The final product signs the random number query with the device's private key.

[0171] 4. The signature is sent back to the host for verification using the device's public key.

[0172] If all steps of the authentication process are completed successfully, the chain of trust has been verified back to the root of trust, and the OTP IC242 is successfully authenticated for use with the host. However, if any step of the authentication process fails, the OTP IC 242 is not authenticated for use with the host, and the use of devices incorporating the OTP IC 242 is restricted or blocked.

[0173] The foregoing outlines the features of several examples or embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the various examples or embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered herein without departing from the spirit and scope of this disclosure.

[0174] Although the subject matter has been described in language specific to structural features or methodological actions, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing at least some of the claims.

[0175] This document provides various operations for examples or implementations. The order in which some or all operations are described should not be construed as implying that these operations must be sequentially related. Alternative orderings will be understood as having the benefits of this description. Furthermore, it should be understood that not all operations must be present in every implementation provided herein. Moreover, it should be understood that not all operations are necessary in some examples or implementations.

[0176] Furthermore, “exemplary” is used herein to mean as an example, instance, illustration, etc., and is not necessarily advantageous. As used in this application, “or” is intended to mean an inclusive “or” rather than an exclusive “or.” Additionally, as used in this application and the appended claims, “a” and “an” are generally interpreted as meaning “one or more” unless otherwise specified or clearly indicated from the context as a singular form. Furthermore, “at least one of A and B” generally means A or B or both A and B. Moreover, with regard to the use of “comprising,” “having,” “has,” “with,” or variations thereof, such terms are intended to be inclusive in a manner similar to the term “including.” Furthermore, unless otherwise specified, “first,” “second,” etc., are not intended to imply temporal, spatial, or sequential aspects. Rather, such terms are merely used as identifiers, names, etc., of features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B, or two different or two identical elements, or the same element.

[0177] Furthermore, while this disclosure has been shown and described with respect to one or more embodiments, equivalent changes and modifications will arise for those skilled in the art upon reading and understanding of this specification and the accompanying drawings. This disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, regarding the various functions performed by the foregoing features (e.g., elements, resources, etc.), unless otherwise indicated, the terms used to describe such features are intended to correspond to any feature that performs the specified function of the described feature (e.g., functionally equivalent), even if not structurally equivalent to the disclosed structure. Additionally, while specific features of this disclosure may have been disclosed with respect to only one of several embodiments, such features may be combined with one or more other features of other embodiments, as may be desired and advantageous for any given or particular application.

[0178] Examples or implementations of the subjects and functional operations described herein may be implemented in digital electronic circuits, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations thereof.

[0179] Some examples or implementations use one or more modules of computer program instructions encoded on a computer-readable medium to enable a data processing apparatus to perform or control the operation of the data processing apparatus. The computer-readable medium can be an manufactured product, such as a hard disk drive in a computer system or embedded system. The computer-readable medium can be separately acquired and later encoded with one or more modules of computer program instructions, such as by delivering one or more modules of computer program instructions over a wired or wireless network. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a combination of one or more of these.

[0180] The terms "computing device" and "data processing apparatus" encompass all means, devices, and machines used for processing data, including, for example, programmable processors, computers, or multiple processors or computers. In addition to hardware, the apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, protocol stacks, database management systems, operating systems, runtime environments, or combinations thereof. Furthermore, the apparatus may employ a variety of different computing model infrastructures, such as web services, distributed computing, and grid computing infrastructures.

[0181] The processes and logic flows described in this specification can be executed by one or more programmable processors that execute one or more computer programs to perform functions by manipulating input data and generating output.

[0182] As an example, processors suitable for executing computer programs include both general-purpose and special-purpose microprocessors, as well as any one or more processors in any kind of digital computer. Typically, the processor receives instructions and data from read-only memory or random access memory, or both. The basic components of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include, or be operatively coupled to, one or more mass storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks) for storing data, to receive data from, transfer data to, or both of these mass storage devices. However, a computer need not have such devices. Devices suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices.

[0183] When used in this specification and claims, the terms "comprising" and "including," and their variations thereof, mean to include the specified features, steps, or integers. These terms should not be construed as excluding the presence of other features, steps, or components.

[0184] The invention may also broadly include any and all combinations of parts, elements, steps, examples, and / or features mentioned or indicated individually or collectively in the specification as two or more of the stated parts, elements, steps, examples, and / or features. In particular, one or more features of any embodiment described herein may be combined with one or more features from any other embodiment described herein.

[0185] You may seek protection for any feature disclosed in any one or more of the publications cited herein in conjunction with this disclosure.

[0186] Although certain exemplary embodiments of the invention have been described, the scope of the appended claims is not intended to be limited to these embodiments. The claims should be interpreted literally and intentionally, and / or cover equivalents.

[0187] Representative characteristics Representative features are stated in the following clauses, which are independent or may be combined in any combination with one or more features disclosed in the text of the specification and / or the accompanying drawings.

[0188] 1. A device for emitting ultrasonic waves, the device comprising: A resonant circuit, wherein the resonant circuit is at least one of an LC oscillating circuit, an antenna, and a piezoelectric transducer; An H-bridge circuit is connected to the resonant circuit, wherein the H-bridge circuit is configured to generate an AC drive signal to drive the resonant circuit to generate and emit the ultrasonic waves. A microchip connected to the H-bridge circuit, wherein the microchip is configured to control the H-bridge circuit to generate the AC drive signal, wherein the microchip is a single unit comprising a plurality of interconnected embedded components and subsystems, the plurality of interconnected embedded components and subsystems including: Oscillator, the oscillator being configured to generate: Master clock signal, A first phase clock signal, wherein the first phase clock signal is high at a first time during the positive half-cycle of the master clock signal and low during the negative half-cycle of the master clock signal, and A second phase clock signal, which is high during a second time in the negative half-cycle of the main clock signal and low during the positive half-cycle of the main clock signal, wherein the phases of the first phase clock signal and the second phase clock signal are center-aligned; A pulse width modulation (PWM) signal generator subsystem, the pulse width modulation (PWM) signal generator subsystem comprising: A delay-locked loop (DLL) is configured to generate a dual-frequency clock signal using a first-phase clock signal and a second-phase clock signal, the dual-frequency clock signal being twice the frequency of the master clock signal. The DLL is configured to control the rising edges of the first-phase clock signal and the second-phase clock signal to synchronize with the rising edges of the dual-frequency clock signal. The DLL is also configured to adjust the frequencies and duty cycles of the first-phase clock signal and the second-phase clock signal in response to a driver control signal to generate a first-phase output signal and a second-phase output signal. The first-phase output signal and the second-phase output signal are configured to drive the H-bridge circuit to generate an AC drive signal to drive the resonant circuit. A first phase output signal terminal is configured to output the first phase output signal to the H-bridge circuit. The second phase output signal terminal is configured to output the second phase output signal to the H-bridge circuit. A feedback input terminal is configured to receive a feedback signal from the H-bridge circuit, the feedback signal indicating the operating parameters of the H-bridge circuit or the AC drive signal when the H-bridge circuit drives the resonant circuit with an AC drive signal. An analog-to-digital converter (ADC) subsystem, the analog-to-digital converter (ADC) subsystem comprising: A plurality of ADC input terminals are configured to receive a plurality of corresponding analog signals, wherein one of the plurality of ADC input terminals is connected to the feedback input terminal such that the ADC subsystem receives the feedback signal from the H-bridge circuit, and wherein the ADC subsystem is configured to sample the analog signals received at the plurality of ADC input terminals at a sampling frequency proportional to the frequency of the master clock signal, and the ADC subsystem is configured to generate an ADC digital signal using the sampled analog signals; A digital processor subsystem configured to receive the ADC digital signal from the ADC subsystem and process the ADC digital signal to generate the driver control signal, wherein the digital processor subsystem is configured to transmit the driver control signal to the PWM signal generator subsystem to control the PWM signal generator subsystem; and A digital-to-analog converter (DAC) subsystem, the digital-to-analog converter (DAC) subsystem comprising: A digital-to-analog converter (DAC) configured to convert digital control signals generated by the digital processor subsystem into analog voltage control signals to control a voltage regulator circuit configured to generate a voltage modulated by the H-bridge circuit; and A DAC output terminal is configured to output the analog voltage control signal to control the voltage regulator circuit to generate a predetermined voltage modulated by the H-bridge circuit, so that the H-bridge circuit drives the resonant circuit in response to a feedback signal instructing the operation of the resonant circuit.

[0189] 2. The apparatus according to Clause 1, wherein the oscillator is configured to generate the master clock signal at a frequency of 50 kHz to 105 MHz.

[0190] 3. The apparatus according to Clause 1 or Clause 2, wherein the microchip further comprises: A frequency divider connected to the oscillator to receive the master clock signal from the oscillator, the frequency divider being configured to divide the master clock signal by a predetermined divisor and output a frequency reference signal to the delay-locked loop.

[0191] 4. The apparatus according to any one of the preceding clauses, wherein the delay-locked loop comprises a plurality of delay lines connected end-to-end, wherein the total delay of the delay lines is equal to the period of the master clock signal.

[0192] 5. The apparatus according to Clause 4, wherein the delay-locked loop is configured to adjust the duty cycle of the first phase clock signal and the second phase clock signal in response to the driver control signal by changing the delay of each delay line in the delay-locked loop.

[0193] 6. The apparatus according to any one of the preceding clauses, wherein the feedback input terminal is configured to receive from the H-bridge circuit a feedback signal in voltage form indicating the root mean square current of the AC drive signal driving the resonant circuit.

[0194] 7. The apparatus according to any one of the preceding clauses, wherein the ADC subsystem includes a plurality of additional ADC input terminals configured to receive a feedback signal indicating at least one of a voltage of a battery connected to the apparatus or a voltage of a battery charger connected to the apparatus.

[0195] 8. The apparatus according to any one of the preceding clauses, wherein the microchip further comprises: A temperature sensor is embedded within the microchip, wherein the temperature sensor is configured to generate a temperature signal indicating the temperature of the microchip, and wherein the temperature signal is received by a separate ADC input terminal of the ADC subsystem, and the temperature signal is sampled by the ADC.

[0196] 9. The apparatus according to any one of the preceding clauses, wherein the ADC subsystem is configured to sequentially sample signals received at the plurality of ADC input terminals, wherein each signal is sampled by the ADC subsystem a corresponding predetermined number of times.

[0197] 10. The apparatus according to any one of the preceding clauses, wherein the microchip further comprises: A battery charging subsystem configured to control the charging of an external battery connected to the microchip.

[0198] 11. The apparatus according to any one of the preceding clauses, wherein the DAC subsystem comprises: Another digital-to-analog converter (DAC) is configured to convert another digital control signal generated by the digital processor subsystem into another analog voltage control signal to control the voltage regulator circuit.

[0199] 12. An apparatus for emitting ultrasonic waves, the apparatus comprising: A resonant circuit, wherein the resonant circuit is at least one of an LC oscillating circuit, an antenna, and a piezoelectric transducer; A microchip connected to the resonant circuit, wherein the microchip is a single unit comprising a plurality of interconnected embedded components and subsystems, the plurality of interconnected embedded components and subsystems including: First power terminal; Second power terminal; The H-bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch, wherein: The first switch and the third switch are connected in series between the first power terminal and the second power terminal; The first output terminal is electrically connected between the first switch and the third switch. The second switch and the fourth switch are connected in series between the first power terminal and the second power terminal, and The second output terminal is electrically connected between the second switch and the fourth switch; A first phase terminal is configured to receive a first phase output signal from a pulse width modulation (PWM) signal generator; A second phase terminal is configured to receive a second phase output signal from the PWM signal generator; A digital state machine is configured to generate a timing signal based on a first phase output signal and a second phase output signal, and to output the timing signal to the switches of the H-bridge circuit to control the switches to be turned on and off in sequence, such that the H-bridge circuit outputs an AC drive signal to the resonant circuit to drive the resonant circuit to generate and emit the ultrasonic waves, wherein the sequence includes a free-floating period in which the first and second switches are turned off and the third and fourth switches are turned on in order to dissipate the energy stored by the resonant circuit; A current sensor, comprising: A first current sensing resistor is connected in series between the first switch and the first power terminal; A first voltage sensor is configured to measure the voltage drop across the first current sensing resistor and provide a first voltage output indicating the current flowing through the first current sensing resistor; The second current sensing resistor is connected in series between the second switch and the first power terminal; A second voltage sensor is configured to measure the voltage drop across the second current-sensing resistor and provide a second voltage output indicating the current flowing through the second current-sensing resistor; and A current sensor output terminal is configured to provide a root-mean-square (RMS) output voltage relative to ground, the RMS output voltage being equivalent to both the first voltage output and the second voltage output. The root mean square output voltage indicates the root mean square current flowing through the first switch or the second switch and the current flowing through the resonant circuit, which is connected between the first output terminal and the second output terminal.

[0200] 13. The apparatus according to Clause 12, wherein the H-bridge circuit is configured to output 22W to 50W of power to the resonant circuit connected to the first output terminal and the second output terminal.

[0201] 14. The apparatus according to Clause 12 or Clause 13, wherein the microchip further comprises: A temperature sensor embedded within the microchip, wherein the temperature sensor is configured to measure the temperature of the microchip and disable at least a portion of the microchip if the temperature sensor senses that the temperature of the microchip exceeds a predetermined threshold.

[0202] 15. An apparatus for emitting ultrasonic waves, the apparatus comprising: A resonant circuit, wherein the resonant circuit is at least one of an LC oscillating circuit, an antenna, and a piezoelectric transducer; A first microchip is connected to the resonant circuit, wherein the first microchip is a single unit comprising a plurality of interconnected embedded components and subsystems, the plurality of interconnected embedded components and subsystems including: First power terminal; Second power terminal; The H-bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch, wherein: The first switch and the third switch are connected in series between the first power terminal and the second power terminal; The first output terminal is electrically connected between the first switch and the third switch, and the first output terminal is connected to the first terminal of the resonant circuit. The second switch and the fourth switch are connected in series between the first power terminal and the second power terminal, and The second output terminal is electrically connected between the second switch and the fourth switch, and the second output terminal is connected to the second terminal of the resonant circuit. A first phase terminal is configured to receive a first phase output signal from a pulse width modulation (PWM) signal generator subsystem; A second phase terminal is configured to receive a second phase output signal from the PWM signal generator; A digital state machine is configured to generate a timing signal based on a first phase output signal and a second phase output signal, and to output the timing signal to the switches of the H-bridge circuit to control the switches to be turned on and off in sequence, such that the H-bridge circuit outputs an AC drive signal to the resonant circuit to drive the resonant circuit to generate and emit the ultrasonic waves, wherein the sequence includes a free-floating period in which the first and second switches are turned off and the third and fourth switches are turned on in order to dissipate the energy stored by the resonant circuit; A current sensor, comprising: A first current sensing resistor is connected in series between the first switch and the first power terminal; A first voltage sensor is configured to measure the voltage drop across the first current sensing resistor and provide a first voltage output indicating the current flowing through the first current sensing resistor; The second current sensing resistor is connected in series between the second switch and the first power terminal; A second voltage sensor is configured to measure the voltage drop across the second current-sensing resistor and provide a second voltage output indicating the current flowing through the second current-sensing resistor; and A current sensor output terminal is configured to provide a root-mean-square (RMS) output voltage relative to ground, the RMS output voltage being equivalent to both the first voltage output and the second voltage output. The root mean square (RMS) output voltage indicates the RMS current flowing through the first switch or the second switch and the current flowing through the resonant circuit, which is connected between the first output terminal and the second output terminal; and A second microchip, connected to the first microchip to control the H-bridge circuit to generate the AC drive signal, wherein the second microchip is a single unit comprising multiple interconnected embedded components and subsystems, the multiple interconnected embedded components and subsystems including: Oscillator, the oscillator being configured to generate: Master clock signal, A first phase clock signal, wherein the first phase clock signal is high at a first time during the positive half-cycle of the master clock signal and low during the negative half-cycle of the master clock signal, and A second phase clock signal, which is high during a second time in the negative half-cycle of the main clock signal and low during the positive half-cycle of the main clock signal, wherein the phases of the first phase clock signal and the second phase clock signal are center-aligned; The pulse width modulation (PWM) signal generator subsystem includes: A delay-locked loop (DLL) is configured to generate a dual-frequency clock signal using a first-phase clock signal and a second-phase clock signal, the dual-frequency clock signal being twice the frequency of the master clock signal. The DLL is configured to control the rising edges of the first-phase clock signal and the second-phase clock signal to synchronize with the rising edges of the dual-frequency clock signal. The DLL is also configured to adjust the frequencies and duty cycles of the first-phase clock signal and the second-phase clock signal in response to a driver control signal to generate a first-phase output signal and a second-phase output signal. The first-phase output signal and the second-phase output signal are configured to drive the H-bridge circuit to generate an AC drive signal to drive the resonant circuit. A first phase output signal terminal is configured to output the first phase output signal to the H-bridge circuit. The second phase output signal terminal is configured to output the second phase output signal to the H-bridge circuit. A feedback input terminal is configured to receive a feedback signal from the H-bridge circuit, the feedback signal indicating the operating parameters of the H-bridge circuit or the AC drive signal when the H-bridge circuit drives the resonant circuit with an AC drive signal. An analog-to-digital converter (ADC) subsystem, the analog-to-digital converter (ADC) subsystem comprising: A plurality of ADC input terminals are configured to receive a plurality of corresponding analog signals, wherein one of the plurality of ADC input terminals is connected to the feedback input terminal such that the ADC subsystem receives the feedback signal from the H-bridge circuit, and wherein the ADC subsystem is configured to sample the analog signals received at the plurality of ADC input terminals at a sampling frequency proportional to the frequency of the master clock signal, and the ADC subsystem is configured to generate an ADC digital signal using the sampled analog signals; A digital processor subsystem configured to receive the ADC digital signal from the ADC subsystem and process the ADC digital signal to generate the driver control signal, wherein the digital processor subsystem is configured to transmit the driver control signal to the PWM signal generator subsystem to control the PWM signal generator subsystem; and A digital-to-analog converter (DAC) subsystem, the digital-to-analog converter (DAC) subsystem comprising: A digital-to-analog converter (DAC) configured to convert digital control signals generated by the digital processor subsystem into analog voltage control signals to control a voltage regulator circuit that generates a voltage modulated by the H-bridge circuit; and A DAC output terminal is configured to output the analog voltage control signal to control the voltage regulator circuit to generate a predetermined voltage modulated by the H-bridge circuit, so that the H-bridge circuit drives the resonant circuit in response to a feedback signal instructing the operation of the resonant circuit.

[0203] 16. The apparatus according to clause 15, wherein the apparatus further comprises: A boost converter circuit configured to increase the voltage of a power supply to a boost voltage in response to an analog voltage output signal from the output terminal of the DAC, wherein the boost converter circuit is configured to provide the boost voltage at the first power supply terminal such that the boost voltage is modulated by switching of the switches of the H-bridge circuit.

[0204] 17. The apparatus according to Clause 15 or Clause 16, wherein the current sensor is configured to sense the current flowing through the resonant circuit during the free float period, and the digital state machine is configured to adjust the timing signal to turn on the first switch or the second switch when the current sensor senses that the current flowing through the resonant circuit during the free float period is zero.

[0205] 18. The apparatus according to any one of clauses 15 to 17, wherein, during the setup phase of operation of the apparatus, the second microchip is configured to: When the first and second switches are open and the third and fourth switches are closed, measure the length of time it takes for the current flowing through the resonant circuit to drop to zero; and Set the length of the free float period to be equal to the measured length of time.

Claims

1. A device for emitting ultrasonic waves, the device comprising: A resonant circuit, wherein the resonant circuit is at least one of an LC oscillating circuit, an antenna, and a piezoelectric transducer; An H-bridge circuit is connected to the resonant circuit, wherein the H-bridge circuit is configured to generate an AC drive signal to drive the resonant circuit to generate and emit the ultrasonic waves. A microchip connected to the H-bridge circuit, wherein the microchip is configured to control the H-bridge circuit to generate the AC drive signal, wherein the microchip is a single unit comprising a plurality of interconnected embedded components and subsystems, the plurality of interconnected embedded components and subsystems including: Oscillator, the oscillator being configured to generate: Master clock signal, A first phase clock signal, wherein the first phase clock signal is high at a first time during the positive half-cycle of the master clock signal and low during the negative half-cycle of the master clock signal, and A second phase clock signal, which is high at a second time during the negative half-cycle of the main clock signal and low during the positive half-cycle of the main clock signal, wherein the phases of the first phase clock signal and the second phase clock signal are center-aligned; A pulse width modulation signal generator subsystem, comprising: A delay-locked loop (DLL) is configured to generate a dual-frequency clock signal using a first-phase clock signal and a second-phase clock signal, the dual-frequency clock signal being twice the frequency of the master clock signal. The DLL is configured to control the rising edges of the first-phase clock signal and the second-phase clock signal to synchronize with the rising edges of the dual-frequency clock signal. The DLL is also configured to adjust the frequencies and duty cycles of the first-phase clock signal and the second-phase clock signal in response to a driver control signal to generate a first-phase output signal and a second-phase output signal. The first-phase output signal and the second-phase output signal are configured to drive the H-bridge circuit to generate an AC drive signal to drive the resonant circuit. A first phase output signal terminal is configured to output the first phase output signal to the H-bridge circuit. The second phase output signal terminal is configured to output the second phase output signal to the H-bridge circuit. A feedback input terminal is configured to receive a feedback signal from the H-bridge circuit, the feedback signal indicating the operating parameters of the H-bridge circuit or the AC drive signal when the H-bridge circuit drives the resonant circuit with an AC drive signal. Analog-to-digital converter subsystem, the analog-to-digital converter subsystem comprising: A plurality of analog-to-digital converter (ADC) input terminals are configured to receive a plurality of corresponding analog signals, wherein one of the plurality of ADC input terminals is connected to the feedback input terminal such that the ADC subsystem receives the feedback signal from the H-bridge circuit, and wherein the ADC subsystem is configured to sample the analog signals received at the plurality of ADC input terminals at a sampling frequency proportional to the frequency of the master clock signal, and the ADC subsystem is configured to generate an ADC digital signal using the sampled analog signals; A digital processor subsystem configured to receive analog-to-digital converter (ADC) digital signals from the ADC subsystem and process the ADC digital signals to generate the driver control signals, wherein the digital processor subsystem is configured to transmit the driver control signals to the pulse width modulation (PWM) signal generator subsystem to control the PWM signal generator subsystem; and A digital-to-analog converter subsystem, comprising: A digital-to-analog converter, configured to convert digital control signals generated by the digital processor subsystem into analog voltage control signals to control a voltage regulator circuit, the voltage regulator circuit being configured to generate a voltage modulated by the H-bridge circuit; and A digital-to-analog converter output terminal is configured to output the analog voltage control signal to control the voltage regulator circuit to generate a predetermined voltage modulated by the H-bridge circuit, so that the H-bridge circuit drives the resonant circuit in response to a feedback signal indicating the operation of the resonant circuit.

2. The apparatus according to claim 1, characterized in that: The oscillator is configured to generate the master clock signal with a frequency of 50 kHz to 105 MHz.

3. The apparatus according to claim 1 or claim 2, characterized in that: The microchip also includes: A frequency divider connected to the oscillator to receive the master clock signal from the oscillator, the frequency divider being configured to divide the master clock signal by a predetermined divisor and output a frequency reference signal to the delay-locked loop.

4. The apparatus according to claim 1, characterized in that: The delay-locked loop includes multiple end-to-end connected delay lines, wherein the total delay of the delay lines is equal to the period of the master clock signal.

5. The apparatus according to claim 4, characterized in that: The delay-locked loop is configured to adjust the duty cycle of the first phase clock signal and the second phase clock signal in response to the driver control signal by changing the delay of each delay line in the delay-locked loop.

6. The apparatus according to claim 1, characterized in that: The feedback input terminal is configured to receive a feedback signal from the H-bridge circuit in the form of a voltage, indicating the root mean square current of the AC drive signal driving the resonant circuit.

7. The apparatus according to claim 1, characterized in that: The analog-to-digital converter subsystem includes a plurality of additional analog-to-digital converter input terminals configured to receive a feedback signal indicating at least one of the voltage of a battery connected to the device or the voltage of a battery charger connected to the device.

8. The apparatus according to claim 1, characterized in that: The microchip also includes: A temperature sensor embedded within the microchip, wherein the temperature sensor is configured to generate a temperature signal indicating the temperature of the microchip, and wherein the temperature signal is received by another analog-to-digital converter input terminal of the analog-to-digital converter subsystem, and wherein the temperature signal is sampled by the analog-to-digital converter.

9. The apparatus according to claim 1, characterized in that: The analog-to-digital converter subsystem is configured to sequentially sample signals received at the plurality of analog-to-digital converter input terminals, wherein each signal is sampled by the analog-to-digital converter subsystem a corresponding predetermined number of times.

10. The apparatus according to claim 1, characterized in that: The microchip also includes: A battery charging subsystem configured to control the charging of an external battery connected to the microchip.

11. The apparatus according to claim 1, characterized in that: The digital-to-analog converter subsystem includes: Another digital-to-analog converter is configured to convert another digital control signal generated by the digital processor subsystem into another analog voltage control signal to control the voltage regulator circuit.

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