Power semiconductor device with high turn-off capability and manufacturing method

Abstract

The present application relates to a power semiconductor device with high turn-off capability and a manufacturing method thereof. The power semiconductor device includes at least one unit cell structure, and each unit cell structure includes an anode structure, a base region structure, a cathode structure, and a gate structure stacked in sequence. Among them, the base region structure includes a floating junction region, the doping type of the floating junction region is opposite to that of the base region structure, and the floating junction region is used to divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure. By adding a floating junction region to the base region structure, the current on the path between the anode structure and the cathode structure can be diverted to the region between the cathode structure and the gate structure, thereby reducing the lateral base voltage drop at the outer edge of the cathode structure, achieving the effect of rapid commutation between the cathode structure and the gate structure, and further effectively improving the turn-off capability of the power semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a power semiconductor device with high turn-off ability and a manufacturing method thereof. Background Art

[0002] In the power system, the reliable DC transmission of long-distance and large-capacity electric energy is one of the key problems to be urgently solved. In the fields of smart grid, new energy, and industrial current conversion and other high-power medium and high-voltage application systems where circuit miniaturization and integration are relatively common, a gate-commutated thyristor (GCT) with low on-state loss, fast switching speed, small switching loss, and strong current-carrying capacity is generally used as a fully-controlled power electronic switching device.

[0003] An important criterion for measuring the performance of GCT devices is the turn-off ability. The criterion for measuring the turn-off ability is whether the cathode current can be reduced to less than one-tenth of the turn-off current during turn-off, so as to avoid re-triggering and resulting in turn-off failure. However, the existing technologies for improving the turn-off ability of GCTs are relatively scarce. Among them, a corrugated base structure effectively improves the turn-off ability of GCTs. However, under the current stringent requirements of high blocking voltage and large turn-off current, the effect of the corrugated base structure in improving the turn-off ability gradually approaches the upper limit.

[0004] Therefore, how to further improve the turn-off ability of power semiconductor devices has become an urgent problem to be solved in the current semiconductor technology field. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a power semiconductor device with high turn-off ability and a manufacturing method thereof that can improve the turn-off ability of power semiconductor devices.

[0006] In a first aspect, the present application provides a power semiconductor device with high turn-off ability. The power semiconductor device includes at least one unit cell structure, and each unit cell structure includes an anode structure, a base region structure, a cathode structure, and a gate structure stacked in sequence; wherein, the base region structure includes a floating junction region, and the doping type of the floating junction region is opposite to that of the base region structure.

[0007] The floating junction region is used to divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure.

[0008] In one embodiment, the gate structure includes: a first gate and a second gate, and the floating junction region includes a first floating junction region and a second floating junction region; the first floating junction region is disposed in the projection region of the base region structure between the first gate and the cathode structure; the second floating junction region is disposed in the projection region of the base region structure between the second gate and the cathode structure.

[0009] In one embodiment, the power semiconductor device further includes: a buffer structure; the buffer structure is stacked under the base region structure, and the buffer structure is stacked on the anode structure; the doping type of the buffer structure determines whether the structure of the power semiconductor device is symmetric.

[0010] In one embodiment, the anode structure includes: an anode and a first anode region stacked in sequence; the first anode region is stacked under the base region structure.

[0011] In one embodiment, the base region structure includes: a first-type base region and a second-type base region; the first-type base region is stacked on the anode structure, and the second-type base region is stacked on the first-type base region; a floating junction region is included in the first-type base region; the doping type of the floating junction region is opposite to that of the first-type base region.

[0012] In one embodiment, the second-type base region includes a first subtype base region and a second subtype base region; the first subtype base region is stacked on the first-type base region layer, and the second subtype base region is stacked on the first subtype base region; the first subtype base region is a planar base region or a wavy base region.

[0013] In one embodiment, the second-type base region includes: a third subtype base region and a fourth subtype base region; the third subtype base region and the fourth subtype base region are arranged in parallel and are both stacked on the first-type base region layer; the third subtype base region is a planar base region or a wavy base region.

[0014] In one embodiment, the cathode structure includes: an emission region and a cathode stacked in sequence; the emission region is stacked on the base region structure.

[0015] In a second aspect, the present application also provides a method for manufacturing a power semiconductor device with high turn-off capability, the method including:

[0016] Forming an anode structure, a base region structure, a cathode structure, and a gate structure stacked in sequence through a preset manufacturing method;

[0017] Wherein, the base region structure includes a floating junction region, and the doping type of the floating junction region is opposite to that of the base region structure; the floating junction region is used to divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure;

[0018] Wherein, the preset manufacturing method includes the way of first performing local ion implantation and then epitaxy or bonding.

[0019] The above-mentioned power semiconductor device with high turn-off ability and its manufacturing method. The power semiconductor device with high turn-off ability includes at least one unit cell structure, and each unit cell structure includes an anode structure, a base region structure, a cathode structure, and a gate structure stacked in sequence. Among them, the base region structure includes a floating junction region, and the doping type of the floating junction region is opposite to that of the base region structure. The floating junction region is used to divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure. By adding a floating junction region to the base region structure, the current on the path between the anode structure and the cathode structure can be diverted to the region between the cathode structure and the gate structure, thereby reducing the base lateral voltage drop at the outer edge of the cathode structure, achieving the effect of rapid commutation between the cathode structure and the gate structure, and effectively improving the turn-off ability of the power semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 It is a structural diagram of a power semiconductor device with high turn-off ability in an embodiment;

[0022] Figure 2 It is a three-dimensional structure schematic diagram of a floating junction region in an embodiment;

[0023] Figure 3 It is a three-dimensional structure schematic diagram of a floating junction region in another embodiment;

[0024] Figure 4 It is a structural comparison diagram between an existing power semiconductor device and the power semiconductor device with high turn-off ability in this embodiment;

[0025] Figure 5 It is a comparison diagram of the forward conduction characteristic curves between an existing power semiconductor device and the power semiconductor device with high turn-off ability in this embodiment;

[0026] Figure 6 It is a structural diagram of a power semiconductor device with high turn-off ability in another embodiment;

[0027] Figure 7 It is a structural diagram of a power semiconductor device with high turn-off ability in another embodiment;

[0028] Figure 8 It is a structural diagram of a power semiconductor device with high turn-off ability in another embodiment;

[0029] Figure 9 Structural diagram of a power semiconductor device with high turn-off capability in another embodiment;

[0030] Figure 10 Structural diagram of a power semiconductor device with high turn-off capability in another embodiment;

[0031] Figure 11 Structural diagram of a power semiconductor device with high turn-off capability in another embodiment;

[0032] Figure 12 Structural diagram of a power semiconductor device with high turn-off capability in another embodiment;

[0033] Figure 13 Structural diagram of a power semiconductor device with high turn-off capability in another embodiment;

[0034] Figure 14 Comparison diagram of turn-off characteristic curves of an existing power semiconductor device and the power semiconductor device with high turn-off capability of this embodiment;

[0035] Figure 15 Comparison diagram of current density distributions during the turn-off process of an existing power semiconductor device and the power semiconductor device with high turn-off capability of this embodiment;

[0036] Description of reference numerals:

[0037] Anode structure 10; Base region structure 20; Cathode structure 30;

[0038] Gate structure 40; Floating junction region 201; Buffer region structure 50;

[0039] First gate 401; Second gate 402; First floating junction region 2010;

[0040] First floating junction region 2011; Second floating junction region 2012; Anode 100;

[0041] First type base region 202; Second type base region 203; Cathode 300;

[0042] First subtype base region 2031; Second subtype base region 2032; Emitter region 301;

[0043] Third subtype base region 2033; Fourth subtype base region 2034; Substrate 60;

[0044] First anode region 101; Second anode region 102. Detailed implementation manners

[0045] To facilitate the understanding of the present application, the present application will be described more comprehensively hereinafter with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application will be thorough and comprehensive.

[0046] It should be understood that when an element or layer is referred to as "connected to" another element or layer, it can be directly connected to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion; for example, the first type base region may be referred to as the second type base region, and similarly, the second type base region may be referred to as the first type base region; the first type base region and the second type base region are different types of base regions. For example, the first type base region may be a P-type structure and the second type base region may be an N-type structure; or, the first type base region may be an N-type structure and the second type base region may be a P-type structure.

[0047] Spatial relationship terms such as "above" may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the figures is flipped, the feature described as "above" will be oriented as "below". Thus, the exemplary term "above" may include both the upper and lower orientations. In addition, the device may also include other orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0048] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the described features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups are not excluded from being present or added. At the same time, as used herein, the term "and / or" includes any and all combinations of the related listed items.

[0049] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the ordinary meanings understood by those with ordinary skills in the technical field to which this application belongs. The words such as "a", "one", "kind", "the" and the like involved in this application do not indicate a quantity limitation and may represent a singular or plural number. The terms "including", "comprising", "having" and any variations thereof involved in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or modules (units) is not limited to the listed steps or units, but may further include unlisted steps or units, or may further include other steps or units inherent to these processes, methods, products or devices. The "plurality" involved in this application means greater than or equal to two. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The terms "first", "second" and the like involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0050] First, before specifically introducing the technical solutions of the embodiments of the present disclosure, the technical background or the technical evolution context based on which the embodiments of the present disclosure are described will be introduced first. In the power system, the reliable DC transmission of long-distance and large-capacity electric energy is one of the key problems that need to be urgently solved. In the fields of smart grid, new energy, and high-power medium-voltage application systems such as industrial variable frequency conversion where circuit miniaturization and integration applications are relatively common, a gate-commutated thyristor (GCT for short), which has low on-state loss, fast switching speed, small switching loss, and strong current-carrying capacity, is generally used as a fully controlled power electronic switching device. An important standard for measuring the performance of GCT devices is the turn-off ability, and the standard for measuring the turn-off ability is whether the cathode current can be reduced to less than one-tenth of the turn-off current during turn-off to avoid re-triggering and turn-off failure. However, the existing technologies for improving the turn-off ability of GCTs are relatively scarce. Although a wavy base structure effectively improves the turn-off ability of GCTs, under the current strict requirements of high blocking voltage and large turn-off current, the effect of improving the turn-off ability of the wavy base gradually approaches the upper limit. Therefore, how to further improve the turn-off ability of power semiconductor devices has become an urgent problem to be solved in the current semiconductor technology field. In addition, it should be noted that the applicant has put in a lot of creative labor for the technical solutions introduced in the following embodiments. Based on this, the present application provides a power semiconductor device with high turn-off ability and a preparation method, aiming to solve the above technical problems. The following embodiments will specifically illustrate the power semiconductor device with high turn-off ability and the preparation method described in the present application.

[0051] In one embodiment, asFigure 1 As shown, a power semiconductor device with high turn-off ability is provided. The power semiconductor device includes: at least one unit cell structure 01, and each unit cell structure 01 includes an anode structure 10, a base region structure 20, a cathode structure 30, and a gate structure 40 stacked in sequence.

[0052] Among them, the base region structure 20 includes a floating junction region 201, and the doping type of the floating junction region 201 is opposite to that of the base region structure 20; the floating junction region 201 is used to divert the current on the path between the anode structure 10 and the cathode structure 30 to the region between the cathode structure 30 and the gate structure 40.

[0053] The above-mentioned anode structure 10 can be composed of multiple semiconductor layers, and the doping types of the semiconductor layers can be the same or different, and the doping types include at least one of P type, P- type, P+ type, N type, N- type, and N+ type. The above-mentioned base region structure 20 can be composed of multiple semiconductor layers, and the doping types of the semiconductor layers can be the same or different, and the doping types include at least one of P type, P- type, P+ type, N type, N- type, and N+ type. The above-mentioned cathode structure 30 can be composed of multiple semiconductor layers, and the doping types of the semiconductor layers can be the same or different, and the doping types include at least one of P type, P- type, P+ type, N type, N- type, and N+ type. The structure of the above-mentioned power semiconductor device can be, but is not limited to, a reverse blocking type, an asymmetric type, and a reverse conducting type structure.

[0054] The number of the above-mentioned floating junction regions 201 can be one or multiple. Preferably, in one unit cell structure 01, the number of the floating junction regions 201 can be the same as the number of the gate structures 40, or the number of the floating junction regions 201 can be the same as the number of the regions between the cathode structure 30 and the gate structure 40. The floating junction region 201 can be a region with a preset size, or can include multiple sub-floating junction regions 2010 with preset sizes. The sub-floating junction regions 2010 can be connected (specifically, see the structure shown in Figure 2 ), or can be not connected (specifically, see the structure shown in Figure 3 ). The size of the preset size can be determined according to actual needs, and the sizes of the sub-floating junction regions 2010 can be the same or different. The shape of the above-mentioned floating junction region 201 can be, but is not limited to, a rectangle, a square, a trapezoid, etc.

[0055] The doping type of the floating junction region 201 includes at least one of P-type, P-type, P+-type, N-type, N-type, and N+-type. The position of the floating junction region 201 can be set according to actual requirements. Preferably, the floating junction region 201 is arranged in the upper half region of the base region structure 20, specifically, it can be correspondingly arranged in the region between the cathode structure 30 and the gate structure 40. The thickness of the floating junction region 201 can be set according to actual requirements. Preferably, the thickness T of the floating junction region 201 ranges from 5 μm to 50 μm. The width of the floating junction region 201 can be set according to actual requirements. The spacing between the floating junction regions 201 can be set according to actual requirements. Preferably, the spacing between the floating junction regions 201 can be determined by the position of the region where the cathode structure 30 and the gate structure 40 are located. The doping concentration of the floating junction region 201 is greater than that of the base region structure 20.

[0056] Exemplarily, the doping concentration of the above floating junction region 201 is slightly greater than that of the base region structure 20. Then, a power semiconductor device is constructed based on the doped floating junction region 201. Then, simulation verification can be carried out on the existing power semiconductor device and the power semiconductor device with high turn-off ability in this embodiment by using the simulation software Sentaurus TCAD software respectively, and the simulation verification results are obtained: Figure 4 FIG. 5 is a structural comparison diagram of the structure of the existing power semiconductor device and the structure of the power semiconductor device with high turn-off ability in this embodiment. Figure 5 FIG. 7 is a forward conduction characteristic curve comparison diagram of the structure of the existing power semiconductor device with high turn-off ability (corresponding to the conventional structure in Figure 5 ) and the structure of the power semiconductor device with high turn-off ability in this embodiment (corresponding to the transparent floating junction structure in Figure 5 ). Among them, the horizontal axis represents voltage, with the unit of volt; the vertical axis represents current, with the unit of ampere. It can be seen from Figure 5 that the forward conduction characteristic curves of the power semiconductor device with high turn-off ability in this embodiment and the existing power semiconductor device basically coincide. Therefore, it can be proved that adding the floating junction region 201 has basically no influence on the conduction characteristic of the original power semiconductor device. Therefore, the floating junction region 201 can be called a "transparent floating junction".

[0057] The power semiconductor device with high turn-off ability provided by the embodiment of the present application can shunt the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure by adding a floating junction region in the base region structure, thereby reducing the base lateral voltage drop at the outer edge of the cathode structure, achieving the effect of rapid commutation between the cathode structure and the gate structure, and further effectively improving the turn-off ability of the power semiconductor device.

[0058] In one embodiment, as shown in Figure 6As shown, the above-mentioned gate structure 40 includes a first gate 401 and a second gate 402, and the floating junction region 201 includes a first floating junction region 2011 and a second floating junction region 2012.

[0059] Among them, the first floating junction region 2011 is disposed in the projection region on the base region structure 20 between the first gate 401 and the cathode structure 30; the second floating junction region 2012 is disposed in the projection region on the base region structure 20 between the second gate 402 and the cathode structure 30.

[0060] The doping type of the above-mentioned first floating junction region 2011 includes at least one of P-type, P-type, P+-type, N-type, N-type, and N+-type. The thickness of the first floating junction region 2011 can be set according to actual needs. Preferably, the thickness T of the first floating junction region 2011 ranges from 5 μm to 50 μm. The width of the first floating junction region 2011 can be set according to actual needs. The doping type of the above-mentioned second floating junction region 2012 includes at least one of P-type, P-type, P+-type, N-type, N-type, and N+-type. The thickness of the second floating junction region 2012 can be set according to actual needs. Preferably, the thickness T of the second floating junction region 2012 ranges from 5 μm to 50 μm. The width of the second floating junction region 2012 can be set according to actual needs.

[0061] In one embodiment, as Figure 6 shown, the above-mentioned power semiconductor device further includes: a buffer structure 50; the buffer structure 50 is stacked under the base region structure 20, and the buffer structure 50 is stacked on the anode structure 10; the doping type of the buffer structure determines whether the structure of the power semiconductor device is symmetric.

[0062] The above-mentioned buffer structure 50 can be composed of one or more semiconductor layers, and the doping types of the semiconductor layers can be the same or different, and the doping types include at least one of P-type, P-type, P+-type, N-type, N-type, and N+-type.

[0063] The structure of the power semiconductor device can be, but is not limited to, a reverse-blocking type, an asymmetric type, and a reverse-conducting type structure. If the doping type of the buffer structure 50 is the same as the doping type of the anode structure 10, the structure of the power semiconductor device is determined to be a symmetric type; if the doping type of the buffer structure 50 is the same as the doping type of the base region structure 20, the structure of the power semiconductor device is determined to be an asymmetric type.

[0064] In one embodiment, as Figure 6As shown, the above-mentioned anode structure 10 includes: an anode 100 and a first anode region 101 stacked in sequence; the first anode region 101 is stacked under the base region structure 20. The above-mentioned first anode region 101 can be composed of one or more semiconductor layers, and the doping types of each semiconductor layer can be the same or different, and the doping types include at least one of P-type, P-type, P+-type, N-type, N-type, and N+-type.

[0065] In one embodiment, as Figure 6 shown, the above-mentioned base region structure 20 includes: a first-type base region 202 and a second-type base region 203.

[0066] Among them, the first-type base region 202 is stacked on the anode structure, and the second-type base region 203 is stacked on the first-type base region 202; the first-type base region 202 includes a floating junction region 201; the doping type of the floating junction region 201 is opposite to that of the first-type base region 202.

[0067] The doping type of the above-mentioned first-type base region 202 includes at least one of P-type, P-type, P+-type, N-type, N-type, and N+-type. The doping type of the above-mentioned second-type base region 203 includes at least one of P-type, P-type, P+-type, N-type, N-type, and N+-type. The second-type base region 203 can be composed of multiple semiconductor layers, and the doping types of each semiconductor layer can be the same or different.

[0068] In one embodiment, as Figure 6 shown, the above-mentioned second-type base region 203 includes a first subtype base region 2031 and a second subtype base region 2032.

[0069] Among them, the first subtype base region 2031 is stacked on the first-type base region 202, and the second subtype base region 2032 is stacked on the first subtype base region 2031; the first subtype base region 2031 is a planar base region or a wavy base region.

[0070] The doping type of the above-mentioned first subtype base region 2031 includes at least one of P-type, P-type, P+-type, N-type, N-type, and N+-type. The doping type of the second subtype base region 2032 includes at least one of P-type, P-type, P+-type, N-type, N-type, and N+-type.

[0071] In one embodiment, as Figure 7 shown, the above-mentioned second-type base region 203 includes: a third subtype base region 2033 and a fourth subtype base region 2034; the anode structure further includes a second anode region 102.

[0072] Among them, the third sub-type base region 2033 and the fourth sub-type base region 2034 are arranged in parallel and are both stacked on the first type base region layer 2031; the third sub-type base region 2033 is a planar base region or a wavy base region. The buffer structure 50 is stacked under the base region structure 20. The second anode region 102 and the first anode region 101 are arranged in parallel, and both the first anode region 101 and the second anode region 102 are stacked on the anode 100, that is, the thyristor structure described in this embodiment is a reverse-conducting type structure.

[0073] The doping type of the above-mentioned third sub-type base region 2033 includes at least one of P-type, P-type, P+-type, N-type, N-type, N+-type. The doping type of the fourth sub-type base region 2034 includes at least one of P-type, P-type, P+-type, N-type, N-type, N+-type. The doping type of the second anode region 102 includes at least one of P-type, P-type, P+-type, N-type, N-type, N+-type. The doping type of the anode 100 includes at least one of P-type, P-type, P+-type, N-type, N-type, N+-type. The doping type of the first anode region 101 includes at least one of P-type, P-type, P+-type, N-type, N-type, N+-type. The doping type of the buffer structure 50 includes at least one of P-type, P-type, P+-type, N-type, N-type, N+-type.

[0074] In one embodiment, as Figure 6 shown, the above-mentioned cathode structure 30 includes: an emitter region 301 and a cathode 300 stacked in sequence; the emitter region 301 is stacked on the base region structure 20.

[0075] Among them, the doping type of the emitter region 301 includes at least one of P-type, P-type, P+-type, N-type, N-type, N+-type.

[0076] For the high-turn-off-capability power semiconductor device described in all the above embodiments, the present application also provides a high-turn-off-capability power semiconductor device, which includes: at least one unit cell structure, and each unit cell structure includes: an anode structure, a base region structure, a cathode structure, a gate structure, and a buffer structure stacked in sequence.

[0077] Among them, the base region structure includes a floating junction region, and the doping type of the floating junction region is opposite to that of the base region structure; the floating junction region is used to divert the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure.

[0078] The above-mentioned gate structure includes: a first gate and a second gate, and the floating junction region includes a first floating junction region and a second floating junction region; the first floating junction region is arranged in the projection region of the base region structure between the first gate and the cathode structure; the second floating junction region is arranged in the projection region of the base region structure between the second gate and the cathode structure. The doping concentration of the floating junction region is greater than that of the base region structure.

[0079] The above base region structure includes: a first-type base region and a second-type base region; the first-type base region is stacked on the anode structure, and the second-type base region is stacked on the first-type base region; the first-type base region includes a floating junction region; the doping type of the floating junction region is opposite to that of the first-type base region. The second-type base region includes a first sub-type base region and a second sub-type base region; the first sub-type base region is stacked on the first-type base region layer, and the second sub-type base region is stacked on the first sub-type base region; the first sub-type base region is a planar base region or a wavy base region. Optionally, the above second-type base region includes: a third sub-type base region and a fourth sub-type base region; the third sub-type base region and the fourth sub-type base region are arranged in parallel and are both stacked on the first-type base region layer; the third sub-type base region is a planar base region or a wavy base region.

[0080] The above anode structure includes: an anode and a first anode region stacked in sequence; the first anode region is stacked under the base region structure. Optionally, the above anode structure further includes: a second anode region; the second anode region is arranged in parallel with the first anode region, and both the first anode region and the second anode region are stacked on the anode. That is, the structure of the power semiconductor device is a reverse-conducting type structure. The above cathode structure includes: an emission region and a cathode stacked in sequence; the emission region is stacked on the base region structure.

[0081] In practical applications, various different power semiconductor device structures can be designed according to the above structures, and examples are as follows:

[0082] Such as Figure 8 The symmetric power semiconductor device structure shown includes an Si substrate 60, an anode (A) 100, a cathode (K) 300, a first gate (G) 401, and a second gate (G) 402. Among them, the doping type of the Si substrate 60 is N-type, the total thickness is H, and longitudinally from bottom to top are the anode (A) 100, P+ first anode region 101, P- buffer structure 50, N- first-type base region 202, P- first floating junction region 2011, P- second floating junction region 2012, P- wavy first sub-type base region 2031, P second sub-type base region 2032, and N+ emission region 301.

[0083] Among them, the P-first floating junction region 2011 and the P-second floating junction region 2012 are located within the N-first type base region 202. The widths of the P-first floating junction region 2011 and the P-second floating junction region 2012 are both W, the thickness is T, the distance between the P-first floating junction region 2011 and the P-second floating junction region 2012 is D, the distances between the P-first floating junction region 2011 and the P-second floating junction region 2012 and the adjacent side boundaries are both D / 2, the distances from the central positions of the P-first floating junction region 2011 and the P-second floating junction region 2012 to the upper surface of the Si substrate 60 are αH, where 0 < α < 1. The width of the N+ emitter region 301 is L. Among them, the P+ first anode region 101 in the Si substrate 60 is heavily doped, the P-buffer structure 50 is lightly doped, the N-first type base region 202 is lightly doped, the P-first floating junction region 2011 and the P-second floating junction region 2012 are lightly doped, the P-wave-shaped first subtype base region 2031 is lightly doped, the P-second subtype base region 2032 is heavily doped, and the N+ emitter region 301 is heavily doped; the doping types of the P-first floating junction region 2011 and the P-second floating junction region 2012 are opposite to the doping type of the N-first type base region 202. If the Si substrate layer 60 is of N type, the six-layer vertical structure from top to bottom is N+ / P / P- / N- / P- / P+, where the doping types of the P-first floating junction region 2011 and the P-second floating junction region 2012 are of P type; if the Si substrate layer 50 is of P type, the six-layer vertical structure from top to bottom is P+ / N / N- / P- / N- / N+, where the doping types of the P-first floating junction region 2011 and the P-second floating junction region 2012 are of N type.

[0084] The anode (A) 100 is located on the lower surface of the P+ first anode region 101; the cathode (K) 300 is located on the upper surface of the N+ emitter region 301; the first gate (G) 401 and the second gate (G) 402 are respectively located on the upper surfaces of the two side P-second subtype base regions 2032. In the distance αH from the central positions of the P-first floating junction region 2011 and the P-second floating junction region 2012 to the upper surface of the Si substrate, the value range of α is 0.2 to 0.5; the thickness T range of the P-first floating junction region 2011 and the P-second floating junction region 2012 is 5 μm to 50 μm. The width W range of the P-first floating junction region 2011 and the P-second floating junction region 2012 is 0.2*L < W < 0.5*L; the spacing D range between the P-first floating junction region 2011 and the P-second floating junction region 2012 is 0.1*L < D < (L - W); the doping concentration of the P-first floating junction region 2011 and the P-second floating junction region 2012 is slightly greater than the doping concentration R of the N-first type base region 202, and the doping concentration range is R to 10*R.

[0085] As Figure 9 shown in the asymmetric power semiconductor device structure, among which, the P-first subtype base region 2031 is a planar base region. AsFigure 10 The shown symmetrical power semiconductor device structure, wherein the P-first subtype base region 2031 is a planar base region. As Figure 11 The shown asymmetrical power semiconductor device structure, wherein the P-first subtype base region 2031 is a wavy base region. As Figure 12 The shown reverse-conducting power semiconductor device structure, wherein the P-first subtype base region 2031 is a planar base region. As Figure 13 The shown reverse-conducting power semiconductor device structure, wherein the P-first subtype base region 2031 is a wavy base region.

[0086] Figure 14 is a comparison chart of the turn-off characteristic curves of the existing power semiconductor device structure (corresponding to the conventional structure in Figure 14 ) and the power semiconductor device structure with high turn-off ability of this embodiment (corresponding to the transparent floating junction structure in Figure 14 ). Among them, the horizontal axis represents time in seconds, the vertical axis represents voltage in volts, or the vertical axis represents current in amperes. In the simulation, two units, GCT1 close to the gate with a small impedance load and an active area ratio of 80%, and GCT2 far from the gate with a large impedance load and an active area ratio of 20%, are interconnected with the impedance through SPICE wires. Next, the turn-off characteristics of GCT2 are mainly simulated and studied. Set the DC voltage source V in the turn-off circuit DC = 4000V, the current flowing through the GCT device I AK = 5000A, and the temperature is 400K. It can be clearly seen from the turn-off characteristic curves of the two that: for the reverse-blocking GCT basic device with a wavy base region, a large current pulse occurs in the cathode current at about 6.7e-5s, and the peak value of its cathode current exceeds 1kA, which is far greater than 10% (90A) of the turn-off current value of 900A, resulting in the re-triggering of the device, and the anode current also surges to more than 2kA accordingly. The anode voltage waveform also shows a change of first decreasing and then increasing, that is, the device fails to turn off under this condition. In the turn-off characteristic curve of the GCT device structure with the transparent floating junction added in this embodiment, the cathode current remains unchanged all the time, without any current pulse spikes, the anode current shows a downward trend as a whole, and the anode voltage does not generate a failure waveform, that is, the GCT device structure with the transparent floating junction added in this embodiment successfully completes the turn-off under this condition. It can be seen that the GCT device structure with the transparent floating junction added provided by the present invention can effectively improve the turn-off ability of the device.

[0087] Figure 15It is a comparison diagram of the current density distribution during the turn-off process of an existing power semiconductor device and the power semiconductor device with high turn-off ability in this embodiment. In the reverse-blocking GCT device with a wavy base region, the current density below the wavy base region is uniformly distributed. However, in the GCT device structure with a transparent floating junction added in this embodiment, the current density near the two transparent floating junctions starts to change. There is an obvious shunt in the current density at the anode to the floating junction near the floating junction, that is, the current in the middle of the device is shunted to the area below the gate near both sides through the transparent floating junction, which helps the device to commutate the anode current from the cathode to the gate during the turn-off process. Therefore, the GCT device structure with a transparent floating junction added in this embodiment can effectively improve the turn-off ability of the device.

[0088] Based on any thyristor provided in the above embodiments, the present application also provides a preparation method of a power semiconductor device with high turn-off ability, which can be used to prepare the thyristor provided in the foregoing embodiments. The method includes:

[0089] Form an anode structure, a base region structure, a cathode structure, and a gate structure stacked in sequence through a preset preparation method;

[0090] Among them, the base region structure includes a floating junction region, and the doping type of the floating junction region is opposite to that of the base region structure; the floating junction region is used to shunt the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure;

[0091] Among them, the preset preparation method includes local ion implantation first and then epitaxy or bonding.

[0092] In the preparation method described in the embodiments of the present application, by adding a floating junction region to the base region structure, the current on the path between the anode structure and the cathode structure can be shunted to the region between the cathode structure and the gate structure, thereby reducing the lateral base voltage drop at the outer edge of the cathode structure, achieving the effect of rapid commutation between the cathode structure and the gate structure, and further effectively improving the turn-off ability of the power semiconductor device.

[0093] The methods described in the above steps have been described in the foregoing embodiments. For detailed content, please refer to the foregoing description and will not be repeated here.

[0094] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear statement in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0095] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0096] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A power semiconductor device with high turn-off capability, characterized in that: The power semiconductor device comprises: at least one unit cell structure, each of which comprises an anode structure, a base structure, a cathode structure, and a gate structure; wherein the base structure comprises a floating junction region, and the doping type of the floating junction region is opposite to the doping type of the base structure; The floating junction region is used to shunt the current on the path between the anode structure and the cathode structure to the region between the cathode structure and the gate structure; Wherein, the gate structure includes: a first gate and a second gate, and the floating junction area includes a first floating junction area and a second floating junction area; the first floating junction area is arranged in a projection area on the base structure between the first gate and the cathode structure; the second floating junction area is arranged in a projection area on the base structure between the second gate and the cathode structure.

2. The power semiconductor device according to claim 1, characterized in that: The power semiconductor device further includes: a buffer structure; the buffer structure is stacked below the base structure, and the buffer structure is stacked above the anode structure; the doping type of the buffer structure determines whether the structure of the power semiconductor device is symmetrical.

3. The power semiconductor device according to claim 1, characterized in that: The anode structure comprises: an anode and a first anode region stacked in sequence; the first anode region is stacked under the base region structure.

4. The power semiconductor device according to claim 1, characterized in that: The base region structure includes: a first type base region and a second type base region; the first type base region is stacked on the anode structure, and the second type base region is stacked on the first type base region; the first type base region includes the floating junction region; the doping type of the floating junction region is opposite to the doping type of the first type base region.

5. The power semiconductor device according to claim 4, characterized in that: The second type base region includes: a first sub-type base region and a second sub-type base region; the first sub-type base region is stacked on the first type base region layer, and the second sub-type base region is stacked on the first sub-type base region; the first sub-type base region is a planar base region or a wavy base region.

6. The power semiconductor device according to claim 4, characterized in that: The second type base region includes: a third subtype base region and a fourth subtype base region; the third subtype base region and the fourth subtype base region are arranged in parallel and are both stacked on the first type base region layer; the third subtype base region is a planar base region or a wavy base region.

7. The power semiconductor device according to claim 6, characterized in that: The anode structure further includes: a second anode region; the second anode region is arranged in parallel with the first anode region in the anode structure, and the first anode region and the second anode region are both stacked on the anode.

8. The power semiconductor device according to any one of claims 1 to 7, characterized in that: The cathode structure comprises: an emitter region and a cathode stacked in sequence; the emitter region is stacked on the base region structure.

9. The power semiconductor device according to any one of claims 1 to 7, characterized in that: The thickness of the floating junction area ranges from 5 μm to 50 μm.

10. A method for preparing a power semiconductor device with high shutoff capability, characterized in that: The method comprises: An anode structure, a base structure, a cathode structure, and a gate structure are formed by a preset preparation method; Wherein, the base structure includes a floating junction area, and the doping type of the floating junction area is opposite to the doping type of the base structure; the floating junction area is used to shunt the current on the path between the anode structure and the cathode structure to the area between the cathode structure and the gate structure; the gate structure includes: a first gate and a second gate, and the floating junction area includes a first floating junction area and a second floating junction area; the first floating junction area is arranged in a projection area on the base structure between the first gate and the cathode structure; the second floating junction area is arranged in a projection area on the base structure between the second gate and the cathode structure; The preset preparation method includes local ion implantation followed by epitaxy or bonding.

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