Display substrate and display device

Abstract

A display substrate (10) and a display device. In a pixel circuit of the display substrate (10), a drive sub-circuit (50) includes a drive transistor (T5), and the size of a drive current flowing through a light emitting element (EL) is controlled in response to a drive control signal received by a gate (GE5) of the drive transistor (T5). A control sub-circuit (40) includes a control transistor (T1), a first electrode of the control transistor (T1) is electrically connected with the gate (GE5) of the drive transistor (T5), a connection position of the first electrode of the control transistor (T1) with an active layer of the control transistor (T1) is a first position, a connection position of a second electrode of the control transistor (T1) with the active layer of the control transistor (T1) is a second position, a connection position of a first electrode of the drive transistor (T5) with an active layer of the drive transistor (T5) is a third position, and the distance between the first position and the second position is greater than the distance between the first position and the third position.

Description

[0001] This application claims priority to PCT patent application No. PCT / CN2023 / 088913, filed on April 18, 2023, and PCT patent application No. PCT / CN2022 / 134711, filed on November 28, 2022, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] At least one embodiment of this disclosure relates to a display substrate and a display device. Background Technology

[0003] Active-matrix organic light-emitting diode (AMOLED) displays offer advantages over traditional liquid crystal displays (LCDs), including self-illumination, wide color gamut, high contrast, and thinness, making them widely used in mobile phones, tablets, and flexible wearable devices such as smartwatches. Typically, pixel circuits are located in the display area, while gate driving circuits, such as GOA driving circuits, are located in the bezel area to provide driving signals to the pixel circuits.

[0004] During the operation of the pixel circuit, in the light-emitting stage, when the transistor electrically connected to the gate of the driving transistor is turned off within one frame of display, if the off-state current of the transistor electrically connected to the gate of the driving transistor is large, it will cause a serious leakage problem through the gate of the driving transistor. The transistor electrically connected to the gate of the driving transistor will cause the potential of the gate of the driving transistor to change, thereby causing the display image to be unable to maintain the written grayscale, resulting in screen flickering on the display panel. Summary of the Invention

[0005] At least one embodiment of this disclosure provides a display substrate including sub-pixels. Each sub-pixel includes a pixel circuit, which further includes a driving sub-circuit, a light-emitting element, and a control sub-circuit. The driving sub-circuit includes a driving transistor, the gate of which is configured to receive a driving control signal. The driving sub-circuit is configured to control the magnitude of a driving current flowing through the light-emitting element in response to the driving control signal. The control sub-circuit includes a control transistor, a first electrode of which is electrically connected to the gate of the driving transistor. The connection point between the first electrode of the control transistor and the active layer of the control transistor is a first position; the connection point between the second electrode of the control transistor and the active layer of the control transistor is a second position; and the connection point between the first electrode of the driving transistor and the active layer of the driving transistor is a third position. The distance between the first position and the second position is greater than the distance between the first position and the third position.

[0006] For example, in the display substrate provided in at least one embodiment of this disclosure, the straight-line distance between the first position and the second position is greater than the straight-line distance between the first position and the third position; or, the distance between the first position and the second position in the first direction is greater than the distance between the first position and the third position in the first direction; or, the sum of the distance between the first position and the second position in the first direction and the distance in the second direction is greater than the sum of the distance between the first position and the third position in the first direction and the distance in the second direction.

[0007] For example, in a display substrate provided in at least one embodiment of this disclosure, the sub-pixel includes a first connection block, which is electrically connected to the gate of the driving transistor, the active layer of the driving transistor, and the active layer of the control transistor through a first connection via, wherein the position of the first connection via is the first position; the second electrode of the control transistor is electrically connected to the active layer of the control transistor through a second connection via, wherein the position of the second connection via is the second position; the sub-pixel includes a second connection block, which is electrically connected to the active layer of the driving transistor through a third connection via, wherein the position of the third connection via is the third position.

[0008] For example, in a display substrate provided in at least one embodiment of this disclosure, the channel region of the driving transistor and the channel region of the control transistor are arranged in a first direction, and a second direction intersects the first direction. The active layer of the control transistor includes a longitudinal portion extending along the first direction and a transverse portion extending along the second direction. The longitudinal portion includes the channel region of the control transistor. The transverse portion is connected to the longitudinal portion and includes a first extension portion and a second extension portion. The first extension portion protrudes from the longitudinal portion toward a first side in the second direction, and the second extension portion protrudes from the longitudinal portion toward a second side opposite to the first side in the second direction.

[0009] For example, in a display substrate provided in at least one embodiment of this disclosure, the channel region of the driving transistor is located on a first side of the longitudinal portion in the second direction, and the length of the first extension portion in the second direction is not less than the length of the second extension portion in the second direction.

[0010] For example, in a display substrate provided in at least one embodiment of this disclosure, the longitudinal portion has a distal end in the first direction that is away from the channel region of the driving transistor, and the first extension portion and the second extension portion are located at the distal end of the longitudinal portion and connected to the distal end.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel circuit includes a data writing sub-circuit, the data writing sub-circuit includes a data writing transistor, and the control transistor includes the data writing transistor; the gate of the data writing transistor is electrically connected to a data writing control signal terminal to receive a data writing control signal, the first terminal of the data writing transistor is electrically connected to the gate of the driving transistor, the second terminal of the data writing transistor is configured to receive a data signal, and the data writing sub-circuit is configured to write the data signal to the gate terminal of the driving transistor in response to the data writing control signal.

[0012] For example, in a display substrate provided in at least one embodiment of this disclosure, a first extension portion of the active layer of the data writing transistor at least partially overlaps with the channel region of the driving transistor in the first direction.

[0013] For example, in at least one embodiment of the display substrate provided in this disclosure, the display substrate includes a data signal line that provides the data signal, and a lateral portion of the active layer of the data writing transistor is electrically connected to the data signal line; the pixel circuit includes a first connection electrode disposed on a different layer from both the active layer and the data signal line, a first extension portion of the lateral portion is electrically connected to the first connection electrode through a first via, and the first connection electrode is electrically connected to the data signal line through a second via, wherein the first via serves as a second position when the control transistor is the data writing transistor.

[0014] For example, in a display substrate provided in at least one embodiment of this disclosure, the first via is located at the end of the first extension portion that is away from the longitudinal portion in the second direction.

[0015] For example, in a display substrate provided in at least one embodiment of this disclosure, the active layer of the data writing transistor further includes an auxiliary extension portion, which is connected to a first extension portion of the lateral portion and extends toward the channel region side of the data writing transistor in the first direction.

[0016] For example, in a display substrate provided in at least one embodiment of this disclosure, there is a gap region between the gate of the data writing transistor and the lateral portion of the active layer of the data writing transistor, and the auxiliary extension portion is located in the gap region.

[0017] For example, in at least one embodiment of the display substrate provided in this disclosure, the display substrate includes a data signal line that provides the data signal, and the lateral portion of the active layer of the data writing transistor is electrically connected to the data signal line; the pixel circuit includes a first connection electrode disposed on a different layer from both the active layer and the data signal line, the auxiliary extension portion is electrically connected to the first connection electrode through a third via, the first connection electrode is electrically connected to the data signal line through a second via, and the third via serves as the second connection via when the control transistor is the data writing transistor.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, the third via is located at the end of the auxiliary extension portion that is away from the first extension portion in the first direction.

[0019] For example, in at least one embodiment of the display substrate provided in this disclosure, the display substrate includes a plurality of sub-pixels, the plurality of sub-pixels including adjacent first sub-pixels and second sub-pixels arranged in the second direction; the gate of the data writing transistor of the first sub-pixel and the gate of the data writing transistor of the second sub-pixel are independent of each other to receive different data writing control signals respectively; the display substrate includes a first auxiliary gate line disposed on a different layer from the gate of the data writing transistor of the first sub-pixel, the first auxiliary gate line being electrically connected to the gate of the data writing transistor of the first sub-pixel through a fourth via; the display substrate includes a second auxiliary gate line disposed on a different layer from the gate of the data writing transistor of the second sub-pixel, the second auxiliary gate line being electrically connected to the gate of the data writing transistor of the second sub-pixel through a fifth via.

[0020] For example, in a display substrate provided in at least one embodiment of this disclosure, a first extension portion of the active layer of the data writing transistor at least partially overlaps with the fourth via in the first direction.

[0021] For example, in a display substrate provided in at least one embodiment of this disclosure, the gates of the common-gate transistors of the first sub-pixel and the second sub-pixel are electrically connected to each other to share the same gate scan signal. The common-gate transistor includes at least one of the transistors in the pixel circuit other than the data writing transistor and the driving transistor. The display substrate includes a second connection electrode disposed on a different layer from the gate of the common-gate transistor. The second connection electrode is electrically connected to the gate of the common-gate transistor of the first sub-pixel through a sixth via and to the gate of the common-gate transistor of the second sub-pixel through a seventh via. In the case where the display substrate includes a data signal line that provides the data signal, the lateral portion of the active layer of the data writing transistor is electrically connected to the data signal line, and the pixel circuit includes a first connection electrode disposed on a different layer from both the active layer and the data signal line, and the first extension portion of the lateral portion is electrically connected to the first connection electrode through a first via, and the first connection electrode is electrically connected to the data signal line through a second via, the first auxiliary gate line, the second auxiliary gate line, and the second connection electrode are all disposed on the same layer as the first connection electrode.

[0022] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel circuit includes a first reset sub-circuit, the first reset sub-circuit includes a first reset transistor, the control transistor includes the first reset transistor; the gate of the first reset transistor is electrically connected to a first reset signal terminal to receive a first reset control signal, the first terminal of the first reset transistor is electrically connected to the gate of the driving transistor, the second terminal of the first reset transistor is electrically connected to a first signal terminal, and the first reset sub-circuit is configured to write a first reset signal from the first signal terminal to the gate terminal of the driving transistor in response to the first reset control signal.

[0023] For example, in a display substrate provided in at least one embodiment of this disclosure, the connection position between the first electrode of the data writing transistor and the active layer of the data writing transistor is a first sub-position, and the connection position between the second electrode of the data writing transistor and the active layer of the data writing transistor is a second sub-position; the connection position between the first electrode of the first reset transistor and the active layer of the first reset transistor is a third sub-position, and the connection position between the second electrode of the first reset transistor and the active layer of the first reset transistor is a fourth sub-position; the distance between the first sub-position and the second sub-position is greater than the distance between the third sub-position and the fourth sub-position.

[0024] For example, in a display substrate provided in at least one embodiment of this disclosure, the active layer of the data writing transistor extends from the first sub-position to the second sub-position, the active layer of the first reset transistor extends from the third sub-position to the fourth sub-position, and the total length of the active layer of the data writing transistor from the first sub-position to the second sub-position is greater than the total length of the active layer of the first reset transistor from the third sub-position to the fourth sub-position.

[0025] For example, in a display substrate provided in at least one embodiment of this disclosure, a first extension portion of the active layer of the first reset transistor at least partially overlaps with the channel region of the driving transistor in the first direction.

[0026] For example, in a display substrate provided in at least one embodiment of this disclosure, when the control transistor includes a data write transistor, in the first direction, the channel region of the driving transistor is located between the channel region of the data write transistor and the channel region of the first reset transistor; in the first direction, the lateral portion of the active layer of the data write transistor is located on the side of the channel region of the data write transistor away from the channel region of the driving transistor, and the lateral portion of the active layer of the first reset transistor is located on the side of the channel region of the first reset transistor away from the channel region of the driving transistor.

[0027] For example, in a display substrate provided in at least one embodiment of this disclosure, the length of the first extension portion of the active layer of the first reset transistor in the second direction is greater than or equal to the length of the first extension portion of the active layer of the data write transistor in the second direction.

[0028] For example, in a display substrate provided in at least one embodiment of this disclosure, a first extension portion of the active layer of the first reset transistor extends beyond the active layer of the data writing transistor in the second direction.

[0029] For example, in at least one embodiment of the present disclosure, the display substrate includes a compensation signal line that provides the compensation signal. A first extension of the lateral portion of the active layer of the first reset transistor is electrically connected to the compensation signal line through an eighth via. The position of the eighth via is the second position when the control transistor is the first reset transistor.

[0030] For example, in at least one embodiment of the display substrate provided in this disclosure, the pixel circuit further includes a storage sub-circuit, the storage sub-circuit includes a storage capacitor; the first electrode of the data writing transistor is electrically connected to the first capacitor electrode of the storage capacitor and the gate of the driving transistor, the second electrode of the data writing transistor is electrically connected to the data signal line to receive the data signal; the first electrode of the driving transistor is electrically connected to the second capacitor electrode of the storage capacitor and configured to be electrically connected to the first electrode of the light-emitting element, the second electrode of the driving transistor is electrically connected to a first power supply voltage terminal to receive the first power supply voltage.

[0031] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel circuit further includes a sensing sub-circuit, the sensing sub-circuit including a sensing transistor; the first electrode of the sensing transistor is electrically connected to the first electrode of the driving transistor and the second capacitor electrode of the storage capacitor, and the sensing transistor is configured to detect the electrical characteristics of the sub-pixel in response to a detection control signal.

[0032] For example, in a display substrate provided in at least one embodiment of this disclosure, the connection position between the first electrode of the data writing transistor and the active layer of the data writing transistor is a first sub-position, and the connection position between the second electrode of the data writing transistor and the active layer of the data writing transistor is a second sub-position; the connection position between the first electrode of the sensing transistor and the active layer of the sensing transistor is a fifth sub-position, and the connection position between the second electrode of the sensing transistor and the active layer of the sensing transistor is a sixth sub-position; the distance between the first sub-position and the second sub-position is greater than the distance between the fifth sub-position and the sixth sub-position.

[0033] For example, in a display substrate provided in at least one embodiment of this disclosure, the control sub-circuit includes a first reset sub-circuit, the control transistor includes a first reset transistor, the gate of the first reset transistor is electrically connected to a first reset signal terminal to receive a first reset control signal, the first terminal of the first reset transistor is electrically connected to the gate of the driving transistor, the second terminal of the first reset transistor is electrically connected to a first signal terminal, and the first reset sub-circuit is configured to write a first reset signal or compensation signal from the first signal terminal to the gate terminal of the driving transistor in response to the first reset control signal, wherein the gate of the driving transistor, the first terminal of the data writing transistor, and the first terminal of the first reset transistor are electrically connected to a first node; the pixel circuit further includes a light emission control sub-circuit, the light emission control sub-circuit includes a light emission control transistor, and the light emission control transistor... The gate of the body transistor is electrically connected to the light-emitting control signal terminal. The first electrode of the light-emitting control transistor is electrically connected to the first power supply voltage terminal, and the second electrode of the light-emitting control transistor is electrically connected to the second electrode of the driving transistor. The pixel circuit further includes a second reset sub-circuit, which includes a second reset transistor. The gate of the second reset transistor is electrically connected to the second reset signal terminal to receive a second reset control signal. The first electrode of the second reset transistor, the first electrode of the driving transistor, the second capacitor electrode of the storage capacitor, and the first electrode of the light-emitting element are electrically connected to a second node. The second electrode of the second reset transistor is electrically connected to a second signal terminal to receive a second reset signal. Under the control of the second reset signal, the second reset sub-circuit is configured to write the second reset signal to the second node in response to the second reset control signal.

[0034] For example, in the display substrate provided in at least one embodiment of this disclosure, the connection position between the first electrode of the data writing transistor and the active layer of the data writing transistor is a first sub-position, and the connection position between the second electrode of the data writing transistor and the active layer of the data writing transistor is a second sub-position; the connection position between the first electrode of the first reset transistor and the active layer of the first reset transistor is a third sub-position, and the connection position between the second electrode of the first reset transistor and the active layer of the first reset transistor is a fourth sub-position; the connection position between the first electrode of the second reset transistor and the active layer of the second reset transistor is a seventh sub-position, and the connection position between the second electrode of the second reset transistor and the active layer of the second reset transistor is an eighth sub-position; the light emission... The connection position between the first electrode of the control transistor and the active layer of the light-emitting control transistor is the ninth sub-position, and the connection position between the second electrode of the light-emitting control transistor and the active layer of the light-emitting control transistor is the tenth sub-position; the distance between the first sub-position and the second sub-position is greater than the distance between the seventh sub-position and the eighth sub-position, and / or, the distance between the first sub-position and the second sub-position is greater than the distance between the ninth sub-position and the tenth sub-position; or, the distance between the third sub-position and the fourth sub-position is greater than the distance between the seventh sub-position and the eighth sub-position, and / or, the distance between the third sub-position and the fourth sub-position is greater than the distance between the ninth sub-position and the tenth sub-position.

[0035] At least one embodiment of this disclosure also provides a display device, which includes any of the display substrates provided in the embodiments of this disclosure. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of the present invention and are not intended to limit the present invention.

[0037] Figure 1 This is a schematic diagram of the overall circuit architecture of a display panel provided in an embodiment of the present disclosure;

[0038] Figure 2 An equivalent circuit diagram of a pixel circuit for a sub-pixel is provided in one embodiment of this disclosure;

[0039] Figure 3 for Figure 2 The image shows a timing diagram of the pixel circuit during actual operation.

[0040] Figure 4 for Figure 2 The diagram shows a possible layout of a pixel circuit.

[0041] Figures 5A-5H They are shown respectively Figure 4 The diagram shows a schematic representation of the structure of each layer of the pixel circuit.

[0042] Figure 5I It is along Figure 4 A schematic diagram of the cross-section of line A1-A2 in the diagram;

[0043] Figure 5J It is along Figure 4 A schematic diagram of the cross-section of line B1-B2 in the diagram;

[0044] Figure 6 This is a schematic diagram of the pixel circuit layout of another display substrate provided in at least one embodiment of the present disclosure;

[0045] Figures 7A-7H They are shown respectively Figure 6 The diagram shows a schematic representation of the structure of each layer of the pixel circuit.

[0046] Figure 8 An equivalent circuit diagram of a pixel circuit for another sub-pixel provided in an embodiment of this disclosure;

[0047] Figures 9A-9C for Figure 8 The timing diagram shown illustrates the operation of the pixel circuit.

[0048] Figure 10 for Figure 8 The diagram shows the layout of the pixel circuit.

[0049] Figures 11A-11H They are shown respectively Figure 10 The diagram shows a schematic representation of the structure of each layer of the pixel circuit.

[0050] Figure 12 This is a schematic block diagram of a display device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0053] It should be noted that the "channel region of a transistor" in this disclosure refers to the region where the active layer of the transistor and the gate of the transistor overlap each other in a direction perpendicular to the main surface of the substrate. That is, the region where the orthographic projection of the active layer of the transistor on the main surface of the substrate overlaps with the orthographic projection of the gate on the main surface of the substrate corresponds to the channel region of the transistor.

[0054] The accompanying drawings in this disclosure are not drawn to scale, and the number of sub-pixels in the display substrate is not limited to the number shown in the figures. The specific dimensions and quantity of each structure can be determined according to actual needs. The accompanying drawings described in this disclosure are only schematic diagrams.

[0055] At least one embodiment of this disclosure provides a display substrate including sub-pixels. Each sub-pixel includes a pixel circuit, which further includes a driving sub-circuit, a light-emitting element, and a control sub-circuit. The driving sub-circuit includes a driving transistor, the gate of which is configured to receive a driving control signal. The driving sub-circuit is configured to control the magnitude of a driving current flowing through the light-emitting element in response to the driving control signal. The control sub-circuit includes a control transistor, a first electrode of which is electrically connected to the gate of the driving transistor. The connection point between the first electrode of the control transistor and the active layer of the control transistor is a first position; the connection point between the second electrode of the control transistor and the active layer of the control transistor is a second position; and the connection point between the first electrode of the driving transistor and the active layer of the driving transistor is a third position. The distance between the first position and the second position is greater than the distance between the first position and the third position.

[0056] At least one embodiment of this disclosure also provides a display device, which includes any of the display substrates provided in the embodiments of this disclosure.

[0057] Figure 1 This is a schematic diagram of the overall structure of a display panel provided in one embodiment of the present disclosure. Figure 1 As shown, the display substrate 10 includes a display area DR and a non-display area NR that at least partially surrounds the display area DR. The display substrate 10 includes a plurality of display units located in the display area DR and arranged in an array, the display units performing display functions. For example, each display unit includes a plurality of sub-pixels P, for example, Figure 1 Taking a display unit PU comprising three sub-pixels P as an example, the number of sub-pixels in a display unit PU is not limited and can be less than or more than three. Each sub-pixel P includes a light-emitting element and a pixel circuit for driving that light-emitting element. Figure 1 As shown, the display substrate 10 also includes multiple scan lines GL and multiple data lines DL. The multiple scan lines GL and multiple data lines DL intersect each other to define multiple pixel regions distributed in an array within the display area DR. Each pixel region contains a pixel circuit for a sub-pixel P. This pixel circuit can be, for example, a conventional pixel circuit, such as a 3T1C (i.e., two transistors and one capacitor) pixel circuit, a 4T2C, a 5T1C, or an nTmC (n and m are positive integers) pixel circuit. In different embodiments, the pixel circuit may further include a compensation sub-circuit, which can be an internal or external compensation sub-circuit, and may include transistors, capacitors, etc. For example, depending on the needs, the pixel circuit may further include a reset circuit, a light emission control sub-circuit, a detection circuit, etc. For example, the display substrate 10 may also include a scan drive circuit SC and a data drive circuit DC located in the non-display area NR. The scan drive circuit SC is, for example, a gate drive circuit (e.g., a GOA drive circuit). The scan drive circuit SC is connected to the pixel circuit via scan line GL to provide various scan signals, and the data drive circuit DC is connected to the pixel circuit via data line DL to provide data signals. Figure 1 The positional relationship of the scan drive circuit SC and data drive circuit DC, scan line GL and data line DL in the display substrate shown is only an example. The actual arrangement can be designed according to needs.

[0058] For example, the display substrate 10 may also include control circuitry (not shown). This control circuitry may be configured to control the data drive circuit DC to apply the data signal and to control the gate drive sub-circuit to apply the scan signal. An example of this control circuitry is a timing control circuit (T-con). The control circuitry can take various forms, such as including a processor and a memory, the memory containing executable code, which the processor runs to perform the detection method described above.

[0059] For example, the processor can be a central processing unit (CPU) or other forms of processing device with data processing and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0060] For example, a storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and a processor may execute the functions expected by the program instructions. Various application programs and various data may also be stored in the computer-readable storage medium.

[0061] Figure 2 This is an equivalent circuit diagram of a pixel circuit for a sub-pixel provided in one embodiment of the present disclosure. For example... Figure 2 As shown, for example, the pixel circuit includes a driving sub-circuit 50, a data writing sub-circuit 40, and a light-emitting unit 60. The light-emitting unit 60 includes a light-emitting element EL. The driving sub-circuit 50 is configured to control the magnitude of the driving current flowing through the light-emitting element EL in response to a driving control signal.

[0062] For example, such as Figure 2 As shown, the pixel circuit also includes a first reset sub-circuit 10, a second reset sub-circuit 20, and a light emission control sub-circuit 30.

[0063] The control terminal of the first reset sub-circuit 10 is electrically connected to the first reset signal terminal to receive the first reset control signal G2. The first terminal of the first reset sub-circuit 10 and the control terminal (corresponding gate) of the drive sub-circuit 50 are both electrically connected to the first node G. The second terminal of the first reset sub-circuit 10 is electrically connected to the first compensation signal terminal Vref. The first reset sub-circuit 10 is configured to write the first reset signal or compensation signal Vref from the first signal terminal to the control terminal of the drive sub-circuit 50 in response to the first reset control signal G2.

[0064] The control terminal (corresponding gate) of the second reset sub-circuit 20 is electrically connected to the second reset signal terminal to receive the second reset control signal G3. The first terminal of the second reset sub-circuit 20 is electrically connected to the second node S, and the second terminal of the second reset sub-circuit 20 is electrically connected to the initial signal terminal Vini. The second reset sub-circuit 20 is configured to write the second reset signal to the second node S in response to the second reset control signal G3.

[0065] The control terminal of the light-emitting control sub-circuit 30 is electrically connected to the control signal terminal to receive the light-emitting control signal EM. The first terminal of the light-emitting control sub-circuit 30 is electrically connected to the first power supply voltage terminal to receive the first power supply voltage VDD. The second terminal of the light-emitting control sub-circuit 30 is electrically connected to the second terminal of the drive sub-circuit 50.

[0066] The control terminal of the data writing sub-circuit 40 is electrically connected to the data writing control signal terminal to receive the data writing control signal G1. The first terminal of the data writing sub-circuit 40 is electrically connected to the first node G. The second terminal of the data writing sub-circuit 40 is electrically connected to the data signal terminal to receive the data signal Vd. The data writing sub-circuit 40 is configured to write the data signal Vd to the control terminal of the drive sub-circuit 50 in response to the data writing control signal G1.

[0067] Thus, the control terminal (corresponding to the gate) of the drive sub-circuit 50, the first terminal of the first reset sub-circuit 10, and the first terminal of the data writing sub-circuit 40 are all electrically connected to the first node G.

[0068] For example, such as Figure 2 As shown, the pixel circuit also includes a storage sub-circuit 70, the first end of which is electrically connected to the first node G, and the second end of which is electrically connected to the second node S.

[0069] For example, such as Figure 2 As shown, the driving sub-circuit 50 includes a driving transistor T5, the gate of which is configured to receive a driving control signal. The gate of the data writing transistor T1 is electrically connected to the data writing control signal terminal to receive the data writing control signal G1. The first terminal of the data writing transistor T1 is electrically connected to the gate of the driving transistor T5, i.e., electrically connected to the first node G. The second terminal of the data writing transistor T1 is configured to receive the data signal Vd. The data writing sub-circuit 40 is configured to write the data signal Vd to the gate terminal of the driving transistor T5 in response to the data writing control signal G1, i.e., input the data signal Vd to the gate of the driving transistor T5.

[0070] For example, the data writing sub-circuit 40 includes a data writing transistor T1. The gate GE1 of the data writing transistor T1 is electrically connected to the data writing control signal terminal to receive the data writing control signal G1. The first terminal of the data writing transistor T1 is electrically connected to the gate of the driving transistor T5. The second terminal of the data writing transistor T1 is configured to receive the data signal Vd. The data writing sub-circuit 40 is configured to write the data signal Vd to the gate terminal of the driving transistor T5 in response to the data writing control signal G1, that is, to input the data signal Vd to the gate of the driving transistor T5.

[0071] For example, the storage sub-circuit 70 includes a storage capacitor Cst, the first terminal of the data writing transistor T1 is electrically connected to the first capacitor electrode of the storage capacitor Cst and the gate of the driving transistor T5, the second terminal of the data writing transistor T1 is electrically connected to the data signal line Data to receive the data signal Vd; the first terminal of the driving transistor T5 is electrically connected to the first electrode of the light-emitting element EL and configured to be electrically connected to the first electrode of the light-emitting element EL, and the second terminal of the driving transistor T5 is electrically connected to the first power supply voltage terminal to receive the first power supply voltage VDD.

[0072] For example, the first reset sub-circuit 10 includes a first reset transistor T2, the gate of which is electrically connected to a first reset signal terminal to receive a first reset control signal G2, the first terminal of which is electrically connected to the gate of a driving transistor T5, and the second terminal of which is electrically connected to a first signal terminal. The first reset sub-circuit 10 is configured to write a first reset signal or compensation signal Vref from the first signal terminal to the gate of the driving transistor T5 in response to the first reset control signal G2. The gate of the driving transistor T5, the first terminal of the data writing transistor T1, and the first terminal of the first reset transistor T2 are electrically connected to a first node G.

[0073] For example, the light emission control sub-circuit 30 includes a light emission control transistor T4. The gate of the light emission control transistor T4 is electrically connected to the light emission control signal terminal to receive the light emission control signal EM. The first terminal of the light emission control transistor T4 is electrically connected to the first power supply voltage terminal to receive the first power supply voltage VDD. The second terminal of the light emission control transistor T4 is electrically connected to the second terminal of the driving transistor T5.

[0074] For example, the second reset sub-circuit 20 includes a second reset transistor T3. The gate of the second reset transistor T3 is electrically connected to the second reset signal terminal to receive the second reset control signal G3. The first electrode of the second reset transistor T3, the first electrode of the driving transistor T5, the second capacitor electrode C2 of the storage capacitor Cst, and the first electrode of the light-emitting element EL are electrically connected to the second node S. The second electrode of the second reset transistor T3 is electrically connected to the second signal terminal to receive the second reset signal. Under the control of the second reset signal, the second reset sub-circuit 20 is configured to write the second reset signal to the second node S in response to the second reset control signal G3.

[0075] The second electrode of the light-emitting element EL is electrically connected to the second power supply voltage terminal to receive the second power supply voltage VSS. For example, the light-emitting element EL is an organic light-emitting diode (OLED) device, the first electrode of the light-emitting element EL is the anode, and the second electrode of the light-emitting element EL is the cathode.

[0076] For example, the first power supply voltage is, for example, a high power supply voltage VDD, and the second power supply voltage is, for example, a low power supply voltage VSS. For example, the second power supply voltage terminal is the ground terminal.

[0077] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure use thin-film transistors as an example for explanation. The source and drain of the transistors used here can be structurally symmetrical, so their structures can be indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal and the other as the second terminal. Furthermore, transistors can be classified into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage). It should be noted that in the following description, the following uses the term "thin-film transistor" as the standard. Figure 3 The transistors used in this example are N-type transistors, but this is not intended to limit the scope of this disclosure.

[0078] Figure 3 for Figure 2 The diagram shown illustrates a timing sequence of the pixel circuit during actual operation. (Reference) Figure 3 The driving process of the pixel circuit mainly includes the following steps:

[0079] Step 1: During the reset phase of the pixel circuit, the first reset sub-circuit 10 is turned on based on the first reset control signal G2 to write the first reference potential to the control terminal of the driving transistor; the second reset sub-circuit 20 is turned on based on the second reset control signal G3 to write the second reference potential to the first terminal of the driving transistor T5.

[0080] During the reset phase, the first reset sub-circuit 10, under the control of the first reset control signal G2, writes the compensation voltage Vref as the first reference potential to the first node G, which is equivalent to writing the compensation signal Vref to the control terminal of the driving transistor T5 for initialization; similarly, the second reset sub-circuit 20, under the control of the second reset control signal G3, writes the initial signal Vini as the second reference potential to the second node S, which is equivalent to writing the initial signal Vini to the first terminal of the driving transistor T5 for initialization.

[0081] In practical implementation, the voltage value of the first reference potential is usually greater than the voltage value of the second reference potential, that is, the voltage value of the compensation signal Vref is greater than the voltage value of the initial signal Vini. Generally, the value of the initial signal Vini can be a constant signal with a small voltage, or it can be set to 0 volts. The compensation signal Vref needs to simultaneously satisfy the driving of the driving transistor T5 during the compensation process. Therefore, it is necessary to ensure that its voltage value is greater than the threshold voltage of the driving transistor T5 (i.e., the turn-on voltage of the driving transistor T5) and less than the first electrode driving voltage of the light-emitting unit 60, so as to avoid the light-emitting unit being lit up during the non-light-emitting stage due to excessive voltage.

[0082] Step 2: During the compensation phase of the pixel circuit, the first reset sub-circuit 10 is continuously turned on based on the first reset control signal G2, and the second reset sub-circuit 20 is turned off; the light emission control sub-circuit 30 is turned on based on the light emission control signal EM to write the first power supply voltage VDD to the second terminal of the driving transistor T5, and the first terminal of the driving transistor T5 is charged after the driving transistor T5 is turned on until the driving transistor T5 is turned off.

[0083] During the compensation phase, the first reset sub-circuit 10 is kept on, the voltage of the first node G is maintained by the compensation signal Vref, the second reset sub-circuit 20 is turned off, and the light-emitting control sub-circuit 30 is turned on by the light-emitting control signal EM. The second node S is charged by the first power supply voltage VDD until the driving transistor T5 is turned off. Specifically, during the reset phase, the voltage at the first node G (i.e., the control terminal of the driving transistor) is Vref, and the voltage at the second node S (i.e., the first terminal of the driving transistor) is Vini. Since the value of Vref is greater than the value of Vini, the gate-source voltage Vgs of the driving transistor T5 is Vref - Vini. Considering the limitation of its actual voltage value, the value of the gate-source voltage Vgs is greater than the threshold voltage Vth of the driving transistor T5. At this time, the driving transistor T5 is in the conducting state. After entering the compensation phase, the second reset sub-circuit 20 is turned off, and the light-emitting control signal EM is turned on, so that the working voltage VDD flows into the driving transistor T5 and charges the second node S. After charging continues for a certain period of time, as the voltage of the second node S continues to increase, the difference between the gate-source voltage Vgs and Vth continues to decrease until Vgs = Vth. At this time, the driving transistor T5 is turned off, and the voltage of the second node S is Vref - Vth, thereby achieving compensation for the driving transistor T5.

[0084] Step 3: During the data writing stage of the pixel circuit, the data writing sub-circuit 40 is turned on based on the data writing control signal G1 to write the data signal Vd to the control terminal of the driving transistor T5.

[0085] The data writing sub-circuit 40 is activated under the control of the data writing control signal G1, writing the data signal Vd to the first node G, which serves as the gate voltage of the driving transistor T5 to control the activation level of the driving transistor T5, thereby controlling the illumination level of the corresponding light-emitting unit 60. When the data writing sub-circuit 40 is activated by the data writing control signal G1, the first reset sub-circuit 10, the second reset sub-circuit 20, and the light-emitting control sub-circuit 30 are all in the off state.

[0086] Step 4: During the light-emitting stage of the pixel circuit, the light-emitting control sub-circuit is turned on based on the pulse width modulation signal, so that the driving transistor T5 is turned on and drives the light-emitting unit 60 to light up under the action of the first power supply voltage VDD and the second power supply voltage VSS.

[0087] In this embodiment, in addition to the light emission control signal EM, the control signal terminal can also input a pulse width modulation (PWM) signal. During the light emission phase, the light emission control sub-circuit is periodically turned on by the PWM signal. The on-time ratio (duty) and the number of switching of the PWM signal are used to control the on-time of the light emission control sub-circuit. The longer the on-time of the light emission control sub-circuit, the higher the brightness of the light emission unit. Correspondingly, the shorter the on-time of the light emission control sub-circuit, the lower the brightness of the light emission unit, so as to achieve brightness control when the light emission unit is lit.

[0088] For pixel circuits, for example Figure 2 The pixel circuit shown exhibits a significant leakage problem during operation. During the light-emitting phase, when the transistor electrically connected to the gate of the driving transistor is turned off within a single frame, a large off-state current in this transistor can cause severe leakage through the gate of the driving transistor (i.e., the first node G). This leakage leads to a potential change in the gate of the driving transistor, resulting in the inability to maintain the written grayscale and causing screen flickering. This is particularly problematic when the transistor connected to the gate of the driving transistor is a low-temperature polysilicon (LTPS) transistor. Due to the high mobility of the active layer in polysilicon, leakage current is significant. In low-frequency or ultra-high PPI displays, the limited space in the pixel circuit layout can result in a small capacitance value for the storage capacitor Cst. In such cases, severe leakage and potential changes at the gate of the driving transistor T5 (first node G) cause the screen flickering due to the inability to maintain the written grayscale. Therefore, a design scheme to improve the leakage at the first node G is needed to achieve better display performance.

[0089] For example, Figure 4 for Figure 2 The diagram shows a layout of a pixel circuit. Figures 5A-5H They are shown respectively Figure 4 The diagram shows a schematic planar view of the structure of each layer of the pixel circuit of the display substrate. Figure 4 What is shown is Figure 2 The diagram shows the pixel circuit layout. Figure 5A A plan view of the semiconductor layer 300 of a display substrate is provided for at least one embodiment of this disclosure. Figure 5B A plan view of the first conductive layer 310 of a display substrate is provided for at least one embodiment of this disclosure. Figure 5C This is a schematic diagram of the stacking of semiconductor layer 300 and first conductive layer 310. Figure 5D This is a plan view of the second conductive layer 320 of a display substrate provided in at least one embodiment of the present disclosure. Figure 5E This is a schematic diagram showing the stacking of semiconductor layer 300, first conductive layer 310, and second conductive layer 320. Figure 5F This is a plan view of the third conductive layer 330 of a display substrate provided in at least one embodiment of the present disclosure. Figure 5G This is a schematic diagram showing the stacking of semiconductor layer 300, first conductive layer 310, second conductive layer 320, and third conductive layer 330. Figure 5H This is a plan view of the fourth conductive layer 340 of a display substrate provided in at least one embodiment of the present disclosure.

[0090] For example, combining Figures 5A-5H And more detailed information to follow. Figure 5J The display substrate also includes a first insulating layer ILD1, a second insulating layer ILD2, a third insulating layer ILD3, and a fourth insulating layer ILD4; the first insulating layer ILD1 is located between the semiconductor layer 300 and the first conductive layer 310, the second insulating layer ILD2 is located between the first conductive layer 310 and the second conductive layer 320, the third insulating layer ILD3 is located between the second conductive layer 320 and the third conductive layer 330, and the fourth insulating layer ILD4 is located between the third conductive layer 330 and the fourth conductive layer 340.

[0091] For example, the display substrate includes a substrate, and pixel circuitry is disposed on the main surface of the substrate. For instance, on the main surface of the substrate and along a direction from near to far from the substrate, a semiconductor layer 300, a first conductive layer 310, a second conductive layer 320, a third conductive layer 330, and a fourth conductive layer 340 are arranged sequentially; that is, the first conductive layer 310 is located on the side of the semiconductor layer 300 away from the substrate, the second conductive layer 320 is located on the side of the first conductive layer 310 away from the substrate, the third conductive layer 330 is located on the side of the second conductive layer 320 away from the substrate, and the fourth conductive layer 340 is located on the side of the third conductive layer 330 away from the substrate. Of course, the display substrate provided in other embodiments may also include a portion of the first conductive layer 310, the second conductive layer 320, the third conductive layer 330, and the fourth conductive layer 340; not all four conductive layers must be disposed in every display substrate provided in every embodiment.

[0092] For example, Figure 4 This illustrates two adjacent sub-pixels, namely the first sub-pixel P1 and the second sub-pixel P2. For example, combining... Figure 1 Adjacent first sub-pixels P1 and P2 can both emit red light to form a red light-emitting unit R, adjacent first sub-pixels P1 and P2 can both emit green light to form a green light-emitting unit G, and adjacent first sub-pixels P1 and P2 can both emit blue light to form a blue light-emitting unit B. For example, the display substrate 10 includes multiple rows of red pixels with red light-emitting units R, rows of green pixels with multiple green light-emitting units G, and rows of blue pixels with multiple blue light-emitting units B. The red, green, and blue pixel rows are arranged sequentially in the first direction D1 and all extend along the second direction D2. A continuously distributed row of red pixels, a row of green pixels, and a row of blue pixels constitute a repeating unit. For example, the display substrate 10 includes multiple repeating units.

[0093] The structure of a subpixel is introduced using a first subpixel P1 as an example. For instance, each subpixel can include a structure that performs the following functions of the first subpixel P1.

[0094] For example, refer to Figure 5A The active layers of each transistor in the first sub-pixel P1 and each transistor in the second sub-pixel P2 are located in the semiconductor layer 300. The active layers of each transistor in the first sub-pixel P1 each include their respective channel regions A1 to A5, and the active layers of each transistor in the second sub-pixel P2 each include their respective channel regions A10 to A50. (Reference) Figure 5BThe gates GE1~GE5 of each transistor in the first sub-pixel P1 and the first capacitor electrode C1 of the storage capacitor Cst are located in the first conductive layer 310. The first conductive layer 310 also includes the gates GE10~GE50 of each transistor in the second sub-pixel P2. (Reference) Figure 5D For each sub-pixel, taking the first sub-pixel P1 as an example, the second capacitor electrode C2 of the storage capacitor Cst is located in the second conductive layer 320; Reference Figure 5F The compensation signal line LVref, the lateral power line VDD1, the first auxiliary gate line AGL1, the second auxiliary gate line AGL2, and each connecting electrode are located in the third conductive layer 330; Reference Figure 5H The vertical power line VDD2 and the data signal line Data are located on the fourth conductive layer 340.

[0095] In the display panel provided in at least one embodiment of this disclosure, the connection position between the first electrode of the control transistor and the active layer of the control transistor is a first position, the connection position between the second electrode of the control transistor and the active layer of the control transistor is a second position, and the connection position between the first electrode of the driving transistor and the active layer of the driving transistor is a third position. The distance between the first position and the second position is greater than the distance between the first position and the third position.

[0096] For example, the pixel circuit of the first sub-pixel P1 includes a control sub-circuit, which includes a control transistor. The first terminal of the control transistor is electrically connected to the gate GE5 of the driving transistor T5. For example, the control sub-circuit may include a data writing sub-circuit 40; that is, the data writing sub-circuit 40 is an example of a control sub-circuit, and the control transistor includes a data writing transistor T1. The structure of the data writing transistor T1 will be described below using the example of the control transistor including the data writing transistor T1.

[0097] certainly, Figure 2 and Figure 4 The pixel circuit shown is a 5T1C circuit. In other embodiments, the pixel circuit may be other types of pixel circuits, not limited to the 5T1C circuit.

[0098] refer to Figure 5A and Figure 5GThe connection point between the first electrode of data writing transistor T1 and the active layer of the first electrode of data writing transistor T1 is the first sub-position, and the connection point between the second electrode of data writing transistor T1 and the active layer of data writing transistor T1 is the second position. That is, when data writing transistor T1 acts as a control transistor, the first sub-position is the aforementioned first position, and the second sub-position is the aforementioned second position. The connection point between the first electrode of driving transistor T5 and the active layer of driving transistor T5 is the third position. The distance between the first sub-position and the second sub-position is greater than the distance between the first sub-position and the third position, thereby increasing the length of the active layer of data writing transistor T1 and increasing the distance between the source and drain of data writing transistor T1. This increases the equivalent resistance of data writing transistor T1 and reduces the leakage current of data writing transistor T1. As a result, the risk of leakage current through the first node G in the off state through data writing transistor T1 can be reduced, and the potential change (undesirable fluctuation) of the gate (first node G) of driving transistor T5 caused by this can be reduced, thus improving or eliminating the screen flickering phenomenon caused by the display panel.

[0099] For example, the material of semiconductor layer 300 is low-temperature polysilicon (LTPS). For example, the active layers of multiple transistors in a sub-pixel P form an integral structure. In this case, the multiple transistors in a sub-pixel P are LTPS type transistors. Since the mobility of the low-temperature polysilicon active layer is high, the leakage current of the corresponding transistors is large. In this case, the problem of potential change (undesirable fluctuation) of the first node G caused by the leakage current of the transistors electrically connected to the first node G is particularly serious. The display substrate provided in the embodiments of this disclosure can significantly improve this problem.

[0100] Of course, the material of the semiconductor layer 300 provided in other embodiments of this disclosure is not limited to low-temperature polycrystalline silicon, but can also be an oxide semiconductor material such as indium gallium zinc oxide (IGZO), or other semiconductor materials. If the material of the semiconductor layer 300 is not low-temperature polycrystalline silicon, the problem of potential change (undesirable fluctuation) of the first node G caused by the leakage current of the transistor electrically connected to the first node G still exists. Similarly, the display substrate provided in the embodiments of this disclosure can also play a role in improving this problem.

[0101] For example, the straight-line distance between the first sub-position and the second sub-position is greater than the straight-line distance between the first sub-position and the third position; or, the distance between the first sub-position and the second sub-position in the first direction D1 is greater than the distance between the first sub-position and the third position in the first direction D1. For example, in each embodiment of this disclosure, for the data writing transistor T1, the distance between the first sub-position and the second sub-position is greater than 0.5 times, 0.7 times, or 0.8 times the width of a sub-pixel, so as to make full use of the limited space of the sub-pixel to achieve sufficient distance between the source and drain of the data writing transistor T1, thereby achieving the desired effect of reducing the leakage current of the data writing transistor T1; for example, the distance between the first sub-position and the second sub-position in the first direction D1 is greater than 0.5 times, 0.7 times, or 0.8 times the width of a sub-pixel in the first direction D1.

[0102] Alternatively, the sum of the distances between the first and second sub-positions in the first direction D1 and the second direction D2 is greater than the sum of the distances between the first and third sub-positions in the first direction D1 and the second direction D2.

[0103] For example, refer to Figure 4 and Figure 5F-5G The first capacitor electrode C1 of the storage capacitor Cst and the gate of the driving transistor T5 are integrally formed. The sub-pixel P1 includes a first connection block CE1, for example, the first connection block CE1 is located in the third conductive layer 330. The first connection block CE1 is electrically connected to the gate of the driving transistor T5 through the first connection via VO3, that is, electrically connected to the first capacitor electrode C1 of the storage capacitor Cst. A portion of the first connection via VO3 exposes a portion of the semiconductor layer 300. Since the active layers of each transistor in the pixel circuit are integrally formed, a portion of the first connection via VO3 exposes a portion of the active layer of the data writing transistor T1. The first connection block CE1 is electrically connected to the active layer of the data writing transistor T1 through the first connection via VO3. (Refer to...) Figure 5A Since the active layer of the data writing transistor T1 and the active layer of the first reset transistor T2 form a continuous integral structure, the first connection block CE1 is also electrically connected to the active layer of the first reset transistor T2 through the first connection via V03. Therefore, the first connection block CE1 acts as the first electrode of the data writing transistor T1, realizing the electrical connection of the first capacitor electrode C1 of the storage capacitor Cst, the gate GE5 of the driving transistor T5, the first electrode of the data writing transistor T1, and the first electrode of the first reset transistor T2 to the first node G. The position of the first connection via V03 is the aforementioned first sub-position.

[0104] For example, the second terminal of the data writing transistor T1 is electrically connected to the active layer of the data writing transistor T1 through a second connection via, and the location of the second connection via is the second sub-position.

[0105] For example, refer to Figure 5F and Figure 5G The pixel circuit includes a first connection electrode L1 that is disposed on a different layer from the active layer of the driving transistor T5 and the data signal line Data. For example, the first connection electrode L1 is located in the third conductive layer 330. Figure 5I It is along Figure 4 A cross-sectional diagram of line A1-A2 in the diagram is shown in the reference diagram. Figure 4 , Figure 5F-5G and Figure 5I The first extension portion 21 of the lateral portion 2 is electrically connected to the first connection electrode L1 through a first via V1, and the first connection electrode L1 is electrically connected to the data signal line Data through a second via V2, thereby realizing the electrical connection between the data signal line Data and the active layer of the data writing transistor T1. In this case, the first via V1 serves as the second connection via, and thus, the position of the first via V1 is the second sub-position. On the one hand, realizing the electrical connection between the data signal line Data and the active layer of the data writing transistor T1 through the two vias, the first via V1 and the second via V2, arranged in a direction perpendicular to the main surface of the substrate, can ensure the reliability of the electrical connection. On the other hand, using the first extension portion 21 with increased length to electrically connect to the data signal line Data via the first via V1 and the first connection electrode L1 is beneficial to increasing the effective length of the active layer of the data writing transistor T1.

[0106] It should be noted that the effective length of the active layer of the data writing transistor T1 refers to the length of the active layer of the data writing transistor T1 that actually participates in conduction during the process of generating leakage current.

[0107] For example, the first via V1 is located at the end of the first extension 21 away from the longitudinal portion 1 in the second direction D2. In this way, the effective length of the active layer of the data writing transistor T1 can be maximized by utilizing the length of the first extension 21, and the entire length of the first extension 21 can be used to increase the effective length of the active layer.

[0108] For example, refer to Figure 5F and Figure 5GThe pattern of the first connecting electrode L1 is basically the same as and overlaps with the pattern of the lateral portion 2 of the active layer of the data writing transistor T1. That is, the orthographic projection of the first connecting electrode L1 on the main surface of the substrate is basically overlapped with the orthographic projection of the lateral portion 2 of the active layer of the data writing transistor T1 on the main surface of the substrate. This avoids the first connecting electrode L1 occupying extra space, reduces the volume of the pixel circuit, and helps to improve the PPI of the display substrate 10.

[0109] Figure 5J It is along Figure 4 A cross-sectional diagram of line B1-B2 in the diagram. For example, refer to... Figure 4 , Figure 5F-5G and Figure 5J The second connecting block CE2 located in the third conductive layer 330 is electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through the third connecting via V04. For example, the upper part of the third connecting via V04 exposes a portion of the second capacitor electrode C2 of the storage capacitor Cst, and the second connecting block CE2 contacts the second capacitor electrode C2 of the storage capacitor Cst through the upper part of the third connecting via V04 to be electrically connected. Since the active layer of the driving transistor T5 and the active layer of the second reset transistor T3 form a continuous integral structure, the lower part of the third connecting via VO4 exposes the active layer T3a of the driving transistor T5, which also exposes the active layer T3a of the second reset transistor T3. The lower part of the third connecting via VO4 is connected to the upper part of the third connecting via VO4, and the lower part of the third connecting via VO4 is located on the side of the upper part of the third connecting via VO4 closer to the substrate 01. Therefore, the second connecting block CE2 is electrically connected to the active layer T5a of the driving transistor T5 through the lower part of the third connecting via VO4, and is also electrically connected to the active layer T3a of the second reset transistor T3 (i.e., electrically connected to the semiconductor layer 300). Therefore, the position of the third connection via V04 is the aforementioned third position. The second connection block CE2 acts as the first electrode of the second reset transistor T3 and the first electrode of the driving transistor T5, realizing that the first electrode of the second reset transistor T3, the first electrode of the driving transistor T5, and the second capacitor electrode C2 of the storage capacitor Cst are electrically connected to the second node S. Furthermore, the second connection block CE2 is electrically connected to the third connection block CE0 located in the fourth conductive layer 340 through the via V05. The third connection block CE0 can be further electrically connected to the first electrode (not shown) of the light-emitting element EL on the side of the fourth conductive layer 340 away from the substrate 01, thereby realizing the electrical connection between the second node S and the first electrode of the light-emitting element EL.

[0110] refer to Figure 4 and Figure 5AFor example, the channel region A5 of the driving transistor T5 and the channel region A1 of the data writing transistor T1 are arranged in a first direction D1, and a second direction D2 intersects the first direction D1, for example, the second direction D2 is perpendicular to the first direction D1. (Reference) Figure 5A The active layer of the data writing transistor T1 includes a vertical portion 1 extending along a first direction D1 and a lateral portion 2 extending along a second direction D2. The vertical portion 1 includes the channel region A1 of the data writing transistor T1, that is, the vertical portion 1 includes the channel region of the control transistor. The lateral portion 2 is connected to the vertical portion 1 and includes a first extension portion 21 and a second extension portion 22. The first extension portion 21 protrudes from the vertical portion 1 toward a first side in the second direction D2, and the second extension portion 22 protrudes from the vertical portion 1 toward a second side opposite to the first side in the second direction D2. In this way, the length of the active layer of the data writing transistor T1 is increased, the distance between the drain and source of the data writing transistor T1 is increased, thereby increasing the equivalent resistance of the data writing transistor T1 and reducing the leakage current of the data writing transistor T1. As a result, the risk of leakage current through the first node G through the data writing transistor T1 in the off state can be reduced, the potential change of the gate (point G) of the driving transistor T5 caused by this can be reduced, and the screen flickering phenomenon caused by the display panel can be improved or eliminated.

[0111] It should be noted that the "channel region of a transistor" in this disclosure refers to the region where the active layer of the transistor and the gate of the transistor overlap each other in a direction perpendicular to the main surface of the substrate. That is, the region where the orthographic projection of the active layer of the transistor on the main surface of the substrate overlaps with the orthographic projection of the gate on the main surface of the substrate corresponds to the channel region of the transistor.

[0112] For example, refer to Figure 5A The channel region A5 of the driving transistor T5 is located on the first side of the vertical portion 1 in the second direction D2. The length of the first extension portion 21 in the second direction D2 is not less than the length of the second extension portion 22 in the second direction D2. Therefore, the space on the first side of the vertical portion 1 in the second direction D2 can be fully utilized to extend the length of the active layer of the data writing transistor T1, increasing the distance between the source and drain of the data writing transistor T1. This minimizes the leakage current of the data writing transistor T1 by utilizing the limited space, thereby reducing the risk of leakage current from the first node G through the data writing transistor T1. For example, the length of the first extension portion 21 in the second direction D2 is not greater than the length of the second extension portion 22 in the second direction D2, or the lengths of the first extension portion 21 and the second extension portion 22 in the second direction D2 are substantially equal.

[0113] For example, refer to Figure 5AThe vertical portion 1 has a distal end in the first direction D1, away from the channel region A5 of the driving transistor T5. The first extension portion 21 and the second extension portion 22 are located at the distal end of the vertical portion 1 and connected to the distal end. In this way, the channel region A1 of the data writing transistor T1 can be formed using the vertical portion 1 extending along the first direction D1, and the lateral portion 2 can be set using the space created on both sides in the second direction D2 at the distal end. The space is used to realize the structure of the data writing transistor T1 in a reasonable way, and the length of the active layer of the data writing transistor T1 is increased to increase the equivalent resistance of the data writing transistor T1.

[0114] For example, refer to Figure 5A The first extension 21 of the active layer of the data writing transistor T1 at least partially overlaps with the channel region A5 of the driving transistor T5 in the first direction D1. Thus, by utilizing the space in the second direction D2 to appropriately increase the length of the first extension 21, which extends at least to the location of the channel region A5 of the driving transistor T5 in the second direction D2, the leakage current of the data writing transistor T1 can reach a suitable value, effectively reducing the leakage current of the data writing transistor T1, without occupying the layout space of other structures in the pixel circuit, ensuring the normal functioning of the pixel circuit and guaranteeing display quality.

[0115] For example, refer to Figure 4 and Figure 5H The display substrate includes a data signal line Data that provides a data signal Vd. The lateral portion 2 of the active layer of the data writing transistor T1 is electrically connected to the data signal line Data. For example, the data signal line Data provides the data signal Vd to both the first sub-pixel P1 and the second sub-pixel P2; that is, the first sub-pixel P1 and the second sub-pixel P2 share a single data signal line Data. Figure 1 In the display substrate 10, there are a first data signal line Data1, a second data signal line Data2, ..., a (N-1)th data signal line Data(N-1), and an Nth data signal line DataN, where N is a positive integer greater than 1. The display substrate 10 includes a plurality of sub-pixels P arranged in a second direction D2. The sub-pixels are numbered starting from 1 along a first direction, thus including sub-pixels with odd numbers and sub-pixels with even numbers. Each adjacent sub-pixel with an odd number and a sub-pixel with an even number share a single data signal line.

[0116] For example, the first sub-pixel P and the second sub-pixel P are arranged and adjacent to each other in the second direction D2; the gate GE1 of the data writing transistor T1 of the first sub-pixel P and the gate GE1 of the data writing transistor T1 of the second sub-pixel P are independent of each other so as to receive different data writing control signals G1 respectively.

[0117] For example, refer to Figure 4 , Figure 5F and Figure 5G The display substrate 10 includes a first auxiliary gate line AGL1 disposed on a different layer from the gate GE1 of the data writing transistor T1 of the first sub-pixel P. For example, the first auxiliary gate line AGL1 is located in the third conductive layer 330, and the first auxiliary gate line AGL1 is electrically connected to the gate GE1 of the data writing transistor T1 of the first sub-pixel P through a fourth via V4. The display substrate 10 includes a second auxiliary gate line AGL2 disposed on a different layer from the gate GE1 of the data writing transistor T1 of the second sub-pixel P. For example, the second auxiliary gate line AGL2 is also located in the third conductive layer 330, and the second auxiliary gate line AGL2 is electrically connected to the gate GE1 of the data writing transistor T1 of the second sub-pixel P through a fifth via V5. The display substrate 10 includes a plurality of sub-pixels P arranged in the second direction D2. The plurality of sub-pixels are numbered starting from 1 along the first direction, thus including sub-pixels with odd numbers and sub-pixels with even numbers. For example, the first auxiliary gate line AGL1 is electrically connected to multiple sub-pixels with odd numbers through multiple fourth vias V4, and the second auxiliary gate line AGL2 is electrically connected to multiple sub-pixels with even numbers through multiple sixth vias V6.

[0118] For example, the first extension 21 of the active layer of the data writing transistor T1 at least partially overlaps with the fourth via V4 in the first direction D1. Thus, by utilizing the space in the second direction D2 to appropriately increase the length of the first extension 21, which extends at least to the location of the fourth via V4 in the second direction D2, the leakage current of the data writing transistor T1 can reach a suitable value, effectively reducing the leakage current of the data writing transistor T1, without occupying the layout space of other structures in the pixel circuit, ensuring the normal functioning of the pixel circuit and guaranteeing display quality.

[0119] For example, the gate of the common-gate transistor of the first sub-pixel P and the gate of the common-gate transistor of the second sub-pixel P are electrically connected to each other to share the same gate scan signal. For example, the common-gate transistor includes at least one of the transistors in the pixel circuit other than the data writing transistor T1 and the driving transistor T5; for example, in Figure 4 In the pixel circuit shown, all transistors except for the data writing transistor T1 and the driving transistor T5 share the same gate line and thus the same gate scan signal. Of course, this is not the only possibility in other embodiments.

[0120] For example, refer to Figure 5F and Figure 5GThe display substrate 10 includes a second connection electrode disposed on a different layer from the gate of a common-gate transistor. The second connection electrode is electrically connected to the gate of the common-gate transistor of the first sub-pixel P1 through a sixth via V6 and to the gate of the common-gate transistor of the second sub-pixel P2 through a seventh via V7. Thus, the gates of the transistors sharing the gate line are electrically connected to each other through the second connection electrode to achieve shared gate scan signals. For example, the second connection electrode includes a first sub-electrode L21, a second sub-electrode L22, a third sub-electrode L23, and a fourth sub-electrode L24; the sixth via V6 includes sub-vias V61, V62, V63, and V64; and the seventh via V7 includes sub-vias V71, V72, V73, and V74. The first sub-electrode L21 is electrically connected to the gate GE2 of the first reset transistor T2 of the first sub-pixel P1 through sub-via V61 and to the gate GE2 of the first reset transistor T2 of the second sub-pixel P2 through sub-via V71. The gate GE20 of the reset transistor T20 is electrically connected. The second sub-electrode L22 is electrically connected to the gate GE3 of the second reset transistor T3 of the first sub-pixel P1 through the sub-via V62 and to the gate GE30 of the second reset transistor T30 of the second sub-pixel P2 through the sub-via V72. The third sub-electrode L23 is electrically connected to the gate GE4 of the light-emitting control transistor T4 of the first sub-pixel P1 through the sub-via V63 and to the gate GE40 of the light-emitting control transistor T40 of the second sub-pixel P2 through the sub-via V73.

[0121] Thus, for reference Figure 5F The first auxiliary gate line AGL1 and the second connecting electrode are both disposed on the same layer as the first connecting electrode L1, for example, both are located in the third conductive layer 330. In this way, the sufficient space of the third conductive layer 330 can be used to arrange these conductive structures, which helps to reduce the space occupied by the pixel circuit of each sub-pixel, thereby helping to improve the PPI of the display substrate 10 and achieve high resolution.

[0122] For example, the aforementioned control transistor also includes a first reset transistor T2. The connection position between the first electrode of the first reset transistor T2 and the active layer of the first reset transistor T2 is the third sub-position, and the connection position between the second electrode of the first reset transistor T2 and the active layer of the first reset transistor T2 is the fourth sub-position; the distance between the first sub-position and the second sub-position is greater than the distance between the third sub-position and the fourth sub-position. Thus, compared to the first reset transistor T2, the length of the active layer of the data writing transistor T1 is increased to a greater extent, thereby increasing the distance between the drain and source of the data writing transistor T1, and thus increasing the equivalent resistance of the data writing transistor T1. Since the compensation signal or the first reset signal Vref (participating voltage) transmitted to the first node G via the first reset transistor T2 is essentially a constant voltage, while the data voltage Vd transmitted to the first node G via the data writing transistor T1 is a voltage that changes in real time, the leakage current of the data writing transistor T1 has a greater impact on the potential stability of the first node G. Therefore, increasing the length of the active layer of the data writing transistor T1 is beneficial for maintaining the stability of the potential of the first node G during the light-emitting stage, and is more conducive to improving display quality.

[0123] For example, refer to Figure 5F The display substrate 10 includes a compensation signal line LVref that provides a compensation signal Vref. A first extension 210 of the lateral portion 20 of the active layer of the first reset transistor T2 is electrically connected to the compensation signal line via an eighth via V8. For example, the end of the first extension 210 away from the longitudinal portion 11 of the active layer of the first reset transistor T2 in the second direction D2 is electrically connected to the compensation signal line LVref via the eighth via V8. The position of the eighth via V8 serves as the second position when the control transistor is the first reset transistor T2, i.e., as the fourth sub-position.

[0124] For example, at least a portion of the pattern of the compensation signal line LVref has the same shape as and overlaps with the pattern of the first extension portion 21 of the active layer of the first reset transistor T2, so as to save space and reduce the difficulty of fabricating the mask used to form the pattern of the compensation signal line LVref and the pattern of the first extension portion 21 of the active layer of the first reset transistor T2 in the patterning process.

[0125] The active layer of the data writing transistor T1 extends from the first sub-position to the second sub-position, and the active layer of the first reset transistor T2 extends from the third sub-position to the fourth sub-position. The total length of the active layer of the data writing transistor T1 from the first sub-position to the second sub-position is greater than the total length of the active layer of the first reset transistor T2 from the third sub-position to the fourth sub-position. Similarly, compared to the first reset transistor T2, the length of the active layer of the data writing transistor T1 is increased to a greater extent, thereby increasing the distance between the drain and source of the data writing transistor T1, which increases the equivalent resistance of the data writing transistor T1. This is beneficial for maintaining the stability of the first node G potential during the light-emitting stage and is more conducive to improving display quality.

[0126] For example, refer to Figure 4 and Figure 5G The connection position between the first electrode of the second reset transistor T3 and the active layer of the second reset transistor is the seventh sub-position; the connection position between the second electrode of the second reset transistor T3 and the active layer of the second reset transistor T3 is the eighth sub-position; the connection position between the first electrode of the light-emitting control transistor T4 and the active layer of the light-emitting control transistor T4 is the ninth sub-position; and the connection position between the second electrode of the light-emitting control transistor T4 and the active layer of the light-emitting control transistor 4T is the tenth sub-position.

[0127] For example, refer to Figure 5F and Figure 5G The display substrate 10 also includes a lateral power line VDD1, which is electrically connected to a first power supply voltage terminal. For example, the lateral power line VDD1 is located in the third conductive layer 330, and it is electrically connected to the active layer of the light-emitting control transistor T4 through a via VO1 to achieve electrical connection between the first terminal of the light-emitting control transistor T4 and the lateral power line VDD1 to receive the first power supply voltage VDD. (Reference) Figure 5H and Figure 4 The display substrate 10 also includes a vertical power line VDD2. For example, the vertical power line VDD2 is located in the fourth conductive layer 340. The vertical power line VDD2 is electrically connected to the horizontal power line VDD1 through the via VO2 to form a horizontal and vertical power line network in the display substrate 10, so as to conduct the first power supply voltage VDD to each sub-pixel.

[0128] For example, refer to Figure 5F and Figure 5G The display substrate 10 also includes an initial signal line LVini. For example, the initial signal line LVini is located in the third conductive layer 330. The initial signal line LVini is electrically connected to the active layer of the second reset transistor T3 through the via V06 to provide a second reset signal.

[0129] Here, the position of the third connecting via V04 is designated as the seventh sub-position, the position of via V06 as the eighth sub-position, and the position of via V01 as the ninth sub-position; the active layer of the driving transistor T5 and the active layer of the light-emitting control transistor T4 are integrally formed, the second electrode of the driving transistor T5 is electrically connected to the second electrode of the light-emitting control transistor T4, and the position O is designated as the tenth sub-position.

[0130] For example, the distance between the first and second sub-positions is greater than the distance between the seventh and eighth sub-positions, and / or the distance between the first and second sub-positions is greater than the distance between the ninth and tenth sub-positions; or, the distance between the fifth and sixth sub-positions is greater than the distance between the seventh and eighth sub-positions, and / or the distance between the fifth and sixth sub-positions is greater than the distance between the ninth and tenth sub-positions.

[0131] For example, the distance between the two positions mentioned above refers to the straight-line distance between the two positions, or the distance between the two positions in the first direction D1, or the sum of the distance between the two positions in the first direction D1 and the distance in the second direction D2.

[0132] The active layer of the second reset transistor T3 extends from the seventh sub-position to the eighth sub-position, and the active layer of the light-emitting control transistor T4 extends from the ninth sub-position to the tenth sub-position; the total length of the active layer of the data writing transistor T1 from the first sub-position to the second sub-position is greater than the total length of the active layer of the second reset transistor T3 from the seventh sub-position to the eighth sub-position, and / or, the total length of the active layer of the data writing transistor T1 from the first sub-position to the second sub-position is greater than the total length of the active layer of the light-emitting control transistor T4 from the ninth sub-position to the tenth sub-position.

[0133] Alternatively, the active layer of the first reset transistor T2 extends from the third sub-position to the fourth sub-position, and the total length of the active layer of the first reset transistor T2 from the third sub-position to the fourth sub-position is greater than the total length of the active layer of the second reset transistor T3 from the seventh sub-position to the eighth sub-position, and / or, the total length of the active layer of the first reset transistor T2 from the third sub-position to the fourth sub-position is greater than the total length of the active layer of the light-emitting control transistor T4 from the ninth sub-position to the tenth sub-position.

[0134] refer to Figure 4 and Figure 5AThe active layer of the first reset transistor T2 includes a vertical portion 11 extending along a first direction D1 and a lateral portion 20 extending along a second direction D2. The vertical portion 11 includes the channel region A2 of the first reset transistor T2, that is, the vertical portion 11 includes the channel region of the control transistor. The lateral portion 20 is connected to the vertical portion 11 and includes a first extension portion 210 and a second extension portion 220. The first extension portion 210 protrudes from the vertical portion 11 toward a first side in the second direction D2, and the second extension portion 220 protrudes from the vertical portion 11 toward a second side opposite to the first side in the second direction D2. In this way, the length of the active layer of the first reset transistor T2 is increased, the distance between the drain and source of the first reset transistor T2 is increased, thereby increasing the equivalent resistance of the first reset transistor T2. This reduces the risk of leakage current through the first node G through the first reset transistor T2, reduces the potential change of the gate (point G) of the driving transistor T5 caused by this, and improves or eliminates the above-mentioned screen flickering phenomenon caused by the display panel.

[0135] For example, refer to Figure 5A The channel region A5 of the driving transistor T5 is located on the first side of the vertical portion 11 in the second direction D2. The length of the first extension portion 210 in the second direction D2 is not less than the length of the second extension portion 220 in the second direction D2. Therefore, the space on the first side of the vertical portion 11 in the second direction D2 can be fully utilized to extend the length of the active layer of the first reset transistor T2, thereby minimizing the leakage current of the first reset transistor T2 within the limited space and reducing the risk of leakage current from the first node G through the first reset transistor T2. For example, the length of the first extension portion 210 in the second direction D2 is not greater than the length of the second extension portion 220 in the second direction D2, or the lengths of the first extension portion 210 and the second extension portion 220 in the second direction D2 are substantially equal.

[0136] For example, refer to Figure 5A The vertical portion 11 has a distal end in the first direction D1, away from the channel region A5 of the driving transistor T5. The first extension portion 210 and the second extension portion 220 are located at the distal end of the vertical portion 11 and connected to the distal end. In this way, the channel region A2 of the first reset transistor T2 can be formed using the vertical portion 11 extending along the first direction D1, and the lateral portion 20 can be set using the space created on both sides in the second direction D2 at the distal end. The structure of the first reset transistor T2 can be realized by making reasonable use of space, and the length of the active layer of the first reset transistor T2 can be increased to increase the equivalent resistance of the first reset transistor T2.

[0137] For example, refer to Figure 5CThe first extension 210 of the active layer of the first reset transistor T2 at least partially overlaps with the channel region A5 of the driving transistor T5 in the first direction D1. Thus, by utilizing the space in the second direction D2 to appropriately increase the length of the first extension 210, which extends at least to the location of the channel region A5 of the driving transistor T5 in the second direction D2, the leakage current of the first reset transistor T2 can reach a suitable value, effectively reducing the leakage current of the first reset transistor T2, without occupying the layout space of other structures in the pixel circuit, ensuring the normal functioning of the pixel circuit and guaranteeing display quality.

[0138] For example, refer to Figure 5A and Figure 5C In the first direction D1, the channel region A5 of the driving transistor T5 is located between the channel region A1 of the data writing transistor T1 and the channel region A2 of the first reset transistor T2; in the first direction D1, the lateral portion 2 of the active layer of the data writing transistor T1 is located on the side of the channel region A1 of the data writing transistor T1 away from the channel region A5 of the driving transistor T5, that is, the first extension portion 21 and the second extension portion 22 of the active layer of the data writing transistor T1 are both located on the side of the channel region A1 of the data writing transistor T1 away from the channel region A5 of the driving transistor T5; and in the first direction D1, the lateral portion 20 of the active layer of the first reset transistor T2 is located on the side of the channel region A2 of the first reset transistor T2 away from the channel region A5 of the driving transistor T5, that is, the first extension portion 210 and the second extension portion 220 of the active layer of the first reset transistor T2 are both located on the side of the channel region A2 of the first reset transistor T2 away from the channel region A5 of the driving transistor T5.

[0139] For example, the length of the first extension portion 210 of the active layer of the first reset transistor T2 in the second direction D2 is greater than or equal to the length of the first extension portion 21 of the active layer of the data writing transistor T1 in the second direction D2. The location of the first extension portion 210 of the active layer of the first reset transistor T2 is also used to set the compensation signal line LVref along the second direction D2. Therefore, in the semiconductor layer 300, the space of the first extension portion 210 of the active layer of the first reset transistor T2 is relatively large, which can sufficiently increase the length of the active layer of the first reset transistor T2 to sufficiently increase the length of the active layer of the first reset transistor T2, so as to make the most of the limited space to reduce the leakage current of the first reset transistor T2 and effectively reduce the risk of leakage current from the first node G through the first reset transistor T2. Furthermore, for example, the first extension portion 210 of the active layer of the first reset transistor T2 extends beyond the active layer of the data writing transistor T1 in the second direction D2. Similarly, by making full use of the space where the first extension portion 210 of the active layer of the first reset transistor T2 is located in the semiconductor layer 300, the length of the first extension portion 210 of the active layer of the first reset transistor T2 is increased, so as to fully increase the length of the active layer of the first reset transistor T2, so as to make the most of the limited space to reduce the leakage current of the first reset transistor T2, and effectively reduce the risk of leakage current from the first node G through the first reset transistor T2.

[0140] For example, refer to Figure 4 and Figure 5F-5G The first capacitor electrode C1 of the storage capacitor Cst and the gate of the driving transistor T5 are integrally formed. The first connection block CE1 located in the third conductive layer 330 is electrically connected to the first capacitor electrode C1 of the storage capacitor Cst through the via VO3. A part of the via VO3 exposes a part of the semiconductor layer 300. Since the active layers of each transistor in the pixel circuit are integrally formed, a part of the active layer of the data writing transistor T1 is exposed through the via VO3. The first connection block CE1 is electrically connected to the active layer of the data writing transistor T1 through the via VO3. Thus, the first connection block CE1 acts as the first electrode of the data writing transistor T1, realizing that the first capacitor electrode C1 of the storage capacitor Cst, the gate of the driving transistor T5 and the first electrode of the data writing transistor T1 are electrically connected to the first node G.

[0141] Figure 5J It is along Figure 4 A cross-sectional diagram of line B1-B2 in the diagram. For example, refer to... Figure 4 , Figure 5F-5G and Figure 5JThe second connecting block CE2 located in the third conductive layer 330 is electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through the via VO4. A portion of the via VO4 exposes the active layer of the second reset transistor T3. Thus, the second connecting block CE2 is electrically connected to the active layer of the second reset transistor T3 (i.e., electrically connected to the semiconductor layer 300) through the via VO4. Therefore, the second connecting block CE2 acts as the first electrode of the second reset transistor T3 and the first electrode of the driving transistor T5, realizing the first electrode of the second reset transistor T3, the first electrode of the driving transistor T5, and the second capacitor electrode C2 of the storage capacitor Cst are electrically connected to the second node S. Furthermore, the second connecting block CE2 is electrically connected to the third connecting block CE0 located in the fourth conductive layer 340 through the via VO5. The third connecting block CE0 can be further electrically connected to the first electrode (not shown) of the light-emitting element EL on the side of the fourth conductive layer 340 away from the substrate 01, thereby realizing the electrical connection between the second node S and the first electrode of the light-emitting element EL.

[0142] For example, refer to Figure 4 For the first sub-pixel P1 and the second sub-pixel P2, apart from their respective data writing transistors T1 and T10, their other structures are substantially symmetrical about an axis of symmetry extending along the first direction D1. For example, the pattern of the active layer of the data writing transistor T1 of the first sub-pixel P1 is substantially symmetrical about an axis of symmetry extending along the first direction D1 with respect to the pattern of the active layer of the data writing transistor T10 of the second sub-pixel P2. Therefore, the active layer of the data writing transistor T10 of the second sub-pixel P2 also has a first extension portion 21a to increase the effective resistance of the data writing transistor T10 and reduce the leakage current of the data writing transistor T10. For example, refer to... Figure 5A The pattern of the active layer of the first reset transistor T2 of the first sub-pixel P1 is substantially symmetrical with respect to the axis of symmetry extending along the first direction D1. Therefore, the active layer of the first reset transistor T20 of the second sub-pixel P2 also has a first extension portion 210a to increase the effective resistance of the first reset transistor T20 and reduce its leakage current. In summary, for example, in any embodiment of this disclosure, the design of the first extension portion of the data writing transistor T1 and / or the first extension portion of the first reset transistor can be applied to each sub-pixel P.

[0143] Figure 6 This is a schematic diagram of the pixel circuit layout of another display substrate provided in at least one embodiment of the present disclosure; Figures 7A-7H They are shown respectively Figure 6 The diagram shows a schematic representation of the structure of each layer of the pixel circuit. Figure 6 and Figures 7A-7HIn the embodiments shown, the stacking relationship of the semiconductor layer 300, the first conductive layer 310, the second conductive layer 320, the third conductive layer 330, and the fourth conductive layer 340 can be referred to the previous description. Figure 6 and Figures 7A-7H The illustrated embodiments and Figure 4 The illustrated embodiments have the following differences.

[0144] refer to Figure 7A The active layer of the data writing transistor T1 also includes an auxiliary extension portion 3, which is connected to the first extension portion 21 of the lateral portion 2 and extends towards the channel region of the data writing transistor T1 in the first direction D1. The lateral portion 2 of the active layer of the data writing transistor T1 has a certain space on the side of the channel region of the data writing transistor T1 in the first direction D1. The auxiliary extension portion 3 is set in this space to further increase the length of the active layer of the data writing transistor T1, further increase the distance between the drain and source of the data writing transistor T1, thereby further increasing the equivalent resistance of the data writing transistor T1 and further reducing the leakage current of the data writing transistor T1. As a result, the risk of leakage current through the first node G through the data writing transistor T1 is further reduced, the potential change of the gate (point G) of the driving transistor T5 caused by this is reduced, and the flickering phenomenon caused by the display panel is improved or eliminated.

[0145] For example, the auxiliary extension portion 3 includes a first portion and a second portion. The first portion of the auxiliary extension portion 3 extends along a first direction D1, and the second portion of the auxiliary extension portion 3 is connected to the first portion of the auxiliary extension portion 3 and extends along a second direction D2 away from the longitudinal portion 1. This utilizes the unused space to further increase the length of the active layer of the data writing transistor T1, further increase the distance between the drain and source of the data writing transistor T1, thereby further increasing the equivalent resistance of the data writing transistor T1 and further reducing the leakage current of the data writing transistor T1.

[0146] Of course, the pattern of the auxiliary extension portion 3 is not limited to the case shown in the figure. As long as the auxiliary extension portion 3 connected to the first extension portion 21 is provided in the space of the transverse portion 2 of the active layer of the data writing transistor T1 on the side of the channel region of the data writing transistor T1 in the first direction D1.

[0147] Furthermore, for example, there is a gap between the gate GE1 of the data writing transistor T1 and the lateral portion 2 of the active layer of the data writing transistor T1, and the auxiliary extension portion 3 is located in the gap. By using the gap, the auxiliary extension portion 3 can be provided to utilize the idle space to further and effectively increase the resistance of the active layer of the data writing transistor T1, thereby reducing the risk of leakage current from the first node G through the data writing transistor T1.

[0148] The auxiliary extension portion 3 is also located in the semiconductor layer 300. For example, the auxiliary extension portion 3, the first extension portion 21, and the vertical portion 1 form an integral structure.

[0149] For example, there is a gap between the gate GE1 of the data writing transistor T1 and the lateral portion 2 of the active layer of the data writing transistor T1, and an auxiliary extension portion 3 is located in the gap. The auxiliary extension portion is provided using the gap to utilize the idle space to further increase the resistance of the active layer of the data writing transistor T1.

[0150] For example, refer to Figure 7F and Figure 7G The pixel circuit includes a first connection electrode L1, for example, the first connection electrode L1 is located in the third conductive layer 330; see reference. Figure 6 , Figure 7F and Figure 7G The auxiliary extension portion 3 is electrically connected to the first connection electrode L1 through a third via V3, and the first connection electrode L1 is electrically connected to the data signal line Data through a second via V2. Thus, both the auxiliary extension portion 3 and the lateral portion 2 of the active layer of the data writing transistor T1 are electrically connected to the data signal line Data, thereby achieving an electrical connection between the data signal line Data and the active layer of the data writing transistor T1. In this case, the third via V3 serves as the aforementioned second connection via. On one hand, achieving the electrical connection between the data signal line Data and the active layer of the data writing transistor T1 through the two vias, the third via V3 and the second via V2, arranged in a direction perpendicular to the main surface of the substrate, ensures the reliability of the electrical connection. On the other hand, using the auxiliary extension portion 3 to electrically connect to the data signal line Data via the first via V1 and the first connection electrode L1 helps to further increase the effective length of the active layer of the data writing transistor T1.

[0151] For example, the third via V3 is located at the end of the auxiliary extension 3 away from the first extension 21 in the first direction D1. In this way, the effective length of the active layer of the data writing transistor T1 can be maximized by utilizing the length of the auxiliary extension 3. The length of the entire auxiliary extension 3 in its extension direction and the length of the first extension 21 in the second direction D2 can be used to increase the effective length of the active layer of the data writing transistor T1.

[0152] For example, refer to Figure 7F and Figure 7G The pattern of the first connecting electrode L1 is basically the same as and overlaps with the pattern of the lateral portion 2 of the active layer of the data writing transistor T1. That is, the orthographic projection of the first connecting electrode L1 on the main surface of the substrate is basically overlapped with the orthographic projection of the lateral portion 2 of the active layer of the data writing transistor T1 on the main surface of the substrate. This avoids the first connecting electrode L1 occupying extra space, reduces the volume of the pixel circuit, and helps to improve the PPI of the display substrate 10.

[0153] For example, in any embodiment of this disclosure, the design of the first extension and auxiliary extension of the data writing transistor T1 and / or the first extension of the first reset transistor can be applied to each sub-pixel P.

[0154] Figure 6 and Figures 7A-7H Other undescribed features of the illustrated embodiments and Figure 4 The same principles apply to the embodiments shown, and will not be repeated here.

[0155] Figure 8 An equivalent circuit diagram of a pixel circuit for a sub-pixel is provided in one embodiment of this disclosure; Figures 9A-9C for Figure 8 The timing diagram shown illustrates the operation of the pixel circuit.

[0156] Figure 8 A schematic diagram of a 3T1C pixel circuit for the display substrate is shown. Depending on the requirements, the pixel circuit may further include compensation circuits, reset circuits, etc., and the embodiments disclosed herein are not limited thereto.

[0157] refer to Figure 8 The pixel circuit includes a driving sub-circuit 50, a data writing sub-circuit 40, a storage sub-circuit 70, and a light-emitting element EL. The driving terminal of the driving sub-circuit 50 is electrically connected to the first terminal of the data writing sub-circuit 40. The data writing sub-circuit 40 is configured to receive a data signal Vd and, in response to a first control signal G1, write the data signal Vd to the driving terminal of the driving sub-circuit 50 and the storage sub-circuit 70. The driving sub-circuit 50 is configured to control the current used to drive the light-emitting element EL under the control of the voltage at its driving terminal.

[0158] refer to Figure 8 For example, the pixel circuit also includes a sensing sub-circuit 80, which is configured to detect the electrical characteristics of the associated sub-pixel P in response to a second control signal G4.

[0159] The data writing sub-circuit 40 includes a data writing transistor T1, the driving sub-circuit 50 includes a driving transistor T5, the storage sub-circuit 70 includes a storage capacitor Cst, and the sensing sub-circuit 80 includes a sensing transistor T6. The first terminal of the data writing transistor T1 is electrically connected to the first capacitor electrode of the storage capacitor Cst and the gate of the driving transistor T5. The second terminal of the data writing transistor T1 is electrically connected to a data signal line to receive a data signal Vd. The second terminal of the data writing transistor T1 is configured to receive the data signal Vd and is configured to write the data signal Vd to the gate of the driving transistor T5 and the storage capacitor Cst in response to a first control signal G1. The first terminal of the driving transistor T5 is electrically connected to the first capacitor electrode of the storage capacitor Cst and to the first electrode of the light-emitting element EL. The second terminal of the driving transistor T5 is electrically connected to a first power supply voltage terminal to receive a first power supply voltage VDD. The driving transistor T5 is configured to control the current used to drive the light-emitting element EL under the control of the voltage at its gate. The first electrode of the sensing transistor T6 is electrically connected to the first electrode of the driving transistor T5 and the second electrode of the storage capacitor Cst. For example, the second electrode of the sensing transistor T6 is connected to the detection line Sense to connect to an external detection circuit. The sensing transistor T6 is configured to detect the electrical characteristics of its sub-pixel P in response to the second control signal G4 to achieve external compensation. These electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the driving transistor T5, or the threshold voltage and drive current of the light-emitting element. The external detection circuit 11 is, for example, a conventional circuit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), etc., which will not be described in detail in the embodiments of this disclosure.

[0160] The following is combined with Figures 9A-9C The signal timing diagram shown is for Figure 9A The working principle of the pixel circuit shown is explained, in which Figure 9A The following is a signal timing diagram of the pixel circuit during the display process. Figure 9B and Figure 9C The signal timing diagram of the pixel circuit during the detection process is shown.

[0161] For example, such as Figure 9A As shown, the display process of each frame of the image includes a data writing and reset phase 1 and a light emission phase 2. Figure 9AThe timing waveforms of each signal in each stage are shown. One operation of the 3T1C pixel circuit includes: In the data writing and reset stage 1, the first control signal G1 and the second control signal G4 are both on signals, the data writing transistor T1 and the sensing transistor T6 are turned on, and the data signal Vd is transmitted to the gate of the driving transistor T5 through the data writing transistor T1. For example, through the analog-to-digital converter, a reset signal is written to the first electrode of the light-emitting element (e.g., the anode of the OLED) through the detection line Sense and the sensing transistor T6. The driving transistor T5 is turned on and generates a driving current to charge the first electrode of the light-emitting element EL to the working voltage; In the light-emitting stage 2, the first control signal G1 and the second control signal G4 are both off signals. Due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged. The driving transistor T5 operates in saturation and the current remains unchanged, driving the light-emitting element to emit light.

[0162] For example, Figure 9A The diagram shows the signal timing of the pixel circuit during threshold voltage detection. One operating process of the 3T1C pixel circuit includes: both the first control signal G1 and the second control signal G4 are enabled; the data writing transistor T1 and the sensing transistor T6 are turned on; the data signal Vd is transmitted to the gate of the driving transistor T5 via the data writing transistor T1; the first switch K1 is turned off; the analog-to-digital converter writes a reset signal to the first electrode (node ​​S) of the light-emitting element through the detection line Sense and the sensing transistor T6; the driving transistor T5 is turned on and charges node S until it is turned off; the digital-to-analog converter samples the voltage on the detection line Sense to obtain the threshold voltage of the driving transistor T5. This process can, for example, be performed when the display device is powered off.

[0163] For example, Figure 9AThe diagram shows the signal timing of the pixel circuit during threshold voltage detection. One operation of the 3T1C pixel circuit includes: In the first stage, both the first control signal G1 and the second control signal G4 are enabled, the data writing transistor T1 and the sensing transistor T6 are turned on, and the data signal Vd is transmitted to the gate of the driving transistor T5 via the data writing transistor T1; for example, an external analog-to-digital converter electrically connected to the detection line Sense writes a reset signal to the first electrode (node ​​S) of the light-emitting element through the detection line Sense and the sensing transistor T6; In the second stage, the first control signal G1 is disabled, the second control signal G4 is enabled, the data writing transistor T1 is turned off, the sensing transistor T6 is turned on, and the detection line Sense is floated; Due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains constant, the driving transistor T5 operates in saturation with a constant current, and drives the light-emitting element to emit light. Then, the digital-to-analog converter samples the voltage on the detection line Sense, and by combining this with the magnitude of the emitting current, the carrier mobility in the driving transistor T5 can be calculated. For example, this process can be performed during the blanking phase between display phases.

[0164] Figure 10 for Figure 8 The diagram shows the layout of the pixel circuit. Figures 11A-11H They are shown respectively Figure 10 The diagram shows a schematic representation of the structure of each layer of the pixel circuit. Figure 10 and Figures 11A-11H In the embodiments shown, the stacking relationship of the semiconductor layer 300, the first conductive layer 310, the second conductive layer 320, the third conductive layer 330, and the fourth conductive layer 340 can be referred to the previous description. Figure 10 and Figures 11A-11H The illustrated embodiments and Figure 6 The illustrated embodiments have the following differences.

[0165] Figure 10 A schematic diagram of the structural layout of a sub-pixel P is shown. For example, refer to... Figure 11A The active layers of each transistor in sub-pixel P are located in semiconductor layer 300, and the active layers of each transistor in sub-pixel P include their respective channel regions A1, A5, and A6; Reference Figure 11B The gates GE1, GE5, and GE6 of each transistor in sub-pixel P, and the first capacitor electrode C1 of the storage capacitor Cst are located in the first conductive layer 310; Reference Figure 11D The second capacitor electrode C2 of the storage capacitor Cst of sub-pixel P is located in the second conductive layer 320; Reference Figure 11FThe detection line Sense, the first gate line GL1 electrically connected to the gate GE1 of the data writing transistor T1 to provide the first control signal G1, the second gate line GL4 electrically connected to the gate GE6 of the sensing transistor T6 to provide the second control signal G4, the lateral power line VDD1, the first connection electrode, and the connection blocks CE4 and CE5 are located on the third conductive layer 330. The structure and function of the connection blocks CE4 and CE5 are similar to those of the third conductive layer 330. Figure 4 The first connecting block CE1 and the second connecting block CE2 in the illustrated embodiment; Reference Figure 5H The vertical power line VDD2, data signal line Data, and connector CE6 are located on the fourth conductive layer 340. The structure and function of connector CE6 are similar to... Figure 4 The third connecting block CE0 in the illustrated embodiment is used for electrical connection with the first electrode of the light-emitting element.

[0166] For example, in this 3T1C circuit, the control transistor includes a data write transistor T1. The structure of the data write transistor T1 will be described below using the example of the control transistor including the data write transistor T1.

[0167] refer to Figure 10 and Figure 11A The channel regions A5 of the driving transistor T5 and A1 of the data writing transistor T1 are arranged in a first direction D1, and a second direction D2 intersects the first direction D1, for example, the second direction D2 is perpendicular to the first direction D1. (Reference) Figure 11A The active layer of the data writing transistor T1 includes a vertical portion 1 extending along a first direction D1 and a lateral portion 2 extending along a second direction D2. The vertical portion 1 includes the channel region A1 of the data writing transistor T1, that is, the vertical portion 1 includes the channel region of the control transistor. The lateral portion 2 is connected to the vertical portion 1 and includes a first extension portion 21 and a second extension portion 22. The first extension portion 21 protrudes from the vertical portion 1 toward a first side in the second direction D2, and the second extension portion 22 protrudes from the vertical portion 1 toward a second side opposite to the first side in the second direction D2. In this way, the length of the active layer of the data writing transistor T1 is increased, the distance between the drain and source of the data writing transistor T1 is increased, thereby increasing the equivalent resistance of the data writing transistor T1 and reducing the leakage current of the data writing transistor T1. As a result, the risk of leakage current through the first node G through the data writing transistor T1 in the off state can be reduced, the potential change of the gate (point G) of the driving transistor T5 caused by this can be reduced, and the screen flickering phenomenon caused by the display panel can be improved or eliminated.

[0168] For example, refer to Figure 11AThe channel region A5 of the driving transistor T5 is located on the first side of the vertical portion 1 in the second direction D2. The length of the first extension portion 21 in the second direction D2 is not less than the length of the second extension portion 22 in the second direction D2. Therefore, the space on the first side of the vertical portion 1 in the second direction D2 can be fully utilized to extend the length of the active layer of the data writing transistor T1, thereby minimizing the leakage current of the data writing transistor T1 within the limited space and reducing the risk of leakage current from the first node G through the data writing transistor T1. For example, the length of the first extension portion 21 in the second direction D2 is not greater than the length of the second extension portion 22 in the second direction D2, or the lengths of the first extension portion 21 and the second extension portion 22 in the second direction D2 are substantially equal.

[0169] For example, refer to Figure 11A The vertical portion 1 has a distal end in the first direction D1, away from the channel region A5 of the driving transistor T5. The first extension portion 21 and the second extension portion 22 are located at the distal end of the vertical portion 1 and connected to the distal end. In this way, the channel region A1 of the data writing transistor T1 can be formed using the vertical portion 1 extending along the first direction D1, and the lateral portion 2 can be set using the space created on both sides in the second direction D2 at the distal end. The space is used to realize the structure of the data writing transistor T1 in a reasonable way, and the length of the active layer of the data writing transistor T1 is increased to increase the equivalent resistance of the data writing transistor T1.

[0170] For example, refer to Figure 11A The first extension 21 of the active layer of the data writing transistor T1 at least partially overlaps with the channel region A5 of the driving transistor T5 in the first direction D1. Thus, by utilizing the space in the second direction D2 to appropriately increase the length of the first extension 21, which extends at least to the location of the channel region A5 of the driving transistor T5 in the second direction D2, the leakage current of the data writing transistor T1 can reach a suitable value, effectively reducing the leakage current of the data writing transistor T1, without occupying the layout space of other structures in the pixel circuit, ensuring the normal functioning of the pixel circuit and guaranteeing display quality.

[0171] refer to Figure 11AThe active layer of the data writing transistor T1 also includes an auxiliary extension portion 3, which is connected to the first extension portion 21 of the lateral portion 2 and extends towards the channel region of the data writing transistor T1 in the first direction D1. The lateral portion 2 of the active layer of the data writing transistor T1 has a certain space on the side of the channel region of the data writing transistor T1 in the first direction D1. The auxiliary extension portion 3 is set in this space to further increase the length of the active layer of the data writing transistor T1, further increase the distance between the drain and source of the data writing transistor T1, thereby further increasing the equivalent resistance of the data writing transistor T1 and further reducing the leakage current of the data writing transistor T1. As a result, the risk of leakage current through the first node G through the data writing transistor T1 is further reduced, the potential change of the gate (point G) of the driving transistor T5 caused by this is reduced, and the flickering phenomenon caused by the display panel is improved or eliminated.

[0172] Of course, the pattern of the auxiliary extension portion 3 is not limited to the case shown in the figure. As long as the auxiliary extension portion 3 connected to the first extension portion 21 is provided in the space of the transverse portion 2 of the active layer of the data writing transistor T1 on the side of the channel region of the data writing transistor T1 in the first direction D1.

[0173] Furthermore, for example, there is a gap between the gate GE1 of the data writing transistor T1 and the lateral portion 2 of the active layer of the data writing transistor T1, and the auxiliary extension portion 3 is located in the gap. By using the gap, the auxiliary extension portion 3 can be provided to utilize the idle space to further and effectively increase the resistance of the active layer of the data writing transistor T1, thereby reducing the risk of leakage current from the first node G through the data writing transistor T1.

[0174] The auxiliary extension portion 3 is also located in the semiconductor layer 300. For example, the auxiliary extension portion 3, the first extension portion 21, and the vertical portion 1 form an integral structure.

[0175] For example, there is a gap between the gate GE1 of the data writing transistor T1 and the lateral portion 2 of the active layer of the data writing transistor T1, and an auxiliary extension portion 3 is located in the gap. The auxiliary extension portion is provided using the gap to utilize the idle space to further increase the resistance of the active layer of the data writing transistor T1.

[0176] refer to Figure 11A and Figure 11GThe connection point between the first electrode of data writing transistor T1 and the active layer of data writing transistor T1 is designated as the first sub-position, and the connection point between the second electrode of data writing transistor T1 and the active layer of data writing transistor T1 is designated as the second position. That is, when data writing transistor T1 acts as a control transistor, the first sub-position is the aforementioned first position, and the second sub-position is the aforementioned second position. The connection point between the first electrode of driving transistor T5 and the active layer of driving transistor T5 is designated as the third position. The distance between the first sub-position and the second sub-position is greater than the distance between the first sub-position and the third position, thereby increasing the length of the active layer of data writing transistor T1 and increasing the distance between the source and drain of data writing transistor T1. This increases the equivalent resistance of data writing transistor T1 and reduces its leakage current. Consequently, the risk of leakage through the first node G in the off state through data writing transistor T1 can be reduced, and the potential change at the gate (point G) of driving transistor T5 caused by this can be reduced, thus improving or eliminating the screen flickering phenomenon caused by the display panel.

[0177] For example, the straight-line distance between the first sub-position and the second sub-position is greater than the straight-line distance between the first sub-position and the third position; or, the distance between the first sub-position and the second sub-position in the first direction D1 is greater than the distance between the first sub-position and the third position in the first direction D1; or, the sum of the distance between the first sub-position and the second sub-position in the first direction D1 and the distance in the second direction D2 is greater than the sum of the distance between the first sub-position and the third position in the first direction D1 and the distance in the second direction D2.

[0178] For example, refer to Figure 10 and Figure 11F-11G The first capacitor electrode C1 of the storage capacitor Cst and the gate of the driving transistor T5 are integrally formed. The sub-pixel P includes a first connection block CE4, for example, the first connection block CE4 is located in the third conductive layer 330; the first connection block CE4 is electrically connected to the gate of the driving transistor T5 through the first connection via VO3, that is, electrically connected to the first capacitor electrode C1 of the storage capacitor Cst; a portion of the first connection via VO3 exposes a portion of the semiconductor layer 300. Since the active layers of each transistor in the pixel circuit are integrally formed, a portion of the first connection via VO3 exposes a portion of the active layer of the data writing transistor T1. The first connection block CE4 is electrically connected to the active layer of the data writing transistor T1 through the first connection via VO3. (Refer to...) Figure 5ASince the active layer of the data writing transistor T1 and the active layer of the first reset transistor T2 form a continuous integral structure, the first connection block CE4 is also electrically connected to the active layer of the first reset transistor T2 through the first connection via V03. Therefore, the first connection block CE4 acts as the first electrode of the data writing transistor T1, realizing the electrical connection of the first capacitor electrode C1 of the storage capacitor Cst, the gate GE5 of the driving transistor T5, the first electrode of the data writing transistor T1, and the first electrode of the first reset transistor T2 to the first node G. The position of the first connection via V03 is the aforementioned first sub-position.

[0179] For example, the second terminal of the data writing transistor T1 is electrically connected to the active layer of the data writing transistor T1 through a second connection via, and the location of the second connection via is the second sub-position.

[0180] For example, refer to Figure 11F and Figure 11G The pixel circuit includes a first connection electrode L1, for example, the first connection electrode L1 is located in the third conductive layer 330; see reference. Figure 10 , Figure 11F and Figure 11G The auxiliary extension portion 3 is electrically connected to the first connection electrode L1 through a third via V3, and the first connection electrode L1 is electrically connected to the data signal line Data through a second via V2. Thus, both the auxiliary extension portion 3 and the lateral portion 2 of the active layer of the data writing transistor T1 are electrically connected to the data signal line Data, thereby achieving an electrical connection between the data signal line Data and the active layer of the data writing transistor T1. In this case, the third via V3 serves as the second connection via when the control transistor is the data writing transistor T1, and therefore, the position of the third via V3 is the aforementioned second sub-position. On one hand, achieving the electrical connection between the data signal line Data and the active layer of the data writing transistor T1 through the two vias, the third via V3 and the second via V2, arranged in a direction perpendicular to the main surface of the substrate, ensures the reliability of the electrical connection. On the other hand, using the auxiliary extension portion 3 to electrically connect to the data signal line Data via the third via V3 and the first connection electrode L1 helps to further increase the effective length of the active layer of the data writing transistor T1.

[0181] For example, the third via V3 is located at the end of the auxiliary extension 3 away from the lateral portion 2 in the first direction D1. In this way, the effective length of the active layer of the data writing transistor T1 can be maximized by utilizing the length of the auxiliary extension 3. The length of the entire auxiliary extension 3 in its extension direction and the length of the first extension 21 in the second direction D2 can be used to increase the effective length of the active layer of the data writing transistor T1.

[0182] For example, refer to Figure 11Fand Figure 11G The pattern of the first connecting electrode L1 is basically the same as and overlaps with the pattern of the lateral portion 2 of the active layer of the data writing transistor T1. That is, the orthographic projection of the first connecting electrode L1 on the main surface of the substrate is basically overlapped with the orthographic projection of the lateral portion 2 of the active layer of the data writing transistor T1 on the main surface of the substrate. This avoids the first connecting electrode L1 occupying extra space, reduces the volume of the pixel circuit, and helps to improve the PPI of the display substrate 10.

[0183] Of course, in the structure of the 3T1C circuit provided in other embodiments, it can also be removed. Figure 11A In the auxiliary extension part 3, in this case, a method similar to... Figure 4 In the embodiment shown, the first via V1 enables the first connecting electrode L1 to be electrically connected to the first extension portion 21.

[0184] The connection point between the first electrode of sensing transistor T6 and the active layer of sensing transistor T6 is the fifth sub-position, and the connection point between the second electrode of sensing transistor T6 and the active layer of sensing transistor T6 is the sixth sub-position. The distance between the first sub-position and the second sub-position is greater than the distance between the fifth sub-position and the sixth sub-position, so as to further increase the length of the active layer of data writing transistor T1, increase the distance between the source and drain of data writing transistor T1, thereby increasing the equivalent resistance of data writing transistor T1 and reducing the leakage current of data writing transistor T1.

[0185] Figure 8 , Figure 10 and Figures 11A-11H Other undescribed features and corresponding technical effects of the illustrated embodiments, such as the relationship between the distance between the first and second positions and the pixel width, are all related to... Figure 4 The same principles apply to the embodiments shown, and will not be repeated here.

[0186] Of course, in other embodiments of the display substrate provided in this disclosure, the pixel circuit can also be a 7T1C or 8T1C circuit. As long as it includes a transistor electrically connected to the first node G, the above-mentioned first extension portion and / or auxiliary extension portion technical solution can be applied to the transistor to reduce the leakage current of the transistor electrically connected to the first node G, so as to prevent display defects caused by unnecessary changes in the voltage of the first node G during the light-emitting stage.

[0187] like Figure 12 As shown, at least one embodiment of this disclosure also provides a display device 100, such as... Figure 12As shown, the display device 100 includes any type of display substrate 10 provided in the embodiments of this disclosure. The display device 100 can be, for example, an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other devices with display functions, or other types of devices. The embodiments of this disclosure do not limit this.

[0188] The structure, function, and technical effects of the display device provided in this disclosure embodiment can be referred to the corresponding description in the display substrate 10 provided in the above disclosure embodiment, and will not be repeated here.

[0189] For example, the display device 100 provided in at least one embodiment of this disclosure can be any product or component with display function, such as a display panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. The embodiments of this disclosure do not limit this.

[0190] The following points need to be explained:

[0191] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0192] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0193] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention, which is determined by the appended claims.

Claims

1. A display substrate comprising sub-pixels, wherein the sub-pixels include pixel circuitry, wherein, The pixel circuit includes: a driving sub-circuit, a light-emitting element, and a control sub-circuit. The driving sub-circuit includes a driving transistor, the gate of which is configured to receive a driving control signal. The driving sub-circuit is configured to control the magnitude of the driving current flowing through the light-emitting element in response to the driving control signal. The control sub-circuit includes a control transistor, the first terminal of which is electrically connected to the gate of the driving transistor; The connection position between the first electrode of the control transistor and the active layer of the control transistor is the first position, the connection position between the second electrode of the control transistor and the active layer of the control transistor is the second position, and the connection position between the first electrode of the driving transistor and the active layer of the driving transistor is the third position. The distance between the first position and the second position is greater than the distance between the first position and the third position.

2. The display substrate according to claim 1, wherein, The channel regions of the driving transistor and the control transistor are arranged in a first direction, and the second direction intersects the first direction; The straight-line distance between the first position and the second position is greater than the straight-line distance between the first position and the third position, or... The distance between the first position and the second position in the first direction is greater than the distance between the first position and the third position in the first direction, or... The sum of the distance between the first position and the second position in the first direction and the distance in the second direction is greater than the sum of the distance between the first position and the third position in the first direction and the distance in the second direction.

3. The display substrate according to claim 1, wherein, The sub-pixel includes a first connection block, which is electrically connected to the gate of the driving transistor, the active layer of the driving transistor, and the active layer of the control transistor through a first connection via. The position of the first connection via is the first position. The second terminal of the control transistor is electrically connected to the active layer of the control transistor through a second connection via, and the location of the second connection via is the second location; The sub-pixel includes a second connection block, which is electrically connected to the active layer of the driving transistor through a third connection via, wherein the location of the third connection via is the third position.

4. The display substrate according to claim 3, wherein, The channel region of the driving transistor and the channel region of the control transistor are arranged in a first direction, and the second direction intersects the first direction. The active layer of the control transistor includes a longitudinal portion extending along the first direction and a lateral portion extending along the second direction. The longitudinal portion includes the channel region of the control transistor. The transverse portion is connected to the longitudinal portion. The transverse portion includes a first extension portion and a second extension portion. The first extension portion protrudes from the longitudinal portion toward a first side in a second direction, and the second extension portion protrudes from the longitudinal portion toward a second side opposite to the first side in the second direction.

5. The display substrate according to claim 4, wherein, The channel region of the driving transistor is located on the first side of the longitudinal portion in the second direction, and the length of the first extension portion in the second direction is not less than the length of the second extension portion in the second direction.

6. The display substrate according to claim 5, wherein, The longitudinal portion has a distal end in the first direction that is away from the channel region of the driving transistor, and the first extension portion and the second extension portion are located at the distal end of the longitudinal portion and connected to the distal end.

7. The display substrate according to claim 4, wherein, The pixel circuit includes a data writing sub-circuit, the data writing sub-circuit includes a data writing transistor, and the control transistor includes the data writing transistor; The gate of the data writing transistor is electrically connected to the data writing control signal terminal to receive the data writing control signal. The first terminal of the data writing transistor is electrically connected to the gate of the driving transistor. The second terminal of the data writing transistor is configured to receive a data signal. The data writing sub-circuit is configured to write the data signal to the gate terminal of the driving transistor in response to the data writing control signal.

8. The display substrate according to claim 7, wherein, The first extension of the active layer of the data writing transistor at least partially overlaps with the channel region of the driving transistor in the first direction.

9. The display substrate according to claim 7, wherein, The display substrate includes a data signal line that provides the data signal, and the lateral portion of the active layer of the data writing transistor is electrically connected to the data signal line; The pixel circuit includes a first connection electrode disposed on a different layer from both the active layer and the data signal line. A first extension of the lateral portion is electrically connected to the first connection electrode through a first via. The first connection electrode is electrically connected to the data signal line through a second via. The first via serves as the second position when the control transistor is the data write transistor.

10. The display substrate according to claim 9, wherein, The first through hole is located at the end of the first extension portion away from the longitudinal portion in the second direction.

11. The display substrate according to claim 7, wherein, The active layer of the data writing transistor further includes an auxiliary extension portion, which is connected to a first extension portion of the lateral portion and extends toward the channel region side of the data writing transistor in the first direction.

12. The display substrate according to claim 11, wherein, There is a gap region between the gate of the data writing transistor and the lateral portion of the active layer of the data writing transistor, and the auxiliary extension portion is located in the gap region.

13. The display substrate according to claim 11, wherein, The display substrate includes a data signal line that provides the data signal, and the lateral portion of the active layer of the data writing transistor is electrically connected to the data signal line; The pixel circuit includes a first connection electrode disposed on a different layer from both the active layer and the data signal line. The auxiliary extension portion is electrically connected to the first connection electrode through a third via. The first connection electrode is electrically connected to the data signal line through a second via. The third via serves as the second connection via when the control transistor is the data write transistor.

14. The display substrate according to claim 13, wherein, The third through hole is located at the end of the auxiliary extension portion that is away from the first extension portion in the first direction.

15. The display substrate according to claim 11, wherein, The display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels includes adjacent first sub-pixels and second sub-pixels arranged in the second direction; The gate of the data write transistor of the first sub-pixel and the gate of the data write transistor of the second sub-pixel are independent of each other so as to receive different data write control signals respectively; The display substrate includes a first auxiliary gate line disposed on a different layer from the gate of the data writing transistor of the first sub-pixel, and the first auxiliary gate line is electrically connected to the gate of the data writing transistor of the first sub-pixel through a fourth via. The display substrate includes a second auxiliary gate line disposed on a different layer from the gate of the data writing transistor of the second sub-pixel. The second auxiliary gate line is electrically connected to the gate of the data writing transistor of the second sub-pixel through a fifth via.

16. The display substrate according to claim 15, wherein, The first extension of the active layer of the data writing transistor at least partially overlaps with the fourth via in the first direction.

17. The display substrate according to claim 15, wherein, The gates of the common-gate transistor of the first sub-pixel and the common-gate transistor of the second sub-pixel are electrically connected to each other to share the same gate scan signal. The common-gate transistor includes at least one of the transistors in the pixel circuit other than the data write transistor and the drive transistor. The display substrate includes a second connection electrode disposed on a different layer from the gate of the common gate transistor. The second connection electrode is electrically connected to the gate of the common gate transistor of the first sub-pixel through a sixth via and to the gate of the common gate transistor of the second sub-pixel through a seventh via. In a display substrate including a data signal line providing the data signal, a lateral portion of the active layer of the data writing transistor is electrically connected to the data signal line. The pixel circuit includes a first connection electrode disposed on a different layer from both the active layer and the data signal line. A first extension of the lateral portion is electrically connected to the first connection electrode via a first via. In a case where the first connection electrode is electrically connected to the data signal line via a second via... The first auxiliary gate line, the second auxiliary gate line, and the second connecting electrode are all disposed in the same layer as the first connecting electrode.

18. The display substrate according to any one of claims 7-17, wherein, The pixel circuit includes a first reset circuit, the first reset circuit includes a first reset transistor, and the control transistor includes the first reset transistor. The gate of the first reset transistor is electrically connected to a first reset signal terminal to receive a first reset control signal. The first terminal of the first reset transistor is electrically connected to the gate of the driving transistor. The second terminal of the first reset transistor is electrically connected to a first signal terminal. The first reset sub-circuit is configured to write a first reset signal from the first signal terminal to the gate terminal of the driving transistor in response to the first reset control signal.

19. The display substrate according to claim 18, wherein, The connection position between the first electrode of the data writing transistor and the active layer of the data writing transistor is the first sub-position, and the connection position between the second electrode of the data writing transistor and the active layer of the data writing transistor is the second sub-position; the connection position between the first electrode of the first reset transistor and the active layer of the first reset transistor is the third sub-position, and the connection position between the second electrode of the first reset transistor and the active layer of the first reset transistor is the fourth sub-position. The distance between the first sub-position and the second sub-position is greater than the distance between the third sub-position and the fourth sub-position.

20. The display substrate according to claim 19, wherein, The active layer of the data write transistor extends from the first sub-position to the second sub-position, and the active layer of the first reset transistor extends from the third sub-position to the fourth sub-position. The total length of the active layer of the data write transistor from the first sub-position to the second sub-position is greater than the total length of the active layer of the first reset transistor from the third sub-position to the fourth sub-position.

21. The display substrate according to claim 18, wherein, The first extension of the active layer of the first reset transistor at least partially overlaps with the channel region of the driving transistor in the first direction.

22. The display substrate according to claim 18, wherein, In the case where the control transistor includes a data write transistor, in the first direction, the channel region of the drive transistor is located between the channel region of the data write transistor and the channel region of the first reset transistor. In the first direction, the lateral portion of the active layer of the data write transistor is located on the side of the channel region of the data write transistor away from the channel region of the driving transistor, and the lateral portion of the active layer of the first reset transistor is located on the side of the channel region of the first reset transistor away from the channel region of the driving transistor.

23. The display substrate according to claim 22, wherein, The length of the first extension portion of the active layer of the first reset transistor in the second direction is greater than or equal to the length of the first extension portion of the active layer of the data write transistor in the second direction.

24. The display substrate according to claim 22, wherein, The first extension portion of the active layer of the first reset transistor extends beyond the active layer of the data write transistor in the second direction.

25. The display substrate according to claim 18, wherein, The display substrate includes a compensation signal line that provides a compensation signal. A first extension of the lateral portion of the active layer of the first reset transistor is electrically connected to the compensation signal line through an eighth via. The position of the eighth via is the second position when the control transistor is the first reset transistor.

26. The display substrate according to any one of claims 7-17, wherein, The pixel circuit further includes a storage sub-circuit, which includes a storage capacitor. The first electrode of the data writing transistor is electrically connected to the first capacitor electrode of the storage capacitor and the gate of the driving transistor, and the second electrode of the data writing transistor is electrically connected to the data signal line to receive the data signal; The first electrode of the driving transistor is electrically connected to the second capacitor electrode of the storage capacitor and configured to be electrically connected to the first electrode of the light-emitting element. The second electrode of the driving transistor is electrically connected to the first power supply voltage terminal to receive the first power supply voltage.

27. The display substrate according to claim 26, wherein, The pixel circuit further includes a sensing sub-circuit, which includes a sensing transistor; The first electrode of the sensing transistor is electrically connected to the first electrode of the driving transistor and the second capacitor electrode of the storage capacitor. The sensing transistor is configured to detect the electrical characteristics of the sub-pixel to which it belongs in response to a detection control signal.

28. The display substrate according to claim 27, wherein, The connection position between the first electrode of the data writing transistor and the active layer of the data writing transistor is the first sub-position, and the connection position between the second electrode of the data writing transistor and the active layer of the data writing transistor is the second sub-position; the connection position between the first electrode of the sensing transistor and the active layer of the sensing transistor is the fifth sub-position, and the connection position between the second electrode of the sensing transistor and the active layer of the sensing transistor is the sixth sub-position. The distance between the first sub-position and the second sub-position is greater than the distance between the fifth sub-position and the sixth sub-position.

29. The display substrate according to claim 26, wherein, The control sub-circuit includes a first reset sub-circuit, the control transistor includes a first reset transistor, the gate of the first reset transistor is electrically connected to a first reset signal terminal to receive a first reset control signal, the first terminal of the first reset transistor is electrically connected to the gate of the driving transistor, and the second terminal of the first reset transistor is electrically connected to a first signal terminal. The first reset sub-circuit is configured to write a first reset signal or compensation signal from the first signal terminal to the gate terminal of the driving transistor in response to the first reset control signal. The gate of the driving transistor, the first terminal of the data writing transistor, and the first terminal of the first reset transistor are electrically connected to the first node; The pixel circuit further includes a light emission control sub-circuit, which includes a light emission control transistor. The gate of the light emission control transistor is electrically connected to the light emission control signal terminal, the first terminal of the light emission control transistor is electrically connected to the first power supply voltage terminal, and the second terminal of the light emission control transistor is electrically connected to the second terminal of the driving transistor. The pixel circuit further includes a second reset sub-circuit, which includes a second reset transistor. The gate of the second reset transistor is electrically connected to a second reset signal terminal to receive a second reset control signal. The first electrode of the second reset transistor, the first electrode of the driving transistor, the second capacitor electrode of the storage capacitor, and the first electrode of the light-emitting element are electrically connected to a second node. The second electrode of the second reset transistor is electrically connected to a second signal terminal to receive a second reset signal. Under the control of the second reset signal, the second reset sub-circuit is configured to write the second reset signal to the second node in response to the second reset control signal.

30. The display substrate according to claim 29, wherein, The connection position between the first electrode of the data writing transistor and the active layer of the data writing transistor is a first sub-position; the connection position between the second electrode of the data writing transistor and the active layer of the data writing transistor is a second sub-position; the connection position between the first electrode of the first reset transistor and the active layer of the first reset transistor is a third sub-position; the connection position between the second electrode of the first reset transistor and the active layer of the first reset transistor is a fourth sub-position; the connection position between the first electrode of the second reset transistor and the active layer of the second reset transistor is a seventh sub-position; the connection position between the second electrode of the second reset transistor and the active layer of the second reset transistor is an eighth sub-position; the connection position between the first electrode of the light-emitting control transistor and the active layer of the light-emitting control transistor is a ninth sub-position; the connection position between the second electrode of the light-emitting control transistor and the active layer of the light-emitting control transistor is a tenth sub-position. The distance between the first sub-position and the second sub-position is greater than the distance between the seventh sub-position and the eighth sub-position, and / or, the distance between the first sub-position and the second sub-position is greater than the distance between the ninth sub-position and the tenth sub-position; or, The distance between the third sub-position and the fourth sub-position is greater than the distance between the seventh sub-position and the eighth sub-position, and / or the distance between the third sub-position and the fourth sub-position is greater than the distance between the ninth sub-position and the tenth sub-position.

31. A display device comprising the display substrate according to any one of claims 1-30.

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