A die and clock synchronization method

Abstract

The embodiment of the application provides a kind of die and clock synchronization method, it is related to chip technical field.Specific scheme is: the first die includes at least one signal path, each signal path is used to and a second die is coupled to form loop, each signal path includes signal sending path and signal receiving path, the first control circuit in signal sending path is used to when sending data signal to the second die, first clock signal adjusting circuit is adjusted the phase of the first clock signal of first die, obtain second clock signal, to send second clock signal to the second die;The second control circuit in signal receiving path is used to control second clock signal adjusting circuit to adjust the phase of received third clock signal to obtain fourth clock signal, to receive data signal from the second die based on fourth clock signal, the second clock signal and third clock signal in second die are not subjected to phase adjustment and frequency adjustment.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more particularly to a die and clock synchronization method. Background Technology

[0002] With the approach of the physical limits of semiconductor device miniaturization, chiplet / 3D architecture has rapidly advanced as a major solution to continue Moore's Law, attracting increasing research attention in both scientific and industrial communities. In industry, the demand for chiplet / 3D products has spurred the commercialization of semiconductor processes, packaging technologies, and design.

[0003] Among these, heterogeneous integration technology offers flexibility and optimal cost. In heterogeneous integration scenarios, the process technology of multiple dies varies significantly, requiring plug-and-play functionality while ensuring the product's required system latency, interface speed, bandwidth, and power consumption, while also considering the complexity of the chip system. How to balance performance and chip system complexity in heterogeneous integration scenarios remains a pressing issue. Summary of the Invention

[0004] This application provides a die and clock synchronization method. A first die and a second die are coupled through a signal path to form a loop, enabling full clock synchronization of the chip system. The control circuit and clock signal conditioning circuit are both located in the first die, reducing the complexity of the second die and solving the adaptation problem of the second die.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a first die, which includes at least one signal path. Each signal path is coupled to a second die to form a loop. Each signal path includes a signal transmission path and a signal reception path. The signal transmission path includes a first control circuit and a first clock signal conditioning circuit, and the signal reception path includes a second control circuit and a second clock signal conditioning circuit. The first control circuit is used to control the first clock signal conditioning circuit to adjust the phase of a first clock signal of the first die to obtain a second clock signal when transmitting a data signal to the second die, so as to transmit the second clock signal to the second die. The second control circuit is used to control the second clock signal conditioning circuit to adjust the phase of a received third clock signal to obtain a fourth clock signal, so as to receive a data signal from the second die based on the fourth clock signal. The second clock signal and the third clock signal in the second die are not subject to phase or frequency adjustment. The first die is a master die, and the second die is a slave die.

[0007] Therefore, the first die and each second die are coupled through a signal path to form a loop. The second clock signal in the first die can be sent to the second die along with the data signal, and the second die samples the data signal based on the second clock signal. Additionally, the first die can receive the third clock signal from the second die. The second and third clock signals in the second die are not subject to phase or frequency adjustment; that is, the second die only serves as a path for the clock signal without performing phase or frequency adjustment. This allows for full clock synchronization of the chip system. Furthermore, the first control circuit, the second control circuit, the first clock signal conditioning circuit, and the second clock signal conditioning circuit are all located in the first die. The second die only involves the data signal path and the clock signal path, thus reducing the circuit design complexity of the second die. When there are multiple process types for the second die in the chip system, only the interface of the second die needs to be compatible with the interface of the first die. Since the clock signal adjustment is completed in the first die, the adaptation of the second die is simpler and more convenient, achieving a plug-and-play effect. This solves the problem of balancing performance and chip system complexity.

[0008] In one possible design, the first die and multiple second dies are housed within the same package.

[0009] In this design, the first die and multiple second dies are housed in the same package to form a 3D stacked architecture. The first die may include control circuitry and clock signal conditioning circuitry in the 3D stacked structure, while the second dies only involve data signal paths and clock signal paths, thereby reducing the circuit design difficulty of the second dies. In addition, the first die can also be compatible with second dies manufactured using different processes.

[0010] In one possible design, at least one signal path includes a first signal path for coupling through a via in at least one die and a second die to form a loop.

[0011] In this design, the first die in the chip system is coupled to the second die through at least one via in the die, forming a loop through a through interconnect. This reduces the design complexity of the second die, significantly reduces the difficulty of chip system integration and adjustment, and greatly improves compatibility.

[0012] In one possible design, the signal transmission path includes a data transmission path and a clock transmission path. The clock transmission path includes a first control circuit and a first clock signal conditioning circuit. The data transmission path is used to transmit data signals to the second die. The first control circuit in the clock transmission path is used to control the first clock signal conditioning circuit to adjust the phase of the first clock signal of the first die to obtain a second clock signal, so as to transmit the second clock signal to the second die. The signal receiving path includes a data receiving path and a clock receiving path. The clock receiving path includes a second control circuit and a second clock signal conditioning circuit. The data receiving path is used to receive data signals transmitted by the second die. The second control circuit in the clock receiving path is used to control the second clock signal conditioning circuit to adjust the phase of the received third clock signal to obtain a fourth clock signal, so as to receive data signals from the second die based on the fourth clock signal. The second clock signal and the third clock signal in the second die are not subject to phase adjustment and frequency adjustment.

[0013] In this design, the first die and each second die are coupled to form a loop, which constructs a fully synchronous clock network for the chip system, greatly improving the chip system's latency, increasing its bandwidth, and reducing its power consumption.

[0014] In one possible design, the data transmission path includes a first register, a second register, and a first buffer; the output of the first register is coupled to the input of the second register, the output of the second register is coupled to the input of the first buffer, and the output of the first buffer is coupled to the second die.

[0015] In this design, the data transmission path includes registers and buffers. The first and second registers can be data registers, used to temporarily store and transmit data signals. The first buffer can be an output buffer, used to temporarily store data signals sent from the first die to the second die.

[0016] In one possible design, the first die also includes a clock circuit; the clock transmission path also includes a second buffer, the input of the first clock signal conditioning circuit is coupled to the output of the clock circuit, the output of the first clock signal conditioning circuit is coupled to the input of the second buffer, and the output of the second buffer is coupled to the second die.

[0017] In this design, the clock transmission path also includes a buffer. The second buffer can be an output buffer, which can be used to temporarily store the second clock signal sent from the first die to the second die. If the first die is a high-speed die and the second die is a low-speed die, by setting the first and second buffers, the data and clock signals between the first and second dies can be coordinated and buffered, achieving synchronization of data and clock signal transmission.

[0018] In one possible design, the data receiving path includes a third buffer, a third register, and a fourth register; the input of the third buffer is coupled to the second die, the output of the third buffer is coupled to the input of the third register, and the output of the third register is coupled to the input of the fourth register.

[0019] In this design, the third and fourth registers can be data registers, used to temporarily store and transmit data signals. The third buffer can be an input buffer, used to temporarily store data signals sent from the second die to the first die.

[0020] In one possible design, the first die also includes a clock circuit; the clock receiving path includes a fourth buffer; the input of the fourth buffer is coupled to the second die, the output of the fourth buffer is coupled to the input of the second clock signal conditioning circuit, and the output of the second clock signal conditioning circuit is coupled to the control terminal of the third register.

[0021] In this design, the fourth buffer can be an input buffer, which can be used to temporarily store the second clock signal sent from the second die to the first die. If the first die is a high-speed die and the second die is a low-speed die, by setting the third and fourth buffers, the data signals and clock signals between the second die and the first die can be coordinated and buffered, thus achieving synchronization of data signal and clock signal transmission.

[0022] In this design, the controller is also integrated into the first die, which reduces the design complexity of the second die. Furthermore, the first and second clock signal conditioning circuits are also integrated into the first die. These circuits can adjust the phase of the clock signal after the chip system integration is complete, reducing design margin, increasing interface frequency, and thus improving bandwidth.

[0023] In one possible design, the first control circuit is further configured to configure the phase adjusted by the first clock signal conditioning circuit based on the timing window of the signal transmission path; the second control circuit is further configured to configure the phase adjusted by the second clock signal conditioning circuit based on the timing window of the signal reception path.

[0024] In this design, the first clock signal conditioning circuit and the second clock signal conditioning circuit can adjust the phase of the clock signal after the chip system integration is completed, which can reduce the design margin, increase the interface frequency, and thus increase the bandwidth.

[0025] Furthermore, considering factors such as die manufacturing process variations, the phase of the first clock signal conditioning circuit should be configured first to ensure the maximum timing window for the first die to transmit data signals to the second die. Then, the phase of the second clock signal conditioning circuit should be configured to ensure the maximum timing window for the second die to transmit data signals to the first die. This completes the timing window configuration for the first die's transmission and reception, ensuring correct data signal transmission.

[0026] Secondly, embodiments of this application provide a clock synchronization method applied to a first die. The first die includes at least one signal path, each signal path being coupled to a second die to form a loop. Each signal path includes a signal transmission path and a signal reception path. The signal transmission path includes a first control circuit and a first clock signal conditioning circuit, and the signal reception path includes a second control circuit and a second clock signal conditioning circuit. The method includes: when transmitting a data signal to the second die, controlling the first control circuit to control the first clock signal conditioning circuit to adjust the phase of a first clock signal of the first die to obtain a second clock signal, and transmitting the second clock signal to the second die; controlling the second control circuit to control the second clock signal conditioning circuit to adjust the phase of a received third clock signal to obtain a fourth clock signal, and receiving a data signal from the second die based on the fourth clock signal, wherein the second clock signal and the third clock signal in the second die are not subject to phase and frequency conditioning.

[0027] For the beneficial effects of the second aspect, please refer to the explanation of the first aspect.

[0028] In one possible design, the first die and multiple second dies are housed within the same package.

[0029] In one possible design, at least one signal path includes a first signal path, which is coupled to a second die through a via in at least one die to form a loop.

[0030] In one possible design, the signal transmission path includes a data transmission path and a clock transmission path. The clock transmission path includes a first control circuit and a first clock signal conditioning circuit. When transmitting a data signal to the second die, controlling the first control circuit to control the first clock signal conditioning circuit to adjust the phase of the first clock signal on the first die to obtain a second clock signal, and transmitting the second clock signal to the second die, includes: controlling the data transmission path to transmit a data signal to the second die, and controlling the first control circuit to control the first clock signal conditioning circuit to adjust the phase of the first clock signal on the first die to obtain a second clock signal, and transmitting the second clock signal to the second die. The signal receiving path includes a data... The receiving path and clock receiving path are provided. The clock receiving path includes a second control circuit and a second clock signal conditioning circuit. Controlling the second control circuit to control the second clock signal conditioning circuit to adjust the phase of the received third clock signal to obtain a fourth clock signal, and receiving data signals from the second die based on the fourth clock signal includes: controlling the data receiving path to receive data signals transmitted by the second die, and controlling the second control circuit to control the second clock signal conditioning circuit to adjust the phase of the received third clock signal to obtain a fourth clock signal, and receiving data signals from the second die based on the fourth clock signal, wherein the second clock signal and the third clock signal in the second die have not undergone phase adjustment and frequency adjustment.

[0031] In one possible design, the data transmission path includes a first register, a second register, and a first buffer; the output of the first register is coupled to the input of the second register, the output of the second register is coupled to the input of the first buffer, and the output of the first buffer is coupled to the second die.

[0032] In one possible design, the first die also includes a clock circuit; the clock transmission path also includes a second buffer, the input of the first clock signal conditioning circuit is coupled to the output of the clock circuit, the output of the first clock signal conditioning circuit is coupled to the input of the second buffer, and the output of the second buffer is coupled to the second die.

[0033] In one possible design, the data receiving path includes a third buffer, a third register, and a fourth register; the input of the third buffer is coupled to the second die, the output of the third buffer is coupled to the input of the third register, and the output of the third register is coupled to the input of the fourth register.

[0034] In one possible design, the first die also includes a clock circuit; the clock receiving path includes a fourth buffer; the input of the fourth buffer is coupled to the second die, the output of the fourth buffer is coupled to the input of the second clock signal conditioning circuit, and the output of the second clock signal conditioning circuit is coupled to the control terminal of the third register.

[0035] In one possible design, the first control circuit controls the first clock signal conditioning circuit to adjust the phase of the first clock signal of the first die by: the first control circuit configures the phase adjusted by the first clock signal conditioning circuit based on the timing window of the signal transmission path; the second control circuit controls the second clock signal conditioning circuit to adjust the phase of the received second clock signal by: the second control circuit configures the phase adjusted by the second clock signal conditioning circuit based on the timing window of the signal reception path.

[0036] Thirdly, embodiments of this application provide a chip system comprising at least two dies, including a first die and a second die. The first die includes at least one signal path, each signal path being coupled to a second die to form a loop, and each signal path including a signal transmitting path and a signal receiving path. The first die is configured to control the signal transmitting path to adjust the phase of a first clock signal of the first die to obtain a second clock signal when transmitting a data signal to the second die, so as to transmit the second clock signal to the second die. The second die is configured to receive the data signal and the second clock signal transmitted by the first die. The second die is also configured to transmit a data signal and a third clock signal to the first die. The first die is also configured to control the signal receiving path to adjust the phase of the received third clock signal to obtain a fourth clock signal, so as to receive a data signal from the second die based on the fourth clock signal, wherein the second clock signal and the third clock signal in the second die are not subject to phase adjustment and frequency adjustment.

[0037] For the beneficial effects of the third aspect, please refer to the explanation of the first aspect.

[0038] In one possible design, the first die and multiple second dies are housed within the same package.

[0039] In one possible design, the signal transmission path includes a first control circuit and a first clock signal conditioning circuit, and the signal reception path includes a second control circuit and a second clock signal conditioning circuit. The first control circuit is used to control the first clock signal conditioning circuit to adjust the phase of the first clock signal of the first die when transmitting a data signal to the second die to obtain a second clock signal, so as to transmit the second clock signal to the second die. The second control circuit is used to control the second clock signal conditioning circuit to adjust the phase of the received second clock signal to obtain a fourth clock signal, so as to receive a data signal from the second die based on the fourth clock signal, wherein the second clock signal and the third clock signal in the second die have not undergone phase adjustment and frequency adjustment.

[0040] In one possible design, the second die includes a receiving circuit and a transmitting circuit. The receiving circuit is used to receive the data signal and the second clock signal transmitted by the first die, and the transmitting circuit is used to transmit the data signal and the third clock signal to the first die.

[0041] Fourthly, embodiments of this application provide a clock synchronization method applied to a chip system. The chip system includes at least two dies, including a first die and a second die. The first die includes at least one signal path, each signal path being coupled to a second die to form a loop. Each signal path includes a signal transmission path and a signal reception path. The method includes: when transmitting a data signal to the second die, the first die controls the signal transmission path to adjust the phase of a first clock signal of the first die to obtain a second clock signal, and transmits the second clock signal to the second die; the second die receives the data signal and the second clock signal; when transmitting a data signal to the first die, the second die transmits the data signal and a third clock signal to the first die; the first die controls the signal reception path to adjust the phase of the received third clock signal to obtain a fourth clock signal, and receives a data signal from the second die based on the fourth clock signal, wherein the second clock signal and the third clock signal in the second die are not subject to phase adjustment and frequency adjustment.

[0042] For the beneficial effects of the fourth aspect, please refer to the explanation of the first aspect.

[0043] In one possible design, the first die and multiple second dies are housed within the same package.

[0044] In one possible design, at least one signal path includes a first signal path for coupling through a via in at least one die and a second die to form a loop.

[0045] Fifthly, embodiments of this application provide an electronic device, which includes a printed circuit board and a first die from the first aspect, the first die being electrically connected to the printed circuit board.

[0046] Sixthly, embodiments of this application provide a computer-readable storage medium including computer instructions that, when executed on an electronic device, cause the electronic device to perform the clock synchronization method in any of the above aspects and any possible implementations.

[0047] In a seventh aspect, embodiments of this application provide a computer program product that, when run on a computer or processor, causes the computer or processor to execute the clock synchronization method in any of the above aspects and any possible implementations.

[0048] Eighthly, embodiments of this application provide a system that may include a wireless access device and at least one electronic device, as described in any possible implementation of any of the foregoing aspects. The electronic device and the wireless access device may execute the clock synchronization method described in any of the foregoing aspects and any possible implementations.

[0049] It is understood that any of the first die, second die, chip system, computer-readable storage medium or computer program product provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects in the corresponding methods, and will not be repeated here.

[0050] These or other aspects of this application will become more readily apparent in the following description. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the structure of an execution device provided in an embodiment of this application;

[0052] Figure 2 This application provides a schematic diagram of the structure of a chip system according to an embodiment of the present application.

[0053] Figure 3 This is a schematic diagram of the structure of a first bare die provided in an embodiment of this application;

[0054] Figure 4 This is a schematic diagram of another chip system provided in an embodiment of this application;

[0055] Figure 5 A schematic diagram of another chip system provided in this application embodiment.

[0056] Figure 6 This is a schematic diagram of another chip system provided in an embodiment of this application;

[0057] Figure 7 A flowchart illustrating a clock synchronization method provided in an embodiment of this application;

[0058] Figure 8 A flowchart of another clock synchronization method provided in an embodiment of this application. Detailed Implementation

[0059] For ease of understanding, the examples provide explanations of some concepts related to the embodiments of this application for reference. As shown below:

[0060] Interposer: A silicon interposer on which logic chips are placed and connected via through silicon vias (TSVs) microelectrodes.

[0061] H-tree is a clock tree structure. Its physical shape resembles the letter H, hence the name H-tree. Each driver in an H-tree is physically connected by an H-shaped metal network, gradually expanding from the root of the clock tree and covering all the drivers.

[0062] A spine-tree is a clock tree structure. A spine-tree has a two-layer architecture, and all devices within it are bidirectional, meaning input devices are also output devices.

[0063] A pseudo-random binary sequence (PRBS) is a random binary sequence of 0s and 1s. The PRBS checksum is as follows: the receiving end first registers the received data for one clock cycle, then encodes the registered data using PRBS, and compares the encoded data with the latest received data. If they match, the PRBS checksum is correct.

[0064] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; "and / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0065] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this embodiment, unless otherwise stated, "a plurality of" means two or more.

[0066] Chiplet technology utilizes through-silicon via (TSV) packaging to encapsulate multiple different wafers or dies within a single chip, combining different dies to achieve the functionality of a complex chip. In heterogeneous integration scenarios, the process technology of these dies can vary significantly, ranging from logic to memory processes. Logic dies can include central processing units (CPUs), while memory dies can include dynamic random access memory (DRAM) and three-dimensional NAND flash memory (3D NAND flash). Furthermore, these dies may have different process nodes. Multiple dies can be coupled together via an interposer and substrate to form a chip system. However, the challenges of achieving plug-and-play functionality across multiple dies within a chip system, while simultaneously balancing chip system performance and complexity, remain to be addressed.

[0067] Therefore, this application provides a first die, which is applied to a chip system. The chip system will be described below.

[0068] Chiplet systems can be applied to various devices, such as... Figure 1 The execution device 10 shown, Figure 1 This is a schematic diagram of the structure of an execution device provided in an embodiment of this application. The execution device 10 can be a terminal, such as a server 11, a mobile terminal 12, a tablet computer 13, a laptop computer 14, or an augmented reality (AR) device. Figure 1 (not shown in the image) Virtual reality (VR) devices (virtual reality technology) Figure 1 (not shown in the image), vehicle terminal ( Figure 1 (not shown in the image), etc. Additionally, a bare die can also be a logic chip.

[0069] This chip system comprises multiple modularly assembled dies with specific functions, such as data storage, computation, signal processing, and data flow management. Based on a rich reserve of intellectual property cores (IP), the chiplet system proposes the concept of IP as a chiplet (IaaC), aiming to achieve "plug-and-play" functionality for specialized IPs using dies. For example, for some core processor IPs, the die can be a graphics processing unit (GPU) IP, a neural network unit (NPU) IP, a video processing unit (VPU) IP, a digital signal processing (DSP) IP, an image signal processor (ISP) IP, and a display processor IP. Furthermore, the die can also be mixed-signal IP and radio frequency (RF) IP.

[0070] The chiplet system in this application can also be referred to as a chip system or a chip-on-chip system. That is, a bare die can also be referred to as a small chip or a chip.

[0071] For example, this chiplet system can be applied to a system-on-a-chip (SoC), on which a variety of functional dies are integrated. For instance, the chip system includes... Figure 2 The first and second bare films shown are shown. Figure 2 This is a schematic diagram of a chip system provided in an embodiment of this application. A second clock signal, a third clock signal, and a data signal can be transmitted between a first die and a second die. The second and third clock signals are in-circuit clocks, and neither the third nor the second clock signals undergo phase or frequency adjustment; that is, the second die only serves as a path for the clock signals without performing phase or frequency adjustment on them.

[0072] For example, the first die can act as a transmitter, and the second die as a receiver. The first die sends a second clock signal and a data signal to the second die. Alternatively, the first die can act as a receiver, and the second die as a transmitter, sending a third clock signal and a data signal to the first die.

[0073] It is understood that, in one example, both the first and second dies are logic process dies. In another example, the first die is a logic process die, and the second die is a memory process die. This application does not specifically limit the process technology of the first and second dies in its embodiments. Furthermore, if both the first and second dies are logic process dies, their process nodes can be the same or different.

[0074] The first bare die provided in the embodiments of this application will be described below.

[0075] This application provides a first bare die 30, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a first die provided in an embodiment of this application. The first die 30 includes at least one signal path. Figure 3 Only one signal path is shown. Each signal path is used to couple with a second die 40 to form a loop, and each signal path includes a signal transmission path (e.g., Figure 3 Signal paths 1-2 and signal receiving paths (e.g.) Figure 3 The signal transmission path 2-1 is coupled to the receiving circuit in the second die 40, and the signal receiving path is coupled to the transmitting circuit in the second die 40. The signal transmission path includes a first control circuit 31 and a first clock signal conditioning circuit 32, and the signal receiving path includes a second control circuit 33 and a second clock signal conditioning circuit 34.

[0076] The first control circuit 31 is used to control the first clock signal adjustment circuit 32 to adjust the phase of the first clock signal of the first die 30 when sending a data signal to the second die 40, so as to obtain a second clock signal and send the second clock signal to the second die 40.

[0077] For example, the first die 30 can act as the master die, and the second die 40 as the slave die. The first clock signal is the clock signal of the first die, and the second clock signal is the accompanying clock. After receiving the data signal and the second clock signal, the second die 40 can sample the data signal based on the second clock signal. The first clock signal adjustment circuit 32 can adjust the phase of the first clock signal to obtain the second clock signal, so as to ensure that the second die 40 can sample the correct data signal based on the second clock signal.

[0078] The second control circuit 33 is used to control the second clock signal adjustment circuit 34 to adjust the phase of the received third clock signal to obtain a fourth clock signal, so as to receive data signals from the second die 40 based on the fourth clock signal.

[0079] For example, if the second die 40 sends a data signal to the first die 30, after receiving the data signal and the third clock signal, the first die 30 can sample the data signal based on the third clock signal. The second clock signal adjustment circuit 34 can adjust the phase of the third clock signal to obtain a fourth clock signal, so as to ensure that the first die 30 can sample the correct data signal based on the fourth clock signal.

[0080] Furthermore, the data signals transmitted in the signal transmission path and the signal reception path can be serial data signals. The first and second clock signals in the signal transmission path, as well as the third and fourth clock signals in the signal reception path, are signals with the same frequency. The second and third clock signals may also have the same phase.

[0081] The first control circuit 31, the second control circuit 33, the first clock signal conditioning circuit 32, and the second clock signal conditioning circuit 34 are all located in the first die 30. The slave DIE only involves the data signal path and the clock signal path, thus reducing the design difficulty of the slave DIE's interface circuit. When there are multiple process types for the slave DIE in the chip system, it is only necessary for the slave DIE's interface to be compatible with the master DIE's interface; that is, the interface of the second die 40 needs to be compatible with the first die 30. Furthermore, since the clock signal conditioning is all completed in the master DIE, slave DIE adaptation is simpler and more convenient. For multiple replaceable slave DIEs, a plug-and-play effect can be achieved.

[0082] The second clock signal and the third clock signal in the second die have not undergone phase adjustment and frequency adjustment.

[0083] For example, in this embodiment, the second die serves only as a path for the clock signal; that is, the second clock signal and the third clock signal can be considered to be the same clock signal. The phase of the second clock signal may differ from the phase of the third clock signal due to various factors (such as voltage variations, temperature variations, and devices in the path). Therefore, the second and third clock signals are used for distinction, but it is not considered that phase adjustment has been performed on the third and second clock signals; that is, the second clock signal has not been actively phase-adjusted. Thus, in one example, the third and second clock signals being buffered before transmission can be considered as not undergoing phase adjustment. Alternatively, phase adjustment can be performed using a phase adjustment circuit (such as a delay-locked loop (DLL) or a phase-locked loop (PLL) circuit), and the phase adjustment should be a controllable adjustment of the phase value.

[0084] In addition, the second clock signal and the third clock signal in the second die were not frequency-adjusted. The frequency of the second clock signal may be different from that of the third clock signal due to various factors, but it is not considered that the frequency of the third clock signal and the second clock signal were adjusted. That is, the second clock signal was not actively frequency-adjusted.

[0085] Optionally, the first die 30 and a plurality of second dies 40 are disposed within the same package.

[0086] For example, the first die 30 and multiple second dies 40 can form a chiplet architecture, wherein the first die 30 and multiple second dies 40 in the chiplet architecture can form a 3D stacked architecture. A single chip system exists within the same package. The first die 30 may include control circuitry and clock signal conditioning circuitry within the chip system, while the second dies 40 only involve data signal paths and clock signal paths, thereby reducing the circuit design complexity of the second dies 40. Furthermore, the first die 30 can also be compatible with second dies 40 manufactured using different processes.

[0087] In another example, the first die and the second die may not be located in the same package. The first die can be configured to connect with the second die in a different package, thereby achieving the adaptation between the first die and the second die.

[0088] Optionally, at least one signal path includes a first signal path for forming a loop through a via in at least one die and a second die 40. For example... Figure 4 As shown, Figure 4 This is a schematic diagram of another chip system provided in an embodiment of this application. Figure 4 The system includes N dies, namely DIE1, DIE2, ..., DIEN-1 and DIEN. The manufacturing processes of DIE1, DIE2, and DIEN are not limited. In one example, DIE1 can be manufactured using a logic process, while DIE2 to DIEN can be manufactured using a register process. DIE1 serves as the master die, i.e., the first die 30 in this embodiment, and DIE2 to DIEN all serve as slave dies, i.e., the second die 40 in this embodiment. A signal path in DIE1 is coupled to DIE2 to form a loop, and another signal path in DIE1 forms a loop through vias in DIE2 to DIEN-1 and the DIE.

[0089] Through-holes (THs) are present in the circuit boards of DIE1, DIE2, or DIEN. These THs are also known as 3D interconnect components. THs can be created using packaging technologies such as TSVs, hybrid bonding (HB), and chip bumps. TSVs and HBs are arbitrary connection media that can achieve interconnection.

[0090] It should be noted that the number of 3D stacked layers can be two or more.

[0091] In addition, such as Figure 5 As shown, Figure 5 This is a schematic diagram of another chip system provided in an embodiment of this application. Figure 5 The diagram illustrates DIE1 and DIE2, which are coupled through an interposer or substrate. DIE1 can be the master DIE, i.e., the first die 30 in this embodiment, and DIE2 can be the slave DIE, i.e., the second die 40 in this embodiment. A signal path in DIE1 is coupled to DIE2 through the interposer or substrate to form a loop. Alternatively, the interposer or substrate can be another die, DIE3, which connects DIE1 and DIE2. This embodiment does not limit the 3D stacking method in the chip system.

[0092] Optionally, the signal transmission path includes a data transmission path and a clock transmission path. The clock transmission path includes a first control circuit 31 and a first clock signal conditioning circuit 32. The data transmission path is used to send data signals to the second die 40. The first control circuit 31 in the clock transmission path controls the first clock signal conditioning circuit 32 to adjust the phase of the first clock signal of the first die 30 to obtain a second clock signal, which is then sent to the second die 40. The signal receiving path includes a data receiving path and a clock receiving path. The clock receiving path includes a second control circuit 33 and a second clock signal conditioning circuit 34. The data receiving path is used to receive data signals sent by the second die 40. The second control circuit 33 in the clock receiving path controls the second clock signal conditioning circuit 34 to adjust the phase of the received third clock signal to obtain a fourth clock signal, which is then used to receive data signals from the second die 40 based on the fourth clock signal. The third and second clock signals are not subject to phase or frequency adjustment.

[0093] For example, in this embodiment of the application, the first die 30 and the second die 40 are coupled to form a loop. The loop may include a data signal loop, i.e., a data transmission path and a data reception path forming a loop, or a clock signal loop, i.e., a clock transmission path and a clock reception path forming a loop.

[0094] That is, after the second clock signal of the first die 30 is sent to the second die 40, the phase of the second clock signal is not adjusted at the second die 40. Therefore, the third clock signal and the second clock signal can be considered as the same signal. The third clock signal will be sent to the second clock signal adjustment circuit 34 of the first die 30 along with the loop when the second die 40 sends a data signal to the first die 30. The second clock signal adjustment circuit 34 adjusts the phase of the third clock signal to obtain the fourth clock signal. The first die 30 can sample the data signal based on the fourth clock signal.

[0095] Thus, the first die 30 and each of the second dies 40 are coupled to form a loop, constructing a fully synchronous clock network for the chip system, which greatly improves the latency of the chip system, increases the bandwidth of the chip system, and reduces the power consumption of the chip system.

[0096] Optional, such as Figure 6 As shown, Figure 6 This is a schematic diagram of another chip system provided in an embodiment of this application. Figure 6 The device includes DIE1, DIE2 and DIE3, where DIE1 is the master DIE, i.e. the first die 30 in this embodiment, and DIE2 and DIE3 are both slave DIEs, i.e. the second die 40 in this embodiment.

[0097] The first die 30 also includes a clock circuit 35, which generates a first clock signal. The clock circuit 35 can be a phase-locked loop (PLL). After generating the first clock signal, the clock circuit 35 can transmit the first clock signal to various regions within the first die 30 via a mesh clock tree. The mesh clock tree can be an H-tree, a spine-tree, or a standard clock tree structure.

[0098] In the signal transmission paths of DIE1 and DIE2 (e.g. Figure 6 In the data transmission path of signal path 1-2), DIE1 includes a first register 36, a second register 37, and a first buffer 38. The output of the first register 36 is coupled to the input of the second register 37, the output of the second register 37 is coupled to the input of the first buffer 38, and the output of the first buffer 38 is coupled to the second die 40. DIE2 includes a fifth buffer 41 and a fifth register 42. The output of the first buffer 38 and the input of the fifth buffer 41 are coupled via HB or ubump, and the output of the fifth buffer 41 is coupled to the input of the fifth register 42.

[0099] In the clock transmission path of the signal transmission paths between DIE1 and DIE2, DIE1 also includes a second buffer 39. The input terminal of the first clock signal conditioning circuit 32 is coupled to the output terminal of the clock circuit 35; the output terminal of the first clock signal conditioning circuit 32 is coupled to the input terminal of the second buffer 39; and the output terminal of the second buffer 39 is coupled to the second die 40. DIE2 includes a sixth buffer 43. The output terminal of the second buffer 39 and the input terminal of the sixth buffer 43 are coupled via HB or ubump; and the output terminal of the sixth buffer 43 is coupled to the control terminal of the fifth register 42. Figure 6 The first control circuit 31 and the second control circuit 33 are not shown.

[0100] In this system, the first register 36 can send a data signal based on the first clock signal generated by the clock circuit 35. The first clock signal adjustment circuit 32 adjusts the first clock signal generated by the clock circuit 35 to obtain a second clock signal. The second register 37 stores the data signal based on the second clock signal. The data signal is temporarily stored in the first buffer 38, and the second clock signal is temporarily stored in the second buffer 39. After the data signal and the second clock signal are sent to DIE2 via HB or ubump respectively, the data signal is temporarily stored in the fifth buffer 41, and the second clock signal is temporarily stored in the sixth buffer 43. The fifth register 42 stores the data signal based on the second clock signal. This completes the process of sending a data signal from DIE1 to DIE2.

[0101] In the signal receiving paths of DIE1 and DIE2 (e.g. Figure 6 In the data receiving path of signal path 2-1), DIE1 includes a third buffer 310, a third register 311, and a fourth register 312. The input of the third buffer 310 is coupled to the second die 40, the output of the third buffer 310 is coupled to the input of the third register 311, and the output of the third register 311 is coupled to the input of the fourth register 312. DIE2 includes a sixth register 44 and a seventh buffer 45. The output of the sixth register 44 is coupled to the input of the seventh buffer 45, and the output of the seventh buffer 45 is coupled to the input of the third buffer 310 via HB or ubump.

[0102] In the clock receiving path of the signal receiving paths of DIE1 and DIE2, DIE1 includes a fourth buffer 313. The input of the fourth buffer 313 is coupled to the second die 40, the output of the fourth buffer 313 is coupled to the input of the second clock signal conditioning circuit 32, and the output of the second clock signal conditioning circuit 32 is coupled to the control terminal of the third register 311. DIE2 includes an eighth buffer 46, the output of which is coupled to the input of the fourth buffer 313 via HB or ubump.

[0103] In this process, the sixth register 44 sends a data signal based on the third clock signal. The data signal is first temporarily stored in the seventh buffer 45, and the third clock signal is also temporarily stored in the eighth buffer 46. The data signal is sent to the third buffer 310 via HB or ubump, and the third clock signal is sent to the fourth buffer 313 via HB or ubump. The second clock signal adjustment circuit 34 adjusts the phase of the third clock signal to obtain the fourth clock signal. The third register 311 registers the data signal based on the fourth clock signal, and then sends the data signal to the fourth register 312. The fourth register 312 registers the data signal based on the first clock signal.

[0104] It is understandable that the register circuits in the signal transmission and signal reception paths can also be implemented by other timing circuits or analog circuits.

[0105] In addition, continue to refer to Figure 6 , Figure 6 The diagram also shows the signal paths for DIE1 and DIE3. These signal paths include signal transmission paths (e.g.,...). Figure 6 Signal paths 1-3 and signal receiving paths (e.g.) Figure 6 (Signal path 3-1). For this signal path, the settings of the registers and buffers in DIE1 and DIE3 can refer to the settings of the registers and buffers in the signal paths of DIE1 and DIE2. Among them, DIE1 and DIE3 transmit data signals and clock signals through the via in DIE2, which can be a TSV.

[0106] Optionally, the first control circuit 31 is further configured to configure the phase adjusted by the first clock signal conditioning circuit 32 based on the timing window of the signal transmission path. The second control circuit 33 is further configured to configure the phase adjusted by the second clock signal conditioning circuit 34 based on the timing window of the signal transmission path.

[0107] For example, the first clock signal conditioning circuit 32 and the second clock signal conditioning circuit 34 can be any circuit capable of phase adjustment. In one example, the first clock signal conditioning circuit 32 may include multiple delay units, and the second clock signal conditioning circuit 32 may also include multiple delay units. The delay units can be delay lines, which can adjust the phase of the clock signal. Multiple delay units can correspond to multiple settings, where all delay units being turned on corresponds to the maximum setting, and all delay units being turned off corresponds to the minimum setting.

[0108] For example, the first control circuit 31, the first clock signal conditioning circuit 32, the second control circuit 33, and the second clock signal conditioning circuit 34 are all integrated into the first die 30, which can reduce the design complexity of the second die 40. Furthermore, the first clock signal conditioning circuit 32 and the second clock signal conditioning circuit 34 can adjust the phase of the clock signal after the chip system integration is completed, which can reduce design margin, increase interface frequency, and thus improve bandwidth.

[0109] For example, the phase in the first clock signal conditioning circuit 32 and the second clock signal conditioning circuit 34 can be determined through a training process before the chip system is operational.

[0110] In timing analysis, the timing window and data signal are related to the setup margin and hold margin of the clock signal. Setup and hold times are two important parameters in timing analysis. The effective time of the data signal before the rising edge of the clock signal is called the setup time, and the effective time of the data signal after the falling edge of the clock signal is called the hold time.

[0111] Considering factors such as manufacturing process variations in the die, the number of delayed units in the first clock signal conditioning circuit 32 that are turned on should be adjusted first to maximize the timing window for the first die 30 to transmit data signals to the second die 40. Then, the number of delayed units in the second clock signal conditioning circuit 34 that are turned on should be adjusted to maximize the timing window for the second die 40 to transmit data signals to the first die 30. This completes the timing window configuration for the first die 30 during transmission and reception, ensuring correct data signal transmission.

[0112] For the first clock signal conditioning circuit 32, the training process can be a process of traversing the delay unit levels. Specifically, the training process can be as follows: the first control circuit 31 controls the first register 36 to output a PRBS, which is a known binary sequence. At this time, the corresponding delay unit level can be the minimum level. The delay unit level is gradually increased, and the PRBS verification is checked for correctness. The delay unit level corresponding to a correct PRBS verification is determined, and this level corresponds to a minimum timing window of the signal transmission path. The delay unit level is then gradually increased again to determine the delay unit level corresponding to an incorrect PRBS verification, which corresponds to another minimum timing window of the signal transmission path. The maximum timing window can be determined from these two minimum timing windows.

[0113] The second clock signal conditioning circuit 34 can also follow the same training process as the first clock signal conditioning circuit 32, thereby determining the phase of the second clock signal conditioning circuit 32.

[0114] Applied to Figure 3 or Figure 6 The first bare die shown in this application embodiment provides a clock synchronization method, such as... Figure 7 As shown, Figure 7 A flowchart illustrating a clock synchronization method provided in an embodiment of this application. The method includes the following steps.

[0115] Step 701: When the signal transmission path sends a data signal to the second die, the first die controls the first control circuit to control the first clock signal adjustment circuit to adjust the phase of the first clock signal of the first die to obtain a second clock signal, so as to send the second clock signal to the second die.

[0116] Step 702: The first die controls the second control circuit to control the second clock signal conditioning circuit to adjust the phase of the received third clock signal to obtain a fourth clock signal, so as to receive a data signal from the second die based on the fourth clock signal, wherein the second clock signal and the third clock signal in the second die have not undergone phase adjustment and frequency adjustment.

[0117] For example, the first die and each second die are coupled through a signal path to form a loop. The second clock signal in the first die can be sent to the second die along with the data signal, and the second die samples the data signal based on the second clock signal. Additionally, the first die can receive a third clock signal from the second die. Neither the third nor the second clock signal undergoes phase or frequency adjustment; that is, the second die only serves as a path for the clock signal without performing phase adjustment. This allows for full clock synchronization of the chip system. Furthermore, the first control circuit, the second control circuit, the first clock signal conditioning circuit, and the second clock signal conditioning circuit are all located in the first die. The second die only involves the data signal path and the clock signal path, thus reducing the circuit design complexity of the second die. When there are multiple process types for the second die in the chip system, it is only necessary for the interface of the second die to be compatible with the interface of the first die. Since the clock signal adjustment is all completed in the first die, the adaptation of the second die is simpler and more convenient, achieving a plug-and-play effect.

[0118] The implementation methods of steps 701 and 702 can be found in the above description of the first bare die.

[0119] Step 701 may include: the first die control data transmission path sending a data signal to the second die, and controlling the first control circuit to control the first clock signal adjustment circuit to adjust the phase of the first clock signal of the first die to obtain a second clock signal, so as to send the second clock signal to the second die.

[0120] Step 702 may include: a first die control data receiving path receiving a data signal transmitted by a second die, and controlling a second control circuit to control a second clock signal adjustment circuit to adjust the phase of the received third clock signal to obtain a fourth clock signal, so as to receive a data signal from the second die based on the fourth clock signal, wherein the second clock signal and the third clock signal in the second die have not undergone phase adjustment and frequency adjustment.

[0121] Specifically, the first control circuit configures the phase adjusted by the first clock signal conditioning circuit based on the timing window of the signal transmission path, and the second control circuit configures the phase adjusted by the second clock signal conditioning circuit based on the timing window of the signal reception path.

[0122] Embodiments of this application also provide a chip system comprising at least two dies, including a first die and a second die. The first die includes at least one signal path, each signal path being coupled to a second die to form a loop. Each signal path includes a signal transmitting path and a signal receiving path. The first die is configured to control the signal transmitting path to adjust the phase of a first clock signal of the first die to obtain a second clock signal when transmitting a data signal to the second die, thereby transmitting the second clock signal to the second die. The second die is configured to receive the data signal and the second clock signal transmitted by the first die. The second die is also configured to transmit a data signal and a third clock signal to the first die. The first die is further configured to control the signal receiving path to adjust the phase of the received third clock signal to obtain a fourth clock signal, thereby receiving a data signal from the second die based on the fourth clock signal. The second and third clock signals in the second die are not subject to phase or frequency adjustment.

[0123] The second die includes a receiving circuit and a transmitting circuit. The receiving circuit is used to receive the data signal and the second clock signal transmitted by the first die, and the transmitting circuit is used to transmit the data signal and the third clock signal to the first die.

[0124] This application also provides a clock synchronization method, such as... Figure 8 As shown, Figure 8 A flowchart of another clock synchronization method provided in an embodiment of this application is shown. The method is applied to a chip system including at least two dies, each die including a first die and a second die. The first die includes at least one signal path, each signal path being coupled to a second die to form a loop. Each signal path includes a signal transmission path and a signal reception path. The method includes the following steps.

[0125] Step 801: When sending a data signal to the second die, the first die control signal transmission path adjusts the phase of the first clock signal of the first die to obtain a second clock signal, so as to send the second clock signal to the second die.

[0126] Step 802: The second die receives the data signal and the second clock signal.

[0127] Step 803: When sending a data signal to the first die, the second die sends a data signal and a third clock signal to the first die.

[0128] Step 804: The first die control signal receiving path adjusts the phase of the received third clock signal to obtain a fourth clock signal, and receives a data signal from the second die based on the fourth clock signal, wherein the second clock signal and the third clock signal in the second die have not undergone phase adjustment and frequency adjustment.

[0129] This application also provides an electronic device, which includes a printed circuit board and the first die described above, and the first die and the printed circuit board are electrically connected.

[0130] Embodiments of this application also provide a computer storage medium storing computer instructions. When these computer instructions are executed on an electronic device, the electronic device performs the aforementioned method steps to implement the clock synchronization method in the above embodiments. The computer storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory (ROM), random access memory (RAM), DRAM, resistive random access memory (RRAM), magnetic disk, or optical disk.

[0131] Embodiments of this application also provide a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the clock synchronization method executed by the electronic device in the above embodiments.

[0132] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component or module. The apparatus may include a connected processor and a memory. The memory is used to store computer execution instructions. When the apparatus is running, the processor can execute the computer execution instructions stored in the memory to cause the chip to execute the clock synchronization method executed by the electronic device in the above method embodiments.

[0133] In this embodiment, the first die, computer storage medium, computer program product, or chip are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0134] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0135] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0136] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0137] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0138] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0139] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A first bare wafer, characterized in that, The first die includes at least one signal path, each signal path being coupled to a second die to form a loop, each signal path including a signal transmission path and a signal reception path, the signal transmission path including a data transmission path and a clock transmission path, the clock transmission path including a first control circuit and a first clock signal conditioning circuit, the signal reception path including a data reception path and a clock reception path, the clock reception path including a second control circuit and a second clock signal conditioning circuit; The data transmission path is used to send data signals to the second die; The first control circuit is used to control the first clock signal adjustment circuit to adjust the phase of the first clock signal of the first die to obtain a second clock signal, so as to send the second clock signal to the second die; The data receiving path is used to receive the data signal sent by the second die; The second control circuit is used to control the second clock signal adjustment circuit to adjust the phase of the received third clock signal to obtain a fourth clock signal, so as to receive the data signal from the second die based on the fourth clock signal, wherein the second clock signal and the third clock signal in the second die have not undergone phase adjustment and frequency adjustment.

2. The first bare wafer according to claim 1, characterized in that, The first die and a plurality of second dies are disposed in the same package.

3. The first bare wafer according to claim 1 or 2, characterized in that, The at least one signal path includes a first signal path, which is used to couple to the second die through a via in at least one die to form a loop.

4. The first bare wafer according to claim 1, characterized in that, The data transmission path includes a first register, a second register, and a first buffer; the output of the first register is coupled to the input of the second register, the output of the second register is coupled to the input of the first buffer, and the output of the first buffer is coupled to the second die.

5. The first bare wafer according to claim 4, characterized in that, The first die also includes a clock circuit; The clock transmission path further includes a second buffer, the input terminal of the first clock signal conditioning circuit is coupled to the output terminal of the clock circuit, the output terminal of the first clock signal conditioning circuit is coupled to the input terminal of the second buffer, and the output terminal of the second buffer is coupled to the second die.

6. The first bare die according to claim 1, characterized in that, The data receiving path includes a third buffer, a third register, and a fourth register; the input of the third buffer is coupled to the second die, the output of the third buffer is coupled to the input of the third register, and the output of the third register is coupled to the input of the fourth register.

7. The first bare wafer according to claim 6, characterized in that, The first die also includes a clock circuit; The clock receiving path includes a fourth buffer; the input of the fourth buffer is coupled to the second die, the output of the fourth buffer is coupled to the input of the second clock signal conditioning circuit, and the output of the second clock signal conditioning circuit is coupled to the control terminal of the third register.

8. The first bare wafer according to claim 1, characterized in that, The first control circuit is further configured to configure the phase adjusted by the first clock signal conditioning circuit based on the timing window of the signal transmission path; the second control circuit is further configured to configure the phase adjusted by the second clock signal conditioning circuit based on the timing window of the signal reception path.

9. A clock synchronization method, characterized in that, The method is applied to a first die, the first die including at least one signal path, each signal path being coupled to a second die to form a loop, each signal path including a signal transmission path and a signal reception path, the signal transmission path including a data transmission path and a clock transmission path, the clock transmission path including a first control circuit and a first clock signal conditioning circuit, the signal reception path including a data reception path and a clock reception path, the clock reception path including a second control circuit and a second clock signal conditioning circuit; the method includes: The data transmission path is controlled to send a data signal to the second die, and the first control circuit is controlled to control the first clock signal adjustment circuit to adjust the phase of the first clock signal of the first die to obtain a second clock signal, so as to send the second clock signal to the second die. The data receiving path is controlled to receive the data signal transmitted by the second die, and the second control circuit is controlled to control the second clock signal adjustment circuit to adjust the phase of the received third clock signal to obtain a fourth clock signal, so as to receive the data signal from the second die based on the fourth clock signal, wherein the second clock signal and the third clock signal in the second die have not undergone phase adjustment and frequency adjustment.

10. The method according to claim 9, characterized in that, The first die and a plurality of second dies are disposed in the same package.

11. The method according to claim 9 or 10, characterized in that, The at least one signal path includes a first signal path, which is coupled to the second die through a via in at least one die to form a loop.

12. The method according to claim 9, characterized in that, The data transmission path includes a first register, a second register, and a first buffer; the output of the first register is coupled to the input of the second register, the output of the second register is coupled to the input of the first buffer, and the output of the first buffer is coupled to the second die.

13. The method according to claim 12, characterized in that, The first die also includes a clock circuit; the clock transmission path also includes a second buffer, the input terminal of the first clock signal conditioning circuit is coupled to the output terminal of the clock circuit, the output terminal of the first clock signal conditioning circuit is coupled to the input terminal of the second buffer, and the output terminal of the second buffer is coupled to the second die.

14. The method according to claim 9, characterized in that, The data receiving path includes a third buffer, a third register, and a fourth register; the input of the third buffer is coupled to the second die, the output of the third buffer is coupled to the input of the third register, and the output of the third register is coupled to the input of the fourth register.

15. The method according to claim 14, characterized in that, The first die also includes a clock circuit; the clock receiving path includes a fourth buffer; the input of the fourth buffer is coupled to the second die, the output of the fourth buffer is coupled to the input of the second clock signal conditioning circuit, and the output of the second clock signal conditioning circuit is coupled to the control terminal of the third register.

16. The method according to claim 9, characterized in that, The first control circuit controls the first clock signal adjustment circuit to adjust the phase of the first clock signal of the first die, including: The first control circuit configures the phase adjusted by the first clock signal conditioning circuit based on the timing window of the signal transmission path; The second control circuit controls the second clock signal conditioning circuit to adjust the phase of the received second clock signal, including: The second control circuit configures the phase adjusted by the second clock signal conditioning circuit based on the timing window of the signal receiving path.

17. A chip system, characterized in that, The chip system includes at least two dies, including a first die and a second die. The first die includes at least one signal path, each signal path being coupled to a second die to form a loop. Each signal path includes a signal transmission path and a signal reception path. The signal transmission path includes a data transmission path and a clock transmission path. The clock transmission path includes a first control circuit and a first clock signal conditioning circuit. The signal reception path includes a data reception path and a clock reception path. The clock reception path includes a second control circuit and a second clock signal conditioning circuit. The first control circuit in the first die is used to control the first clock signal adjustment circuit in the signal transmission path to adjust the phase of the first clock signal of the first die to obtain a second clock signal when sending a data signal to the second die, so as to send the second clock signal to the second die. The second die is used to receive the data signal and the second clock signal sent by the first die; The second die is also used to send the data signal and the third clock signal to the first die; The second control circuit in the first die is further configured to control the second clock signal adjustment circuit in the signal receiving path to adjust the phase of the received third clock signal to obtain a fourth clock signal, so as to receive the data signal from the second die based on the fourth clock signal, wherein the second clock signal and the third clock signal in the second die are not subject to phase adjustment and frequency adjustment.

18. The chip system according to claim 17, characterized in that, The first die and a plurality of second dies are disposed in the same package.

19. The chip system according to claim 17, characterized in that, The second die includes a receiving circuit and a transmitting circuit. The receiving circuit is used to receive the data signal and the second clock signal transmitted by the first die, and the transmitting circuit is used to transmit the data signal and the third clock signal to the first die.

20. A clock synchronization method, characterized in that, The method is applied to a chip system comprising at least two dies, the at least two dies including a first die and a second die, the first die including at least one signal path, each signal path being coupled to a second die to form a loop, each signal path including a signal transmitting path and a signal receiving path, the signal transmitting path including a data transmitting path and a clock transmitting path, the clock transmitting path including a first control circuit and a first clock signal conditioning circuit, the signal receiving path including a data receiving path and a clock receiving path, the clock receiving path including a second control circuit and a second clock signal conditioning circuit; the method includes: When sending a data signal to the second die, the first control circuit in the first die controls the first clock signal adjustment circuit in the signal transmission path to adjust the phase of the first clock signal of the first die to obtain a second clock signal, so as to send the second clock signal to the second die. The second die receives the data signal and the second clock signal; When the data signal is sent to the first die, the second die sends the data signal and the third clock signal to the first die; The second control circuit in the first die controls the second clock signal adjustment circuit in the signal receiving path to adjust the phase of the received third clock signal to obtain a fourth clock signal, and receives the data signal from the second die based on the fourth clock signal, wherein the second clock signal and the third clock signal in the second die have not undergone phase adjustment and frequency adjustment.

21. The method according to claim 20, characterized in that, The first die and a plurality of second dies are disposed in the same package.

22. The method according to claim 20 or 21, characterized in that, The at least one signal path includes a first signal path, which is used to couple to the second die through a via in at least one die to form a loop.

23. An electronic device, characterized in that, The electronic device includes a printed circuit board and a first die as described in any one of claims 1 to 8, wherein the first die and the printed circuit board are electrically connected.

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