A timing controller applied to a cholesteric liquid crystal display device

Abstract

A timing controller applied to a cholesteric liquid crystal display device is disclosed. The timing controller includes a receiving end unit, a transmitting end unit, a control unit and a line buffer. The receiving end unit is used to receive high-speed differential signals. The transmitting end unit is coupled to the receiving end unit and used to output the high-speed differential signals. The control unit is coupled between the receiving end unit and the transmitting end unit and used to generate a control signal according to handshake control between the timing controller and a host. The line buffer is coupled to the control unit and used to perform horizontal / vertical line scanning according to the control signal.

Description

Technical Field

[0001] This invention relates to timing controllers, and more particularly to a timing controller for use in a cholesterol liquid crystal display device. Background Technology

[0002] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a timing controller traditionally used in cholesterol liquid crystal display devices. Figure 1 As shown, the timing controller 10 of the conventional cholesteric liquid crystal display device 1 still requires an external frame buffer 12 (e.g., static random access memory, SRAM) to store the entire frame of image data before displaying it on the cholesteric liquid crystal display panel 16 via the row / column drive device 14. However, this also leads to a significant increase in the power consumption and cost required for the operation of the conventional cholesteric liquid crystal display device 1, which urgently needs to be improved. Summary of the Invention

[0003] Therefore, the present invention proposes a timing controller for cholesterol liquid crystal display devices to effectively solve the above-mentioned problems encountered in the prior art.

[0004] A preferred embodiment of the present invention provides a timing controller for a cholesterol-based liquid crystal display device. In this embodiment, the timing controller includes a receiving unit, a transmitting unit, a control unit, and a line buffer. The receiving unit receives high-speed differential signals. The transmitting unit is coupled to the receiving unit and outputs high-speed differential signals. The control unit is coupled between the receiving unit and the transmitting unit and generates control signals based on the handover control between the timing controller and the host computer. The line buffer is coupled to the control unit and performs horizontal / vertical line scanning based on the control signals.

[0005] In one embodiment, the cholesteric liquid crystal display device further includes a row driving device, a column driving device, and a cholesteric liquid crystal display panel. The row driving device is coupled to a timing controller to provide row driving signals based on high-speed differential signals. The column driving device is coupled to the timing controller to provide column driving signals based on high-speed differential signals. The cholesteric liquid crystal display panel is coupled to both the row driving device and the column driving device, and is driven by the row driving signals and the column driving signals to display an image.

[0006] In one embodiment, horizontal line scanning includes performing high-speed differential signal line scanning on the cholesterol liquid crystal display panel sequentially from top to bottom or from bottom to top.

[0007] In one embodiment, vertical line scanning includes performing high-speed differential signal line scanning on the cholesterol liquid crystal display panel sequentially from left to right or from right to left.

[0008] In one embodiment, the receiving unit and the transmitting unit are respectively a high-speed differential signal receiver and a high-speed differential signal transmitter.

[0009] In one embodiment, the high-speed differential signal includes display data.

[0010] In one embodiment, the timing controller further includes another receiving unit for receiving a low-speed serial signal.

[0011] In one embodiment, the other receiving unit is a low-speed serial signal receiver.

[0012] In one embodiment, the low-speed serial signal includes write instructions and read instructions.

[0013] In one embodiment, horizontal line scanning includes sequentially scanning the cholesterol liquid crystal display panel with the low-speed serial signal from top to bottom or bottom to top.

[0014] In one embodiment, vertical line scanning includes sequentially scanning the cholesterol liquid crystal display panel with the low-speed serial signal from left to right or from right to left.

[0015] In one embodiment, when the timing controller performs arbitrary scanning display of the high-speed differential signal, during the first period, the control signal is a write instruction to take n0 lines of data from p lines and write them to the first storage area of ​​the line buffer; during the second period, the control signal is a write instruction to take n1 lines of data from (p-n0) lines and write them to the second storage area of ​​the line buffer; during the third period, the control signal is a write instruction to take n2 lines of data from (p-n0-n1) lines and write them to the first storage area of ​​the line buffer; during the fourth period, the control signal is a write instruction to take n3 lines of data from (p-n0-n1-n2) lines and write them to the second storage area of ​​the line buffer, where p, n0, n1, n2, and n3 are all positive integers and p is greater than n0, n1, n2, and n3.

[0016] In one embodiment, the line buffer is a static random access memory (SRAM).

[0017] In one embodiment, the cholesterol liquid crystal display device does not require a frame buffer, thereby reducing power consumption and cost.

[0018] Compared to existing technologies, the timing controller disclosed in this invention, applied to a cholesterol liquid crystal display device, achieves substantial benefits such as reducing chip area and pin count, lowering power consumption and cost by replacing the traditional external frame buffers with line buffers inside the timing controller through its handshake control with the host. Attached Figure Description

[0019] Figure 1 This is a schematic diagram showing that the timing controller traditionally used in cholesterol liquid crystal display devices still requires an external frame buffer.

[0020] Figure 2 This is a schematic diagram of a timing controller for a cholesterol liquid crystal display device that does not require an external frame buffer, according to a preferred embodiment of the present invention.

[0021] Figure 3 A timing diagram of an embodiment of the high-speed differential signal and low-speed serial signal received by the timing controller.

[0022] Figure 4 A schematic diagram illustrating the use of horizontal line scanning from top to bottom and vertical line scanning from left to right to display images in a cholesterol liquid crystal display device.

[0023] Figure 5 The timing diagram for the low-speed serial signals received by the timing controller, including write instructions and parameters.

[0024] Figure 6 This is a schematic diagram showing the total number of scan lines when the cholesterol liquid crystal display device is in reset mode.

[0025] Figure 7 This is a schematic diagram showing the total number of scan lines for a cholesterol liquid crystal display device to perform a horizontal scan display from top to bottom.

[0026] Figure 8 This is a schematic diagram showing the total number of scan lines for a cholesterol liquid crystal display device performing a vertical scan from left to right.

[0027] Figure 9 This is a timing diagram showing a horizontal scan of a high-speed differential signal from top to bottom.

[0028] Figures 10A to 10D These are schematic diagrams showing the cholesterol liquid crystal display device performing a horizontal scan display from top to bottom after being in reset mode.

[0029] Figures 11A to 11D These are schematic diagrams showing a cholesterol-based liquid crystal display device performing a horizontal scan from bottom to top after being in reset mode.

[0030] Figure 12 This is a timing diagram showing a vertical scan of a high-speed differential signal from left to right.

[0031] Figures 13A to 13D These are schematic diagrams showing a cholesterol liquid crystal display device performing a vertical scan from left to right.

[0032] Figures 14A to 14D These are schematic diagrams showing a cholesterol liquid crystal display device performing a vertical scan from right to left.

[0033] Figure 15 This is a timing diagram for displaying high-speed differential signals by arbitrary scanning.

[0034] Figure 16 This is a timing diagram showing a horizontal scan of a low-speed serial signal from top to bottom.

[0035] Figure 17 This is a timing diagram for displaying an arbitrary horizontal scan of a low-speed serial signal.

[0036] Figure 18 This is a timing diagram showing a vertical scan of a low-speed serial signal from left to right.

[0037] Figure 19 This is a timing diagram for displaying a low-speed serial signal in an arbitrary vertical scan.

[0038] Explanation of key component symbols:

[0039] 1…Cholesterol LCD display device

[0040] 10… Timing Controller

[0041] 12…frame buffer

[0042] 14… Row / Column Drive Unit

[0043] 16… Cholesterol LCD Panel

[0044] 2…Cholesterol LCD display device

[0045] 20… Timing Controller

[0046] 22… Row / column drive unit

[0047] 24… Cholesterol LCD Display Panel

[0048] 200~201… Receiver Unit

[0049] 202…Transmission end unit

[0050] 204…Control Unit

[0051] 206…line buffer

[0052] DIF…high-speed differential signaling

[0053] SER…low-speed serial signal

[0054] CTL… control signal

[0055] CRD… Row / Column Drive Signal

[0056] BK…Blank Period

[0057] FD…frame data

[0058] W…Write command

[0059] R…Read command

[0060] PM… parameters

[0061] PM1~PM(n-1)…First parameter~(n-1)th parameter

[0062] IMG... visuals

[0063] SCLK… clock signal

[0064] t0~tn…time

[0065] SLI…Starting Line Indicator

[0066] SPI... Sequence Peripheral Interface Signals

[0067] RX… Receiver Unit

[0068] TX…Transmitter Unit

[0069] INT… signal

[0070] SRAM0… storage area

[0071] SRAM1… storage area

[0072] DET…Detection period

[0073] VL…Vertical line

[0074] Blocks B0~B(n-1)…

[0075] DL(0)~DL(n-1)… data

[0076] DLa~DLx… data

[0077] DVL0~DVLN… data

[0078] DVLa~DVLx… data

[0079] Number of lines p, n0, n1, n2, n3, n…

[0080] W(p,n0)...Write command

[0081] W(p-n0,n1)...Write command

[0082] W(p-n0-n1,n2)…Write command

[0083] W(p-n0-n1-n2,n3)…Write command Detailed Implementation

[0084] A preferred embodiment of the present invention is a timing controller for a cholesterol liquid crystal display device. In this embodiment, the timing controller can replace the traditionally external frame buffers with its internal line buffers through the handshake control between itself and the host, thereby achieving substantial effects such as reducing chip area and pin count, reducing power consumption and cost, and thus effectively solving the problems encountered in the prior art.

[0085] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a timing controller applied to a cholesterol liquid crystal display device in this embodiment. Figure 2 As shown, the cholesteric liquid crystal display device 2 includes a timing controller 20, a row / column driver 22, and a cholesteric liquid crystal display panel 24. The timing controller 20 is coupled to the row / column driver 22. The row / column driver 22 is coupled to the cholesteric liquid crystal display panel 24. The cholesteric liquid crystal display panel 24 includes multiple row pixels and multiple column pixels; the row / column driver 22 includes a row driver and a column driver, which are used to drive the multiple row pixels and multiple column pixels of the cholesteric liquid crystal display panel 24 to display the image.

[0086] The timing controller 20 includes receiving units 200-201, transmitting unit 202, control unit 204, and line buffer 206. Receiving unit 200 is coupled to control unit 204. Receiving unit 201 is coupled to control unit 204. Control unit 204 is coupled to both transmitting unit 202 and line buffer 206. Transmitting unit 202 is coupled to row / column drive device 22. Receiving unit 200 receives high-speed differential signal DIF and transmits it to control unit 204. Receiving unit 201 receives low-speed serial signal SER and transmits it to control unit 204.

[0087] In practice, the receiving unit 200 can be a high-speed differential signal receiver and the transmitting unit 202 can be a high-speed differential signal transmitter. The receiving unit 201 can be a low-speed serial signal receiver, but is not limited thereto. The line buffer 206 can be a static random access memory (SRAM), but is not limited thereto. The high-speed differential signal DIF and the low-speed serial signal SER can come from the host (not shown in the figure), but are not limited thereto. The high-speed differential signal DIF can include display data and the low-speed serial signal SER can include write instructions, read instructions, and handshake control information between the timing controller 20 and the host (not shown in the figure), but are not limited thereto.

[0088] Control unit 204 generates control signal CTL to line buffer 206 based on the handover control information between timing controller 20 and host (not shown) included in low-speed serial signal SER. Line buffer 206 performs horizontal or vertical line scanning based on control signal CTL.

[0089] In one embodiment, horizontal line scanning includes performing high-speed differential signal DIF line scanning on the cholesterol liquid crystal display panel 24 sequentially from top to bottom or from bottom to top; vertical line scanning includes performing high-speed differential signal DIF line scanning on the cholesterol liquid crystal display panel 24 sequentially from left to right or from right to left.

[0090] In another embodiment, horizontal line scanning includes performing a low-speed serial signal SER line scan on the cholesterol liquid crystal display panel 24 sequentially from top to bottom or from bottom to top; vertical line scanning includes performing a low-speed serial signal SER line scan on the cholesterol liquid crystal display panel 24 sequentially from left to right or from right to left.

[0091] The transmitting unit 202 is used to output the high-speed differential signal DIF from the control unit 204 to the row / column driving device 22. The row / column driving device 22 is used to provide row / column driving signals CRD to the cholesteric liquid crystal display panel 24 according to the high-speed differential signal DIF including display data, so as to drive the cholesteric liquid crystal display panel 24 to display the image.

[0092] Please refer to Figure 3 , Figure 3 This is a timing diagram of an embodiment of a timing controller receiving high-speed differential signals and low-speed serial signals. (See diagram below.) Figure 3 As shown, in this embodiment, the high-speed differential signal DIF includes, in chronological order, blanking periods BK and frame data FD, but is not limited thereto. The low-speed serial signal SER includes write instructions W and parameters PM, but is not limited thereto. As for... Figure 4This is a schematic diagram of a cholesterol liquid crystal display device that can perform horizontal line scanning from top to bottom and vertical line scanning from left to right to display the image IMG.

[0093] Please refer to Figure 5 , Figure 5 The timing diagram shows the low-speed serial signals received by the timing controller, including write commands and parameters. For example... Figure 5 As shown, the low-speed serial signal SER includes the write instruction CMD during time t0 to t1 and the parameter PM during time t1 to tn. The parameter PM may also include a first parameter PM1 during time t1 to t2, a second parameter PM2 during time t2 to t3, ..., and a (n-1)th parameter PM(n-1) during time t(n-1) to tn. Controlled by the clock signal SCLK, the duration of each of the time periods t0 to t1, t1 to t2, ..., and t(n-1) to tn is eight units from 0 to 7, but is not limited to this.

[0094] Please refer to the following respectively Figures 6 to 8 .like Figure 6 As shown, when the cholesterol liquid crystal display device is in Reset mode, the Start line index (SLI) is the horizontal line at the top of the cholesterol liquid crystal display panel. That is, the total number of scan lines in Reset mode is counted from the top horizontal line of the cholesterol liquid crystal display panel to the bottom horizontal line.

[0095] like Figure 7 As shown, when the cholesterol liquid crystal display device performs a horizontal scan display from top to bottom, the starting line index SLI is the horizontal line at the top of the display area (white) of the cholesterol liquid crystal display panel. That is, the total number of scan lines during the horizontal scan display is counted from the top horizontal line of the display area (white) to the bottom horizontal line of the display area (white).

[0096] like Figure 8 As shown, when the cholesterol liquid crystal display device performs a vertical scan display from left to right, the starting line index SLI is the horizontal line at the far left of the display area (white) of the cholesterol liquid crystal display panel. That is, the total number of scan lines during the vertical scan display is counted from the leftmost vertical line of the display area (white) to the rightmost vertical line of the display area (white).

[0097] Please refer to Figure 9 , Figure 9 This is a timing diagram showing a horizontal scan of a high-speed differential signal from top to bottom. (Example:) Figure 9As shown, the high-speed differential signal DIF includes blanking periods BK and frame data FD in time sequence. That is, the high-speed differential signal DIF is blanking period BK during time t0 to t1, time t2 to t3, time t4 to t5, ..., time t12 to t13, and time t14 to t15, and is frame data FD during time t1 to t2, time t3 to t4, time t5 to t6, ..., time t11 to t12, and time t13 to t14, but is not limited to these.

[0098] The SPI (Sequence Peripheral Interface) signal transmits the write command W during time t1 to t2 and the read command R after time t15. The receiver unit RX detects the valid display data strobe signal (DE) and the vertical synchronization signal (VSYN) during the detection period DET (i.e., the blank periods BK such as time t2 to t3, time t4 to t5, ..., time t12 to t13, time t14 to t15).

[0099] When the receiving unit RX ends the detection period DET at time t3, the control signal CTL is set to a write command W, executing a write operation to the SRAM0 memory area of ​​the line buffer, followed by a write operation to the SRAM1 memory area of ​​the line buffer. After the write operation to SRAM0 is completed, the control signal CTL is set to a read command R, executing a read operation to SRAM0. After the read operation to SRAM0 is completed, the control signal CTL is set to a read command R, executing a read operation to SRAM1.

[0100] During the reading of SRAM1, the control signal CTL changes to a write instruction W again, executing the write operation to SRAM0. After the reading operation of SRAM1 is completed, the control signal CTL changes to a read instruction R, executing the read operation to SRAM0. The rest follow the same logic and will not be elaborated further here. After the writing operation of SRAM1 is completed, the transfer unit TX begins generating data and timing signals until the signal INT changes from a low level to a high level.

[0101] Please refer to Figures 10A to 11D . Figure 10A This is a schematic diagram of a cholesterol liquid crystal display device in reset mode. Figures 10B to 10D These are schematic diagrams illustrating the horizontal scanning display of a cholesterol liquid crystal display device from top to bottom until completion. Figure 11A This is a schematic diagram of a cholesterol liquid crystal display device in reset mode. Figures 11B to 11DThese are schematic diagrams illustrating the horizontal scanning display of a cholesterol liquid crystal display device from bottom to top until completion.

[0102] Please refer to Figure 12 , Figure 12 This is a timing diagram showing a vertical scan of a high-speed differential signal from left to right. (Example:) Figure 12 As shown, the high-speed differential signal DIF consists of blanking periods BK and frame data FD in time sequence. That is, the high-speed differential signal DIF is blanking period BK during time t0 to t1, time t2 to t3, time t4 to t5, ..., time t12 to t13, and time t14 to t15, and is frame data FD during time t1 to t2, time t3 to t4, time t5 to t6, ..., time t11 to t12, time t13 to t14, and time t15 to t16, but this is not a limitation.

[0103] The SPI (Sequence Peripheral Interface) signal transmits the write command W during time t1 to t2 and the read command R after time t16. The receiver unit RX detects the valid display data strobe signal (DE) and the vertical synchronization signal (VSYN) during the detection period DET (i.e., the blank periods BK such as time t2 to t3, time t4 to t5, ..., time t12 to t13, time t14 to t15).

[0104] When the receiving unit RX ends the detection period DET at time t3, the control signal CTL issues write instructions W(VL B0) and W(VLB1) to the storage areas SRAM0 and SRAM1 of the line buffer respectively during time t3 to t4 (i.e., during frame data FD). Simultaneously, it writes block B0 of the vertical line VL to storage area SRAM0 and block B1 of the vertical line VL to storage area SRAM1. When the write operation of storage area SRAM0 ends (i.e., time t4), the control signal CTL issues a read instruction R(VLB0), starting the reading of block B0 of the vertical line VL from storage area SRAM0 until time t6. When the read operation of storage area SRAM0 ends (i.e., time t6), the control signal CTL issues a read instruction R(VL B1), starting the reading of block B1 of the vertical line VL from storage area SRAM1 until time t8.

[0105] When the receiving unit RX ends the detection period DET at time t7, the control signal CTL issues a write instruction W (VL B2) to the storage area SRAM0 of the line buffer between time t7 and t8, writing block B2 of the vertical line VL to storage area SRAM0 to replace the originally stored block B0 of the vertical line VL. When the write operation of storage area SRAM0 ends (i.e., at time t8), the control signal CTL changes to a read instruction R (VL B2) to storage area SRAM0 of the line buffer, starting to read block B2 of the vertical line VL from storage area SRAM0 until time t10.

[0106] When the receiving unit RX ends the detection period DET at time t9, the control signal CTL issues a write instruction W (VL B3) to the SRAM1 storage area of ​​the line buffer between time t9 and t10, writing block B3 of the vertical line VL to SRAM1 to replace the originally stored block B1 of the vertical line VL. When the write operation of SRAM1 ends (i.e., at time t10), the control signal CTL changes to a read instruction R (VL B3) to SRAM1, starting to read block B3 of the vertical line VL from SRAM1 until time t12. The rest can be deduced in the same way, and will not be elaborated further here. The transmitting unit TX will start generating data and timing signals from time t4 to t5 until the signal INT changes from the original low level to the high level.

[0107] Please refer to Figures 13A to 14D . Figures 13A to 13D These are schematic diagrams illustrating the vertical scanning display of a cholesterol liquid crystal display device from left to right until completion. Figures 14A to 14D These are schematic diagrams illustrating the vertical scanning display of a cholesterol liquid crystal display device from right to left until completion.

[0108] Please refer to Figure 15 , Figure 15 This is a timing diagram for arbitrary scanning and display of the high-speed differential signal DIF. For example... Figure 15 As shown, the high-speed differential signal DIF consists of blanking periods BK and frame data FD in chronological order. That is, the high-speed differential signal DIF is blanking period BK during time t0 to t1, time t2 to t3, time t4 to t5, ..., time t12 to t13, and time t14 to t15, and is frame data FD during time t1 to t2, time t3 to t4, time t5 to t6, ..., time t11 to t12, time t13 to t14, and time t15 to t16, but this is not a limitation.

[0109] The SPI (Sequence Peripheral Interface) signal transmits the write command W during time t1 to t2 and the read command R after time t16. The receiver unit RX detects the valid display data strobe signal (DE) and the vertical synchronization signal (VSYN) during the detection period DET (i.e., the blank periods BK such as time t2 to t3, time t4 to t5, ..., time t12 to t13, time t14 to t15).

[0110] The receiving unit RX performs detection during time t2 to t3. When the receiving unit RX ends the detection period DET at time t3, the control signal CTL is a write instruction W(p,n0) to write n0 lines of data from p lines of data into the storage area SRAM0 of the line buffer during time t3 to t4 (i.e., during frame data FD), and a corresponding scan signal is generated at the transmitting unit TX. When the write operation of storage area SRAM0 ends (i.e., time t4), the control signal CTL changes to a read instruction R to read n0 lines of data from storage area SRAM0, until time t6.

[0111] The receiving unit RX performs detection during time t4 to t5. When the receiving unit RX ends the detection period DET at time t5, the control signal CTL is a write instruction W(p-n0,n1) to write n1 lines of data from (p-n0) lines of data into the storage area SRAM1 of the line buffer during time t5 to t6 (i.e., during frame data FD), and a corresponding scan signal is generated at the transmitting unit TX. When the write operation of storage area SRAM1 ends (i.e., time t6), the control signal CTL changes to a read instruction R to read n1 lines of data from storage area SRAM1, until time t8.

[0112] The receiving unit RX performs detection during time t6 to t7. When the receiving unit RX ends the detection period DET at time t7, the control signal CTL is a write instruction W(p-n0-n1,n2) to write n2 lines of data from (p-n0-n1) lines of data into the storage area SRAM0 of the line buffer during time t7 to t8 (i.e., during frame data FD), and a corresponding scan signal is generated at the transmitting unit TX. When the write operation of storage area SRAM0 ends (i.e., time t8), the control signal CTL changes to a read instruction R to read n2 lines of data from storage area SRAM0, until time t10.

[0113] The receiving unit RX performs detection during time t7 to t8. When the receiving unit RX ends the detection period DET at time t8, the control signal CTL, during time t8 to t9 (i.e., during frame data FD), is a write instruction W(p-n0-n1-n2,n3) to write n3 lines of data from (p-n0-n1-n2) lines of data into the storage area SRAM0 of the line buffer, and a corresponding scan signal is generated at the transmitting unit TX. When the write operation of storage area SRAM1 ends (i.e., time t9), the control signal CTL changes to a read instruction R to read n3 lines of data from storage area SRAM1, until time t12. Here, p, n0, n1, n2, and n3 are all positive integers, and p is greater than n0, n1, n2, and n3. The rest can be deduced by analogy and will not be elaborated further here.

[0114] Please refer to Figure 16 , Figure 16 This is a timing diagram showing a horizontal scan of a low-speed serial signal from top to bottom. (Example:) Figure 16 As shown, the low-speed serial signal SER is the write command W during time t0 to t1, data DL0 during time t1 to t2, the write command W again during time t3 to t4, data DL1 during time t4 to t5, the read command R during time t6 to t7, the write command W again during time t8 to t9, data DL2 during time t9 to t10, the read command R again during time t11 to t12, the write command W again during time t13 to t14, and data DL3 during time t14 to t15. The rest can be deduced similarly and will not be elaborated further here.

[0115] During time t1 to t2, the control signal CTL issues a write instruction W(DL0) to the SRAM0 storage area of ​​the line buffer, writing data DL0 to SRAM0. At time t2, the control signal CTL changes to a read instruction R(DL0) for SRAM0, starting to read data DL0 from SRAM0. During time t4 to t5, the control signal CTL issues a write instruction W(DL1) to the SRAM1 storage area of ​​the line buffer, writing data DL1 to SRAM1. When the read operation of SRAM0 ends, the control signal CTL changes to a read instruction R(DL1) for SRAM1, starting to read data DL1 from SRAM1 until time t10.

[0116] During time t9 to t10, the control signal CTL issues a write instruction W(DL2) to the storage area SRAM0 of the line buffer, writing data DL2 to SRAM0 to replace the previously stored data DL0. After the write operation is completed, the control signal CTL changes to a read instruction R(DL2) for SRAM0, starting to read data DL2 from SRAM0. The rest can be deduced similarly and will not be elaborated further here.

[0117] After time t2, the transmitting unit TX will begin transmitting data DL0 and timing signals until signal INT changes from a low level to a high level. At time t6, the transmitting unit TX will begin transmitting data DL1 and timing signals until signal INT changes from a low level to a high level. At time t11, the transmitting unit TX will begin transmitting data DL2 and timing signals until signal INT changes from a low level to a high level. The rest can be deduced similarly and will not be elaborated further here.

[0118] Please refer to Figure 17 , Figure 17 This is a timing diagram for displaying an arbitrary horizontal scan of a low-speed serial signal. For example... Figure 17 As shown, the low-speed serial signal SER is the write command W during time t0 to t1, data DLa during time t1 to t2, the write command W again during time t3 to t4, data DLb during time t4 to t5, the read command R during time t6 to t7, the write command W again during time t8 to t9, data DLc during time t9 to t10, the read command R again during time t11 to t12, the write command W again during time t13 to t14, and data DLd during time t14 to t15. The rest can be deduced similarly and will not be elaborated further here.

[0119] During time t1 to t2, the control signal CTL issues a write instruction W(DLa) to SRAM0 of the line buffer, writing data DLa to SRAM0. At time t2, the control signal CTL changes to a read instruction R(DLa) for SRAM0, starting to read data DLa from SRAM0. During time t4 to t5, the control signal CTL issues a write instruction W(DLb) to SRAM1 of the line buffer, writing data DLb to SRAM1. When the read operation of SRAM0 ends, the control signal CTL changes to a read instruction R(DLb) for SRAM1 of the line buffer, starting to read data DLb from SRAM1 until time t10.

[0120] During time t9 to t10, the control signal CTL issues a write instruction W(DLc) to the storage area SRAM0 of the line buffer, writing data DLc to SRAM0 to replace the previously stored data DLa. After the write operation is completed, the control signal CTL changes to a read instruction R(DLc) for SRAM0, starting to read data DLc from SRAM0. The rest can be deduced similarly and will not be elaborated further here.

[0121] After time t2, the transmitting unit TX will begin transmitting data DLa and timing signals until signal INT changes from a low level to a high level. At time t6, the transmitting unit TX will begin transmitting data DLb and timing signals until signal INT changes from a low level to a high level. At time t11, the transmitting unit TX will begin transmitting data DLc and timing signals until signal INT changes from a low level to a high level. The rest can be deduced similarly and will not be elaborated further here.

[0122] Please refer to Figure 18 , Figure 18 This is a timing diagram showing a low-speed serial signal displayed in a vertical scan from left to right. (Example:) Figure 18 As shown, the low-speed serial signal SER is the write instruction W during time t0 to t1, data DVL0 during time t1 to t2, the write instruction W again during time t3 to t4, data DVL1 during time t4 to t5, the read instruction R during time t6 to t7, the write instruction W during time t8 to t9, data DVL2 during time t9 to t10, the read instruction R again during time t11 to t12, the write instruction W during time t13 to t14, and data DVL3 during time t14 to t15. The rest can be deduced similarly and will not be elaborated further here.

[0123] During time t1 to t2, the control signal CTL issues a write instruction W (DVL0) to the SRAM0 storage area of ​​the line buffer, writing data DVL0 to SRAM0. At time t2, the control signal CTL changes to a read instruction R (DVL0) for SRAM0, starting to read data DVL0 from SRAM0. During time t4 to t5, the control signal CTL issues a write instruction W (DVL1) to the SRAM1 storage area of ​​the line buffer, writing data DVL1 to SRAM1. When the read operation of SRAM0 ends, the control signal CTL changes to a read instruction R (DVL1) for SRAM1, starting to read data DVL1 from SRAM1 until time t10.

[0124] During time t9 to t10, the control signal CTL issues a write instruction W (DVL2) to the storage area SRAM0 of the line buffer, writing data DVL2 into SRAM0 to replace the previously stored data DVL0. After the write operation is completed, the control signal CTL changes to a read instruction R (DVL2) for SRAM0, starting to read data DVL2 from SRAM0. The rest can be deduced similarly and will not be elaborated further here.

[0125] After time t2, the transmitting unit TX will begin transmitting data DVL0 and timing signals until signal INT changes from a low level to a high level. At time t6, the transmitting unit TX will begin transmitting data DVL1 and timing signals until signal INT changes from a low level to a high level. At time t11, the transmitting unit TX will begin transmitting data DVL2 and timing signals until signal INT changes from a low level to a high level. The rest can be deduced similarly and will not be elaborated further.

[0126] Please refer to Figure 19 , Figure 19 This is a timing diagram for displaying a low-speed serial signal using arbitrary vertical scanning. For example... Figure 19 As shown, the low-speed serial signal SER is the write command W during time t0 to t1, the data DVLa during time t1 to t2, the write command W again during time t3 to t4, the data DVLb during time t4 to t5, the read command R during time t6 to t7, the write command W again during time t8 to t9, the data DVLc during time t9 to t10, the read command R again during time t11 to t12, the write command W again during time t13 to t14, and the data DVLd during time t14 to t15. The rest can be deduced similarly and will not be elaborated further here.

[0127] During time t1 to t2, the control signal CTL issues a write instruction W (DVLa) to SRAM0 of the line buffer, writing data DVLa to SRAM0. At time t2, the control signal CTL changes to a read instruction R (DVLa) for SRAM0, starting to read data DVLa from SRAM0. During time t4 to t5, the control signal CTL issues a write instruction W (DVLb) to SRAM1 of the line buffer, writing data DVLb to SRAM1. When the read operation of SRAM0 ends, the control signal CTL changes to a read instruction R (DVLb) for SRAM1 of the line buffer, starting to read data DVLb from SRAM1 until time t10.

[0128] During time t9 to t10, the control signal CTL issues a write instruction W (DVLc) to the storage area SRAM0 of the line buffer, writing data DVLc to SRAM0 to replace the previously stored data DVLa. After the write operation is completed, the control signal CTL changes to a read instruction R (DVLc) for SRAM0, starting to read data DVLc from SRAM0. The rest can be deduced similarly and will not be elaborated further here.

[0129] After time t2, the transmitting unit TX will begin transmitting data DVLa and timing signals until signal INT changes from a low level to a high level. At time t6, the transmitting unit TX will begin transmitting data DVLb and timing signals until signal INT changes from a low level to a high level. At time t11, the transmitting unit TX will begin transmitting data DVLc and timing signals until signal INT changes from a low level to a high level. The rest can be deduced similarly and will not be elaborated further.

[0130] Compared to existing technologies, the timing controller disclosed in this invention, applied to a cholesterol liquid crystal display device, achieves substantial benefits such as reducing chip area and pin count, lowering power consumption and cost by replacing the traditional external frame buffer with an internal line buffer through its handshake control with the host.

Claims

1. A timing controller applied to a cholesterol-based liquid crystal display device, characterized in that, The timing controller includes: A receiver unit for receiving a high-speed differential signal; A transmitting unit, coupled to the receiving unit, is used to output the high-speed differential signal; A control unit, coupled between the receiving unit and the transmitting unit, is used to generate a control signal according to the handshake control between the timing controller and a host. A one-line buffer, coupled to the control unit, is used to perform horizontal / vertical line scanning according to the control signal; and Another receiving unit is a low-speed serial signal receiver, used to receive a low-speed serial signal from a host, and the low-speed serial signal includes a write command, a read command and a handshake control information between the timing controller and the host. The control unit generates the control signal to the line buffer according to the handshake control information in the low-speed serial signal. Specifically, when the timing controller performs arbitrary scanning display on the high-speed differential signal, during a first period, the control signal is a write instruction to take n0 lines of data from p lines and write them into a first storage area of ​​the line buffer; during a second period, the control signal is a write instruction to take n1 lines of data from (p-n0) lines and write them into a second storage area of ​​the line buffer; during a third period, the control signal is a write instruction to take n2 lines of data from (p-n0-n1) lines and write them into the first storage area of ​​the line buffer; and during a fourth period, the control signal is a write instruction to take n3 lines of data from (p-n0-n1-n2) lines and write them into the second storage area of ​​the line buffer, where p, n0, n1, n2, and n3 are all positive integers and p is greater than n0, n1, n2, and n3. The first period, the second period, the third period, and the fourth period are different frame data periods.

2. The timing controller as described in claim 1, characterized in that, The cholesterol liquid crystal display device also includes: A line drive device, coupled to the timing controller, is used to provide a line drive signal based on the high-speed differential signal; A train drive unit, coupled to the timing controller, is used to provide a train drive signal based on the high-speed differential signal; and A cholesterol-based liquid crystal display panel is coupled to the row drive device and the column drive device respectively, and is used to display the image by being driven by the row drive signal and the column drive signal.

3. The timing controller as described in claim 2, characterized in that, The horizontal line scan includes sequentially scanning the cholesterol liquid crystal display panel with the high-speed differential signal from top to bottom or bottom to top.

4. The timing controller as described in claim 2, characterized in that, The vertical line scan includes sequentially scanning the cholesterol liquid crystal display panel with the high-speed differential signal from left to right or from right to left.

5. The timing controller as described in claim 1, characterized in that, The receiving unit and the transmitting unit are respectively a high-speed differential signal receiver and a high-speed differential signal transmitter.

6. The timing controller as described in claim 1, characterized in that, This high-speed differential signal includes the displayed data.

7. The timing controller as described in claim 1, characterized in that, The horizontal line scan includes a low-speed serial signal line scan of the cholesterol liquid crystal display panel sequentially from top to bottom or bottom to top.

8. The timing controller as described in claim 1, characterized in that, The vertical line scan includes a low-speed serial signal line scan of the cholesterol liquid crystal display panel sequentially from left to right or from right to left.

9. The timing controller as described in claim 1, characterized in that, This line buffer is a static random access memory.

10. The timing controller as claimed in claim 1, characterized in that, This cholesterol-based liquid crystal display device eliminates the need for a frame buffer, thereby reducing power consumption and cost.

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