Display device

Abstract

A display device is disclosed. The display device according to an example embodiment of the present disclosure can include a display panel including a plurality of pixels in an active area of the display panel and at least one common electrode overlapping at least a portion of the plurality of pixels; a gate driver configured to provide a gate signal to the plurality of pixels; a source driving integrated circuit configured to provide a data signal to the plurality of pixels and configured to provide a common voltage to the common electrode; a noise compensator circuit configured to receive a plurality of sensing signals from a plurality of sensing lines connected to at least one of the display panel, the gate driver, or the source driving integrated circuit, to generate a plurality of inverted sensing signals by applying different gain values for signals obtained by inverting a phase of each of the plurality of sensing signals, and to generate a noise compensation signal based on at least one of the plurality of inverted sensing signals.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10-2023-0012955, filed in Korea on January 31, 2023, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device. Background Technology

[0004] As society evolves towards an information-driven society, the field of display devices is rapidly developing. Accordingly, various display devices with superior performance in terms of thinness, weight reduction, and low power consumption are being developed. Examples of such display devices include liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs).

[0005] The display device may include: a display panel having pixels thereon for displaying images; a data driver for providing data signals to data lines disposed on the display panel; a gate driver for sequentially providing gate signals to gate lines disposed on the display panel; and a drive circuit, such as a timing controller, for controlling the data driver and the gate driver. Furthermore, the display device may include touch electrodes for detecting user input (e.g., touch), and the display device can detect touch points by sensing changes in capacitance formed on the touch electrodes.

[0006] In electronic devices such as display devices, performance defects may occur due to electromagnetic interference (EMI). Summary of the Invention

[0007] One aspect of this disclosure is to provide a display device capable of reducing electromagnetic interference (EMI) levels.

[0008] The purpose of this disclosure is not limited to the purposes mentioned above, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0009] A display device according to an example embodiment of the present disclosure may include: a display panel including a plurality of pixels in an effective area of ​​the display panel and at least one common electrode overlapping at least a portion of the plurality of pixels; a gate driver configured to provide gate signals to the plurality of pixels; a source driver integrated circuit configured to provide data signals to the plurality of pixels and to provide a common voltage to the common electrode; and a noise compensation circuit configured to: receive a plurality of sensing signals from a plurality of sensing lines connected to at least one of the display panel, the gate driver, or the source driver integrated circuit; generate a plurality of inverted sensing signals by applying different gain values ​​for signals obtained by inverting the phase of each of the plurality of sensing signals; and generate a noise compensation signal based on at least one of the plurality of inverted sensing signals.

[0010] Further details of the exemplary implementation are included in the detailed implementation and the accompanying drawings.

[0011] A display device according to an exemplary embodiment of this disclosure can sense noise generated according to each noise generation cause (e.g., pixel, gate driver, and / or multiplexer) by using multiple sensing lines, and can generate a noise compensation signal to cancel the noise by applying different gain values ​​to the noise. Therefore, the level of electromagnetic interference can be reduced more effectively.

[0012] The effects of this disclosure are not limited to those exemplified above, and include a variety of other effects as described in this specification. Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0014] Figure 2 It is shown in Figure 1 A diagram illustrating an example of the structure of touch electrodes disposed in the sensing area of ​​a display device.

[0015] Figure 3 It is used for explanation Figure 1 A timing diagram showing examples of display driving periods and touch driving periods for a display device.

[0016] Figure 4A It is shown Figure 1 A plan view of an example display panel included in a display device.

[0017] Figure 4B It is shown Figure 1 A plan view of an example display panel included in a display device.

[0018] Figure 5 It is shown Figure 1 A block diagram of an example source driver integrated circuit included in a display device.

[0019] Figure 6A and Figure 6B This is a diagram used to illustrate electromagnetic interference (EMI) generated in a display device.

[0020] Figure 7 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0021] Figure 8 It is used to explain in Figure 7 A timing diagram of examples of signals provided during the display driving period and touch driving period of a display device.

[0022] Figure 9 It is shown Figure 7 A diagram showing an example of a gate driver included in a display device.

[0023] Figure 10 It shows along Figure 9 The example cross-sectional view obtained by line II′ is shown.

[0024] Figure 11 It shows along Figure 9 The example cross-sectional view obtained by line II-II′ is shown.

[0025] Figure 12 It is shown Figure 7 A block diagram of an example noise compensator included in a display device.

[0026] Figure 13 It is shown Figure 12 A circuit diagram of an example of an inverting circuit included in a noise compensator.

[0027] Figure 14 It is used for explanation Figure 12 A timing diagram illustrating an example of the operation of a noise compensator.

[0028] Figure 15 This is a diagram illustrating the level of electromagnetic interference in a display device according to an exemplary embodiment of the present disclosure.

[0029] Figure 16 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0030] Figure 17 It is shown Figure 16 A block diagram of an example noise compensator included in a display device.

[0031] Figure 18This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0032] Figure 19 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0033] Figure 20 It is shown Figure 19 A diagram showing an example of a multiplexer included in a display device.

[0034] Figure 21 It shows along Figure 20 The example cross-sectional view obtained by line III-III′ is shown.

[0035] Figure 22 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0036] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure. Therefore, this disclosure is limited only by the scope of the appended claims.

[0037] The shapes, dimensions, scales, angles, numbers, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, similar reference numerals generally denote similar elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0038] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0039] When using terms such as “above,” “over,” “below,” and “beside” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless the term is used with the terms “immediately adjacent” or “directly.”

[0040] When one element or layer is placed "on" another element or layer, the other layer or element can be placed directly on or between the other elements.

[0041] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from others. Therefore, the first component mentioned below can be a second component in the technical concept of this disclosure.

[0042] Throughout the specification, similar reference numerals generally denote similar elements.

[0043] The dimensions and thicknesses of each component shown in the accompanying drawings are for ease of description, and this disclosure is not limited to the dimensions and thicknesses of the components shown.

[0044] Features of various embodiments of this disclosure may be added to or combined with each other in part or in whole, and may be technically interlocked and operated in various ways. The embodiments may be performed independently of each other or in relation to each other.

[0045] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0047] Reference Figure 1 The display device 1000 according to an exemplary embodiment of the present disclosure may include a display panel 100, a gate driver 200, a data driver 300, a timing controller 400, and a touch driver 500.

[0048] The display panel 100 (or display unit or pixel unit) may include an effective area for displaying images and an ineffective area other than the effective area.

[0049] Pixels PX for displaying images can be provided in the effective area of ​​the display panel 100. Furthermore, multiple gate lines GL and multiple data lines DL can be provided in the effective area of ​​the display panel 100. Gate lines GL can be configured in one direction (e.g., a first direction DR1, see...). Figure 4A On the data line DL, it can be set in a direction different from the first direction (e.g., a second direction DR2, see...). Figure 4A )superior.

[0050] Each pixel PX can be connected to a corresponding gate line in gate line GL and a corresponding data line in data line DL. Therefore, gate signals and data signals can be applied to each pixel PX through the gate lines and data lines. Furthermore, each pixel PX can realize a grayscale level through the applied gate signals and data signals, and ultimately, an image can be displayed in the effective area of ​​the display panel 100 through the grayscale level displayed by each pixel PX.

[0051] Power lines, gate drivers 200, and various signal lines can be provided in the non-active areas of the display panel 100, through which signals for controlling the operation of pixels PX located in the active areas are transmitted.

[0052] In an exemplary embodiment, the display panel 100 may include a sensing area for sensing user touches, etc., and a non-sensing area other than the sensing area. That is, the display panel 100 may also be used as a touch panel. In other words, the touch panel may be implemented as an embedded touch method (e.g., Advanced Embedded Touch (AIT) method) embedded in the pixel array area of ​​the display panel 100. In the embedded touch method, the display device 1000 (e.g., touch driver 500) can sense user touches, etc., by using electrodes formed in the shape of blocks (or dots) inside the display panel 100 as touch electrodes.

[0053] Multiple touch electrodes for sensing user touches, etc., can be provided in the sensing area of ​​the display panel 100. According to an embodiment, the sensing area may correspond to the effective area. For example, the sensing area may have substantially the same area as the effective area and may be located at the same position as the effective area. In this case, the non-sensing area may correspond to the non-effective area. However, this is merely an example, and the sensing area and the effective area may have different areas or may be located at different positions.

[0054] The timing controller 400 (or timing control circuit) can receive the input image signal DATA1 and the input control signal CS from an external source (e.g., the main system).

[0055] The timing controller 400 can generate image data DATA2 corresponding to the operating conditions of pixel PX based on the input image signal DATA1, and provide the generated image data DATA2 to the data driver 300.

[0056] The timing controller 400 can generate control signals for controlling the gate driver 200 and the data driver 300 based on the input control signal CS. For example, the input control signal CS may include timing signals such as a clock signal, a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal. Here, the horizontal synchronization signal is a signal indicating the time taken to display a horizontal line on the screen, the vertical synchronization signal is a signal indicating the time taken to display one frame on the screen, and the data enable signal may correspond to a signal used to indicate the time period for providing data signals to the pixel PX.

[0057] The timing controller 400 can use the timing signal included in the input control signal CS to generate a gate control signal GCS for controlling the operating timing of the gate driver 200, and provide the generated gate control signal GCS to the gate driver 200.

[0058] In addition, the timing controller 400 can use the timing signal included in the input control signal CS to generate a data control signal DCS for controlling the operating timing of the data driver 300, and provide the generated data control signal DCS to the data driver 300.

[0059] Gate driver 200 (or gate drive circuit, scan driver, or scan drive circuit) can receive gate control signal GCS from timing controller 400 and sequentially provide gate signals to gate line GL in response to gate control signal GCS. For this purpose, each gate driver 200 may include a shift register, level shifter, etc. Gate signal GCS may include a gate start signal for generating gate signals, and multiple clock signals.

[0060] The data driver 300 (or data driving circuit) can receive a data control signal DCS from the timing controller 400 and, in response to the data control signal DCS, convert the image data DATA2 into an analog data signal (e.g., data voltage). The data driver 300 can output the data signal to the data line DL and provide the data signal to the pixel PX.

[0061] The touch driver 500 can detect the presence and location of a user's touch by using multiple touch lines TL connected to multiple touch electrodes disposed on the display panel 100. For example, when a user touches a portion of the sensing area of ​​the display panel 100, the touch driver 500 can sense the touch signal of the touch electrodes disposed on the display panel 100 via the touch lines TL, and detect the presence and location of the user's touch.

[0062] More specifically, the touch driver 500 can provide touch driving signals to touch electrodes disposed on the display panel 100 and receive touch sensing signals from the touch electrodes. The touch driver 500 can use the applied touch sensing signals to detect whether a user's touch is present and the touch location. For example, the touch driver 500 can determine whether a user's touch is present and the touch location by using a mutual capacitance method that utilizes the mutual capacitance change of the touch electrodes or a self-capacitance method that utilizes the self-capacitance change of the touch electrodes.

[0063] At the same time, Figure 1 In this illustration, the data driver 300 and the touch driver 500 are shown as separate components, but this is for ease of explanation, and embodiments of this disclosure are not limited thereto. For example, the data driver 300 and the touch driver 500 may be configured as a single integrated circuit (e.g., Figure 4A Source driver integrated circuit (SiC).

[0064] Meanwhile, examples of the display device 1000 according to exemplary embodiments of the present disclosure may include various types of display devices, such as liquid crystal display devices, organic light-emitting display devices, plasma display devices, quantum dot display devices, etc.

[0065] For example, when the display device 1000 according to an exemplary embodiment of the present disclosure is a liquid crystal display device, the display panel 100 may include a liquid crystal layer formed between two substrates (e.g., an upper substrate and a lower substrate), and the display panel 100 may operate in any known mode, such as twisted nematic (TN) mode, vertical alignment (VA) mode, in-plane switching (IPS) mode, or edge field switching (FFS) mode.

[0066] A black matrix, color filters, etc., can be formed on the upper substrate of the display panel 100, and thin-film transistors, pixels (PXs), etc., can be formed on the lower substrate of the display panel 100. The display panel 100 can be implemented using a color filter on a TFT (COT) structure. In this case, the black matrix and color filter can be formed on the lower substrate of the display panel 100.

[0067] Furthermore, a common electrode can be formed on the upper or lower substrate of the display panel 100, and a common voltage can be provided to the common electrode. A polarizer can be attached to the upper and lower substrates of the display panel 100, and an alignment layer for setting the tilt angle of the liquid crystal can be formed on the inner surface of the alignment layer that contacts the liquid crystal.

[0068] A columnar spacer for maintaining the cell gap of the liquid crystal cells can be formed between the upper substrate and the lower substrate of the display panel 100. In the case of a liquid crystal display device, a backlight unit is provided below the rear surface of the lower polarizer of the display panel 100, and the backlight unit can be implemented as an edge type or a direct type.

[0069] Here, in the liquid crystal display device, the plurality of touch electrodes disposed on the display panel 100 for sensing user touch can be common electrodes to which a common voltage for display driving is applied.

[0070] In an exemplary embodiment, the common voltage applied to the common electrode (touch electrode) can be provided from the touch driver 500 via the touch line TL.

[0071] As another example, when the display device 1000 according to an exemplary embodiment of the present disclosure is an organic light-emitting display device, it may include: a first electrode (anode electrode) constituting an organic light-emitting diode (OLED), an organic light-emitting layer and a second electrode (cathode electrode); an encapsulation layer having a sealing function; and a touch sensor metal layer.

[0072] Here, in the organic light-emitting display device, multiple touch electrodes disposed on the display panel 100 for sensing user touch, etc., can be formed on the touch sensor metal layer and can be formed on the second electrode layer constituting the cathode electrode of the organic light-emitting diode.

[0073] Meanwhile, the common voltage applied to the common electrode or touch electrode can be set to the following direct current (DC) voltage: when the level of the data signal supplied to the display panel 100 changes during the driving period of the display device 1000, this DC voltage is applied at a specific voltage level for a certain period of time. Furthermore, depending on the type of display device (e.g., a liquid crystal display device or an organic light-emitting display device), the common voltage applied to the common electrode or touch electrode can be referred to as the display voltage or other names.

[0074] Meanwhile, as noise that may occur within the display device 1000, there may be electromagnetic waves generated by the pixels PX of the display panel 100, electromagnetic waves generated by the gate driver 200, and / or electromagnetic waves generated by the aforementioned source driver integrated circuit (e.g., a multiplexer included in the source driver integrated circuit). As described above, due to the influence of noise that may occur within the display device 1000 (i.e., electromagnetic interference (EMI)), the system stability of the display device 1000 may decrease. In this case, the touch sensing signal (voltage) obtained when the display device 1000 senses touch input may be affected, which may cause a decrease in the touch sensing performance of the display device 1000; or other signals (voltages) required for the display device 1000 to display an image may also be affected, which may cause a decrease in display performance.

[0075] Therefore, the display device 1000 according to the exemplary embodiment of this disclosure can sense electromagnetic waves that may be noise within the display device 1000, and generate a noise compensation signal NCS (see [link to NCS]) based on the sensing. Figure 7 For example, the display device 1000 can sense electromagnetic waves generated by the pixels PX of the display panel 100, electromagnetic waves generated by the gate driver 200, and / or electromagnetic waves generated by the aforementioned source driver integrated circuit (e.g., a multiplexer included in the source driver integrated circuit). Furthermore, the display device 1000 can generate a noise compensation signal NCS (see [reference needed]) based on the sensing. Figure 7 ), and the noise compensation signal NCS (see Figure 7 The voltage generator VG (see) provides the voltage to generate the common voltage. Figure 7 Therefore, the electromagnetic interference level of the display device 1000 can be reduced.

[0076] Therefore, in an exemplary embodiment, the display device 1000 may further include a noise compensator NCP (see Figure 7 (This will be referred to in the following text) Figure 7 To describe it in more detail.

[0077] Figure 2 It is shown in Figure 1 A diagram illustrating an example of the structure of touch electrodes disposed in the sensing area of ​​a display device.

[0078] Reference Figure 1 and Figure 2As described above, in the display device 1000 according to an exemplary embodiment of the present disclosure, the touch panel can be implemented as being embedded in the pixel array region of the display panel 100 using an embedded touch method (e.g., an advanced embedded touch (AIT) method). In the embedded touch method, the touch driver 500 can sense user touches by using common electrodes CE arranged in the shape of blocks or dots inside the display panel 100 as touch electrodes TE1, TE2, TE3, and TE4.

[0079] For example, in an embedded touch method, in the display panel 100, a common electrode CE corresponding to at least some of the pixels among a plurality of pixels PX formed within the display panel 100 forms one of touch electrodes TE1, TE2, TE3, and TE4. That is, each touch electrode TE1, TE2, TE3, and TE4 can be defined by a common electrode CE formed separately in the display panel 100. Here, each of the touch electrodes TE1, TE2, TE3, and TE4 corresponding to the common electrode CE formed separately in the display panel 100 can form a common electrode segment. This common electrode segment is commonly connected to the plurality of pixels PX, such that a common voltage Vcom can be applied to the connected plurality of pixels PX.

[0080] Multiple touch electrodes TE1, TE2, TE3, and TE4 can be arranged linearly (i.e., in the first direction DR1 and the second direction DR2) within the sensing area (or effective area) of the display panel 100. For each of the touch electrodes TE1, TE2, TE3, and TE4, a touch drive signal TDS can be provided, and a touch line TL configured to receive touch sensing signals can be connected.

[0081] Each of the touch electrodes TE1, TE2, TE3, and TE4 can be implemented as a touch sensor that uses a capacitance-based touch sensing method to sense touch input. In this case, each of the touch electrodes TE1, TE2, TE3, and TE4 can provide a common voltage Vcom to its corresponding pixel PX during the display driving period and receive a touch driving signal TDS during the touch driving period.

[0082] At the same time, as referenced Figure 1 When the display device 1000 according to the exemplary embodiment of this disclosure is an organic light-emitting display device, the touch electrodes TE1, TE2, TE3, and TE4, defined by a common electrode CE formed separately in the display panel 100, can be configured as cathode electrodes of an organic light-emitting diode (in other words, Figure 2 The common electrode CE can constitute at least a portion of the cathode electrode of the organic light-emitting diode.

[0083] Figure 3 It is used for explanation Figure 1 A timing diagram showing examples of display driving periods and touch driving periods for a display device.

[0084] Reference Figures 1 to 3 According to an exemplary embodiment of the present disclosure, the display device 1000 can perform display driving to display an image during a display driving period DP defined within a frame time period, and can perform touch driving to sense touch input by the user during a touch driving period TP defined within a frame time period.

[0085] Therefore, the display device 1000 may also use the common electrode CE, which is used to drive the pixel PX, as an electrode for touch sensing. Thus, during the display driving period DP, a common voltage Vcom can be provided to the thin-film transistor connected to the common electrode CE, and during the touch driving period TP, a touch driving signal TDS can be provided to the common electrode CE, which operates as touch electrodes TE1, TE2, TE3, and TE4.

[0086] Display driving period (DP) and touch driving period (TP) can be the same or overlapping periods in time, or they can be separate periods in time.

[0087] Meanwhile, when the display driving period (DP) and touch driving period (TP) are separated in time, it can be called time-sharing driving. On the other hand, when the display driving period (DP) and touch driving period (TP) are the same in time, display driving and touch driving can be performed simultaneously, and this driving method can be called time-free driving.

[0088] In time-sharing mode, the display driving period (DP) and the touch driving period (TP) can be alternated.

[0089] In this way, when the display driving period DP and the touch driving period TP alternate and are separated in time, the touch driving period TP can correspond to a blank period when the display driving is not executed.

[0090] Simultaneously, the display device 1000 can generate a touch synchronization signal Tsync that oscillates between high and low levels, thereby identifying or controlling the display driving period DP and the touch driving period TP. In other words, the touch synchronization signal Tsync can be a timing control signal that defines the touch driving period TP.

[0091] For example, the high-level period (or low-level period) of the touch synchronization signal Tsync can correspond to the display driving period DP, while the low-level period (or high-level period) of the touch synchronization signal Tsync can correspond to the touch driving period TP.

[0092] In this configuration, the touch driver 500 can apply the touch drive signal TDS to the touch electrodes TE1, TE2, TE3 and TE4 during the touch drive period TP based on the touch synchronization signal Tsync, and use the touch sensing signals received from TE1, TE2, TE3 and TE4 to detect the presence and location of a touch.

[0093] Meanwhile, regarding the method of allocating a display driving period DP and a touch driving period TP within a display frame time period, a display frame time period is divided into a display driving period DP and a touch driving period TP. Display driving is performed during a display driving period DP, and touch driving for sensing user touch input can be performed during a touch driving period TP corresponding to a blank period.

[0094] In other words, the display device 1000 can be driven once for touch during the display frame period, and the display frame period is one cycle of the frame frequency or screen refresh rate of the display panel 100.

[0095] For example, when the frame rate is 60Hz, a touch driving period TP for touch sensing can be executed for a predetermined time interval after the display driving is executed within a 1 / 60-second (sec) time period. In this case, the touch report rate can correspond to 60Hz.

[0096] As another example, a display frame period is divided into two or more display drive periods (DP) and two or more touch drive periods (TP). Display drives can be performed during the two or more display drive periods (DP), and touch drives for sensing user touch input can be performed once, twice, or more times in the entire or a portion of the screen during the two or more touch drive periods (TP) within a single display frame period.

[0097] Figure 4A It is shown Figure 1 A plan view of an example display panel included in a display device.

[0098] Figure 4B It is shown Figure 1 A plan view of an example display panel included in a display device.

[0099] Figure 5 It is shown Figure 1 A block diagram of an example source driver integrated circuit included in a display device.

[0100] Reference Figure 1 , Figure 2 , Figure 3 and Figure 4AThe display panel 100 may include a substrate SUB (e.g., a lower substrate), multiple pixels PX, gate lines GL, data lines DL, power lines PL, gate control lines GCL, gate driver GIP, source driver integrated circuit SiC, and data connection lines DLL.

[0101] For reference Figure 1 The display panel 100 may include an effective area DA for displaying images and an ineffective area NDA. According to an exemplary embodiment, the effective area DA may correspond to a sensing area SA for sensing user touch input, and the ineffective area NDA may correspond to a non-sensing area NSA. However, embodiments of this disclosure are not limited to this; for example, a portion of the ineffective area NDA may correspond to the sensing area SA.

[0102] The effective area DA (or sensing area SA) can be parallel to the surface defined by a first directional axis (e.g., an axis extending in the first direction DR1) and a second directional axis (e.g., an axis extending in the second direction DR2). The normal direction of the display surface, i.e., the thickness direction of the display panel 100, can be defined as the third direction DR3.

[0103] The front (or upper) and rear (or lower) surfaces of each component or unit of the display device 1000 (or display panel 100) described below can be distinguished in a third direction DR3. However, the first directions DR1, DR2, and DR3 shown in this disclosure are merely exemplary, and are relative concepts that can be changed to other directions. Hereinafter, for ease of explanation, the same reference numerals will be used to refer to the first directions DR1, DR2, and DR3.

[0104] Furthermore, when “overlapping” is described in this disclosure, unless otherwise specified, it refers to two components overlapping in the thickness direction (i.e., third direction DR3) of the display device 1000 (or display panel 100).

[0105] At the same time, Figure 4A and Figure 4B In the illustration, the display panel 100 is shown to have a circular shape at the corner where a long side intersects a short side, but this is merely exemplary, and the shape of the display panel 100 is not limited thereto. For example, the display panel 100 may have an angular shape at the corner where a long side intersects a short side.

[0106] In an exemplary embodiment, the display panel 100 may include an effective area DA with a planar shape, but this disclosure is not limited thereto. For example, the display panel 100 may include a curved effective area or a three-dimensional effective area.

[0107] Multiple pixels PX can be disposed within the effective region DA. Each pixel PX can be connected to a corresponding gate line in gate line GL, a corresponding data line in data line DL, and a power line PL. According to an exemplary embodiment, each pixel PX may include a driving transistor, at least one switching transistor, a light-emitting element, and a storage capacitor.

[0108] The display panel 100 may include gate lines GL, data lines DL, and power lines PL.

[0109] In an exemplary embodiment, the gate line GL may extend in a first direction DR1, and the data line DL may extend in a second direction DR2. The power line PL may include at least one line extending in the first direction DR1, and a plurality of lines branching from at least one line in the first direction DR1.

[0110] In an exemplary embodiment, a source driver integrated circuit (SiC), a gate driver (GIP), a gate control line (GCL), and a data connection line (DLL) may also be disposed on the display panel 100. The source driver integrated circuit (SiC), the gate driver (GIP), the gate control line (GCL), and the data connection line (DLL) may be disposed in the non-active area NDA (or the non-sensing area NSA).

[0111] At the same time, despite Figure 4A The gate driver GIP is shown as being disposed in the inactive region NDA corresponding to one side of the active region DA, but this is merely exemplary, and embodiments of this disclosure are not limited thereto. For example, two gate driver GIPs may be disposed in the inactive regions NDA corresponding to both sides of the active region DA.

[0112] Simultaneously, the gate driver GIP can be compared with the reference. Figure 1 The gate driver 200 described is substantially the same as or similar to the gate driver 200.

[0113] The source driver integrated circuit (SIC) can provide data signals to the data line DL via the data connection line DLL. Furthermore, the source driver integrated circuit (SIC) can generate a gate control signal for controlling the gate driver GIP via the gate control line GCL, and provide the gate control signal to the gate driver GIP.

[0114] In an exemplary embodiment, the source driver integrated circuit SIC is configured as an integrated circuit (IC) and can be attached to the substrate SUB by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, an ultrasonic bonding method, or the like.

[0115] At the same time, as referenced Figure 1 The source driver integrated circuit SiC can be configured to include a reference. Figure 1 The data driver 300 and touch driver 500 are integrated circuits. That is, the source driver integrated circuit SIC can not only provide data signals to the data line DL through the data connection line DLL, but also provide the common voltage Vcom (or touch drive signal TDS) to the common electrode CE (or touch electrodes TE1, TE2, TE3 and TE4).

[0116] In an exemplary embodiment, the source driver integrated circuit (SIC) may include a multiplexer (MUX). For example, a touch driver 500 included in the source driver integrated circuit (SIC) may use the multiplexer (MUX) to selectively detect touch sensing signals, which have different sensing values ​​depending on whether a touch is present in the sensing area (SA). In this case, the power consumption of touch sensing can be reduced.

[0117] At the same time, this is merely an example, and the implementation of this disclosure is not limited thereto. For example, further reference... Figure 4B The source driver integrated circuit SiC_1 included in the display panel 100_1 may not include a multiplexer, such as Figure 4B As shown.

[0118] In an exemplary embodiment, as referred to Figures 1 to 3 The source driver integrated circuit SIC (e.g., touch driver 500) can provide a common voltage Vcom to a common electrode CE located in the active area DA (or sensing area SA) via the touch line TL.

[0119] For example, refer to Figure 5 The source driver integrated circuit SiC may also include a voltage generator VG. The voltage generator VG can provide a common voltage Vcom to the common electrode CE (or touch electrodes TE1, TE2, TE3 and TE4) via the touch line TL.

[0120] At the same time, as referenced Figure 1 As mentioned above, due to the influence of noise (i.e., electromagnetic interference (EMI)) that may occur within the display device 1000, the system stability of the display device 1000 may decrease, and the touch sensing performance and display performance of the display device 1000 may also decrease.

[0121] Therefore, a display device 1000 according to an exemplary embodiment of this disclosure (e.g., a noise compensator NCP, see...) Figure 7 A noise compensation signal (NCS) can be generated based on the sensed noise (e.g., electromagnetic waves). Figure 7 For example, the noise compensation signal NCS (see Figure 7The noise compensation signal (NCS) is generated by adjusting the inverse signal of the sensed noise into a single intensity, and the noise compensation signal (NCS) can be provided to the voltage generator (VG). Therefore, the electromagnetic interference level of the display device 1000 can be reduced.

[0122] Figure 6A and Figure 6B This is a diagram used to illustrate electromagnetic interference (EMI) generated in a display device.

[0123] Reference Figure 6A and Figure 6B Noise can be generated by various reasons in the display device.

[0124] For example, refer to Figure 6A and Figure 6B As a possible source of noise in a display device, electromagnetic waves generated by the pixels (PX) on the display panel may exist. Figure 6B (Illustrated as "EMI3"), electromagnetic waves generated by the gate driver GIP (in... Figure 6B (shown as "EMI1"), and / or electromagnetic waves generated by the multiplexer MUX included in the source-driven integrated circuit (in... Figure 6B (It is shown as "EMI2" in the image).

[0125] Here, as Figure 6B As shown, each type of noise is pulse-type, and depending on the cause of the noise (e.g., pixel PX, gate driver GIP, or multiplexer MUX), the noise can have a specific point in the effective area DA (or sensing area SA) (in Figure 6A and Figure 6B The different intensities of the noise are shown as "sensing point 1" and "sensing point 2". Therefore, it is necessary to generate a compensation signal to cancel out the noise by applying a different gain value (gain) to each type of noise.

[0126] Therefore, the display device 1000 according to an exemplary embodiment of this disclosure can sense noise generated from each of the pixel PX, gate driver GIP, and multiplexer MUX according to each cause of noise generation, and generate a noise compensation signal NCS for canceling noise by applying a different gain value to each type of noise (see Figure 7 In the following text, reference will be made to... Figures 7 to 22 This will be explained in more detail.

[0127] Figure 7 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0128] Figure 8 It is used to explain in Figure 7A timing diagram of examples of signals provided during the display driving period and touch driving period of a display device.

[0129] Figure 9 It is shown Figure 7 A diagram showing an example of a gate driver included in a display device.

[0130] Figure 10 It shows along Figure 9 The example cross-sectional view obtained by line II′ is shown.

[0131] Figure 11 It shows along Figure 9 The example cross-sectional view obtained by line II-II′ is shown.

[0132] Figure 12 It is shown Figure 7 A block diagram of an example noise compensator included in a display device.

[0133] Figure 13 It is shown Figure 12 A circuit diagram of an example of an inverting circuit included in a noise compensator.

[0134] Figure 14 It is used for explanation Figure 12 A timing diagram illustrating an example of the operation of a noise compensator.

[0135] Figure 15 This is a diagram illustrating the level of electromagnetic interference in a display device according to an exemplary embodiment of the present disclosure.

[0136] At the same time, Figure 7 The diagram shows only the minimum components related to the noise compensator NCP used to describe the configuration for generating the noise compensation signal NCS.

[0137] At the same time, to avoid redundant descriptions, in Figures 7 to 14 The text primarily describes the reference. Figures 1 to 6B For content that is not repeated, and for parts not specifically described, the same as the above-described embodiments. The same reference numerals indicate the same elements, and similar reference numerals indicate similar constituent elements.

[0138] Reference Figure 1 , Figure 2 , Figure 4A , Figure 5 and Figure 7 The display device 1000 according to an exemplary embodiment of the present disclosure may include a plurality of common electrodes CE, a gate driver GIP, a source driver integrated circuit SiC, and a noise compensator NCP disposed in the effective area DA (or sensing area SA) of the display panel 100.

[0139] Multiple common electrodes CE can be arranged linearly in the effective area DA (or sensing area SA) of the display panel 100. For example, the common electrodes CE can be arranged in a matrix in multiple rows R1 to Rn (where n is an integer greater than 0) and multiple columns C1 to Cm (where m is an integer greater than 0).

[0140] In an exemplary embodiment, at least a portion of the common electrode CE can be connected to the first switch SW1, and at least another portion of the common electrode CE can be connected to the second switch SW2. For example, each common electrode CE in the first row R1 of a plurality of rows R1 to Rn can be connected to the first switch SW1, and each common electrode CE in the nth row Rn can be connected to the second switch SW2.

[0141] At the same time, Figure 7 The illustration shows a common electrode CE in the first row R1 of a plurality of rows R1 to Rn connected to a first switch SW1, but embodiments of this disclosure are not limited thereto. For example, the common electrode CE in any row of the second row R2 to the nth row Rn can be connected to the first switch SW1. Furthermore, in the above example, when the common electrode CE in the nth row Rn of the plurality of rows R1 to Rn is connected to the first switch SW1, the common electrode CE in any row of the first row R1 to the (n-1)th row Rn-1 of the plurality of rows R1 to Rn can be connected to the second switch SW2.

[0142] Similarly, in Figure 7 The illustration shows a common electrode CE located in the nth row Rn of multiple rows R1 to Rn connected to a second switch SW2, but embodiments of this disclosure are not limited to this. For example, the common electrode CE located in any row of the first row R1 to the (n-1)th row Rn-1 can be connected to the second switch SW2. Furthermore, in the above example, when the common electrode CE located in the first row R1 of multiple rows R1 to Rn is connected to the second switch SW2, the common electrode CE located in any row of the second row R2 to the nth row Rn of multiple rows R1 to Rn can be connected to the first switch SW1.

[0143] At the same time, Figure 7The illustration shows a common electrode CE in one of the multiple rows R1 to Rn (i.e., the first row R1) connected to a first switch SW1, but embodiments of this disclosure are not limited to this. For example, the common electrode CE in at least two of the multiple rows R1 to Rn (including the nth row Rn) can be connected to the first switch SW1. Furthermore, in the above example, when the common electrode CE in at least two of the multiple rows R1 to Rn (including the nth row Rn) is connected to the first switch SW1, the common electrode CE in any row of the multiple rows R1 to Rn, other than the row with the common electrode CE connected to the first switch SW1, can be connected to a second switch SW2.

[0144] Similarly, in Figure 7 The illustration shows a common electrode CE in one of the multiple rows R1 to Rn (i.e., the nth row Rn) connected to a second switch SW2, but embodiments of this disclosure are not limited to this. For example, the common electrode CE in at least two of the multiple rows R1 to Rn (including the first row R1) can be connected to the second switch SW2. Furthermore, in the above example, when the common electrode CE in at least two of the multiple rows R1 to Rn (including the first row R1) is connected to the second switch SW2, the common electrode CE in any row of the multiple rows R1 to Rn, other than the row containing the common electrode CE connected to the second switch SW2, can be connected to the first switch SW1.

[0145] In an exemplary embodiment, each of the first switch SW1 and the second switch SW2 may be located in the active region DA (or sensing region SA). However, the exemplary embodiments of this disclosure are not limited thereto, and at least a portion of the first switch SW1 and the second switch SW2 may be located in the inactive region NDA (or non-sensing region NSA).

[0146] According to an exemplary embodiment, each of the first switch SW1 and the second switch SW2 can be connected to a common electrode CE disposed in a first region of the display panel 100 and a common electrode CE disposed in a second region of the display panel 100. More specifically, when the effective area DA of the display panel 100 is divided into an upper region and a lower region and is further divided into a first region and a second region (e.g., the first region corresponds to the upper region and the second region corresponds to the lower region), the first switch SW1 can be connected to the common electrode CE in at least one row (e.g., the first row R1) of a plurality of rows R1 to Rn, and the second switch SW2 can be connected to the common electrode CE in at least one row (e.g., the nth row Rn) of a plurality of rows R1 to Rn.

[0147] According to an exemplary embodiment, the row (e.g., the first row R1) provided with a common electrode CE connected to the first switch SW1 can be positioned above the row (e.g., the nth row Rn) provided with a common electrode CE connected to the second switch SW2, but the embodiments of this disclosure are not limited thereto.

[0148] Meanwhile, as will be described later, the noise compensator NCP can sense noise (electromagnetic waves) from the multiplexer MUX via the second sensing line SL2 connected to the second switch SW2. For this purpose, in an exemplary embodiment, the common electrode CE connected to the second switch SW2 can be positioned adjacent to the multiplexer MUX. For example, the row (e.g., the nth row Rn) among the multiple rows R1 to Rn containing the common electrode CE connected to the second switch SW2 can be positioned adjacent to the multiplexer MUX. In this case, for proper detection of noise (electromagnetic waves) generated by the multiplexer MUX, the common electrode CE connected to the first switch SW1 (or the row containing the common electrode CE connected to the first switch SW1) may not be positioned between the common electrode CE connected to the second switch SW2 (or the row containing the common electrode CE connected to the second switch SW2) and the multiplexer MUX (i.e., the common electrode CE connected to the first switch SW1 is positioned above the common electrode CE connected to the second switch SW2).

[0149] Furthermore, according to an exemplary embodiment, at least one row can be provided between the row of multiple rows R1 to Rn in which a common electrode CE connected to the first switch SW1 is provided and the row in which a common electrode CE connected to the second switch SW2 is provided. For example, at least one row can be provided between the row of multiple rows R1 to Rn in which a common electrode CE connected to the first switch SW1 is provided and the row in which a common electrode CE connected to the second switch SW2 is provided, wherein a common electrode CE not connected to any switch is provided in the at least one row. However, this is merely exemplary, and the embodiments of this disclosure are not limited thereto. The row of multiple rows R1 to Rn in which a common electrode CE connected to the first switch SW1 is provided and the row in which a common electrode CE connected to the second switch SW2 is provided can be arranged to be adjacent to each other.

[0150] Furthermore, the first switch SW1 can be connected to the first sensing line SL1, and the second switch SW2 can be connected to the second sensing line SL2. Therefore, when a first switch control signal with an on level is provided to the first switch SW1, the first switch SW1 is turned on, and the common electrode CE disposed in the first row R1 can be connected to the first sensing line SL1. Furthermore, when a second switch control signal with an on level is provided to the second switch SW2, the second switch SW2 is turned on, and the common electrode CE disposed in the nth row Rn can be connected to the second sensing line SL2.

[0151] In an exemplary embodiment, during a frame period when the display device 1000 is driven, the first switch SW1 and the second switch SW2 can be turned on during the display driving period and turned off during the touch driving period.

[0152] For example, further reference Figure 8 During the frame period, each of the first switch control signal SWCS1 provided to the first switch SW1 and the second switch control signal SWCS2 provided to the second switch SW2 may have an on level (e.g., high level) during the display drive period DP and an off level (e.g., low level) during the touch drive period TP.

[0153] Therefore, the common electrode CE, which is connected to the first switch SW1, can be electrically connected to the first sensing line SL1 during the display driving period DP, and can be electrically open during the touch driving period TP without being connected to the first sensing line SL1.

[0154] Similarly, the common electrode CE connected to the second switch SW2, i.e., the common electrode CE set in the nth row Rn, can be electrically connected to the second sensing line SL2 during the display driving period DP, and can be electrically open during the touch driving period TP without being connected to the second sensing line SL2.

[0155] The noise compensator NCP can sense noise (e.g., electromagnetic waves) that may occur within the display device 1000. For example, the noise compensator NCP can receive a first sensing signal SS1 via a first sensing line SL1, and can sense noise (electromagnetic waves) generated by the pixels PX of the display panel 100 based on the first sensing signal SS1. Furthermore, the noise compensator NCP can receive a second sensing signal SS2 via a second sensing line SL2, and can sense noise (electromagnetic waves) generated by the source driver integrated circuit SIC (e.g., a multiplexer MUX included in the source driver integrated circuit SIC) based on the second sensing signal SS2. Additionally, the noise compensator NCP can receive a third sensing signal SS3 via a third sensing line SL3, and can sense noise (electromagnetic waves) generated by the gate driver GIP based on the third sensing signal SS3.

[0156] More specifically, during the display driving period DP, the noise compensator NCP is electrically connected to the common electrode CE disposed in the first row R1 via the first sensing line SL1 and the first switch SW1, and receives the first sensing signal SS1 corresponding to noise (electromagnetic wave) generated from the common electrode CE. For example, during the display driving period DP, noise (electromagnetic wave) can be generated from the pixel PX by the common voltage Vcom provided to the common electrode CE for display driving. Therefore, during the display driving period DP, the noise compensator NCP can receive the first sensing signal SS1 via the first sensing line SL1 and sense the noise (electromagnetic wave) generated from the pixel PX.

[0157] Meanwhile, as described above, the first switch SW1 can be turned off during the touch driving period TP. This is to prevent the touch driving performance from degrading by electrically connecting the common electrode CE (i.e., the touch electrode) to the first sensing line SL1 during the touch driving period TP, since the common electrode CE is used as the touch electrode and the touch driving signal TDS is applied to the common electrode CE during the touch driving period TP.

[0158] Furthermore, during the display driving period DP, the noise compensator NCP can be electrically connected to the common electrode CE located in the nth row Rn via the second sensing line SL2 and the on second switch SW2, and receives the second sensing signal SS2 corresponding to noise (electromagnetic wave) generated from the common electrode CE. For example, in the case of the multiplexer MUX, noise (electromagnetic wave) can be generated by the clock signal (e.g., the multiplexer clock signal) provided to the multiplexer MUX. Therefore, during the display driving period DP, the noise compensator NCP can sense the noise (electromagnetic wave) generated from the multiplexer MUX via the following common electrode CE: this common electrode CE is located in the nth row Rn adjacent to the multiplexer MUX. That is, during the display driving period DP, the noise compensator NCP can receive the second sensing signal SS2 via the second sensing line SL2 and sense the noise (electromagnetic wave) generated from the multiplexer MUX.

[0159] Meanwhile, as described above, the second switch SW2 can be turned off during the touch driving period TP. This is to prevent the touch driving performance from degrading during the touch driving period TP by electrically connecting the common electrode CE (i.e., the touch electrode) located in the nth row Rn to the second sensing line SL2, since the common electrode CE is used as the touch electrode and the touch driving signal TDS is applied to the common electrode CE during the touch driving period TP.

[0160] Meanwhile, as described above, the second sensing line SL2 for sensing noise (electromagnetic waves) generated from the multiplexer MUX can be connected to a common electrode CE that is positioned adjacent to the multiplexer MUX, i.e., the common electrode CE located in the nth row Rn (e.g., connected during the period when the second switch SW2 is on). Here, in order for the noise compensator NCP to sense the noise (electromagnetic waves) generated from the pixel PX via the first sensing line SL1, it is necessary to sense the noise (electromagnetic waves) in the region (or point) where the influence of the noise (electromagnetic waves) generated by the multiplexer MUX is minimal. Therefore, as described above, the first sensing line SL1 for sensing the noise (electromagnetic waves) generated from the pixel PX can be connected to a common electrode CE located at a relatively far distance from the multiplexer MUX, i.e., the common electrode CE located in the first row R1 (e.g., connected during the period when the first switch SW1 is on). Therefore, the aforementioned noise (e.g., noise generated from the pixel PX and noise generated from the multiplexer MUX) can be sensed more accurately.

[0161] Furthermore, the noise compensator NCP can receive a third sensing signal SS3 via the third sensing line SL3 and sense the noise (electromagnetic waves) generated by the gate driver GIP. For example, in the case of the gate driver GIP, noise (electromagnetic waves) can be generated by a clock signal (e.g., a gate clock signal) provided via the gate control line GCL. Therefore, the noise compensator NCP can sense the noise (electromagnetic waves) generated by the gate driver GIP based on the third sensing signal SS3 received via the third sensing line SL3 connected to the gate driver GIP.

[0162] Reference Figure 9 To provide a more detailed explanation, the generation of the reference signal can be provided to the gate driver GIP via the first clock signal line CLKL1, the second clock signal line CLKL2, and the third clock signal line CLKL3, respectively. Figure 1 The first gate clock signal, the second gate clock signal, and the third gate clock signal are necessary for the described gate signal.

[0163] Each of the first clock signal line CLKL1, the second clock signal line CLKL2, and the third clock signal line CLKL3 may extend in the second direction DR2 and be spaced apart from each other in the first direction DR1.

[0164] In an exemplary embodiment, a first sub-sensing line SSL1 and a second sub-sensing line SSL2 may also be provided in the gate driver GIP. The first sub-sensing line SSL1 and the second sub-sensing line SSL2 may be spaced apart from the first clock signal line CLKL1, the second clock signal line CLKL2, and the third clock signal line CLKL3, and are disposed between the first clock signal line CLKL1, the second clock signal line CLKL2, and the third clock signal line CLKL3. For example, the first sub-sensing line SSL1 may be disposed between the first clock signal line CLKL1 and the second clock signal line CLKL2, and the second sub-sensing line SSL2 may be disposed between the second clock signal line CLKL2 and the third clock signal line CLKL3.

[0165] Furthermore, the first sub-sensing line SSL1 and the second sub-sensing line SSL2 can be connected to each other through contact holes (e.g., CNT1 and CNT2) disposed below them, passing through at least one layer (e.g., interlayer insulation layer).

[0166] For example, further reference Figure 10 , Figure 10 The diagram shows: a substrate SUB, a buffer layer BUF, a gate insulating layer GI, an interlayer insulating layer ILD, first clock signal lines to third clock signal lines CLKL1, CLKL2 and CLKL3, a first sub-sensing line SSL1 and a second sub-sensing line SSL2, and a first connection electrode CTE1.

[0167] The substrate SUB is the base material of the display panel 100 and can be a substantially transparent light-transmitting substrate. The substrate SUB can be a flexible substrate formed of plastic material. Here, flexibility can be interpreted as having the same meaning as being bendable, not easily broken, rollable, or foldable.

[0168] For example, the substrate SUB may comprise plastic, and in this case, the substrate SUB may also be referred to as a plastic film or a plastic substrate. For example, the substrate SUB may comprise at least one selected from the group consisting of: polyester-based polymers, silicon-based polymers, acrylic-based polymers, polyolefin-based polymers, and polymers of the above polymers. For example, the substrate SUB may comprise polyimide (PI).

[0169] This is an example, and the material of the substrate SUB is not limited thereto. For example, the substrate SUB can be a rigid substrate, including glass or tempered glass.

[0170] A buffer layer (BUF) can be provided on the substrate SUB. Meanwhile, although... Figure 10Not shown separately, but components corresponding to the effective area DA of the display panel 100, for at least one thin-film transistor, storage capacitor and light-emitting element included in each pixel PX, may be provided on the buffer layer BUF.

[0171] A buffer layer (BUF) is disposed on the substrate (SUB) and can be used to protect components included in the pixel (PX) (e.g., thin-film transistors) from impurities (such as alkali ions) flowing out from the substrate (SUB). For example, the buffer layer (BUF) can be formed of silicon nitride (SiNx), silicon oxide (SiOx), or multiple layers of the above materials. Furthermore, the buffer layer (BUF) can improve the adhesion between the layers formed thereon and the substrate (SUB) and prevent moisture or oxygen from permeating through the substrate (SUB).

[0172] A gate insulating layer GI can be disposed on the buffer layer BUF. Meanwhile, although... Figure 10 Not shown separately, but on the buffer layer BUF, the following may be provided: a semiconductor layer (or semiconductor pattern or active layer) of the thin-film transistor included in the pixel PX in the effective region DA, and gate, source, and drain electrodes overlapping the semiconductor layer. A gate insulating layer GI can insulate the semiconductor layer and gate electrode of the thin-film transistor. For example, the gate insulating layer GI may include an insulating inorganic material, such as silicon oxide (SiOx) or silicon nitride (SiNx), but this is exemplary. The gate insulating layer GI may also include insulating organic materials other than the aforementioned insulating materials.

[0173] A first connection electrode CTE1 may be disposed on the gate insulating layer GI. The first connection electrode CTE1 may include a conductive metal material.

[0174] An interlayer insulating layer (ILD) may be disposed on the gate insulating layer GI. For example, the interlayer insulating layer (ILD) may be disposed on the gate insulating layer GI to cover the first connection electrode CTE1.

[0175] The interlayer insulating layer (ILD) can be configured as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of the above materials, but is not limited thereto.

[0176] On the interlayer insulating layer (ILD), the first clock signal line CLKL1, the second clock signal line CLKL2, and the third clock signal line CLKL3 can be configured to be spaced apart from each other in the first direction DR1. The first sub-sensing line SSL1 and the second sub-sensing line SSL2 can be disposed between the first clock signal line CLKL1, the second clock signal line CLKL2, and the third clock signal line CLKL3.

[0177] The first sub-sensing line SSL1 can be electrically connected to the first connecting electrode CTE1 through the first contact hole CNT1 passing through the interlayer insulating layer ILD. Furthermore, the second sub-sensing line SSL2 can be electrically connected to the first connecting electrode CTE1 through the second contact hole CNT2 passing through the interlayer insulating layer ILD. Therefore, the first sub-sensing line SSL1 and the second sub-sensing line SSL2 can be electrically connected.

[0178] Furthermore, the first sub-sensing line SSL1 and the second sub-sensing line SSL2 can be connected to the third sensing line SL3 through contact holes (e.g., CNT3, CNT4 and CNT5) disposed thereunder that pass through at least one layer (e.g., interlayer insulation layer).

[0179] For example, refer to Figure 11 The third sensing line SL3 can be configured on the interlayer insulating layer (ILD) to be spaced apart from the first sub-sensing line SSL1, the second sub-sensing line SSL2, and the first clock signal lines to the third clock signal lines CLKL1, CLKL2, and CLKL3. For example, the third sensing line SL3 can be disposed on one side of the first clock signal line CLKL1. Furthermore, a second connection electrode CTE2 can be disposed on the gate insulating layer (GI). The second connection electrode CTE2 can comprise a conductive metal material.

[0180] The first sub-sensing line SSL1 can be electrically connected to the second connecting electrode CTE2 through the third contact hole CNT3 passing through the interlayer insulating layer ILD. Furthermore, the second sub-sensing line SSL2 can be electrically connected to the second connecting electrode CTE2 through the fourth contact hole CNT4 passing through the interlayer insulating layer ILD. Additionally, the third sensing line SL3 can be electrically connected to the second connecting electrode CTE2 through the fifth contact hole CNT5 passing through the interlayer insulating layer ILD. Therefore, the first sub-sensing line SSL1 and the second sub-sensing line SSL2 can be electrically connected to the third sensing line SL3.

[0181] As described above, by providing a first sub-sensing line SSL1 and a second sub-sensing line SSL2 (which is the cause of noise (electromagnetic waves) generated by the gate driver GIP) between the first clock signal line CLKL1, CLKL2 and CLKL3, and a third sensing line SL3 electrically connected to the first sub-sensing line SSL1 and the second sub-sensing line SSL2, the noise compensator NCP can receive the third sensing signal SS3 and sense the noise (electromagnetic waves) from the gate driver GIP.

[0182] Refer to the return Figure 7In an exemplary embodiment, the noise compensator NCP can generate a noise compensation signal NCS based on a first sensing signal SS1, a second sensing signal SS2, and a third sensing signal SS3. For example, the noise compensator NCP can adjust the inverted signals of each of the first sensing signal SS1, the second sensing signal SS2, and the third sensing signal SS3 to individual intensities by applying different gain values, and generate a signal obtained by combining the adjusted signals as the noise compensation signal NCS. Here, an inverted signal can refer to a signal whose phase is reversed.

[0183] Reference Figure 12 To provide a more detailed description, the noise compensator NCP may include a first inverting circuit IVT1, a second inverting circuit IVT2, a third inverting circuit IVT3, and a merging circuit MRG. The first sensing signal SS1, the second sensing signal SS2, and the third sensing signal SS3 provided to the noise compensator NCP may be provided to the first inverting circuit IVT1, the second inverting circuit IVT2, and the third inverting circuit IVT3, respectively.

[0184] Each of the first inverting circuit IVT1, the second inverting circuit IVT2, and the third inverting circuit IVT3 can invert the phase of the provided signal (i.e., the first sensing signal SS1, the second sensing signal SS2, and the third sensing signal SS3), adjust the signal strength, and output an inverted signal.

[0185] For example, further reference Figure 13 The inverting circuit IVT (e.g., the first inverting circuit IVT1, the second inverting circuit IVT2, or the third inverting circuit IVT3) may include an inverting amplifier, which includes an input resistor Rin, an output resistor Rout, and an amplifier OP. Therefore, for an input signal IN (e.g., the first sensing signal SS1, the second sensing signal SS2, and / or the third sensing signal SS3) provided through the input terminals, the phase of the signal can be inverted, and an output signal OUT (e.g., the first inverted sensing signal SS1_C, the second inverted sensing signal SS2_C, and the third inverted sensing signal SS3_C) can be output through the output terminals.

[0186] Reference Figure 14 To explain in more detail, the first inverting circuit IVT1 can receive the first sensing signal SS1 and invert its phase, then apply a first gain value K1 to control the signal strength, and output the first inverted sensing signal SS1_C. For example, the phases of the first sensing signal SS1 and the first inverted sensing signal SS1_C are opposite to each other, and the strength (amplitude) of the first inverted sensing signal SS1_C can be equal to the value obtained by multiplying the strength (amplitude) of the first sensing signal SS1 by the first gain value K1.

[0187] Furthermore, the second inverting circuit IVT2 can receive the second sensing signal SS2 and invert its phase, then apply a second gain value K2 to control the signal strength, and output a second inverted sensing signal SS2_C. For example, the phases of the second sensing signal SS2 and the second inverted sensing signal SS2_C are opposite to each other, and the strength (amplitude) of the second inverted sensing signal SS2_C can be equal to the value obtained by multiplying the strength (amplitude) of the second sensing signal SS2 by the second gain value K2.

[0188] Furthermore, the third inverting circuit IVT3 can receive the third sensing signal SS3 and invert its phase, then apply a third gain value K3 to control the signal strength, and output a third inverted sensing signal SS3_C. For example, the phases of the third sensing signal SS3 and the third inverted sensing signal SS3_C are opposite to each other, and the strength (amplitude) of the third inverted sensing signal SS3_C can be equal to the value obtained by multiplying the strength (amplitude) of the third sensing signal SS3 by the third gain value K3.

[0189] At the same time, as referenced Figure 7 As described, the first sensing line SL1 for sensing noise (electromagnetic waves) generated from pixel PX can be connected only to the common electrode CE disposed in a portion of the common electrode CE (e.g., the common electrode CE disposed in the first row R1). As described above, a first sensing signal SS1 can be detected in response to noise (electromagnetic waves) generated from some pixels in pixel PX (e.g., pixels disposed to overlap with the common electrode CE in the first row R1). Furthermore, since the first sensing line SL1 is connected to the common electrode CE disposed in the first row R1, it can be longer than other sensing lines (e.g., the second sensing line SL2 and the third sensing line SL3). Therefore, the amplitude of the first sensing signal SS1 may attenuate when detected through the first sensing line SL1.

[0190] In addition, as referenced Figures 7 to 11As described, the third sensing line SL3 for sensing noise (electromagnetic waves) generated by the gate clock signal of the gate driver GIP can be connected to the first sub-sensing line SSL1 and the second sub-sensing line SSL2 (which are directly disposed between the first clock signal line to the third clock signal line CLKL1, CLKL2, and CLKL3 where the gate clock signal is provided), so that the third sensing signal SS3 can be sensed. On the other hand, the second sensing line SL2 for sensing noise (electromagnetic waves) generated by the multiplexer clock signal of the multiplexer MUX is not directly connected to the multiplexer MUX, but is electrically connected to the common electrode CE disposed in the active region DA (or sensing region SA), so that the second sensing signal SS2 can be sensed indirectly. Therefore, the amplitude of the second sensing signal SS2 can be smaller than the amplitude of the third sensing signal SS3.

[0191] As described above, the amplitudes of the first sensing signal SS1, the second sensing signal SS2, and the third sensing signal SS3 detected by the first sensing line SL1, the second sensing line SL2, and the third sensing line SL3 can be different. For example, as mentioned above, the amplitude of the first sensing signal SS1 can be the smallest, while the amplitude of the third sensing signal SS3 can be the largest.

[0192] Therefore, the noise compensator NCP according to the exemplary embodiment of this disclosure can apply different gain values ​​K1, K2 and K3, and generate a first inverted sensing signal SS1_C, a second inverted sensing signal SS2_C and a third inverted sensing signal SS3_C with the same amplitude (intensity).

[0193] That is, in the exemplary embodiment, the first gain value K1, the second gain value K2, and the third gain value K3 can be different. For example, the first gain value K1 applied to the phase-reversed signal corresponding to the first sensing signal SS1 is the largest. The third gain value K3 applied to the phase-reversed signal corresponding to the third sensing signal SS3 can be the smallest.

[0194] Meanwhile, the first gain value K1, the second gain value K2, and the third gain value K3 can be determined based on the magnitude of the output resistor Rout included in the inverting circuit IVT.

[0195] Refer to the return Figure 12 The inverted sensing signals SS1_C, SS2_C, and SS3_C output from the inverting circuits IVT1, IVT2, and IVT3 can be provided to the merging circuit MRG. For example... Figure 14As shown, the merging circuit MRG can combine the inverted sensing signals SS1_C, SS2_C, and SS3_C into a single signal and output that signal, thereby generating a noise compensation signal NCS. For example, the merging circuit MRG may include AND logic gates, but this is exemplary, and embodiments of this disclosure are not limited thereto. Meanwhile, in this case, as referenced... Figure 6A and Figure 6B The points where noise occurs, i.e., the peaks of the sensing signals SS1, SS2, and SS3, vary depending on the cause of the noise. Therefore, in generating the noise compensation signal NCS, even if the inverted sensing signals SS1_C, SS2_C, and SS3_C are combined into a single signal, their intensities (magnitudes) do not affect each other, enabling the normal generation of the noise compensation signal NCS to cancel out the individual noises (electromagnetic waves).

[0196] The noise compensation signal NCS can be provided to the voltage generator VG. That is, as a noise compensation signal NCS used to cancel out various noises (electromagnetic waves), the following noise compensation signal NCS can be provided to the voltage generator VG: the noise compensation signal NCS includes the peak values ​​of the inverted sensing signals SS1_C, SS2_C, and SS3_C corresponding to the inverted signals of the sensed noise. Therefore, the electromagnetic interference (EMI) level of the display device 1000 can be reduced.

[0197] For example, refer to Figure 15 ,like Figure 15 As shown, compared to the electromagnetic interference level EMI_C of a comparative example that does not perform separate noise compensation, the electromagnetic interference level EMI can be significantly reduced by the noise compensation signal NCS in the display device 1000 of the exemplary embodiment of this disclosure.

[0198] In particular, the display device 1000 according to an exemplary embodiment of the present disclosure can detect noise (electromagnetic waves) by using different sensing lines SL1, SL2 and SL3 according to the cause of noise generation, and generate a noise compensation signal NCS based on the detected noise, thereby more effectively reducing the level of electromagnetic interference.

[0199] Figure 16 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0200] Figure 17 It is shown Figure 16 A block diagram of an example noise compensator included in a display device.

[0201] at the same time, Figure 16 and Figure 17 A reference is shown for the noise compensator NCP_1. Figures 7 to 15Modified embodiments of the exemplary embodiments described herein. Here, to avoid redundancy, only the parts that differ from the above exemplary embodiments will be described; parts not specifically described are consistent with the above exemplary embodiments. The same reference numerals denote the same elements, and similar reference numerals denote similar constituent elements.

[0202] Reference Figure 16 and Figure 17 The display device 1000_1 according to an exemplary embodiment of the present disclosure may include a plurality of common electrodes CE, a gate driver GIP, a source driver integrated circuit SIC_1, and a noise compensator NCP_1 disposed in the effective area DA (or sensing area SA) of the display panel 100.

[0203] At the same time, Figure 16 In the display device 1000_1, the source driver integrated circuit SiC_1 can be a reference Figure 4B The described source driver integrated circuit SIC_1. That is, it includes... Figure 16 The source driver integrated circuit SIC_1 in the display device 1000_1 may not include a multiplexer.

[0204] Therefore, the display device 1000_1 can be configured such that it does not include a reference. Figure 7 The described sensing line (e.g., second sensing line SL2) is used to sense noise (electromagnetic waves) generated from the multiplexer.

[0205] Therefore, as Figure 16 and Figure 17 As shown, the noise compensator NCP_1 can receive only the first sensing signal SS1 and the third sensing signal SS3, and use the merging circuit MRG_1 to output the first inverted sensing signal SS1_C and the third inverted sensing signal SS3_C output by the inverting circuits IVT1 and IVT3 as a single signal, thereby generating the noise compensation signal NCS_1 and outputting it.

[0206] Figure 18 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0207] at the same time, Figure 18 References are shown for sensing lines SL1_1, SL2_1, and SL3_1. Figures 7 to 15 Modified embodiments of the exemplary embodiments described herein. Here, to avoid redundancy, only the parts that differ from the above exemplary embodiments will be described; parts not specifically described are consistent with the above exemplary embodiments. The same reference numerals denote the same elements, and similar reference numerals denote similar constituent elements.

[0208] Reference Figure 18 The display device 1000_2 according to an exemplary embodiment of the present disclosure may include a plurality of common electrodes CE, a gate driver GIP, a source driver integrated circuit SiC, and a noise compensator NCP disposed in the effective area DA (or sensing area SA) of the display panel 100.

[0209] At the same time, Figure 18 In the display device 1000_2, the gate driver GIP can be disposed on either side (e.g., the left or right side) of the effective region DA, or on both sides of the effective region DA. In the following, unless otherwise stated, the gate driver GIP is assumed to be disposed on the right side of the effective region DA (in...). Figure 18 The present disclosure is described as “GIP1”, but the implementation of the present disclosure is not limited thereto.

[0210] Multiple common electrodes CE can be arranged linearly in the effective area DA (or sensing area SA) of the display panel 100.

[0211] In an exemplary embodiment, at least a portion of the common electrode CE can be connected to the first switch SW1, at least another portion of the common electrode CE can be connected to the second switch SW2, and at least yet another portion of the common electrode CE can be connected to the third switch SW3.

[0212] For example, each common electrode CE located in the first row R1 of the plurality of rows R1 to Rn, and in columns C1 to Cm-1 excluding the m-th column Cm (the last column of the plurality of columns C1 to Cm), can be connected to the first switch SW1. Furthermore, each common electrode CE located in the nth row Rn of the plurality of rows R1 to Rn, and in columns C1 to Cm-1 excluding the m-th column Cm (the last column of the plurality of columns C1 to Cm), can be connected to the second switch SW2. Furthermore, each common electrode CE located in the m-th column Cm of the plurality of columns C1 to Cm can be connected to the third switch SW3.

[0213] Furthermore, the first switch SW1 can be connected to the first sensing line SL1_1, the second switch SW2 can be connected to the second sensing line SL2_1, and the third switch SW3 can be connected to the third sensing line SL3_1. Therefore, when a first switch control signal with an on level is provided to the first switch SW1, the first switch SW1 is turned on, and the common electrode CE located in the first row R1 and the first column C1 to the (m-1)th column Cm-1 can be connected to the first sensing line SL1_1. Similarly, when a second switch control signal with an on level is provided to the second switch SW2, the second switch SW2 is turned on, and the common electrode CE located in the nth row Rn and the first column C1 to the (m-1)th column Cm-1 can be connected to the second sensing line SL2_1. Finally, when a third switch control signal with an on level is provided to the third switch SW3, the third switch SW3 is turned on, and the common electrode CE located in the mth column Cm can be connected to the third sensing line SL3_1.

[0214] In an exemplary embodiment, during a frame period in which the display device 1000_2 is driven, the first switch SW1, the second switch SW2, and the third switch SW3 can be turned on during the display driving period and turned off during the touch driving period. For example, as shown in reference Figure 8 Each of the first switch control signal provided to the first switch SW1, the second switch control signal provided to the second switch SW2, and the third switch control signal provided to the third switch SW3 may have an on level (e.g., high level) during the display driving period DP of the frame period and may have an off level (e.g., low level) during the touch driving period TP of the frame period.

[0215] Therefore, the common electrode CE connected to the first switch SW1, that is, the common electrode CE set in the first row R1 and the first column C1 to the (m-1)th column Cm-1, can be electrically connected to the first sensing line SL1_1 during the display driving period DP, and can be electrically open during the touch driving period TP without being connected to the first sensing line SL1_1.

[0216] Similarly, the common electrode CE connected to the second switch SW2, i.e. the common electrode CE set in the nth row Rn and the first column C1 to the (m-1)th column Cm-1, can be electrically connected to the second sensing line SL2_1 during the display driving period DP, and can be electrically open during the touch driving period TP without being connected to the second sensing line SL2_1.

[0217] Similarly, the common electrode CE connected to the third switch SW3, i.e. the common electrode CE set in the m-th column Cm, can be electrically connected to the third sensing line SL3_1 during the display driving period DP, and can be electrically open during the touch driving period TP without being connected to the third sensing line SL3_1.

[0218] In an exemplary embodiment, the noise compensator NCP can sense noise (e.g., electromagnetic waves) that may occur within the display device 1000_2. For example, the noise compensator NCP can receive a first sensing signal SS1 via a first sensing line SL1_1, and can sense noise (electromagnetic waves) generated by the pixels PX of the display panel 100 based on the first sensing signal SS1. Furthermore, the noise compensator NCP can receive a second sensing signal SS2 via a second sensing line SL2_2, and can sense noise (electromagnetic waves) generated by the source driver integrated circuit SIC (e.g., a multiplexer MUX included in the source driver integrated circuit SIC) based on the second sensing signal SS2. Additionally, the noise compensator NCP can receive a third sensing signal SS3 via a third sensing line SL3_1, and can sense noise (electromagnetic waves) generated by the gate driver GIP based on the third sensing signal SS3.

[0219] More specifically, it is essentially similar to a reference. Figure 7 As described, during the display driving period DP, the noise compensator NCP can be electrically connected to the common electrode CE located in the first row R1 and the first column C1 to the (m-1)th column Cm-1 via the first sensing line SL1_1 and the first switch SW1, and receives the first sensing signal SS1 corresponding to the noise (electromagnetic wave) generated from the common electrode CE, and detects the noise (electromagnetic wave) generated from the pixel PX.

[0220] Furthermore, during the display driving period DP, the noise compensator NCP can be electrically connected to the common electrode CE located in the nth row Rn and the first column C1 to the (m-1)th column Cm-1 via the second sensing line SL2_1 and the on second switch SW2, and receive the second sensing signal SS2 generated from the common electrode CE corresponding to the noise (electromagnetic wave), and detect the noise (electromagnetic wave) generated from the multiplexer MUX.

[0221] Furthermore, during the display driving period DP, the noise compensator NCP can be electrically connected to the common electrode CE located in the m-th column Cm through the third sensing line SL3_1 and the turned-on third switch SW3, and receive the third sensing signal SS3 corresponding to the noise (electromagnetic wave) generated from the common electrode CE, and detect the noise (electromagnetic wave) generated from the gate driver GIP.

[0222] At the same time, Figure 18 The diagram shows a common electrode CE disposed in the m-th column Cm of a plurality of columns C1 to Cm connected to a third switch SW3, but embodiments of the present disclosure are not limited thereto. For example, the common electrode CE disposed in at least one of the first columns C1 to the (m-1)-th columns Cm-1 can be connected to the third switch SW3.

[0223] Meanwhile, in an exemplary embodiment, the common electrode CE connected to the third switch SW3 can be configured adjacent to the gate driver GIP, the third switch SW3 being connected to a third sensing line SL3_1 for detecting noise (electromagnetic waves) generated from the gate driver GIP. For example, as described above, in Figure 18 In the case where the gate driver GIP is located on the right side of the active region DA, the common electrode CE connected to the third switch SW3 can be located in the m-th column Cm adjacent to the gate driver GIP.

[0224] Meanwhile, unlike this, when the gate driver GIP is set to the left of the active region DA (in Figure 18 (As shown in the diagram, designated "GIP2"), the common electrode CE connected to the third switch SW3 can be positioned adjacent to the gate driver GIP. For example, the common electrode CE connected to the third switch SW3 can be positioned in the first column C1 adjacent to the gate driver GIP.

[0225] In addition, as referenced Figure 4A As mentioned above, two gate drivers GIP can be disposed on both sides of the effective region DA (in Figure 18 (These are shown as "GIP1" and "GIP2"). In this case, the common electrode CE connected to the third switch SW3 can be configured to be adjacent to one of the two gate driver GIPs. For example, the common electrode CE connected to the third switch SW3 can be configured to be adjacent to the gate driver GIP1 located on the right side (e.g., in column m Cm), or it can be configured to be adjacent to the gate driver GIP1 located on the left side (e.g., in column c1). However, this is merely exemplary, and embodiments of this disclosure are not limited thereto. For example, when two gate driver GIPs are provided on both sides of the effective region DA, the common electrode CE connected to the third switch SW3 can be configured in two columns. For example, the common electrode CE connected to the third switch SW3 can be configured in all columns adjacent to each of the two gate driver GIPs located on both sides (e.g., column c1 and column m C1).

[0226] Figure 19 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0227] Figure 20 It is shown Figure 19 A diagram showing an example of a multiplexer included in a display device.

[0228] Figure 21 It shows along Figure 20 The example cross-sectional view obtained by line III-III′ is shown.

[0229] at the same time, Figures 19 to 21 References are shown regarding the common electrode CE_1 and the multiplexer MUX_1. Figures 7 to 15 Modified embodiments of the exemplary embodiments described herein. Here, to avoid redundancy, only the parts that differ from the above exemplary embodiments will be described; parts not specifically described are consistent with the above exemplary embodiments. The same reference numerals denote the same elements, and similar reference numerals denote similar constituent elements.

[0230] at the same time, Figure 19 The display device 1000_3 may not include a touch panel embedded in accordance with the above-described embedded touch method (e.g., Advanced In-line Touch (AIT) method). That is, the common electrode CE_1 included in the display device 1000_3 is used only as an electrode for applying the common voltage Vcom for display driving, and may not be used as a touch electrode for applying the touch drive signal TDS.

[0231] The display device 1000_3 according to an exemplary embodiment of the present disclosure may include a common electrode CE_1, a gate driver GIP, a source driver integrated circuit SIC_2, and a noise compensator NCP disposed in the effective area DA (or sensing area SA) of the display panel 100.

[0232] A common electrode CE_1 may be provided in the effective area DA (or sensing area SA) of the display panel 100. The common electrode CE_1 can be connected to the source driver integrated circuit SIC_2 (e.g., the voltage generator VG included in the source driver integrated circuit SIC_2) via the common voltage line COML, and receives the common voltage Vcom.

[0233] At the same time, Figure 19 Although the illustration shows a common electrode CE_1 disposed in the effective region DA, this is merely exemplary, and embodiments of the present disclosure are not limited thereto. For example, at least two common electrodes CE_1 may be disposed in the effective region DA.

[0234] In an exemplary embodiment, the common electrode CE_1 can be connected to the first sensing line SL1_2. Therefore, the noise compensator NCP can receive the first sensing signal SS1 through the first sensing line SL1_2 electrically connected to the common electrode CE_1, and detect noise (electromagnetic waves) generated from the pixel PX among the noise that may occur in the display device 1000_3.

[0235] In addition, the noise compensator NCP can receive the second sensing signal SS2 through the second sensing line SL2_2 and sense the noise (electromagnetic wave) generated by the multiplexer MUX_1.

[0236] For example, in the case of multiplexer MUX_1, noise (electromagnetic waves) may be generated by the clock signal (e.g., the multiplexer clock signal) provided to multiplexer MUX_1. Therefore, the noise compensator NCP can sense the noise (electromagnetic waves) generated by the multiplexer (MUX_1) based on a second sensing signal SS2, which is received through a second sensing line SL2_2 connected to multiplexer MUX_1.

[0237] Reference Figure 20 To provide a more detailed explanation, the first and second multiplexer clock signals necessary for driving (operation) can be provided to the multiplexer MUX_1 via the fourth clock signal line CLKL4 and the fifth clock signal line CLKL5, respectively.

[0238] Each of the fourth clock signal line CLKL4 and the fifth clock signal line CLKL5 extends in the first direction DR1 and may be spaced apart from each other in the second direction DR2.

[0239] In an exemplary embodiment, a third sub-sensing line SSL3 may also be provided in the multiplexer MUX_1. The third sub-sensing line SSL3 may be spaced apart from the fourth clock signal line CLKL4 and the fifth clock signal line CLKL5, and may be disposed between the fourth clock signal line CLKL4 and the fifth clock signal line CLKL5. For example, the third sub-sensing line SSL3 may be disposed between the fourth clock signal line CLKL4 and the fifth clock signal line CLKL5.

[0240] Furthermore, the third sub-sensing line SSL3 can be connected to the second sensing line SL2_2 via contact holes (e.g., CNT6 and CNT7) disposed beneath it that pass through at least one layer (e.g., interlayer insulation layer).

[0241] For example, further reference Figure 21 , Figure 21The diagram shows the substrate SUB, buffer layer BUF, gate insulating layer GI, interlayer insulating layer ILD, fourth clock signal line CLKL4 and fifth clock signal line CLKL5, third sub-sensor line SSL3 and third connection electrode CTE3.

[0242] A third connection electrode CTE3 may be disposed on the gate insulating layer GI. The third connection electrode CTE3 may include a conductive metal material.

[0243] On the interlayer insulating layer (ILD), the fourth clock signal line CLKL4 and the fifth clock signal line CLKL5 can be arranged to be spaced apart from each other in the second direction DR2, and the third sub-sensing line SSL3 can be arranged between the fourth clock signal line CLKL4 and the fifth clock signal line CLKL5.

[0244] The second sensing line SL2_2 can be configured on the interlayer insulating layer (ILD) to be spaced apart from the third sub-sensing line SSL3, the fourth clock signal line CLKL4, and the fifth clock signal line CLKL5. For example, the second sensing line SL2_2 can be disposed on one side of the fifth clock signal line CLKL5.

[0245] The third sub-sensing line SSL3 can be electrically connected to the third connecting electrode CTE3 through the sixth contact hole CNT6 of the interlayer insulating layer ILD. Furthermore, the second sensing line SL2_2 can be electrically connected to the third connecting electrode CTE3 through the seventh contact hole CNT7 of the interlayer insulating layer ILD. Therefore, the third sub-sensing line SSL3 can be electrically connected to the second sensing line SL2_2.

[0246] As described above, by setting the third sub-sensing line SSL3 between the fourth clock signal line CLKL4 and the fifth clock signal line CLKL5 and configuring it to provide the multiplexer clock signal (which is the cause of noise (electromagnetic waves) generated by the multiplexer MUX_1), and the second sensing line SL2_2 electrically connected to the third sub-sensing line SSL3, the noise compensator NCP can receive the second sensing signal SS2 and sense the noise (electromagnetic waves) from the multiplexer MUX_1.

[0247] Furthermore, the noise compensator NCP can receive the third sensing signal SS3 via the third sensing line SL3 and sense the noise (electromagnetic wave) generated by the gate driver GIP. This is consistent with the reference... Figure 7 The content described is basically the same or similar, so the same description will not be repeated.

[0248] Figure 22 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0249] at the same time, Figure 22A reference is shown for the noise compensator NCP_2. Figures 19 to 21 Modified embodiments of the exemplary embodiments described herein. Here, to avoid redundancy, only the parts that differ from the above exemplary embodiments will be described; parts not specifically described are consistent with the above exemplary embodiments. The same reference numerals denote the same elements, and similar reference numerals denote similar constituent elements.

[0250] Reference Figure 22 The display device 1000_4 according to an exemplary embodiment of the present disclosure may include a common electrode CE_1, a gate driver GIP, a source driver integrated circuit SIC_3, and a noise compensator NCP_2 disposed in the effective area DA (or sensing area SA) of the display panel 100.

[0251] At the same time, Figure 22 In the display device 1000_4, the source driver integrated circuit SiC_3 can be used with the reference... Figure 4B The source driver integrated circuit SIC_1 described is basically the same. That is to say, it includes... Figure 22 The source driver integrated circuit SIC_3 in the display device 1000_4 may not include a multiplexer.

[0252] Therefore, the display device 1000_4 can be configured such that it does not include a reference. Figures 19 to 21 The described sensing line (e.g., second sensing line SL2_2) is used to sense noise (electromagnetic waves) generated from the multiplexer.

[0253] Therefore, as Figure 22 As shown, the noise compensator NCP_2 can receive only the first sensing signal SS1 and the third sensing signal SS3, and generate and output the noise compensation signal NCS_2 by using the merging circuit MRG_1 to output the first inverted sensing signal SS1_C and the third inverted sensing signal SS3_C output by the inverting circuit (e.g., the first inverting circuit IVT1 and the third inverting circuit IVT3) as a single signal.

[0254] As described above, the display device according to exemplary embodiments of this disclosure can sense noise generated according to each noise source (e.g., pixel, gate driver, and / or multiplexer) by using multiple sensing lines, and can generate a noise compensation signal to cancel the noise by applying different gain values ​​to the noise. Therefore, the level of electromagnetic interference can be reduced more effectively.

[0255] Exemplary embodiments of this disclosure can also be described as follows:

[0256] A display device according to an exemplary embodiment of the present disclosure may include: a display panel including an effective area, a plurality of pixels disposed in the effective area, and at least one common electrode overlapping at least a portion of the pixels; a gate driver configured to provide a gate signal to the pixels; a source driver integrated circuit configured to provide a data signal to the pixels and configured to provide a common voltage to the common electrode; and a noise compensator configured to: receive a plurality of sensing signals from a plurality of sensing lines, generate a plurality of inverted sensing signals by applying different gain values ​​for signals obtained by inverting the phases of the respective sensing signals, and generate a noise compensation signal by merging the inverted sensing signals.

[0257] Multiple common electrodes can be set in the first to nth rows and the first to mth columns of the effective region, where n is an integer greater than 0 and m is an integer greater than 0.

[0258] Multiple sensing lines may include a first sensing line, a second sensing line, and a third sensing line.

[0259] The first sensing line can be connected to the common electrode in the first row of the common electrode, the second sensing line can be connected to the common electrode in the nth row of the common electrode, and the third sensing line can be connected to the gate driver.

[0260] The display device may further include: a plurality of first switches, the plurality of first switches being respectively disposed between a first sensing line and a common electrode disposed in a first row; and a plurality of second switches, the plurality of second switches being respectively disposed between a second sensing line and a common electrode disposed in an nth row.

[0261] A frame period may include a display driving period in which a common voltage is provided to a common electrode and a touch driving period in which a touch driving signal is provided to a common electrode; and each of the first switch and the second switch may be turned on during the display driving period and turned off during the touch driving period.

[0262] The display device may further include: a first clock signal line, a second clock signal line, and a third clock signal line, the first clock signal line, the second clock signal line, and the third clock signal line being configured to provide a gate clock signal to a gate driver and being spaced apart from each other; a first sub-sensing line and a second sub-sensing line, the first sub-sensing line and the second sub-sensing line being disposed between the first clock signal line, the second clock signal line, and the third clock signal line. The first sub-sensing line and the second sub-sensing line may be electrically connected to the third sensing line.

[0263] The display device may further include: a substrate; a buffer layer disposed on the substrate; a gate insulating layer disposed on the buffer layer; a first connection electrode and a second connection electrode disposed on the gate insulating layer; and an interlayer insulating layer disposed on the gate insulating layer to cover the first connection electrode and the second connection electrode. The first clock signal line, the second clock signal line, and the third clock signal line, as well as the first sub-sensing line and the second sub-sensing line, may be configured to be spaced apart from each other on the interlayer insulating layer.

[0264] The first sub-sensing line can be connected to the first connecting electrode through a first contact hole passing through the interlayer insulating layer, and the second sub-sensing line can be connected to the first connecting electrode through a second contact hole passing through the interlayer insulating layer.

[0265] The first sub-sensing line can be connected to the second connecting electrode through the third contact hole passing through the interlayer insulating layer, the second sub-sensing line can be connected to the second connecting electrode through the fourth contact hole passing through the interlayer insulating layer, and the third sensing line can be connected to the second connecting electrode through the fifth contact hole passing through the interlayer insulating layer.

[0266] The noise compensator may include: a first inverting circuit configured to receive a first sensing signal from a first sensing line and output a first inverted sensing signal by applying a first gain value for a signal obtained by inverting the phase of the first sensing signal; a second inverting circuit configured to receive a second sensing signal from a second sensing line and output a second inverted sensing signal by applying a second gain value for a signal obtained by inverting the phase of the second sensing signal; a third inverting circuit configured to receive a third sensing signal from a third sensing line and output a third inverted sensing signal by applying a third gain value for a signal obtained by inverting the phase of the third sensing signal; and a combining circuit configured to generate a noise compensation signal by combining the first inverted sensing signal, the second inverted sensing signal, and the third inverted sensing signal.

[0267] Among the first gain value, the second gain value, and the third gain value, the first gain value can be the largest, and the third gain value can be the smallest.

[0268] The multiple sensing lines may include a first sensing line, a second sensing line, and a third sensing line. The first sensing line may be connected to the common electrode located in the first row and the first to (m-1)th columns of the common electrode, the second sensing line may be connected to the common electrode located in the nth row and the first to (m-1)th columns of the common electrode, and the third sensing line may be connected to the common electrode located in the mth column of the common electrode.

[0269] The display device may further include: a plurality of first switches, the plurality of first switches being respectively disposed between a first sensing line and a common electrode disposed in a first row and from the first to the (m-1)th column; a plurality of second switches, the plurality of second switches being respectively disposed between a second sensing line and a common electrode disposed in an nth row and from the first to the (m-1)th column; and a plurality of third switches, the plurality of third switches being respectively disposed between a third sensing line and a common electrode disposed in the mth column.

[0270] A frame period may include a display driving period in which a common voltage is provided to a common electrode and a touch driving period in which a touch driving signal is provided to a common electrode, and each of the first switch, the second switch and the third switch may be turned on during the display driving period and turned off during the touch driving period.

[0271] Multiple sensing lines may include a first sensing line, a second sensing line, and a third sensing line.

[0272] The first sensing line can be connected to at least one common electrode, the second sensing line can be connected to a multiplexer included in the source driver integrated circuit, and the third sensing line can be connected to the gate driver.

[0273] The display device may further include: a fourth clock signal line and a fifth clock signal line configured to provide a multiplexer clock signal to the multiplexer and spaced apart from each other; and a third sub-sensing line disposed between the fourth and fifth clock signal lines. The third sub-sensing line may be electrically connected to the second sensing line.

[0274] The display device may further include: a substrate; a buffer layer disposed on the substrate; a gate insulating layer disposed on the buffer layer; a third connection electrode disposed on the gate insulating layer; and an interlayer insulating layer disposed on the gate insulating layer to cover the third connection electrode. The fourth clock signal line, the fifth clock signal line, and the third sub-sensing line may be configured to be spaced apart from each other on the interlayer insulating layer.

[0275] The third sub-sensing line can be connected to the third connecting electrode through the sixth contact hole passing through the interlayer insulating layer, and the second sensing line can be connected to the third connecting electrode through the seventh contact hole passing through the interlayer insulating layer.

[0276] Although exemplary embodiments of this disclosure have been described in detail with reference to the accompanying drawings, this disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of this disclosure. Therefore, exemplary embodiments of this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of this disclosure. The scope of the technical concept of this disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit this disclosure. The scope of protection of this disclosure should be interpreted based on the claims, and all technical concepts within their equivalents should be construed as falling within the scope of this disclosure.

Claims

1. A display device, comprising: The display panel includes a plurality of pixels in an effective area of ​​the display panel and a plurality of common electrodes overlapping at least a portion of the plurality of pixels; A gate driver configured to provide gate signals to the plurality of pixels; A source driver integrated circuit, configured to provide data signals to the plurality of pixels and configured to provide a common voltage to the common electrode; as well as A noise compensation circuit is configured to receive multiple sensing signals from multiple sensing lines, wherein the multiple sensing lines are connected to the display panel, the gate driver, and the source driver integrated circuit, or to the display panel and the gate driver, or to different portions of a common electrode in the display panel. The noise compensation circuit is further configured to generate multiple inverted sensing signals by applying different gain values ​​to a signal obtained by inverting the phase of each of the multiple sensing signals, and to generate a noise compensation signal based on at least one of the multiple inverted sensing signals. The common voltage supplied to the common electrode is adjusted based on the noise compensation signal.

2. The display device according to claim 1, wherein, The plurality of common electrodes are arranged in multiple rows and multiple columns of common electrodes in the effective area.

3. The display device according to claim 2, wherein, The plurality of sensing lines include: a first sensing line connected to the first row of common electrodes that is furthest from the source driver integrated circuit; a second sensing line connected to the second row of common electrodes that is closest to the source driver integrated circuit; and a third sensing line connected to the gate driver.

4. The display device according to claim 3, further comprising: Multiple first switches, each first switch being located between the first sensing line and a corresponding common electrode in the first row of common electrodes; as well as Multiple second switches, each second switch being located between the second sensing line and a corresponding common electrode in the second row of common electrodes.

5. The display device according to claim 4, wherein, A frame cycle includes a display driving period and a touch driving period, during which a common voltage is provided to the plurality of common electrodes, and during the touch driving period, a touch driving signal is provided to the plurality of common electrodes; and The plurality of first switches and the plurality of second switches are turned on during the display driving period and turned off during the touch driving period.

6. The display device according to claim 3, further comprising: A plurality of clock signal lines configured to provide a gate clock signal to the gate driver, the plurality of clock signal lines including a first clock signal line, a second clock signal line and a third clock signal line spaced apart from each other; as well as A plurality of sub-sensing lines are electrically connected to the third sensing line. The plurality of sub-sensing lines include a first sub-sensing line located between the first clock signal line and the second clock signal line, and a second sub-sensing line located between the second clock signal line and the third clock signal line.

7. The display device according to claim 3, wherein, The noise compensator circuit includes: A first inverting circuit is configured to receive a first sensing signal from the first sensing line and, for a signal obtained by inverting the phase of the first sensing signal, output a first inverted sensing signal by applying a first gain value. The second inverting circuit is configured to receive a second sensing signal from the second sensing line, and to output a second inverted sensing signal by applying a second gain value to a signal obtained by inverting the phase of the second sensing signal. A third inverting circuit is configured to receive a third sensing signal from the third sensing line and, for a signal obtained by inverting the phase of the third sensing signal, output a third inverting sensing signal by applying a third gain value. The noise compensation signal is at least one of the first inverted sensing signal at a first time, the second inverted sensing signal at a second time, and the third inverted sensing signal at a third time.

8. The display device according to claim 7, wherein, The first gain value is greater than the second gain value and the third gain value, and the third gain value is less than the first gain value and the second gain value.

9. The display device according to claim 2, wherein, The plurality of sensing lines include: A first sensing line is connected to the following common electrode: the common electrode is the first row of common electrodes that is furthest from the source driver integrated circuit among the multiple rows of common electrodes, but excludes the common electrode in the first row that is included in the last column of common electrodes among the multiple columns of common electrodes. The second sensing line is connected to the following common electrode: the common electrode is the second row common electrode closest to the source driver integrated circuit among the multiple rows of common electrodes, excluding common electrodes in the second row that are included in the last column of common electrodes; and The third sensing line is connected to the column electrode included in the last column of common electrodes.

10. The display device according to claim 9, further comprising: Multiple first switches, each first switch being located between the first sensing line and a corresponding common electrode, the corresponding common electrode being derived from the first row of common electrodes, but excluding common electrodes in the first row that are included in the last column of common electrodes; Multiple second switches, each second switch being located between the second sensing line and a corresponding common electrode, the corresponding common electrode being from the second row of common electrodes, but excluding the common electrodes in the second row that are included in the last column of common electrodes; as well as Multiple third switches, each third switch being located between the third sensing line and the corresponding common electrode in the last column of common electrodes.

11. The display device according to claim 10, wherein, A frame cycle includes a display driving period and a touch driving period, during which a common voltage is provided to the plurality of common electrodes, and during the touch driving period, a touch driving signal is provided to the plurality of common electrodes; and Each of the plurality of first switches, the plurality of second switches, and the plurality of third switches is turned on during the display driving period and turned off during the touch driving period.

12. The display device according to claim 1, wherein, The plurality of sensing lines include a first sensing line connected to a common electrode in the display panel, a second sensing line connected to a multiplexer included in the source driver integrated circuit, and a third sensing line connected to the gate driver.

13. The display device according to claim 12, further comprising: Multiple clock signal lines are configured to provide a multiplexer clock signal to the multiplexer, the multiple clock signal lines including a first clock signal line and a second clock signal line spaced apart from the first clock signal line; as well as A third sub-sensing line is electrically connected to the second sensing line and is located between the first clock signal line and the second clock signal line.

14. A display device, comprising: The display panel includes a plurality of pixels and a plurality of common electrodes overlapping the plurality of pixels; A gate driver configured to provide gate signals to the plurality of pixels; A source driver integrated circuit, configured to provide data signals to the plurality of pixels and configured to provide a common voltage to the common electrode; Multiple sensing lines, each sensing line connected to a different part of the display device; as well as A noise compensation circuit is configured to receive multiple sensing signals from the plurality of sensing lines, indicating noise at different locations of the display device, and to generate a noise compensation signal based on the plurality of sensing signals. The common voltage supplied to the common electrode is adjusted based on the noise compensation signal.

15. The display device according to claim 14, wherein, For a signal obtained by inverting the phase of each of the plurality of sensing signals, the noise compensator circuit generates the noise compensation signal by applying different gain values, and at least one of the inverted sensing signals is the noise compensation signal.

16. The display device according to claim 14, wherein, The plurality of sensing signals include a first sensing signal indicating noise generated by the plurality of pixels, a second sensing signal indicating noise generated by the source driver integrated circuit, and a third sensing signal indicating noise generated by the gate driver, or include the first sensing signal and the third sensing signal, or include a plurality of sensing signals indicating noise generated at different portions of a common electrode in the display panel.

17. The display device according to claim 14, wherein, The plurality of common electrodes are arranged in multiple rows and multiple columns, and the plurality of sensing lines include: a first sensing line configured to receive a first sensing signal from a first row of common electrodes that is furthest from the source driver integrated circuit; a second sensing line configured to receive a second sensing signal from a second row of common electrodes that is closest to the source driver integrated circuit; and a third sensing line configured to receive a third sensing signal from the gate driver.

18. The display device according to claim 17, further comprising: Multiple first switches, each first switch being located between the first sensing line and a corresponding common electrode in the first row of common electrodes; as well as Multiple second switches, each second switch being located between the second sensing line and a corresponding common electrode in the second row of common electrodes.

19. The display device according to claim 17, further comprising: A plurality of clock signal lines configured to provide a gate clock signal to the gate driver, the plurality of clock signal lines including a first clock signal line, a second clock signal line and a third clock signal line spaced apart from each other; as well as A plurality of sub-sensing lines are electrically connected to the third sensing line to provide the third sensing signal to the third sensing line. The plurality of sub-sensing lines include a first sub-sensing line located between the first clock signal line and the second clock signal line, and a second sub-sensing line located between the second clock signal line and the third clock signal line.

20. The display device according to claim 16, wherein, The noise compensator circuit includes: A first inverting circuit is configured to receive the first sensing signal from a first sensing line and, for a signal obtained by inverting the phase of the first sensing signal, output a first inverted sensing signal by applying a first gain value. The second inverting circuit is configured to receive the second sensing signal from the second sensing line and, for a signal obtained by inverting the phase of the second sensing signal, output a second inverted sensing signal by applying a second gain value. A third inverting circuit is configured to receive the third sensing signal from a third sensing line, and, for a signal obtained by inverting the phase of the third sensing signal, output a third inverted sensing signal by applying a third gain value. The noise compensation signal is at least one of the first inverted sensing signal at a first time, the second inverted sensing signal at a second time, and the third inverted sensing signal at a third time.

21. The display device according to claim 20, wherein, The first inverted sensing signal, the second inverted sensing signal, and the third inverted sensing signal have the same amplitude.

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