RF switches, RF front-end modules, RF front-end chips and terminal equipment

Abstract

The present application discloses a radio frequency switch, a radio frequency front-end module, a radio frequency front-end chip and a terminal device, and relates to the field of communication technology. The radio frequency switch includes a first target switching channel and a second target switching channel connected to the same antenna; the radio frequency switch is used to switch between a first state and a second state; the second target switching channel includes a second series branch and a second parallel branch, the first end of the second series branch and the first end of the second parallel branch are connected to the same transmission node, the second end of the second series branch is connected to the antenna, the second end of the second parallel branch is connected to the ground terminal, the gate of each MOSFET in the second series branch is connected to the first control terminal through a first bias resistor, the gate of at least one MOSFET in the second parallel branch is connected to the second control terminal through a second bias resistor, and the second bias resistor is greater than the first bias resistor. The present application can avoid burrs during the switching process of the radio frequency switch and solve the problem of instantaneous impedance.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communication technology, and in particular to a radio frequency switch, a radio frequency front-end module, a radio frequency front-end chip and a terminal device. Background Art

[0002] With the development of mobile communication technology, the fifth generation wireless systems (5G) networking modes include standalone (SA) mode and non-standalone (NSA) mode. The NSA mode uses the long term evolution (LTE) standard and the new radio (NR) standard for networking, that is, the NSA mode supports EUTRA NR Dual-Connectivity (ENDC) technology.

[0003] At present, in NSA mode, LTE and NR work simultaneously and reuse the RF switch. Since the frequency band signal of the NR standard of time-division duplex (TDD) requires the RF switch to switch between single-on and double-on when switching the receive channel (receive, RX) and the transmit channel (transport, TX), the gain and phase of the frequency band signal of the LTE standard of frequency-division duplex (FDD) will jump, resulting in the deterioration of the error vector magnitude (EVM), which in turn affects the throughput of the FDD frequency band signal.

[0004] Therefore, a new solution is urgently needed to solve the above problems. Summary of the invention

[0005] The embodiments of the present application provide a radio frequency switch, a radio frequency front-end module, a radio frequency front-end chip and a terminal device, which can avoid glitches during the switching process of the radio frequency switch, solve the instantaneous impedance problem, and improve EVM and throughput.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, a radio frequency switch is provided, comprising a first target switching channel and a second target switching channel connected to the same antenna;

[0008] The RF switch is used to switch between a first state and a second state, the first state indicates that the first target switching channel is turned on and the second target switching channel is turned off, and the second state indicates that both the first target switching channel and the second target switching channel are turned on;

[0009] The second target switching channel includes a second series branch and a second parallel branch, a first end of the second series branch and a first end of the second parallel branch are connected to the same transmission node, a second end of the second series branch is connected to the antenna, and a second end of the second parallel branch is connected to a ground terminal;

[0010] The second series branch and the second parallel branch each include k MOSFETs, and the source and drain of the k MOSFETs are connected in sequence, k≥2, and k is an integer;

[0011] The gate of each MOSFET in the second series branch is connected to the first control terminal through a first bias resistor, and the gate of at least one MOSFET in the second parallel branch is connected to the second control terminal through a second bias resistor, and the resistance value of the second bias resistor is greater than the resistance value of the first bias resistor;

[0012] The first control end is used to receive a first control signal, and the second control end is used to receive a second control signal, and the first control signal is different from the second control signal.

[0013] Optionally, the first bias resistor is the sum of the first common resistor and the parallel resistor provided in the embodiment of the present application, and the second bias resistor is the sum of the second common resistor and the series resistor provided in the embodiment of the present application.

[0014] The embodiment of the present application makes the second bias resistor corresponding to the gate of at least one MOSFET in the second parallel branch greater than the first bias resistor corresponding to the gate of the MOSFET in the second series branch, so that when the second state is switched to the first state, the opening speed of the second parallel branch can be slowed down and the opening time can be prolonged. In this way, the situation where the second series branch and the second parallel branch are turned on at the same time can be avoided, thereby avoiding the impedance mismatch of the first target switching channel, the generation of burrs in the transmitted signal, affecting the EVM, and deteriorating the throughput.

[0015] In a possible implementation of the first aspect, a gate of at least one MOSFET in the second parallel branch is connected to the second control end through a third bias resistor, and a resistance value of the third bias resistor is smaller than a resistance value of the first bias resistor.

[0016] Optionally, the third bias resistor is the second common resistor provided in the embodiment of the present application. It should be understood that the second bias resistor and the third bias resistor are equivalent to partial resistor reuse.

[0017] The embodiment of the present application makes the third bias resistor corresponding to the gate of at least one MOSFET in the second parallel branch smaller than the first bias resistor corresponding to the gate of the MOSFET in the second series branch, so that when the first state is switched to the second state, the closing speed of the second parallel branch can be accelerated and the closing time can be shortened. Therefore, the situation where the second series branch and the second parallel branch are turned on at the same time can be avoided, thereby avoiding the impedance mismatch of the first target switching channel, the generation of burrs in the transmitted signal, the impact on EVM, and the deterioration of throughput.

[0018] In a possible implementation of the first aspect, the second series branch includes a first common node, the first common node is connected to the first control end through a first common resistor, the first common node is connected to the gate of each MOSFET in the second series branch through a first resistor, and the first bias resistor includes the first common resistor and the first resistor; the second parallel branch includes a second common node, the second common node is connected to the second control end through a second common resistor, the second common node is connected to the gate of any one MOSFET in the second parallel branch, the gates of two adjacent MOSFETs in the second parallel branch are connected through a second resistor, the second bias resistor includes the second common resistor and one or more of the second resistors, and the third bias resistor includes the second common resistor.

[0019] The first resistor is the series resistor described in the embodiment of the present application, and the second resistor is the parallel resistor described in the embodiment of the present application.

[0020] The embodiment of the present application makes the second series branch adopt parallel bias, and the second parallel branch adopts series bias; when switching from the second state to the first state, the opening speed of the second parallel branch can be slowed down and the opening time lengthened, thereby avoiding the situation where the second series branch and the second parallel branch are turned on at the same time. Similarly, when switching from the first state to the second state, the closing speed of the second parallel branch can be accelerated and the closing time length shortened, thereby avoiding the situation where the second series branch and the second parallel branch are turned on at the same time, thereby avoiding the impedance mismatch of the intermediate frequency signal, the signal generates burrs, affects the EVM, and deteriorates the throughput.

[0021] In a possible implementation of the first aspect, the source of the first MOSFET in the second parallel branch is connected to the transmission node, and the drain of the kth MOSFET is connected to the ground terminal; the second common node is connected to the gate of the first MOSFET in the second parallel branch, and the gates of two adjacent MOSFETs in the second parallel branch are connected through the second resistor.

[0022] The above is a radio frequency switch structure provided by an embodiment of the present application. Under this connection mode, when switching from the second state to the first state, the opening speed of the second parallel branch can be relatively slowed down and the opening time can be longest.

[0023] In a possible implementation manner of the first aspect, resistance values ​​of the plurality of second resistors are the same or different.

[0024] Exemplarily, from the first MOSFET to the kth MOSFET, the resistance values ​​of the connected plurality of second resistors gradually increase.

[0025] Optionally, the resistance values ​​of the plurality of second resistors may be different and have no regular variation, and may be specifically set as required.

[0026] In a possible implementation manner of the first aspect, a control switch is further connected between the second common node and the gate of the MOSFET in the second parallel branch, and a plurality of the control switches are used to be turned on under the control of a third control signal.

[0027] In this implementation, the embodiment of the present application connects a control switch between the second common node and the gate of the MOSFET in the second parallel branch, and then realizes the gating of multiple control switches through software settings, so that when the RF switch switches from the first state to the second state, different increases in the opening time and different reductions in the closing time can be realized. In other words, flexible configuration of the opening time and the closing time can be realized.

[0028] In a possible implementation manner of the first aspect, the source and the drain of each MOSFET in the second series branch and the second parallel branch are further connected via a voltage dividing resistor.

[0029] In this implementation, the voltage dividing resistor is used to make the gate-source voltage Vgs of each MOSFET have the same voltage magnitude, thereby achieving average voltage division.

[0030] In a possible implementation manner of the first aspect, the second series branch and the second parallel branch are configured not to be turned on in the same time period.

[0031] The embodiment of the present application avoids the situation where the second series branch and the second parallel branch are turned on at the same time when the RF switch is switched from the first state to the second state, or when the RF switch is switched from the second state to the first state, thereby avoiding the impedance mismatch of the intermediate frequency signal and the generation of burrs in the signal, thereby avoiding affecting the EVM and deteriorating the throughput.

[0032] Exemplarily, in an ENDC scenario, the first state may indicate a B3 single state, and the second state may indicate a B3+N41CA state.

[0033] In a possible implementation manner of the first aspect, the second series branch and the second parallel branch are configured to be disconnected in different time periods or in the same time period.

[0034] It should be understood that in this implementation, when the second series branch and the second parallel branch are disconnected at the same time, for the second series branch, the impedance of the second parallel branch is equivalent to being infinite, and does not affect the impedance of the first target switching channel.

[0035] In a possible implementation manner of the first aspect, when the first target switching channel is turned on, it is used to implement reception and transmission of intermediate frequency signals, and when the second target switching channel is turned on, it is used to implement reception of TDD mode signals.

[0036] In a possible implementation of the first aspect, the RF switch is applied to an ENDC scenario; the intermediate frequency signal includes at least one of the following frequency bands: B1, B2, B3, B34, B39; and the TDD mode signal includes at least one of the following frequency bands: N41, N40.

[0037] In a possible implementation of the first aspect, the RF switch is applied to a DSDS scenario or a DSDA scenario; the intermediate frequency signal includes at least one of the following frequency bands: N1, N2, N3, B1, B2, B3, B34, B39; the TDD mode signal includes at least one of the following frequency bands: B40, B41, N41, N40.

[0038] In a second aspect, a radio frequency front-end module is provided, which includes a first communication link and a second communication link, wherein the first communication link and the second communication link are used to connect to at least the same antenna through a radio frequency switch as described in the first aspect or any one of the first aspects; when the first target switching channel in the radio frequency switch is turned on, the first communication link receives and transmits intermediate frequency signals through the antenna; when the second target switching channel in the radio frequency switch is turned on, the second communication link receives TDD mode signals through the antenna.

[0039] In a third aspect, a radio frequency front-end chip is provided, comprising the radio frequency front-end module described in the second aspect.

[0040] In a fourth aspect, a terminal device is provided, which includes an RF transceiver chip and the RF front-end chip as described in the third aspect, and an antenna subsystem, wherein the antenna subsystem includes the antenna; the RF transceiver chip is connected to the first control end and the second control end, and outputs the first control signal to the first control end and outputs the second control signal to the second control end to control the conduction or disconnection of the second series branch and the second parallel branch in the RF switch.

[0041] In a possible implementation of the fourth aspect, when the RF front-end module includes a control switch, the terminal device also includes a MIPI register, and the MIPI register connects multiple control switches and outputs the third control signal to the multiple control switches to control the selection of the multiple control switches.

[0042] In this implementation, different control signals can be set to be output through the MIPI register to control the gating of multiple second control switches, so that the access position of the common resistor Rcom in the second parallel branch can be adjusted, and the length of the on and off time can be controlled.

[0043] In a possible implementation of the fourth aspect, the terminal device also includes a power subsystem, and the power subsystem is used to provide voltage to the RF front-end module.

[0044] The beneficial effects of the second to fourth aspects can refer to the beneficial effects of the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of a scenario applicable to an embodiment of the present application;

[0046] Figure 2 A schematic diagram of the structure of a terminal device provided in an embodiment of the present application;

[0047] Figure 3 A schematic diagram of the structure of the connection between a radio frequency subsystem and an antenna subsystem provided in an embodiment of the present application;

[0048] Figure 4 It is a structural schematic diagram of a radio frequency front-end module in the related art;

[0049] Figure 5 for Figure 4 The equivalent structural diagram of the corresponding RF front-end module;

[0050] Figure 6 for Figure 5 A schematic diagram of a circuit structure of a second switching channel;

[0051] Figure 7 for Figure 5 The corresponding circuit diagrams in B3 single state and B3+N41 CA state;

[0052] Figure 8 for Figure 7 The corresponding opening and closing timing diagram;

[0053] Fig. 9is a circuit schematic diagram when the second series branch and the second parallel branch are both turned on;

[0054] Fig.10 The opening and closing timing diagram corresponding to the second switching channel provided in the embodiment of the present application;

[0055] Fig.11 A schematic diagram of an equivalent structure of a radio frequency front-end module provided in an embodiment of the present application;

[0056] Fig.12 A schematic diagram of the structure of the second target switching channel provided in an embodiment of the present application;

[0057] Fig.13 A schematic diagram of the structure of a second parallel branch in a second target switching channel provided in an embodiment of the present application;

[0058] Fig.14 for Fig.13 A schematic diagram of the opening and closing time of the corresponding second parallel branch;

[0059] Fig.15 A schematic diagram of the structure of another second parallel branch provided in an embodiment of the present application;

[0060] Fig.16 A schematic diagram of the structure of another second parallel branch provided in an embodiment of the present application.

[0061] Reference numerals:

[0062] 1-terminal device; 10-baseband subsystem; 20-RF subsystem; 21-RF transceiver chip; 22-RF front-end module; 221-first communication link; 222-second communication link; 223-antenna switch; 2231-first switching channel; 2232-second switching channel; 224-target antenna switch; 2241-first target switching channel; 2242-second target switching channel; 30-antenna subsystem; 40-power subsystem. DETAILED DESCRIPTION

[0063] The technical solutions in the embodiments of the present application will be described clearly and in detail below in conjunction with the accompanying drawings. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in the text is only a description of the association relationship of the associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0064] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as suggesting or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features, and in the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0065] First, some terms in the embodiments of the present application are explained to facilitate understanding by those skilled in the art.

[0066] 1. Transmit (TX)

[0067] In the field of communications, transmission refers to the act of sending data from one device to another device or a group of devices.

[0068] 2. Receive (Receive, RX)

[0069] In the field of communications, reception refers to the process of converting transmitted signals into perceptible information.

[0070] 3. FDD and TDD

[0071] FDD mode refers to the working mode of RX channel and TX channel in different frequency channels; TDD mode refers to the working mode of RX channel and TX channel in the same frequency channel. It can be understood that in FDD mode, RX channel and TX channel work at the same time; in TDD mode, RX channel and TX channel work in time-sharing; therefore, for the frequency band signal applied to FDD mode, its RX channel and TX channel need to be configured with different filters, while for the frequency band signal applied to TDD mode, its RX channel and TX channel can reuse the same filter.

[0072] 4. Bx and Nx

[0073] B is the beginning of the frequency band number of the LTE standard, N is the beginning of the frequency band number of the NR standard, and x is the frequency band number. Bx represents the frequency band corresponding to the LTE frequency band number x; Nx represents the frequency band corresponding to the NR frequency band number x. For example, B3 represents the frequency band corresponding to the LTE frequency band number 3, the frequency range corresponding to the B3 uplink frequency band is 1710MHz~1785MHz, and the frequency range corresponding to the B3 downlink frequency band is 1805MHz~1880MHz; B41 represents the frequency band corresponding to the LTE frequency band number 41, that is, 2496MHz~2690MHz; N41 represents the frequency band corresponding to the NR frequency band number 41, and the frequency range corresponding to the uplink frequency band and the downlink frequency band is the same, that is, 2496MHz~2690MHz.

[0074] 5. LB, MB, HB

[0075] LB refers to low frequency band (LB); MB refers to middle frequency band (MB); HB refers to high frequency band (HB), and MHB refers to middle and high frequency band (MHB middle & high frequency band). It should be understood that low frequency, middle frequency, middle and high frequency, and high frequency refer to the relative high and low frequencies, and the frequency band division can be adjusted as needed, and middle and high frequency include middle frequency and high frequency.

[0076] 6. Power amplifier module within integrated duplexer (PAMiD)

[0077] In order to reduce the area occupied by the RF front end, the power amplifier (PA), filter, duplexer and RF switch are integrated into one chip to form PAMiD.

[0078] 7. Power amplifier module with integrated low noise amplifier (LNA) (LNA and power amplifier module with integrated duplexer, LPAMiD)

[0079] LNA is further integrated on the basis of PAMiD to form LPAMiD.

[0080] 8. Error vector magnitude (EVM)

[0081] EVM refers to the difference between the theoretical waveform and the actual waveform received, and is the root mean square value of the ratio of the average error vector signal power to the average reference signal power. Generally, the global system for mobile communications (GSM) requires ≤6% (RMS), and wideband code division multiple access (WCDMA) requires ≤12.5% ​​(RMS).

[0082] 9. RC time constant

[0083] The RC time constant represents the constant of the time process of the transient reaction. In a resistor and capacitor circuit, it is the product of the resistor and the capacitor. If the unit of C is F (farad), the unit of R is Ω (ohm), and the unit of the time constant is seconds.

[0084] 10. Dual Sim Dual Standby (DSDS) and dual SIM dual active (DSDA)

[0085] Terminal devices that support two mobile phone cards or subscriber identity modules (SIM) are called dual-card terminal devices. Currently, dual-card terminal devices on the market can be mainly divided into two forms: dual-card dual standby single-channel terminal and dual-card dual standby dual-channel terminal. Dual-card dual standby means that both cards are waiting for network paging and are available. Dual-card single-channel means that the two cards share a channel when on standby. At this time, the terminal device needs to switch quickly to ensure that both cards can interact with the base station, but when one card is making a call, the other card cannot interact with the base station. Dual-card dual-channel means that the two cards can interact with the base station in real time respectively. When one card is making a call, it does not affect the interaction and use of the other card.

[0086] The above is a brief introduction to the nouns involved in the embodiments of the present application, which will not be repeated below.

[0087] Figure 1 The present invention is a schematic diagram of a scenario applicable to an embodiment of the present application.

[0088] The user can communicate using the terminal device 1. The embodiment of the present application does not specifically limit the type of the terminal device 1. In some embodiments, the terminal device 1 in the embodiment of the present application can be a mobile phone, a wearable device (such as a smart bracelet, a smart watch, a headset, etc.), a tablet computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a cellular phone, a personal digital assistant (personal digital assistant, PDA), an augmented reality (Augmented reality, AR)\virtual reality (virtual reality, VR) device and other IOT (internet of things, Internet of Things) devices, and can also be a television, a large screen, a printer, a projector and other devices. For ease of understanding, the following embodiments are exemplified by taking the terminal device 1 as a mobile phone as an example.

[0089] Figure 2 A schematic diagram of the structure of a terminal device provided in an embodiment of the present application.

[0090] The terminal device 1 may include a baseband subsystem 10, a radio frequency subsystem 20 consisting of a radio frequency integrated circuit (RFIC) and a radio frequency front end (RFFE), an antenna (ANT) subsystem 30, a power subsystem 40, etc. These devices may be coupled via various interconnection buses or other electrical connection methods.

[0091] The baseband subsystem 10 can extract useful information or data bits from the baseband signal, or convert the information or data bits into a baseband signal to be sent. These information or data bits can be data representing user data or control information such as voice, text, video, etc. Exemplarily, the baseband subsystem 10 can implement signal processing operations such as modulation and demodulation, encoding and decoding. Different baseband signal processing operations can be provided for different wireless access technologies, such as 5G NR and 4G LTE. Therefore, in order to support multiple mobile communication modes, the baseband subsystem 10 may include multiple processing cores or multiple hardware accelerators (HAC) at the same time. The baseband subsystem 10 can be integrated into one or more chips.

[0092] Exemplarily, the baseband subsystem 10 can be used as an independent chip, which can be called a modem chip. The hardware components of the baseband subsystem 10 can be manufactured and sold in units of modem chips. Modem chips can also be called baseband chips or baseband processors. In addition, the baseband subsystem 10 can also be further integrated in a system on chip (system on chip technology, SOC) chip, which can be manufactured and sold in units of SOC chips. The software components of the baseband subsystem 10 can be built into the hardware components of the chip before the chip leaves the factory, or can be imported from other non-volatile memories into the hardware components of the chip after the chip leaves the factory, or these software components can be downloaded and updated online through the network.

[0093] In addition, since the radio frequency signal is an analog signal, the signal processed by the baseband subsystem 10 is mainly a digital signal, and an analog-to-digital converter device is also required in the electronic device. The analog-to-digital converter device includes an analog-to-digital converter (ADC) that converts an analog signal into a digital signal, and a digital-to-analog converter (DAC) that converts a digital signal into an analog signal. It should be understood that the analog-to-digital converter device can be set in the baseband subsystem 10 or in the radio frequency subsystem 20, and the embodiment of the present application does not impose any restrictions on this.

[0094] The RF subsystem 20 can be divided into an RF receive path and an RF transmit path. The RF receive path can receive RF signals through an antenna, process the RF signals, such as amplification, filtering, down-conversion and analog-to-digital conversion, to obtain baseband signals, and transmit them to the baseband subsystem 10. The RF transmit path can receive baseband signals from the baseband subsystem 10, process the baseband signals, such as up-conversion, amplification, filtering and digital-to-analog conversion, to obtain RF signals, and radiate the RF signals into space through an antenna. Specifically, the RF subsystem 20 may include electronic devices such as RF switches, duplexers, antenna tuners, low noise amplifiers (LNA), power amplifiers, mixers, local oscillators (LO), filters, etc., which can be integrated into one or more chips as needed. The antenna can sometimes also be considered as part of the RF subsystem 20.

[0095] Exemplarily, the above electronic devices can be separately arranged in the antenna, the RF front-end module 22 and the RF transceiver chip 21 as needed. The RF transceiver chip 21 can be composed of devices such as a mixer and a local oscillator. Among them, the local oscillator is used to provide a local oscillator signal; the mixer is used to mix the RF signal with the local oscillator signal provided by the local oscillator. The RF transceiver chip 21 can also be called a receiver, a transmitter or a transceiver.

[0096] The RF front-end module 22 can be composed of electronic devices such as filters, low-noise amplifiers, power amplifiers, and RF switches. The RF switch is used to switch between receiving and transmitting RF signals and between different frequency bands; the duplexer is used to isolate the transmitting and receiving paths of the RF signal, thereby ensuring that the receiving and transmitting can work normally when sharing the same antenna; the filter is used to retain the signal within a specific frequency band and filter out the signal outside the characteristic frequency band. The low-noise amplifier is used to amplify the RF signal of the receiving channel; the power amplifier is used to amplify the RF signal of the transmitting path.

[0097] Here, the RF transceiver chip 21 can output control signals to components such as RF switches in the RF front-end module 22 through control lines to control the RF switches to switch between different links.

[0098] In the embodiment of the present application, the radio frequency switch may include an antenna switch, and may also include a first switch, a second switch, and the like.

[0099] It should be understood that the above is only an example, and the RF subsystem 20 may also include other devices or adopt other integration methods. For example, some devices belonging to the RF front-end module 22 may be integrated into the RF transceiver chip 21, or the antenna and the RF front-end module 22 may be integrated into the RF transceiver chip 21. The specific settings and modifications can be made as needed, and the embodiments of the present application do not impose any restrictions on this.

[0100] The antenna subsystem 30 includes multiple antennas, where ANT1 represents the first antenna, ANTn represents the nth antenna, and n is a positive integer greater than 1. The antenna subsystem 30 may also include an antenna switch for switching to different antennas so that different signals can be transmitted using different antennas.

[0101] The power subsystem 40 is used to supply power to various devices, for example, the power supply can provide voltage to the power amplifier. The power subsystem 40 may include multiple power supplies, which may be the same or different.

[0102] The terminal device 1 may also include two SIM cards, for example, respectively referred to as a first SIM card and a second SIM card. The first SIM card and the second SIM card may be installed on a circuit board inside the terminal device 1, and the baseband subsystem 10 and the radio frequency subsystem 20 described above may also be arranged on the circuit board. The first SIM card may be used as an information storage device to store the user's identity information, such as a telephone number used to indicate the user's identity. In addition, the first SIM card may also be used to store the user's personal information, such as a key used to encrypt voice content during a voice call, the user's phone book, etc. Among them, the SIM card is also called a user identity card, a smart card, etc.

[0103] It should be noted that, only after the first SIM card is installed on the terminal device 1, the terminal device 1 can communicate with the base station 2 or other terminal devices 1 through the information stored on the first SIM card.

[0104] The second SIM card is also installed on the circuit board inside the terminal device 1. Usually, the second SIM card and the first SIM card are installed on the same circuit board. The second SIM card can also be used as an information storage device to store user identification information, user personal information, etc.

[0105] The user identity information stored on the second SIM card is different from the user identity information stored on the first SIM card. For example, the first SIM card stores the user's first identity information, such as a first telephone number used to indicate the user's identity. The second SIM card stores the user's second identity information, such as a second telephone number used to indicate the user's identity. In addition, the user personal information stored on the first SIM card and the user personal information stored on the second SIM card may be the same or partially the same, or may be different.

[0106] It should be noted that, only after the second SIM card is installed on the terminal device 1, the terminal device 1 can communicate with the base station 2 or other terminal devices 1 through the information stored on the second SIM card.

[0107] Exemplarily, the first SIM card can be called a primary card, and the second SIM card can be called a secondary card. Of course, the second SIM card can also be used as a primary card, and the first SIM card can also be used as a secondary card, and the embodiment of the present application does not impose any restrictions on this. Among them, the primary card can be understood as the SIM card used by the user when performing single-card communication.

[0108] In addition, the terminal device 1 may also include an application subsystem, which may serve as the main control system or main computing system of the terminal device 1, for running the main operating system and application programs, managing the software and hardware resources of the entire terminal device 1, and providing a user operation interface for the user. The application subsystem may include one or more processing cores. In addition, the application subsystem may also include driver software related to other subsystems (such as the baseband subsystem 10). The baseband subsystem 10 may also include one or more processing cores, as well as hardware accelerators and caches, etc.

[0109] It should be understood that the above is only an example of the structure of the terminal device 1, and the terminal device 1 may also include other subsystems or components, which can be configured and modified as needed, and the embodiments of the present application do not impose any limitations on this.

[0110] like Figure 2As shown in the figure, with the widespread application of 5G with higher transmission efficiency, the current 5G networking modes include NSA and SA modes. Among them, the NSA mode introduces dual connection (DC) technology to support the terminal device 1 to connect to the 4G base station and the 5G base station at the same time. According to the different roles of the two base stations, the 4G base station and the 5G base station, the DC architecture in the NSA mode can be divided into three architectures: ENDC, NR-EUTRA Dual-Connection (NEDC), and NG-RAN E-UTRA-NR Dual-Connectivity (NGEN-DC).

[0111] In addition, when working in the TDD frequency band under the NR standard, a sounding reference signal (SRS) service is required, that is, SRS is sent to the base station through multiple antennas to help the base station achieve more accurate beamforming, thereby achieving a better downlink experience for the terminal equipment.

[0112] In an embodiment provided in the present application, the ENDC architecture of the terminal device 1 supporting MB+N41 in the NSA mode is taken as an example. Figure 3 As shown, the signals transmitted between the RF transceiver chip and the RF front-end module may include: MB transmission signal, MB reception signal, N41 transmission signal, N41 reception signal, and N41 SRS signal, etc. Among them, the MB transmission signal refers to the transmission signal whose frequency is in the frequency band corresponding to MB, and the MB reception signal refers to the reception signal whose frequency is in the frequency band corresponding to MB; the N41 transmission signal refers to the transmission signal whose frequency is in the frequency band corresponding to N41, and the N41 reception signal refers to the reception signal whose frequency is in the frequency band corresponding to N41. The SRS signal of N41 refers to the SRS signal whose frequency is in the frequency band corresponding to N41.

[0113] exist Figure 3 On the basis of Figure 4 A schematic diagram of LPAMiD of an ENDC architecture provided for related technologies. Figure 4 As shown, for example, the module can realize the simultaneous operation of MHB and N41, thereby meeting the ENDC requirements of MHB+N41. Among them, MHB can include B1, B2, B3, B34, and B39.

[0114] exist Figure 4In the LPAMiD, an intermediate frequency port MB_IN, a high frequency port HB_IN and multiple antenna ports for connecting antennas are configured. The intermediate frequency port MB_IN is used to receive 4G signals of multiple intermediate frequency bands emitted by RFIC. The first communication link 221 in the LPAMiD can filter and amplify the input multiple intermediate frequency 4G signals, and transmit them through the antenna connected to the antenna port to achieve transmission control of multiple intermediate frequency 4G signals. The high frequency port HB_IN is used to receive high-frequency 4G signals and 5G signals (such as N41 signals) emitted by RFIC. The second communication link 222 in the LPAMiD can filter and amplify the input high-frequency 4G signals and 5G signals, and transmit them through the antenna connected to the antenna port to achieve transmission control of high-frequency 4G signals and 5G signals. The antenna is also used to receive 4G signals and 5G signals. Then, the LPAMiD can filter and amplify the input signals and transmit the processed signals to the RFIC to achieve reception control of 4G signals and 5G signals. The antenna switch can connect the first communication link 221, the second communication link 222 and multiple antenna ports for performing antenna switching under the control of the RFIC.

[0115] Exemplarily, taking the B3 signal + N41 signal as an example, the first communication link 221 is connected to the intermediate frequency port MB_IN and the antenna switch 223 respectively, and can be used for receiving and transmitting the B3 signal; the second communication link 222 is connected to the high frequency port HB_IN and the antenna switch 223 and the antenna switch 224 respectively, and can be used for receiving and transmitting the N41 signal. Among them, the first communication link 221 can include an intermediate frequency power amplifier MB_PA, a first switch and a duplexer in sequence, MB_PA is connected to the intermediate frequency port MB_IN, and the duplexer is connected to the antenna switch 223; the second communication link 222 can include a high frequency power amplifier HB_PA, a second switch and a TRX filter in sequence, HB_PA is connected to the high frequency port HB_IN, and the TRX filter is connected to the antenna switch 223 and the antenna switch 224. Among them, the antenna switch 223 is integrated inside the RF front-end module, but the antenna switch 224 is not integrated inside the RF front-end.

[0116] Specifically, when the antenna switch 223 connects the first communication link 221 to the first antenna ANT1 under the control of the RFIC, the first antenna ANT1 can serve as the common end for the main set reception and transmission of the intermediate frequency signal, and is responsible for the reception (TX) and main set reception (PRX) of the B3 signal; when the antenna switch 223 connects the first communication link 221 to the second antenna ANT2 under the control of the RFIC, the second antenna ANT2 is responsible for the diversity reception of the B3 signal. When the antenna switch 224 connects the second communication link 222 to the third antenna ANT3 and the fourth antenna ANT4 under the control of the RFIC, the third antenna ANT3 is responsible for the main set reception and transmission of N41, and the fourth antenna ANT4 is responsible for the diversity reception of N41. The first antenna ANT1 and the second antenna ANT2 also serve as the MIMO1 antenna and the MIMO2 antenna that support multiple input multiple output (MIMO) of the N41 signal. It should be understood that MIMO is used to indicate that multiple antennas are used in transmission and reception to form multiple channels, greatly improving the channel capacity.

[0117] When the N41 signal performs SRS polling of 1T4R, the antenna switch 223 and the antenna switch 224 will, under the control of the RFIC, turn on the second communication link 222 and the first antenna ANT1 to the fourth antenna ANT4 in turn, so that the N41 signal can be transmitted in turn on the first antenna ANT1 to the fourth antenna ANT4, wherein the N41 signal will be transmitted on the first antenna ANT1, the second antenna ANT2, and the fourth antenna ANT4 for one symbol time respectively. The third antenna ANT3 is the main transmitting antenna of the N41 signal. Except for the SRS of one symbol time, the transmission of other uplink time slots is completed on ANT3. In addition, when receiving the N41 signal, the first antenna ANT1 to the fourth antenna ANT4 simultaneously receive the N41 signal.

[0118] like Figure 4 As shown in (a), since the N41 signal belongs to the TDD mode, in the downlink receiving time slot of N41, the B3 duplexer (duplex, DUP) in the first communication link 221 and the TRX filter of N41 in the second communication link 222 are simultaneously connected to the first antenna ANT1, and the reception of the B3 signal and the reception of the N41 signal are performed through the same antenna, that is, the B3 duplexer and the TRX filter of the N41 signal are both turned on (or share the same antenna) to achieve carrier aggregation (CA). This state can also be called the antenna switch 223 is in a double-on mode, and the first antenna ANT1 receives the B3 signal and the N41 signal at the same time to increase the bandwidth and the downlink transmission rate. Figure 4As shown in (b), in the uplink transmission time slot of the N41 signal, most of the N41 signal is transmitted on the third antenna ANT3, and the B3 signal is transmitted through the first antenna ANT1. The transmission of the B3 signal and the transmission of the N41 signal are performed on separate antennas, that is, the B3 duplexer and the TRX filter of the N41 signal are unlocked (or there is no shared antenna). This state can also be called the single-open mode of the antenna switch 223.

[0119] Therefore, combined with Figure 4 (a) and Figure 4 In the structure shown in (b), when the N41 signal is switched uplink / downlink (U / D), the antenna switch 223 switches from single-open mode to dual-open mode, or from dual-open mode to single-open mode, and this switching will cause impedance mismatch of the B3 signal, affecting the EVM of the transmission and reception of the B3 signal. This problem can be called a steady-state impedance problem. In addition, in addition to the steady-state impedance problem, the switching of the antenna switch 223 between single-open and dual-open will also cause transient impedance problems (detailed analysis will be performed later). It should be understood that this problem will also occur under the conditions of transmitting and receiving signals in other frequency bands.

[0120] In one possible implementation, the discontinuity can be reduced by optimizing the design of the matching network (phase shifter), thereby optimizing the steady-state impedance change and improving the steady-state EVM. The matching network can be a matching circuit composed of multiple inductors and / or multiple capacitors. However, this method can only solve the steady-state impedance problem, and still cannot solve the transient impedance problem.

[0121] In another possible implementation, a B41 RX filter is added to the LPAMiD. During the uplink and downlink switching of the N41 signal, the B41 RX filter always works in the dual-on state of the B3 signal + N41 signal. Thus, the steady-state impedance can be kept continuous to solve the impact caused by the uplink and downlink switching of the N41 signal. However, when the SRS signal of N41 is transmitted to the TRX antenna of MB, similar problems of the above-mentioned state switching will still occur. At this time, even if a matching network is also set up, it is still only possible to reduce the discontinuity to optimize the steady-state impedance change and improve the steady-state EVM, but the transient impedance problem cannot be solved.

[0122] Therefore, a new solution is urgently needed to solve the above-mentioned transient impedance problem.

[0123] In view of this, an embodiment of the present application provides a radio frequency switch, including a first target switching channel and a second target switching channel, the first target switching channel and the second target switching channel are connected to the same antenna, the first target switching channel is used to receive and transmit intermediate frequency signals when it is turned on, and the second target switching channel is used to receive TDD mode signals when it is turned on.

[0124] The second target switching channel includes a second series branch and a second parallel branch. In the embodiment of the present application, the gate bias of the second series branch is set to a parallel bias, and the gate bias of the second parallel branch is set to a series bias. By slowing down the opening speed of the second parallel branch and speeding up the closing speed, the working timing of the switch is coordinated, so that when the second target switching channel is switched from on to off, or from off to on, the second series branch and the second parallel branch are prevented from being turned on at the same time, thereby avoiding the problem of instantaneous impedance at the switching moment, that is, severe impedance mismatch, generating burrs, avoiding affecting EVM, and deteriorating throughput.

[0125] Furthermore, the gate bias voltage of the second parallel branch can be set by software, so that the software can flexibly configure the start-up time.

[0126] Combine the following Figures 5 to 14 , a specific analysis is made on the generation of the transient impedance problem, and a detailed introduction is given to the RF front-end module provided in the embodiment of the present application. Figure 5 It is a schematic diagram of the equivalent structure of a radio frequency front-end module.

[0127] like Figure 5 As shown, Figure 4 When the first communication link 221 is connected to the first antenna ANT1 through the antenna switch, the antenna switch may include a first switching channel 2231 and a second switching channel 2232, the first switching channel is respectively connected to the first communication link 221 and the antenna port a1; the second switching channel is respectively connected to the second communication link 222 and the antenna port a1, and the antenna port a1 is connected to the first antenna ANT1. In this way, the first switching channel can be turned on or off under the control of the RFIC, thereby controlling the conduction or disconnection between the first communication link 221 and the first antenna ANT1, and the second switching channel can be turned on or off under the control of the RFIC, thereby controlling the conduction or disconnection between the second communication link 222 and the first antenna ANT1.

[0128] Alternatively, if Figure 5 As shown, the first switching channel may include a first series branch, which may be equivalently represented as a switch S1. When the switch S1 is closed, the first switching channel may be turned on; when the switch S1 is opened, the first switching channel may be turned off.

[0129] Similarly, if Figure 5 As shown, the second switching channel may include a second series branch, and the second series branch may be equivalently illustrated as a switch S2. When the switch S2 is closed, the second switching channel may be turned on; when the switch S2 is opened, the second switching channel may be turned off.

[0130] On this basis, a first parallel branch may be connected to the node b1 where the first communication link 221 is connected to the first series branch, and the first parallel branch may be equivalently represented as a switch P1 with one end connected to the node b1 and the other end connected to the ground, so as to achieve enhanced isolation. Similarly, a second parallel branch may be connected to the node b2 where the second communication link 222 is connected to the second series branch, and the second parallel branch may be equivalently represented as a switch P2 with one end connected to the node b2 and the other end connected to the ground.

[0131] It should be noted that if the second parallel branch is cancelled, or if the switch P2 is opened when the switch S2 is closed, the insertion loss of the radio frequency signal may be affected, thereby increasing the insertion loss of the radio frequency signal.

[0132] exist Figure 5 On the basis of Figure 6 A schematic diagram of the circuit structure of a second switching channel provided in the related art is shown.

[0133] like Figure 6 As shown, the switch S2 in the second series branch and the switch P2 in the second parallel branch have the same circuit structure, both of which are composed of multiple MOSFETs connected in series; in addition, the gate bias of the MOSFET adopts the form of parallel resistors, that is, each MOSFET gate is connected in series with a resistor, and multiple resistors are in parallel relationship, and the common node of the multiple resistors is connected in series with a common resistor; a voltage divider resistor is also connected between the source and drain of each MOSFET. In addition, the common resistor corresponding to the switch S2 is connected to the control port VCT1, and the common resistor corresponding to the switch P2 is connected to the control port VCT2.

[0134] Based on the above circuit structure, by adjusting the signal magnitudes of the control port VCT1 and the control port VCT2, the switch S2 and the switch P2 can be turned on and / or off, thereby realizing the on and off switching of the second switching channel.

[0135] It should be noted that, since the equivalent resistance will become smaller after the parallel resistors connected to the gates of multiple MOSFETs in the switch S2 or the switch P2 are connected in parallel, it is necessary to add a common resistor with a larger resistance value to increase the impedance of the circuit and reduce leakage. For example, the resistance value of the common resistor can be 10k.

[0136] It should also be noted that in order to make the gate-source voltage Vgs of each MOSFET have the same voltage magnitude and realize average voltage division, a voltage dividing resistor needs to be connected between the source and drain of each MOSFET. For example, the resistance value of the voltage dividing resistor can be 10k.

[0137] It should be understood that the larger the MOSFET area, the more charge it can hold, resulting in a wider path for current flow, and therefore, a smaller on-resistance; the smaller the on-resistance, the smaller the loss. For the MOSFET in the second parallel branch, if the area is larger, it is equivalent to a smaller grounding resistance of the b2 node when it is turned on, and the signal leaked to the b2 node is directly absorbed into the ground, achieving a better isolation effect; but when it is turned off, it is equivalent to connecting a larger equivalent capacitor in parallel to the second series branch, resulting in a larger insertion loss. Therefore, compared with the two, considering the greater impact of insertion loss, the area of ​​the MOSFET in the second parallel branch is generally smaller than the area of ​​the MOSFET in the second series branch. For example, the width of the MOSFET gate in the second parallel branch is 500μm~1000um, and the width of the MOSFET gate in the second series branch is 1500μm~3000um.

[0138] Since the MOSFET area of ​​the second parallel branch is smaller than that of the second series branch, when the resistance is the same, the RC time constant of the second parallel branch is smaller than that of the second series branch. Therefore, the second parallel branch is turned on and off faster than the second series branch. For the MOSFET itself, the turn-on speed is also faster than the turn-off speed.

[0139] Combined with the above Figure 5 and Figure 6 The circuit structure diagram shown in Figure 7 (a) in FIG. 1 shows the circuit diagram corresponding to the B3 single state. Figure 7 (b) shows the circuit diagram corresponding to the B3+N41 CA state. Figure 8 Shows Figure 7 The corresponding opening and closing timing diagram, Fig. 9 A circuit schematic diagram is shown when both the second series branch and the second parallel branch are turned on.

[0140] When switching from the B3+N41 CA state to the B3 single state, that is, from Figure 7 The circuit structure shown in (b) is switched to Figure 7In the circuit structure shown in (a), at the moment when switch P2 switches from off to on and switch S2 switches from on to off, since the time constant of the second parallel branch (equivalent to switch P2) is smaller than the time constant of the second series branch (equivalent to switch S2), the time for switch P2 to switch from off to on is smaller than the time for switch S2 to switch from on to off. Therefore, at a certain moment, switch P2 and switch S2 may be turned on at the same time.

[0141] For example, Figure 8 As shown in (a) in the figure, for example, at time t1, switch P2 starts to switch from off to on, and switch S2 switches from on to off. The switching time of switch P2 is very short. Assuming that at time t2 after time t1, switch P2 is in the on state, then the time t12 between time t1 and time t2 can be considered as the corresponding on time of switch P2; however, the switching time of switch S2 is relatively long (the actual time is actually very short, the figure is not drawn to scale, it is only for illustration), assuming that the switching is completed at time t3, then the time period t13 between time t1 and time t3 can be considered as the corresponding off time of switch S2, which is still in the on state; at this time, it is equivalent to that in the short period of time t23, switch P2 and switch S2 are turned on at the same time, that is, Fig. 9 As shown in (a), at this moment, switch P2 and switch S2 are both closed.

[0142] At the moment of switching from the B3 single state to the B3+N41 CA state, that is, from Figure 7 The circuit structure shown in (a) is switched to Figure 7 In the circuit structure shown in (b), at the moment when switch P2 switches from on to off and switch S2 switches from off to on, since the turn-on speed of MOSFET itself is faster than the turn-off speed, even if the time constant of switch S2 is greater than the time constant of switch P2, it is possible that the turn-on speed of switch S2 is faster than the turn-off speed of switch P2. In this case, switch S2 and switch P2 may be turned on at the same time.

[0143] For example, Figure 8As shown in (b) in FIG. 4 , for example, at time t4, switch P2 starts to switch from on to off, and switch S2 switches from off to on. Since switch S2 is turned on faster and for a shorter time, assuming that switch S2 is in the on state at time t5 after time t4, the time t45 between time t4 and time t5 can be considered as the corresponding on time of switch S2. However, switch P2 is turned off relatively slowly and the process is longer (the actual time is also very short). Assuming that the switching is completed at time t6, switch P2 can be considered to be still in the on state during the time period t46 between time t4 and time t6. At this time, it is equivalent to that switch P2 and switch S2 are still turned on at the same time during the short time t56, that is, as shown in FIG. Fig. 9 As shown in (a), at this moment, switch P2 and switch S2 are both closed.

[0144] Combination Fig. 9 In the circuit shown in (a), if switch S2 and switch P2 are turned on at the same time, it is equivalent to saying that the second series branch and the second parallel branch are turned on at the same time, which will cause the impedance of the second switching channel including the second series branch and the second parallel branch to become very small. Combined with the above example of B3+N41, if switch S2 and switch P2 are turned on at the same time, the impedance of branch N41 will become very small (close to short circuit to ground), which will cause the impedance of duplexer B3 to deviate and cause serious mismatch, which will cause the phase and amplitude of B3 to change.

[0145] For example, assuming that switch S2 and switch P2 are turned on at the same time, the impedance of switch P2 is about 5Ω, and the impedance of switch S2 is about 2Ω. The sum of the two is equivalent to a total impedance of the grounded N41 branch of about 7Ω; if the original impedance of the B3 branch is about 50Ω, then the impedance is only 6.14Ω after being connected in parallel with the 7Ω N41 branch, which is equivalent to an impedance deviation of 43.86Ω, which is a serious deviation.

[0146] It should be noted that, in the embodiment of the present application, the magnitude of the impedance is approximately equal to the magnitude of the resistance.

[0147] For example, Fig. 9 As shown in (b) in the figure, in the two different states of B3 single state and B3+N41 CA state, the impedance of the B3 branch is inevitably different. Therefore, the gain of the B3 signal is different. In addition, in the two states of B3 single state and B3+N41 CA state, the size of the B3 signal will be different. This is exactly the steady-state impedance change mentioned above. In addition, Fig. 9As shown in (b), at the moment of switching from the B3 single state to the B3+N41 CA state, since the switch P2 and the switch S2 are turned on at the same time, the impedance of the N41 branch becomes smaller, causing the phase and amplitude of the B3 signal to change dramatically (this change is greater than the change in the steady-state impedance, which seriously affects the receiving and transmitting performance of the B3 signal. Therefore, at this moment, the B3 signal will have a glitch as shown in the dotted circle. The glitch can be understood as a drastic change in the size of the B3 signal in a short period of time. At this time, the size of the B3 signal is different from that in the B3 single state and the B3+N41 CA state.

[0148] Similarly, at the moment of switching from B3+N41 CA state to B3 single state, since switch P2 and switch S2 are turned on at the same time, the impedance of N41 branch becomes smaller, so that the phase and amplitude of B3 signal are changed, affecting the receiving and transmitting performance of B3 signal. Therefore, at this moment, a burr as shown in another dotted circle will also appear. The burrs appearing in these two places can be used to indicate the instantaneous impedance problem mentioned above.

[0149] In combination with the above, in addition to the ENDC scenario of B3+N41, for other ENDC scenarios, two frequency bands are also required to work simultaneously, reuse the RF switch, and further require the RF switch to switch between single-on mode and dual-on mode. Therefore, the aforementioned instantaneous impedance problem will also occur during switching. The above two frequency bands may include the LTE frequency band and the NR frequency band, and may also include other frequency band signals.

[0150] In addition, for dual-SIM dual-standby scenarios and dual-SIM dual-channel scenarios, the LTE and NR frequency bands are also required to work simultaneously, and the aforementioned transient impedance problem will also occur during switching.

[0151] Similarly, for DSDS scenarios or DSDA scenarios, the aforementioned instantaneous impedance problem will also occur when the two frequency band signals in the intermediate frequency signal and the TDD mode signal work at the same time, where the intermediate frequency signal may include N1, N2, N3, B1, B2, B3, B34, B39, etc.; the TDD mode signal may include B40, B41, N41, N40, etc.

[0152] For example, SIM card 1 works in the N1 band, and SIM card 2 works in the N41 band. The two bands will also reuse the RF switch, that is, the RF switch will work in a single-on or double-on state. As a TDD band, N41 has TX / RX switching, which requires the RF switch to switch between single-on and double-on, and will also cause the impedance of the other N1 band to jump, resulting in EVM deterioration, which in turn affects the throughput rate of the SIM card 1 band signal.

[0153] Based on the above analysis, it can be seen that the transient impedance problem is mainly caused by the fact that at the moment when the B3+N41 CA state and the B3 single state are switched, the second series branch and the second parallel branch included in the branch where N41 is located are turned on at the same time. In order to solve this problem, the embodiment of the present application changes the circuit structure so that when the circuit is switched, the second series branch and the second parallel branch are not turned on at the same time, thereby avoiding the aforementioned transient impedance problem.

[0154] The embodiment of the present application provides a new RF front-end module, which can avoid the situation where the second series branch and the second parallel branch are turned on at the same time by slowing down the opening speed of the second parallel branch and lengthening the opening time when switching from the B3+N41 CA state to the B3 single state. Similarly, when switching from the B3 single state to the B3+N41 CA state, the situation where the second series branch and the second parallel branch are turned on at the same time can be avoided by speeding up the closing speed of the second parallel branch and shortening the closing time.

[0155] Example 1: Fig.10 (a) and Fig.10 As shown in (c) in FIG. 1 , when switching from the B3+N41 CA state to the B3 single state, the opening speed of the second parallel branch is slowed down, which is equivalent to lengthening the opening time of the second parallel branch from disconnection to conduction. Fig.10 As shown in (a), originally the switch P2 is turned on in the time period t12 between the time t1 and the time t2, and is completely turned on at the time t2. However, in the embodiment of the present application, Fig.10 As shown in (c), by slowing down the opening speed of switch P2, switch P2 can be turned on at the time equal to t3, that is, the moment when switch S2 is turned off; or, the opening of P2 is later than the closing of S2, that is, after S2 is turned off, a certain interval is left before the opening of P2.

[0156] In addition, if the switch P2 is turned on very slowly, later than time t3, the switch P2 and the switch S2 may be turned off at the same time. Then, for the second series branch, the impedance of the second parallel branch is equivalent to being infinite and will not affect the impedance of B3.

[0157] Example 2: Fig.10 (b) and Fig.10 As shown in (d) in FIG. 1 , when switching from the B3 single state to the B3+N41 CA state, the closing speed of the second parallel branch is accelerated, which is equivalent to shortening the closing time of the second parallel branch from being on to being off. Fig.10 As shown in (b), originally the switch P2 is closed in the time period t46 between the time t4 and the time t6, and is completely disconnected at the time t6, but in the embodiment of the present application, Fig.10 As shown in (d) in FIG. 1 , by accelerating the closing speed of the switch P2 , the switch P2 can be turned off at the time t5 , that is, the time when the switch S2 is turned on.

[0158] In addition, if the switch P2 is closed very quickly, later than the moment t4 but earlier than the moment t5, the switch P2 and the switch S2 may be disconnected at the same time. Then, for the second series branch, the impedance of the second parallel branch is equivalent to being infinite and will not affect the impedance of the B3 branch.

[0159] It should be understood that the above-mentioned time misalignment can avoid the situation where switch S2 and switch P2 are turned on at the same time, thereby avoiding impedance mismatch of branch B3, and further avoiding changes in phase and amplitude of B3, thereby solving the burr problem.

[0160] For the above two examples, the present application embodiment provides a radio frequency switch (such as Fig.11 The target antenna switch 224 shown in FIG. 2 is used to achieve the purpose of slowing down the opening speed and accelerating the closing speed corresponding to the second parallel branch.

[0161] refer to Fig.11 , Fig.11 An equivalent structural schematic diagram of a radio frequency front-end module is provided for an embodiment of the present application. The radio frequency front-end module may include a target antenna switch 224. The radio frequency front-end module is connected to the first antenna ANT1 through the antenna port a1.

[0162] like Fig.11 As shown, the target antenna switch 224 may include a first target switching channel 2241 and a second target switching channel 2242. The structure and connection relationship of the first target switching channel 2241 are similar to those of Figure 5 The first switching channel 2231 in the example is the same as that in the example above, and reference may be made to the description of the first switching channel, which will not be repeated here.

[0163] The second target switching channel 2242 and Figure 5 The second target switching channel 2242 is similar to the second switching channel in the embodiment, and the second series branch included is the same as the second series branch included in the second switching channel. You can refer to the aforementioned description of the second series branch and will not repeat it here; however, the second parallel branch included in the second target switching channel 2242 has a different structure from the second parallel branch in the second switching channel.

[0164] refer to Fig.12 , Fig.12 A schematic diagram of the structure of a second target switching channel 2242 provided in an embodiment of the present application; Fig.13 , Fig.14 They are Fig.12Schematic diagrams of several circuit structures of the second parallel branch included in the second target switching channel 2242.

[0165] like Fig.12 As shown, the second target switching channel 2242 includes a second series branch and a second parallel branch; the second series branch and the second parallel branch are connected to the node b2'. The second series branch can be equivalently illustrated as a switch S2 with one end connected to the node b2 and the other end connected to the antenna port. Figure 5 The switch S2 described in the previous section is the same as that in the previous section, and adopts a parallel bias structure. For details, please refer to Figure 5 The introduction of switch S2 in FIG. 1 is omitted here.

[0166] like Fig.12 As shown, the second parallel branch can be equivalently illustrated as a switch P2' with one end connected to the node b2' and the other end connected to the ground. Figure 5 The switch P2 described in the embodiment of the present application has a structure different from that of the switch P2 described in the embodiment of the present application. The switch P2' provided in the embodiment of the present application adopts a series bias structure to achieve the purpose of slowing down the opening speed and accelerating the closing speed, which is described in detail below.

[0167] like Figure 12 to Figure 14 As shown, the switch P2' can be composed of multiple MOSFETs connected in series; in addition, the gate bias of the MOSFET is in the form of a series resistor, that is, a series resistor is connected between the gates of two adjacent MOSFETs; a common resistor is connected in series with the gate of any MOSFET, and a voltage divider resistor is also connected between the source and drain of each MOSFET. In addition, the common resistor corresponding to the switch S2 is connected to the control port VCT1, and the common resistor corresponding to the switch P2' is connected to the control port VCT2.

[0168] The functions of the common resistor and the voltage divider resistor can be referred to in the previous Figure 5 The description will not be repeated here.

[0169] Based on the above circuit structure, by adjusting the signal size of the control port VCT1 and the control port VCT2, for example, by making the high and low levels of the control port VCT1 and the control port VCT2 opposite, the switch S2 and the switch P2' can be turned on and / or off, thereby realizing the on and off switching of the second target switching channel, and at the same time, slowing down the opening speed of the switch P2' and speeding up the closing speed of the switch P2'.

[0170] The switch P2 ′ and the switch S2 include the same number of MOSFETs.

[0171] It should be noted that the number of MOSFETs included in switch P2' and switch S2 is determined by the power that needs to be borne by other branches in the disconnected state. For example, when N41 is transmitting, switch S2 is turned on and switch P2' is turned off, and a large RF swing is generated at node b2. At this time, switch S2 needs multiple MOSFET stacks (stacks), and multiple MOSFETs evenly distribute the RF swing to avoid burning the MOSFET. For another example, when B3 is transmitting and receiving, switch S2 is turned off and switch P2' is turned on, and a large RF swing is generated at node a1. At this time, switch S2 needs to withstand the RF swing on node a1, and multiple MOSFETs need to be stacked and cascaded. It should be understood that the RF swing can also be called the RF amplitude, which is used to indicate the strength and power of the RF signal.

[0172] Optionally, the number of the plurality of MOSFETs connected in series may be an even number or an odd number.

[0173] For example, Fig.13 As shown, taking the odd number 5 as an example, the switch P2' can be composed of 5 MOSFETs connected in series.

[0174] For example, taking 5 MOSFETs connected in series as an example, the 5 MOSFETs connected in series are respectively called T1~T5, the source of T1 is connected to node b2', and the drain of T5 is connected to the ground end; a series resistor Rg1 is connected between the gate of T1 and the gate of T2, a series resistor Rg2 is connected between the gate of T2 and the gate of T3, a series resistor Rg3 is connected between the gate of T3 and the gate of T4, and a series resistor Rg3 is connected between the gate of T4 and the gate of T5; a voltage divider resistor R1 is connected between the source and drain of T1, a voltage divider resistor R2 is connected between the source and drain of T2, a voltage divider resistor R3 is connected between the source and drain of T3, a voltage divider resistor R4 is connected between the source and drain of T4, and a voltage divider resistor R5 is connected between the source and drain of T5.

[0175] In addition, if Fig.13 As shown in (a) of FIG. 1 , the control port VCT2 can be connected to the node q1 through the common resistor Rcom2 and the gate of T1 and the series resistor Rg1 .

[0176] Or, if Fig.13 As shown in (b) in FIG. 1 , the control port VCT2 can be connected to the node q2 via a common resistor Rcom2 and the gate of T2 , a series resistor Rg1 , and a series resistor Rg2 .

[0177] Or, if Fig.13 As shown in (c) in FIG. 1 , the control port VCT2 can be connected to the node q3 via the common resistor Rcom2 , the gate of T3 , the series resistor Rg2 , and the series resistor Rg3 .

[0178] Or, if Fig.13 As shown in (d) in FIG. 1 , the control port VCT2 can be connected to the node q4 through the common resistor Rcom2 and the gate of T4 , the series resistor Rg3 , and the series resistor Rg4 .

[0179] Or, if Fig.13 As shown in (e), the control port VCT2 can be connected to the node q5 through the common resistor Rcom2, the gate of T5, and the series resistor Rg4.

[0180] Optionally, the resistance values ​​of the series resistors connected between the gates of two adjacent MOSFETs may be the same or different.

[0181] For example, in Fig.13 In (a), the resistance values ​​of the series resistor Rg1, the series resistor Rg2, the series resistor Rg3 and the series resistor Rg4 may be the same, or may be different.

[0182] For example, in Fig.13 In (b), the resistance values ​​of the series resistor Rg1 and the series resistor Rg2 may be the same; the resistance values ​​of the series resistor Rg2, the series resistor Rg3 and the series resistor Rg4 may be different.

[0183] For example, in Fig.13 In (c), the resistance values ​​of the series resistor Rg1 and the series resistor Rg4 may be the same, the resistance values ​​of the series resistor Rg2 and the series resistor Rg3 may be the same, and the resistance value of the series resistor Rg3 may be smaller than the resistance value of the series resistor Rg4.

[0184] For example, in Fig.13 In (d), the resistance values ​​of the series resistor Rg3 and the series resistor Rg4 may be the same, and the resistance values ​​of the series resistor Rg3, the series resistor Rg2, and the series resistor Rg1 may be different.

[0185] For example, in Fig.13 In (e), the resistance values ​​of the series resistor Rg4, the series resistor Rg3, the series resistor Rg2, and the series resistor Rg1 may be the same, or may be different.

[0186] Since the resistance from each MOSFET to the control port VCT2 is different, the corresponding RC time constant will be different. Therefore, combined with Fig.13 It can be seen that if the resistance of the four series resistors is the same, then Fig.13 (a) and Fig.13 In the two connection structures shown in (e), the resistances from the five MOSFETs to the control port VCT2 are arranged symmetrically, so it can be considered that: Fig.13 (a) and Fig.13(e) in is equivalent to the same type of connection structure; Fig.13 (b) and Fig.13 In the two connection structures shown in (d), the resistance size arrangement of the five MOSFETs to the control port VCT2 is also symmetrical, so it can be considered that: Fig.13 (b) and Fig.13 (d) in the figure is equivalent to the same type of connection structure.

[0187] against Fig.13 (a) Fig.13 (b) and Fig.13 For the three types of connection structures shown in (c), the bias resistance corresponding to the MOSFET directly connected to the common resistor is the smallest, the bias resistance corresponding to the MOSFET indirectly connected to the common resistor through a series resistor is larger, and the bias resistance corresponding to the MOSFET indirectly connected to the common resistor through two series resistors is even larger. In other words, the more series resistors are indirectly connected to the common resistor, the larger the bias resistance corresponding to the MOSFET. Among them, the bias resistance can be understood as the sum of the resistors connected from the control port VCT2 to the gate of the MOSFET.

[0188] For example, for Fig.13 For (c), the bias resistance corresponding to T3 is the smallest and can be regarded as Rcom; the bias resistance corresponding to T2 and T4 is the second largest, which is the sum of Rcom and Rg2 or the sum of Rcom and Rg3; the bias resistance corresponding to T1 and T5 is the largest, which is the sum of Rcom, Rg2 and Rg1, or the sum of Rcom, Rg3 and Rg4.

[0189] This is equivalent to the five MOSFETs being divided into a three-stage cascade relationship, with T3 being the first stage, T2 and T4 being the second stage, and T1 and T5 being the third stage. The bias resistors of MOSFETs at different levels are different. If the bias resistors at different levels are different, the turn-on time of the corresponding MOSFETs will be different; and the smaller the bias resistor, the shorter the turn-on time of the corresponding MOSFET; the larger the bias resistor, the longer the turn-on time of the corresponding MOSFET.

[0190] Therefore, for Fig.13 In (c), we can say that the five MOSFETs are turned on step by step from T3 to the upper and lower sides. Specifically, T3 is turned on first, followed by T2 and T4, and finally T1 and T5. If the time for the first MOSFET to be turned on is t on , then the three-stage conduction time can be roughly recorded as three times t on ; and for Figure 5For the switch P2 shown in the diagram, if there are 5 MOSFETs, the bias resistance of each MOSFET is equivalent to the size of Rcom2 and Rg1, and the conduction time is greater than t on , but less than 3t on . It can be seen from this that the embodiment of the present application provides Fig.13 The circuit structure shown in (c) can shorten the conduction time, or lengthen the conduction time, compared with the prior art.

[0191] In addition, the bias resistor corresponding to T3 is smaller than the bias resistor of any MOSFET in the prior art, and the turn-off time will be faster; and because one MOSFET is turned off, the entire switch P2' will be turned off. Therefore, the embodiment of the present application provides Fig.13 The switch P2' shown in (c) can speed up the turn-off time compared with the prior art.

[0192] Similarly, for Fig.13 In the structure (a), the five MOSFETs are turned on step by step from T1 to T5. If the time for the first MOSFET to be turned on is t on , then the five-stage conduction time can be roughly recorded as 5 times t on ; Then, the embodiments of the present application provide Fig.13 The switch P2' shown in (a) can shorten the conduction time compared with the prior art.

[0193] In addition, the bias resistor corresponding to T1 is smaller than the bias resistor of any MOSFET in the prior art, and the turn-off time will be faster. Therefore, the embodiment of the present application provides Fig.13 The switch P2' shown in (a) can speed up the turn-off time compared with the prior art.

[0194] Similarly, for Fig.13 In the structure (b), the five MOSFETs are turned on step by step from T2 to the upper and lower sides. Specifically, T2 is turned on first, followed by T1 and T3, then T4, and finally T5. If the turn-on time of the first MOSFET is t on , then the conduction time of the four-stage can be roughly recorded as 4 times t on Therefore, compared with the prior art, the switch P2' provided in the embodiment of the present application can slow down the conduction time.

[0195] In addition, the bias resistor corresponding to T2 is smaller than the bias resistor of any MOSFET in the prior art, and the turn-off time will be faster. Therefore, the embodiment of the present application provides Fig.13 The switch P2' shown in (b) can speed up the turn-off time compared with the prior art.

[0196] refer to Fig.14 , Fig.14 for Fig.13 (a) Fig.13 (b) and Fig.13 (c) in the figure shows the corresponding turn-on and turn-off time test diagrams. Fig.14 In the figure, the horizontal axis is used to indicate time (time, in μs), the area above the vertical axis is used to indicate the control voltage (VCT2, in V) received by the control port VCT2, and the area below the vertical axis is used to indicate the output voltage (Vout, in mV), that is, the voltage at the node b2' to which the second parallel circuit is connected.

[0197] When the control voltage received at the control port VCT2 switches from a high level (such as 2.5V) to a low level (such as -2.5V), Fig.13 The second parallel circuit shown in (a) begins to disconnect at time m11 and is completely disconnected at time m12. Fig.14 The duration between m11 and m12 shown in (a) can be used as Fig.13 The turn-off time Toff1 corresponding to (a) in FIG.

[0198] When the control voltage received at the control port VCT2 switches from a low level (such as -2.5V) to a high level (such as 2.5V), Fig.13 The second parallel circuit shown in (a) starts to conduct at time m51 and completes conduction at time m61. Fig.14 The duration between m51 and m61 shown in (b) can be used as Fig.13 The on-time Ton1 corresponding to (a) in FIG.

[0199] Similarly, when the control voltage received at the control port VCT2 switches from a high level (such as 2.5V) to a low level (such as -2.5V), Fig.13 The second parallel circuit shown in (b) begins to disconnect at time m12 and is completely disconnected at time m22. Fig.14 The duration between m21 and m22 shown in (c) can be used as Fig.13 The turn-off time Toff2 corresponding to (b) in FIG.

[0200] When the control voltage received at the control port VCT2 switches from a low level (such as -2.5V) to a high level (such as 2.5V), Fig.13 The second parallel circuit shown in (b) starts to conduct at time m52 and completes conduction at time m62. Fig.14 The duration between m52 and m62 shown in (d) can be used as Fig.13The conduction time Ton2 corresponding to (b) in FIG.

[0201] Similarly, when the control voltage received at the control port VCT2 switches from a high level (such as 2.5V) to a low level (such as -2.5V), Fig.13 The second parallel circuit shown in (c) begins to disconnect at time m13 and is completely disconnected at time m23. Fig.14 The duration between m13 and m23 shown in (e) can be used as Fig.13 The turn-off time Toff3 corresponding to (c) in FIG.

[0202] When the control voltage received at the control port VCT2 switches from a low level (such as -2.5V) to a high level (such as 2.5V), Fig.13 The second parallel circuit shown in (c) starts to conduct at time m53 and completes conduction at time m63. Fig.14 The duration between m53 and m63 shown in (f) can be used as Fig.13 The conduction time Ton3 corresponding to (c) in FIG.

[0203] according to Fig.14 As shown in the figure, when the common resistor Rcom2 is connected to the gate of different MOSFETs, different on-times will be generated, while the off-times are basically the same, and the off-time is significantly smaller than the on-time. In addition, the off-time is also turned off step by step. And, based on Fig.14 As shown in (b), (d) and (e) in Figure 1, it can be clearly seen that the more equivalent layers of MOSFET, the longer the conduction time. Fig.13 The MOSFET in (a) is equivalent to a five-stage cascade. Fig.13 (b) in the figure is equivalent to a four-stage cascade. Fig.13 (c) in is equivalent to a three-stage cascade, then Fig.13 The conduction time corresponding to (a) is greater than Fig.13 The conduction time corresponding to (b) in Fig.13 The conduction time corresponding to (b) is greater than Fig.13 The conduction time corresponding to (c) in FIG.

[0204] For example, Fig.15 As shown, taking the even number 4 as an example, the switch P2' can be composed of 4 MOSFETs connected in series.

[0205] For example, taking four MOSFETs connected in series as an example, the four MOSFETs connected in series are respectively called T1~T4, the source of T1 is connected to node b2', and the drain of T4 is connected to the ground end; a series resistor Rg1 is connected between the gate of T1 and the gate of T2, a series resistor Rg2 is connected between the gate of T2 and the gate of T3, and a series resistor Rg3 is connected between the gate of T3 and the gate of T4; a voltage divider resistor R1 is connected between the source and drain of T1, a voltage divider resistor R2 is connected between the source and drain of T2, a voltage divider resistor R3 is connected between the source and drain of T3, and a voltage divider resistor R4 is connected between the source and drain of T4.

[0206] In addition, if Fig.15 As shown in (a) of FIG. 1 , the control port VCT2 can be connected to the node q1 through the common resistor Rcom2 and the gate of T1 and the series resistor Rg1 .

[0207] Or, if Fig.15 As shown in (b) in FIG. 1 , the control port VCT2 can be connected to the node q2 via a common resistor Rcom2 and the gate of T2 , a series resistor Rg1 , and a series resistor Rg2 .

[0208] Or, if Fig.15 As shown in (c) in FIG. 1 , the control port VCT2 can be connected to the node q3 via the common resistor Rcom2 , the gate of T3 , the series resistor Rg2 , and the series resistor Rg3 .

[0209] Or, if Fig.15 As shown in (d) in FIG. 1 , the control port VCT2 can be connected to the node q4 through the common resistor Rcom2 and the gate of T4 and the series resistor Rg3 .

[0210] Optionally, the resistance values ​​of the series resistors connected between the gates of two adjacent MOSFETs may be the same or different.

[0211] For example, in Fig.15 In (a), the resistance values ​​of the series resistor Rg1, the series resistor Rg2 and the series resistor Rg3 may be the same, or may be different.

[0212] For example, in Fig.15 In (b), the resistance values ​​of the series resistor Rg1 and the series resistor Rg2 may be the same; the resistance value of the series resistor Rg2 may be smaller than the series resistor Rg3.

[0213] For example, in Fig.15 In (c), the resistance values ​​of the series resistor Rg2 and the series resistor Rg3 may be the same; the resistance value of the series resistor Rg2 may be smaller than the series resistor Rg1.

[0214] For example, in Fig.15In (d), the resistance values ​​of the series resistor Rg3, the series resistor Rg2 and the series resistor Rg1 may be the same, or may be different.

[0215] The above are four different embodiments. Since the resistance from each MOSFET to the control port VCT2 is different, the corresponding RC time constant will be different. Fig.15 It can be seen that Fig.15 (a) and Fig.15 In the two connection structures shown in (d), the resistance size arrangement of the four MOSFETs to the control port VCT2 is symmetrical, so it can be considered that: Fig.15 (a) and Fig.15 (d) in the figure is equivalent to the same type of connection structure; Fig.15 (b) and Fig.15 In the two connection structures shown in (c), the resistance size arrangement of the four MOSFETs to the control port VCT2 is also symmetrical, so it can be considered that: Fig.15 (b) and Fig.15 (c) in the figure is equivalent to the same type of connection structure.

[0216] against Fig.15 (a) and Fig.15 For the two types of connection structures shown in (b) in FIG. 1 , the more series resistors indirectly connected to the common resistor, the larger the bias resistor corresponding to the MOSFET.

[0217] against Fig.15 For example, in (a), the four MOSFETs are divided into four stages of cascade connection. Fig.15 For example, in (b), the four MOSFETs are divided into three stages of cascade connection, with T2 as the first stage, T1 and T3 as the second stage, and T4 as the third stage. Different stages have different bias resistors, so the corresponding MOSFETs have different conduction times; and the smaller the bias resistor, the shorter the conduction time of the corresponding MOSFET; the larger the bias resistor, the longer the conduction time of the corresponding MOSFET.

[0218] Therefore, for Fig.15 In (b), the four MOSFETs are turned on step by step from T2 to the upper and lower sides. Specifically, T2 is turned on first, followed by T1 and T3, and T4 is turned on last. If the time for the first MOSFET to be turned on is t on , then the three-stage conduction time can be roughly recorded as three times t on ; It can be seen that the embodiment of the present application provides Fig.15The circuit structure shown in (b) can reduce the turn-on time compared to the prior art. In addition, it can speed up the turn-off time compared to the prior art.

[0219] Similarly, for Fig.15 In (a), it can be said that the four MOSFETs are turned on step by step starting from T1. If the time for the first MOSFET to be turned on is t on , then the conduction time of the four-stage can be roughly recorded as 4 times t on ; It can be seen that the embodiment of the present application provides Fig.15 The circuit structure shown in (a) can reduce the turn-on time compared to the prior art. In addition, it can speed up the turn-off time compared to the prior art.

[0220] Based on the above, it can be known that, regardless of whether the switch P2' is composed of an even number or an odd number of MOSFETs, the opening time of the switch P2' can be adjusted by changing the access point of the common resistor, for example, it can be adjusted within the range of 100ns to 10us.

[0221] refer to Fig.16 , is a schematic diagram of the structure of two adjustable switches P2' provided in an embodiment of the present application. Fig.16 (a) and Fig.13 correspond, Fig.16 (b) and Fig.15 correspond.

[0222] For example, Fig.16 As shown in (a) in FIG. 1 , for the switch P2' composed of five MOSFETs, a switch SC1 can be added between the common resistor and T1, a switch SC2 can be added between the common resistor and T2, and a switch SC3 can be added between the common resistor and T3. Thus, the access position of the common resistor Rcom can be adjusted by targeting SC1, SC2, and SC3, thereby controlling the length of the conduction time.

[0223] Similarly, if Fig.16 As shown in (b), for the switch P2' composed of four MOSFETs, a switch SC1 can be added between the common resistor and T1, and a switch SC2 can be added between the common resistor and T2. Thus, the access position of the common resistor Rcom can be adjusted by the switches SC1, SC2 and SC3, thereby controlling the length of the conduction time.

[0224] Optionally, the selection switches SC1, SC2 and SC3 can be set through the MIPI register. The switches SC1, SC2 and SC3 can also be implemented by MOSFET, and the gates of the switches SC1, SC2 and SC3 can be connected to the MIPI register to receive a signal from the MIPI register to turn on or off.

[0225] Optionally, when the switch P2' includes 2N MOSFETs, there are N access positions for the common resistor. When the switch P2' includes 2N+1 MOSFETs, there are N+1 access positions for the common resistor.

[0226] Therefore, in combination with the above examples, it can be seen that the antenna switch provided in the embodiment of the present application, by making the second series branch adopt parallel bias, the second parallel branch adopts series bias; when switching from B3+N41 CA state to B3 single state, the opening speed of the second parallel branch can be slowed down, and the opening time lengthened, thereby avoiding the situation where the second series branch and the second parallel branch are turned on at the same time. Similarly, when switching from B3 single state to B3+N41 CA state, the closing speed of the second parallel branch can be accelerated, and the closing time length can be shortened, thereby avoiding the situation where the second series branch and the second parallel branch are turned on at the same time, thereby avoiding B3 impedance mismatch, signal glitches, affecting EVM, and deteriorating throughput.

[0227] Furthermore, the embodiments of the present application can realize flexible configuration of software start time through software settings.

[0228] Furthermore, the embodiment of the present application can also achieve different increases in the opening time and different shortenings in the closing time in the two switching situations of switching from the B3+N41 CA state to the B3 single state and from the B3 single state to the B3+N41 CA state through software settings.

[0229] The structure of the radio frequency switch (ie, the target antenna switch 224 ) provided in the embodiment of the present application is described in detail above in conjunction with the accompanying drawings, and other related devices are introduced below.

[0230] The embodiment of the present application further provides a radio frequency front-end module 22, comprising the radio frequency switch as described above.

[0231] The RF front-end module includes a first communication link and a second communication link, and the first communication link and the second communication link are used to connect to at least the same antenna through a RF switch; when the first target switching channel in the RF switch is turned on, the first communication link receives and transmits the intermediate frequency signal through the antenna; when the second target switching channel in the RF switch is turned on, the second communication link receives the TDD mode signal through the antenna.

[0232] For an introduction to the specific structure of the RF front-end module 22, please refer to Figure 4 The introduction of , I will not go into details here.

[0233] Optionally, for the ENDC scenario, the RF front-end module 22 provided in the embodiment of the present application may be applicable to frequency band combinations of MB+N41 and MB+N40; wherein MB may include B1, B2, B3, B34, B39, etc.

[0234] Optionally, for DSDS scenarios and DSDA scenarios, the RF front-end module 22 provided in the embodiment of the present application may be applicable to the frequency band combination of MB+N41, MB+N40 or MB+B41, MB+B40; MB may be a signal under the LTE standard or a signal under the NR standard. That is, MB may include N1, N2, N3, B1, B2, B3, B34, B39, etc.

[0235] The embodiment of the present application also provides a radio frequency front-end chip, including the radio frequency front-end module 22 as described above.

[0236] An embodiment of the present application also provides a terminal device, including a radio frequency transceiver chip and the radio frequency front-end chip as described above, and an antenna subsystem, wherein the antenna subsystem includes an antenna.

[0237] The RF transceiver chip is connected to the first control terminal and the second control terminal, and outputs a first control signal to the first control terminal and a second control signal to the second control terminal to control the conduction or disconnection of the second series branch and the second parallel branch in the RF switch.

[0238] It should be noted that the first control terminal may indicate the control port VCT1 , and the second control terminal may indicate the control port VCT2 .

[0239] Optionally, the terminal device also includes a MIPI register, which connects the first control switch and the second control switch, and outputs a third control signal to the first control switch and a fourth control signal to the second control switch to control the first control switch and the second control switch to be selected.

[0240] It should be noted that the second control switch can indicate Fig.16 The switches SC1, SC2, and SC3 shown in (a) of FIG. 1 ; the second control switch can indicate Fig.16 The switch SC1 and the switch SC2 shown in (b) in FIG.

[0241] It should be understood that different control signals can be set to be output through the MIPI register to control the gating of multiple second control switches, so that the access position of the common resistor Rcom in the second parallel branch can be adjusted, and the length of the conduction time can be controlled.

[0242] Optionally, the terminal device also includes a power subsystem, which is used to provide voltage to the RF front-end module.

[0243] The beneficial effects that can be achieved by the terminal device and chip provided in the above-mentioned embodiments of the present application can refer to the corresponding beneficial effects of the method provided above, and will not be repeated here.

[0244] It should be understood that the above is only to help those skilled in the art to better understand the embodiments of the present application, rather than to limit the scope of the embodiments of the present application. According to the above examples given, those skilled in the art can obviously make various equivalent modifications or changes. For example, some steps in each embodiment of the above detection method may be unnecessary, or some steps may be newly added. Or a combination of any two or any multiple embodiments of the above. Such modifications, changes or combined schemes also fall within the scope of the embodiments of the present application.

[0245] It should also be understood that the above description of the embodiments of the present application focuses on emphasizing the differences between the various embodiments. The same or similar points that are not mentioned can be referenced to each other. For the sake of brevity, they will not be repeated here.

[0246] It should also be understood that the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0247] It should also be understood that in the embodiments of the present application, "pre-setting" and "pre-definition" can be achieved by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in a device (for example, including an electronic device), and the present application does not limit its specific implementation method.

[0248] It should also be understood that the division of the methods, situations, categories and embodiments in the embodiments of the present application is only for the convenience of description and should not constitute a special limitation. The features of various methods, categories, situations and embodiments can be combined without contradiction.

[0249] It should also be understood that in the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0250] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A radio frequency switch, characterized in that: including a first target switching channel and a second target switching channel connected to the same antenna; The RF switch is used to switch between a first state and a second state, the first state indicates that the first target switching channel is turned on and the second target switching channel is turned off, and the second state indicates that both the first target switching channel and the second target switching channel are turned on; The second target switching channel includes a second series branch and a second parallel branch, a first end of the second series branch and a first end of the second parallel branch are connected to the same transmission node, a second end of the second series branch is connected to the antenna, and a second end of the second parallel branch is connected to a ground terminal; The second series branch and the second parallel branch each include k MOSFETs, and the source and drain of the k MOSFETs are connected in sequence, k≥2, and k is an integer; The gate of each MOSFET in the second series branch is connected to the first control terminal through a first bias resistor, and the gate of at least one MOSFET in the second parallel branch is connected to the second control terminal through a second bias resistor, and the resistance value of the second bias resistor is greater than the resistance value of the first bias resistor; The first control end is used to receive a first control signal, and the second control end is used to receive a second control signal, and the first control signal is different from the second control signal.

2. The radio frequency switch according to claim 1, characterized in that: A gate of at least one MOSFET in the second parallel branch is connected to the second control end via a third bias resistor, and a resistance value of the third bias resistor is smaller than a resistance value of the first bias resistor.

3. The radio frequency switch according to claim 2, characterized in that: The second series branch includes a first common node, the first common node is connected to the first control terminal through a first common resistor, the first common node is connected to the gate of each MOSFET in the second series branch through a first resistor, and the first bias resistor includes the first common resistor and the first resistor; The second parallel branch includes a second common node, the second common node is connected to the second control end through a second common resistor, the second common node is connected to the gate of any one MOSFET in the second parallel branch, the gates of two adjacent MOSFETs in the second parallel branch are connected through a second resistor, the second bias resistor includes the second common resistor and one or more second resistors, and the third bias resistor includes the second common resistor.

4. The radio frequency switch according to claim 3, characterized in that: The source of the first MOSFET in the second parallel branch is connected to the transmission node, and the drain of the kth MOSFET is connected to the ground terminal; The second common node is connected to the gate of the first MOSFET in the second parallel branch, and the gates of two adjacent MOSFETs in the second parallel branch are connected via the second resistor.

5. The radio frequency switch according to claim 4, characterized in that: The resistance values ​​of the plurality of second resistors are the same or different.

6. The radio frequency switch according to any one of claims 3 to 5, characterized in that: A control switch is further connected between the second common node and the gate of the MOSFET in the second parallel branch, and a plurality of the control switches are used to be switched on under the control of a third control signal.

7. The radio frequency switch according to claim 6, characterized in that: The source and the drain of each MOSFET in the second series branch and the second parallel branch are also connected via a voltage dividing resistor.

8. The radio frequency switch according to any one of claims 1 to 5 and 7, characterized in that: The second series branch and the second parallel branch are configured to be turned on in different time periods.

9. The radio frequency switch according to any one of claims 1 to 5 and 7, characterized in that: The second series branch and the second parallel branch are used to be disconnected in different time periods or in the same time period.

10. The radio frequency switch according to any one of claims 1 to 5 and 7, characterized in that: When the first target switching channel is turned on, it is used to realize the reception and transmission of intermediate frequency signals, and when the second target switching channel is turned on, it is used to realize the reception of TDD mode signals.

11. The radio frequency switch according to claim 10, characterized in that: The RF switch is applied to the ENDC scenario; the intermediate frequency signal includes at least one of the following frequency bands: B1, B2, B3, B34, B39; The TDD mode signal includes at least one of the following frequency bands: N41, N40.

12. The radio frequency switch according to claim 10, characterized in that: The RF switch is applied to a DSDS scenario or a DSDA scenario; the intermediate frequency signal includes at least one of the following frequency bands: N1, N2, N3, B1, B2, B3, B34, B39; the TDD mode signal includes at least one of the following frequency bands: B40, B41, N41, N40.

13. A radio frequency front-end module, characterized in that: The RF front-end module comprises a first communication link and a second communication link, wherein the first communication link and the second communication link are used to connect to at least the same antenna through the RF switch according to any one of claims 1 to 12; When the first target switching channel in the radio frequency switch is turned on, the first communication link receives and transmits intermediate frequency signals through the antenna; When the second target switching channel in the RF switch is turned on, the second communication link receives the TDD mode signal through the antenna.

14. A radio frequency front-end chip, characterized in that: Includes the radio frequency front-end module as described in claim 13.

15. A terminal device, characterized in that: comprising a radio frequency transceiver chip and the radio frequency front-end chip as claimed in claim 14, and an antenna subsystem, wherein the antenna subsystem comprises the antenna; The RF transceiver chip is connected to the first control end and the second control end, and outputs the first control signal to the first control end and outputs the second control signal to the second control end to control the conduction or disconnection of the second series branch and the second parallel branch in the RF switch.

16. The terminal device according to claim 15, characterized in that: When the RF front-end module includes a control switch, the terminal device also includes a MIPI register, which is connected to a plurality of the control switches and outputs a third control signal to the plurality of the control switches to control the gating of the plurality of the control switches.

17. The terminal device according to claim 15 or 16, characterized in that: The terminal device also includes a power subsystem, which is used to provide voltage to the RF front-end module.

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