Display device and method of manufacturing the same

Abstract

Each of the first terminal electrode and the second terminal electrode of the first thin film transistor and the third terminal electrode and the fourth terminal electrode of the second thin film transistor (20x) has a lower side metal layer (6), an intermediate metal layer (7), and an upper side metal layer (8) stacked in this order, the intermediate metal layer (7) has a lower resistance and a lower melting point than the lower side metal layer (6) and the upper side metal layer (8), in an end portion of each terminal electrode (20x), an end surface of the lower side metal layer (6) and an end surface of the intermediate metal layer (7) coincide with each other, and the upper side metal layer (8) is provided so as to cover the mutually coincident end surfaces.

Description

Technical Field

[0001] This invention relates to a display device and a method for manufacturing the same. Background Technology

[0002] In recent years, self-emissive organic EL (OLED) displays, which utilize organic electroluminescence (EL) elements, have attracted attention as a replacement for liquid crystal displays. In these OLED displays, multiple thin-film transistors (TFTs) are provided for each sub-pixel, which is the smallest unit of an image. Here, the semiconductor layer constituting the TFT is known to be, for example, a semiconductor layer made of polycrystalline silicon with high mobility, or a semiconductor layer made of oxide semiconductors such as In-Ga-Zn-O with low leakage current.

[0003] For example, Patent Document 1 discloses a display device having a hybrid structure in which a first TFT using polycrystalline silicon semiconductor and a second TFT using oxide semiconductor are respectively formed on a substrate.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2020-17558 Summary of the Invention

[0007] The technical problem to be solved by the present invention

[0008] However, in organic EL display devices with a hybrid structure in which each sub-pixel has a TFT using polysilicon and a TFT using oxide semiconductor, in order to improve the aperture ratio of each sub-pixel, there is an overlap between the lower layer wiring formed on the same layer as the gate electrode of the TFT using polysilicon and the upper layer wiring formed on the same layer as the gate electrode of the TFT using oxide semiconductor. Here, in the overlapping portion of the lower and upper layer wiring, the surface height difference between the inorganic insulating film covering the lower layer wiring and other inorganic insulating films covering the upper layer wiring becomes larger. Therefore, if multiple conductive layers such as wiring are formed on this composite film, a metal film constituting the conductive layer remains in the portion of the surface height difference of the composite film (see reference). Figure 20 In the case of R), the adjacent conductive layer may short-circuit due to the remaining metal film.

[0009] The present invention was made in view of the point that its purpose is to suppress short circuits between adjacent conductive layers.

[0010] Solution to the problem

[0011] To achieve the above objectives, the display device according to the present invention comprises: a substrate; and a thin-film transistor layer disposed on the substrate, wherein a first semiconductor film made of polycrystalline silicon, a first inorganic insulating film, a first metal film, a second inorganic insulating film, a second semiconductor film made of oxide semiconductor, a third inorganic insulating film and a second metal film, a fourth inorganic insulating film and a third metal film are sequentially stacked. In the thin-film transistor layer, a first thin-film transistor and a second thin-film transistor are disposed for each sub-pixel constituting a display area. The first thin-film transistor has a first semiconductor layer formed of the first semiconductor film, and the second thin-film transistor has a second semiconductor layer formed of the second semiconductor film. The first thin-film transistor comprises: the first semiconductor layer defining a first conductor region and a second conductor region in a mutually separated manner, and defining a first channel region between the first conductor region and the second conductor region; a first gate electrode disposed on the first semiconductor layer, separated by the first inorganic insulating film, and formed of the first metal film; and a first terminal electrode and a second terminal electrode passing through the third metal film in a mutually separated manner. The second thin-film transistor comprises: a second semiconductor layer defining a third conductor region and a fourth conductor region in a mutually separated manner, and defining a second channel region between the third conductor region and the fourth conductor region; a second gate electrode disposed on the second semiconductor layer through the third inorganic insulating film and formed of the second metal film; and a third terminal electrode and a fourth terminal electrode disposed through the third metal film in a mutually separated manner and electrically connected to the third conductor region and the fourth conductor region, respectively. The display device is characterized in that each terminal electrode of the first terminal electrode, the second terminal electrode, the third terminal electrode, and the fourth terminal electrode comprises a lower metal layer, an intermediate metal layer, and an upper metal layer stacked sequentially, the intermediate metal layer having a lower resistance and a lower melting point than the lower metal layer and the upper metal layer, and at the ends of each terminal electrode, the end faces of the lower metal layer and the intermediate metal layer are aligned with each other, and the upper metal layer is disposed to cover the aligned end faces.

[0012] Invention Effects

[0013] According to the present invention, short circuits between adjacent conductive layers can be suppressed. Attached Figure Description

[0014] Figure 1 This is a top view showing the schematic structure of the organic EL display device according to the first embodiment of the present invention.

[0015] Figure 2 This is a top view of the display area of ​​the organic EL display device according to the first embodiment of the present invention.

[0016] Figure 3 This is a cross-sectional view of the display area of ​​the organic EL display device according to the first embodiment of the present invention.

[0017] Figure 4 This is an equivalent circuit diagram of the TFT layer of the organic EL display device constituting the first embodiment of the present invention.

[0018] Figure 5 This is a cross-sectional view of the terminal electrodes of the organic EL display device constituting the first embodiment of the present invention.

[0019] Figure 6 This is a cross-sectional view of the organic EL layer constituting the organic EL display device according to the first embodiment of the present invention.

[0020] Figure 7 This is a first cross-sectional view showing a part of the manufacturing process of the organic EL display device according to the first embodiment of the present invention.

[0021] Figure 8 This indicates a continuation of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 7 The second sectional view.

[0022] Figure 9 This indicates a continuation of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 8 The third sectional view.

[0023] Figure 10 This indicates a continuation of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 9 The fourth sectional view.

[0024] Figure 11 This indicates a continuation of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 10 The fifth sectional view.

[0025] Figure 12 This indicates a continuation of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 11 The sixth sectional view.

[0026] Figure 13 This indicates a continuation of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 12 The seventh sectional view.

[0027] Figure 14 This indicates a continuation of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 13 The eighth sectional view.

[0028] Figure 15 This indicates a continuation of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 14 The ninth sectional view.

[0029] Figure 16 This indicates a continuation of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 15 The tenth sectional view.

[0030] Figure 17 This indicates a continuation of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 16 The eleventh sectional view.

[0031] Figure 18 This indicates a continuation of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 17 The twelfth sectional view.

[0032] Figure 19 This indicates a continuation of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 18 The thirteenth sectional view.

[0033] Figure 20 This is following the patterning step of the third metal film in the manufacturing process of the organic EL display device according to the first embodiment of the present invention. Figure 2 The sectional view corresponding to the XX-XX line in the diagram. Detailed Implementation

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0035] First Implementation Method

[0036] Figures 1 to 20 This paper illustrates a first embodiment of the display device and its manufacturing method according to the present invention. Furthermore, in the following embodiments, an organic EL display device having an organic EL element layer is exemplified as a display device having a light-emitting element layer. Here, Figure 1This is a top view showing the schematic structure of the organic EL display device 50 according to this embodiment. Furthermore, Figure 2 as well as Figure 3 These are top views and cross-sectional views of the display area D of the organic EL display device 50. Furthermore, Figure 4 This is an equivalent circuit diagram of the TFT layer 30 that constitutes the organic EL display device 50. Furthermore, Figure 5 This is a cross-sectional view of the terminal electrodes 20x that constitute the organic EL display device 50. Furthermore, Figure 6 This is a cross-sectional view of the organic EL layer 33 that constitutes the organic EL display device 50.

[0037] like Figure 1 As shown, the organic EL display device 50 includes, for example, a display area D for displaying images, which is arranged in a rectangular shape, and a border area F disposed around the display area D. In addition, in this embodiment, a rectangular display area D is shown, but the rectangular shape also includes, for example, a shape with rounded edges, a shape with rounded corners, or a shape with a notch in part of the edge, etc., which are generally rectangular shapes.

[0038] like Figure 2 As shown, multiple sub-pixels P are arranged in a matrix in the display area D. Furthermore, in the display area D, as... Figure 2 As shown, for example, sub-pixels P having a red emitting area Er for displaying red, sub-pixels P having a green emitting area Eg for displaying green, and sub-pixels P having a blue emitting area Eb for displaying blue are set to be adjacent to each other. Furthermore, in the display area D, for example, a pixel is formed by three adjacent sub-pixels P having the red emitting area Er, the green emitting area Eg, and the blue emitting area Eb.

[0039] Terminal T is in one direction ( Figure 1 The extension method (in the Y direction) is set in the border area F. Figure 1 The positive end in the X direction. Furthermore, in the border region F, as... Figure 1 As shown, a bent portion B, which can be bent at, for example, 180° (U-shape) with the Y direction in the figure as the bending axis, is provided between the display area D and the terminal portion T, extending in one direction (the Y direction in the figure).

[0040] like Figure 3 As shown, the organic EL display device 50 includes: a resin substrate 10 provided as a substrate, a TFT layer 30 provided on the resin substrate 10, an organic EL element layer 40 provided on the TFT layer 30 as a light-emitting element layer, and a sealing film 45 provided on the organic EL element layer 40.

[0041] The resin substrate 10 is made of organic resin materials such as polyimide resin.

[0042] like Figure 3 As shown, the TFT layer 30 includes: a base coating film 11 disposed on the resin substrate 10, four first TFTs 9A and three second TFTs 9B disposed on the base coating film 11 for each sub-pixel P, and a capacitor 9h (see reference). Figure 4 A protective insulating film 21 and a planarization film 22 are sequentially disposed on each of the first TFT 9A, each of the second TFT 9B, and each capacitor 9h. Here, as... Figure 2 As shown, in the TFT layer 30, a plurality of gate lines 14g are provided, extending parallel to each other along the X direction in the figure. Furthermore, as... Figure 2 As shown, in the TFT layer 30, a plurality of light-emitting control lines 14e are provided, extending parallel to each other along the X direction in the figure. Furthermore, as... Figure 2 As shown, in the TFT layer 30, a plurality of second initialization power lines 18i are provided, extending parallel to each other along the X direction in the figure. Additionally, as... Figure 2 As shown, each light-emitting control line 14e is positioned adjacent to each gate line 14g and each second initialization power supply line 18i. Furthermore, as... Figure 2 As shown, each of the second initialization power lines 18i is configured to overlap with each of the light-emitting control lines 14e. Furthermore, as... Figure 2 As shown, in the TFT layer 30, a plurality of source lines 20f are provided, extending parallel to each other along the Y direction in the figure. Furthermore, as... Figure 2 As shown, multiple power lines 20g are provided on the TFT layer 30, extending parallel to each other along the Y direction in the figure. Additionally, as... Figure 2 As shown, each power line 20g is configured to be adjacent to each source line 20f.

[0043] In TFT layer 30, such as Figure 3 As shown, a base coating film 11 and a first semiconductor film 12 (described later) are sequentially stacked on the resin substrate 10. Figure 7 ), first gate insulating film (first inorganic insulating film) 13, first metal film 14 (see below) Figure 9 ), first interlayer insulating film (second inorganic insulating film) 15, second semiconductor film 16 (see below) Figure 12 ), second gate insulating film (third inorganic insulating film) 17a, second metal film 18 (see below) Figure 14 ), second interlayer insulating film (fourth inorganic insulating film) 19, third metal film 20 (see below) Figure 17The protective insulating film 21 and the planarization film 22 are formed. Here, the gate line 14g and the light-emitting control line 14e are formed by the first metal film 14. In addition, the second initialization power line 18i is formed by the second metal film 18. In addition, the source line 20f and the power line 20g are formed by the third metal film 20.

[0044] The base coating 11, the first gate insulating film 13, the first interlayer insulating film 15, the second gate insulating film 17a, the second interlayer insulating film 19, and the protective insulating film 21 are, for example, composed of a single layer or a stack of inorganic insulating films such as silicon nitride, silicon oxide, or silicon oxynitride. Here, at least the second semiconductor layer 16a side of the first interlayer insulating film 15 (described later) and the second semiconductor layer 16a side of the second gate insulating film 17a are, for example, composed of a silicon oxide film.

[0045] like Figure 3 As shown, the first TFT9A includes: a first semiconductor layer 12a disposed on a base coating film 11, a first gate electrode 14a disposed on the first semiconductor layer 12a through a first gate insulating film 13, a first terminal electrode 20a and a second terminal electrode 20b disposed separately on a second interlayer insulating film 19.

[0046] The first semiconductor layer 12a is formed by a first semiconductor film 12, for example, made of polycrystalline silicon such as LTPS (low temperature polysilicon). Figure 3 As shown, it includes a first conductor region 12aa and a second conductor region 12ab defined in a mutually separated manner; and a first channel region 12ac defined between the first conductor region 12aa and the second conductor region 12ab.

[0047] The first gate electrode 14a is formed of a first metal film 14, such as Figure 3 As shown, it is configured to overlap with the first channel region 12ac of the first semiconductor layer 12a and to control the conduction between the first conductor region 12aa and the second conductor region 12ab of the first semiconductor layer 12a.

[0048] The first terminal electrode 20a and the second terminal electrode 20b are formed from a third metal film 20, such as Figure 3 As shown, the first contact hole Ha and the second contact hole Hb formed by the stacked film of the first gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 19 are respectively electrically connected to the first conductor region 12aa and the second conductor region 12ab of the first semiconductor layer 12a.

[0049] like Figure 3As shown, the second TFT9B includes: a second semiconductor layer 16a disposed on the first interlayer insulating film 15, a second gate electrode 18a disposed on the second semiconductor layer 16a through the second gate insulating film 17a, a third gate electrode 14b disposed on the resin substrate 10 side of the second semiconductor layer 16a through the first interlayer insulating film 15, a third terminal electrode 20c disposed separately from each other on the second interlayer insulating film 19, and a fourth terminal electrode 20d.

[0050] The second semiconductor layer 16a is formed by a second semiconductor film 16, for example, an oxide semiconductor of the In-Ga-Zn-O system, such as... Figure 3 As shown, the device includes a third conductor region 16aa and a fourth conductor region 16ab defined in a mutually separated manner, and a second channel region 16ac defined between the third conductor region 16aa and the fourth conductor region 16ab. Here, the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited. Furthermore, the In-Ga-Zn-O semiconductor can be amorphous or crystalline. In addition, as a crystalline In-Ga-Zn-O semiconductor, a crystalline In-Ga-Zn-O semiconductor with its c-axis oriented substantially perpendicular to the layer is preferred. Furthermore, other oxide semiconductors may be included instead of the In-Ga-Zn-O semiconductor. Other oxide semiconductors may include, for example, In-Sn-Zn-O semiconductors (e.g., In2O3-SnO2-ZnO; InSnZnO). Here, In-Sn-Zn-O semiconductors are ternary oxides of In (indium), Sn (tin), and Zn (zinc). Other oxide semiconductors may also include In-Al-Zn-O semiconductors, In-Al-Sn-Zn-O semiconductors, Zn-O semiconductors, In-Zn-O semiconductors, Zn-Ti-O semiconductors, Cd-Ge-O semiconductors, Cd-Pb-O semiconductors, CdO (cadmium oxide), Mg-Zn-O semiconductors, In-Ga-Sn-O semiconductors, In-Ga-O semiconductors, Zr-In-Zn-O semiconductors, Hf-In-Zn-O semiconductors, Al-Ga-Zn-O semiconductors, Ga-Zn-O semiconductors, In-Ga-Zn-Sn-O semiconductors, InGaO3(ZnO)5, and magnesium zinc oxide (MgO). x Zn 1-x O), cadmium zinc oxide (Cd) x Zn 1-xIn addition, as a Zn-O semiconductor, it is possible to use amorphous (amorphous) structures of ZnO with one or more impurity elements from Group 1, Group 13, Group 14, Group 15, and Group 17, polycrystalline structures, microjunction structures with a mixture of amorphous and polycrystalline states, or structures without any impurity elements added.

[0051] The second gate electrode 18a is formed from the second metal film 18, such as Figure 3 As shown, it is configured to overlap with the second channel region 16ac of the second semiconductor layer 16a, and is configured to control the conduction between the third conductor region 16aa and the fourth conductor region 16ab of the second semiconductor layer 16a. Here, as... Figure 3 As shown, the second gate insulating film 17a is arranged in an island shape, overlapping with the second gate electrode 18a.

[0052] The third gate electrode 14b is formed from the first metal film 14, such as Figure 3 As shown, the third gate electrode 14b is configured to overlap with the second channel region 16ac of the second semiconductor layer 16a, and is configured to control the conduction between the third conductor region 16aa and the fourth conductor region 16ab of the second semiconductor layer 16a by being electrically connected to the second gate electrode 18a. Furthermore, the third gate electrode 14b is configured to suppress light incident on the second channel region 16ac or the arrival of impurity ions contained in the resin substrate 10 on the second channel region 16ac by overlapping with it.

[0053] The third terminal electrode 20c and the fourth terminal electrode 20d are formed from the third metal film 20, such as Figure 3 As shown, the third conductor region 16aa and the fourth conductor region 16ab of the second semiconductor layer 16a are electrically connected via the third contact hole Hc and the fourth contact hole Hd formed in the second interlayer insulating film 19, respectively.

[0054] like Figure 5 As shown, each of the terminal electrodes 20x—first terminal electrode 20a, second terminal electrode 20b, third terminal electrode 20c, and fourth terminal electrode 20d—has a lower metal layer 6, a middle metal layer 7, and an upper metal layer 8 stacked sequentially. Here, the lower metal layer 6 and the upper metal layer 8 are formed of, for example, a titanium film or a molybdenum film. Furthermore, the middle metal layer 7 is formed of, for example, an aluminum film. Therefore, the middle metal layer 7 has a lower resistance and a lower melting point than the lower metal layer 6 and the upper metal layer 8. Alternatively, the lower metal layer 6 and the upper metal layer 8 may be formed of, for example, an alloy film of titanium or molybdenum, and the middle metal layer 7 may be formed of, for example, an alloy film of aluminum. Moreover, at the ends of each terminal electrode 20x, such as… Figure 5As shown, the end faces of the lower metal layer 6 and the middle metal layer 7 are aligned, and the upper metal layer 8 is provided to cover their aligned end faces. Furthermore, the source line 20f and the power line 20g are formed in the same layer as the first terminal electrode 20a, the second terminal electrode 20b, the third terminal electrode 20c, and the fourth terminal electrode 20d using the same material. Therefore, like each terminal electrode 20x, they have a lower metal layer 6, a middle metal layer 7, and an upper metal layer 8 stacked sequentially. Moreover, at both ends of the source line 20f and the power line 20g, the end faces of the lower metal layer 6 and the middle metal layer 7 are aligned, and the upper metal layer 8 is provided to cover their aligned end faces (see reference). Figure 5 ).

[0055] In this embodiment, four first TFTs 9A having a first semiconductor layer 12a formed of polysilicon are exemplified by a writing TFT 9c, a driving TFT 9d, a power supply TFT 9e, and a light emission control TFT 9f, which will be described later. Three second TFTs 9B having a second semiconductor layer 16a formed of oxide semiconductor are exemplified by an initialization TFT 9a, a compensation TFT 9b, and an anode discharge TFT 9g, which will be described later (see reference). Figure 4 Additionally, in Figure 4 In the equivalent circuit diagram, the circled numbers 1 and 2 represent the first terminal electrode 20a and the second terminal electrode 20b of each TFT 9c, 9d, 9e, and 9f, and the circled numbers 3 and 4 represent the third terminal electrode 20c and the fourth terminal electrode 20d of each TFT 9a, 9b, and 9g. Furthermore, in Figure 4 The equivalent circuit diagram shows the pixel circuit of sub-pixel P in row n and column m, but also includes a portion of the pixel circuit of sub-pixel P in row (n-1) and column m. Furthermore, in Figure 4 In the equivalent circuit diagram, the power line 20g supplying the high power supply voltage ELVDD also serves as the first initialization power line, but power line 20g and the first initialization power line can also be provided separately. Furthermore, the same voltage as the low power supply voltage ELVSS is input to the second initialization power line 18i, but this is not a limitation; a voltage different from the low power supply voltage ELVSS can also be input, such as a voltage that turns off the organic EL element 35 described later.

[0056] Initialization using TFT9a, such as Figure 4 As shown, in each sub-pixel P, its gate electrode is electrically connected to the gate line 14g(n-1) of the previous stage (n-1 segment), its third terminal electrode is electrically connected to the lower conductive layer of the capacitor 9h described later and the gate electrode of the driving TFT 9d, and its fourth terminal electrode is electrically connected to the power line 20g.

[0057] Compensation using TFT9b, such as Figure 4 As shown, in each sub-pixel P, its gate electrode is electrically connected to the gate line 14g(n) of the current level (n level), its third terminal electrode is electrically connected to the gate electrode of the driving TFT 9d, and its fourth terminal electrode is electrically connected to the first terminal electrode of the driving TFT 9d.

[0058] Write using TFT9c, such as Figure 4 As shown, in each sub-pixel P, its gate electrode is electrically connected to the gate line 14g(n) of the current level (n level), its first terminal electrode is electrically connected to the corresponding source line 20f, and its second terminal electrode is electrically connected to the second terminal electrode of the driving TFT 9d.

[0059] TFT9d for driving Figure 4 As shown, in each sub-pixel P, its gate electrode is electrically connected to the third terminal electrode of the initialization TFT 9a and the compensation TFT 9b, its first terminal electrode is electrically connected to the fourth terminal electrode of the compensation TFT 9b and the second terminal electrode of the power supply TFT 9e, and its second terminal electrode is electrically connected to the second terminal electrode of the writing TFT 9c and the first terminal electrode of the light emission control TFT 9f. Here, the driving TFT 9d is configured to control the driving current of the organic EL element 35.

[0060] TFT9e for power supply, such as Figure 4 As shown, in each sub-pixel P, its gate electrode is electrically connected to the light-emitting control line 14e of the current level (n level), its first terminal electrode is electrically connected to the power supply line 20g, and its second terminal electrode is electrically connected to the first terminal electrode of the driving TFT 9d.

[0061] TFT9F for light emission control, such as Figure 4 As shown, in each sub-pixel P, its gate electrode is electrically connected to the light emission control line 14e of the current level (n level), its first terminal electrode is electrically connected to the second terminal electrode of the driving TFT 9d, and its second terminal electrode is electrically connected to the first electrode 31 of the organic EL element 35 described later.

[0062] TFT9g for anode discharge Figure 4 As shown, in each sub-pixel P, its gate electrode is electrically connected to the gate line 14g(n) of the current level (n level), its third terminal electrode is electrically connected to the first electrode 31 of the organic EL element 35, and its fourth terminal electrode is electrically connected to the second initialization power line 18i.

[0063] The capacitor 9h, for example, includes: a lower conductive layer (not shown) formed of a first metal film 14, a first interlayer insulating film 15 covering the lower conductive layer, and a second gate insulating film (not shown), and an upper conductive layer (not shown) formed of a second metal film 18 disposed on the second gate insulating film in a manner overlapping the lower conductive layer. Furthermore, the capacitor 9h, as... Figure 4 As shown, in each sub-pixel P, its lower conductive layer is electrically connected to the gate electrode of the driving TFT9d, the initialization TFT9a, and the third terminal electrode of the compensation TFT9b, and its upper conductive layer is electrically connected to the third terminal electrode of the anode discharge TFT9g, the second terminal electrode of the light emission control TFT9f, and the first electrode 31 of the organic EL element 35.

[0064] The planarization film 22 has a flat surface in the display area D, and is made of organic resin materials such as polyimide resin and acrylic resin, or polysiloxane-based SOG (spin on glass) materials.

[0065] Organic EL element layer 40 Figure 3 The device includes: a plurality of organic EL elements 35 arranged in a matrix to correspond to a plurality of sub-pixels P as a plurality of light-emitting elements; and an edge cover 32 arranged in a grid pattern and shared with all sub-pixels P to cover the periphery of the first electrode 31 of each organic EL element 35.

[0066] Organic EL element 35 such Figure 3 As shown, each sub-pixel P includes: a first electrode 31 disposed on the planarization film 22 of the TFT layer 30, an organic EL layer 33 disposed on the first electrode 31, and a second electrode 34 disposed on the organic EL layer 33.

[0067] The first electrode 31 is electrically connected to the second terminal electrode of the TFT 9f for light emission control of each sub-pixel P via a contact hole formed in the laminated film of the protective insulating film 21 and the planarization film 22. Furthermore, the first electrode 31 has the function of injecting holes (holes) into the organic EL layer 33. Moreover, to improve the hole injection efficiency into the organic EL layer 33, the first electrode 31 is preferably formed of a material with a high working function. Examples of materials constituting the first electrode 31 include, for example, metallic materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). Additionally, the material constituting the first electrode 31 may also be an alloy such as astatine (At) / atamine oxide (AtO2). Furthermore, the material constituting the first electrode 31 can be, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Additionally, the first electrode 31 can be formed by stacking multiple layers composed of the aforementioned materials. Furthermore, compound materials with high working functions are, for example, indium tin oxide (ITO) and indium zinc oxide (IZO).

[0068] like Figure 6 As shown, the organic EL layer 33 comprises: a hole injection layer 1, a hole transport layer 2, a light emission layer 3, an electron transport layer 4, and an electron injection layer 5 sequentially disposed on the first electrode 31.

[0069] Hole injection layer 1, also known as the anode buffer layer, functions to bring the energy levels of the first electrode 31 and the organic EL layer 33 closer together and improve the hole injection efficiency from the first electrode 31 to the organic EL layer 33. Examples of materials constituting hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrene-anthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0070] The hole transport layer 2 has the function of improving the efficiency of hole transport from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styreneamine derivatives, polyvinylcarbazole, poly(p-phenylenevinylene), polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrene-anthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.

[0071] The light-emitting layer 3 is a region in which holes and electrons are injected from the first electrode 31 and the second electrode 34 respectively when a voltage is applied through the first electrode 31 and the second electrode 34, and the holes and electrons recombine. Here, the light-emitting layer 3 is formed of a material with high luminous efficiency. Moreover, examples of materials constituting the light-emitting layer 3 include, for example, oxynoid compounds [8-hydroxyquinoline metal complexes], naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzene derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazolium derivatives, styryl derivatives, styrylamine derivatives, bis(styryl)benzene derivatives, tristyrylbenzene derivatives, perylene derivatives, piperidinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, acridine derivatives, phenoxazine, quinacridone derivatives, rubrene, poly(p-phenylenevinylene), polysilane, etc.

[0072] The electron transport layer 4 has the function of efficiently moving electrons to the light-emitting layer 3. Here, as a material constituting the electron transport layer 4, examples of organic compounds include oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinone dimethane derivatives, biphenylquinone derivatives, fluorenone derivatives, thiophene derivatives, and oxynoid compounds.

[0073] The electron injection layer 5 functions to bring the energy levels of the second electrode 34 and the organic EL layer 33 closer together, thereby improving the efficiency of electron injection from the second electrode 34 into the organic EL layer 33. This function reduces the driving voltage of the organic EL element 35. Furthermore, the electron injection layer 5 is also referred to as the cathode buffer layer. Examples of materials constituting the electron injection layer 5 include, for instance, inorganic alkaline compounds such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), and barium fluoride (BaF2), as well as alumina (Al2O3) and strontium oxide (SrO).

[0074] like Figure 3As shown, the second electrode 34 is shared with all sub-pixels P in a manner that covers each organic EL layer 33 and the edge mask 32. Furthermore, the second electrode 34 has the function of injecting electrons into the organic EL layer 33. Moreover, to improve the electron injection efficiency into the organic EL layer 33, the second electrode 34 is preferably made of a material with a low working function. Examples of materials constituting the second electrode 34 include, for instance, silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). Furthermore, the second electrode 34 may also be formed of alloys such as magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO2), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). Additionally, the second electrode 34 may also be formed of conductive oxides such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). Furthermore, the second electrode 34 may also be formed by stacking multiple layers composed of the above-mentioned materials. In addition, materials with small working functions include, for example, magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al), etc.

[0075] The edge cover 32 is made of organic resin materials such as polyimide resin and acrylic resin, or SOG materials based on polysiloxane.

[0076] like Figure 3 As shown, the sealing film 45 is configured to cover the second electrode 34 and has a first inorganic sealing film 41, an organic sealing film 42 and a second inorganic sealing film 43 sequentially stacked on the second electrode 34, which has the function of protecting the organic EL layer 33 of the organic EL element layer 35 from the influence of moisture and oxygen.

[0077] The first inorganic sealing membrane 41 and the second inorganic sealing membrane 43 are, for example, composed of inorganic insulating membranes such as silicon nitride membrane, silicon oxide membrane, and silicon oxynitride membrane.

[0078] Organic sealing film 42 is composed of organic resin materials such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, and polyamide resin.

[0079] In the organic EL display device 50 with the above-described structure, in each sub-pixel P, firstly, if the light-emitting control line 14e is selected and becomes inactive, the organic EL element 35 becomes non-light-emitting. In this non-light-emitting state, the gate line 14g(n-1) of the preceding stage is selected, and the gate signal is input to the initialization TFT 9a via the gate line 14g(n-1), thereby turning on the initialization TFT 9a. The high power supply voltage ELVDD of the power supply line 20g is applied to the capacitor 9h, and the driving TFT 9d becomes on. As a result, the charge of the capacitor 9h is discharged, and the voltage applied to the gate electrode of the driving TFT 9d is initialized. Next, the gate line 14g(n) of this stage is selected to become active, thereby turning on the compensation TFT 9b and the writing TFT 9c. The predetermined voltage corresponding to the source signal transmitted via the corresponding source line 20f is written to the capacitor 9h via the driving TFT 9d connected to the diode, and the anode discharge TFT 9g becomes active. The initialization signal is applied to the first electrode 31 of the organic EL element 35 via the second initialization power line 18i, and the charge accumulated on the first electrode 31 is reset. Thereafter, the light emission control line 14e is selected, and the power supply TFT 9e and the light emission control TFT 9f become active. The driving current corresponding to the voltage applied to the gate electrode of the driving TFT 9d is supplied to the organic EL element 35 from the power line 20g. Thus, in the organic EL display device 50, in each sub-pixel P, the organic EL element 35 emits light with a brightness corresponding to the driving current to display an image.

[0080] Next, the manufacturing method of the organic EL display device 50 according to this embodiment will be described. Furthermore, the manufacturing method of the organic EL display device 50 includes a TFT layer formation process, an organic EL element layer formation process, and a sealing film formation process. Here, Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 as well as Figure 19 These are cross-sectional views showing the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, and thirteenth steps of the manufacturing process (TFT layer formation process) of the organic EL display device 50. Furthermore, Figure 20 This is following the patterning process of the third metal film 20 in the manufacturing process (TFT layer formation process) of the organic EL display device 50. Figure 2The sectional view corresponding to the XX-XX line in the diagram.

[0081] <TFT layer formation process>

[0082] First, for example, on a resin substrate 10 formed on a glass substrate, a silicon nitride film (about 50 nm thick) and a silicon oxide film (about 250 nm thick) are sequentially formed by plasma CVD (Chemical Vapor Deposition) to form a base coating film 11.

[0083] Next, on the surface of the substrate on which the base coating 11 is formed, for example, an amorphous silicon film (approximately 50 nm thick) is formed by plasma CVD, and the amorphous silicon film is crystallized by laser annealing or the like. Figure 7 As shown, a first semiconductor film 12 made of polycrystalline silicon is formed. Subsequently, the first semiconductor film 12 is patterned, as shown... Figure 8 As shown, a first semiconductor layer 12a is formed.

[0084] Furthermore, on the surface of the substrate where the first semiconductor layer 12a is formed, for example, a silicon oxide film (approximately 100 nm thick) is formed by plasma CVD. After the first gate insulating film 13 is formed, for example, a molybdenum film (approximately 200 nm thick) is formed by sputtering. Figure 9 As shown, a first metal film 14 is formed.

[0085] Subsequently, the first metal film 14 is patterned, such as... Figure 10 As shown, a first gate electrode 14a and a third gate electrode 14b are formed.

[0086] Next, using the first gate electrode 14a as a mask, as follows: Figure 11 As shown, phosphorus and other impurity ions are doped, thereby forming a first conductor region 12aa, a second conductor region 12ab, and a first channel region 12a in the first semiconductor layer 12a.

[0087] Furthermore, on the surface of a substrate doped with impurity ions, for example, a silicon nitride film (approximately 150 nm thick) and a silicon oxide film (approximately 100 nm thick) are sequentially formed by plasma CVD, thereby forming a first interlayer insulating film 15. Then, for example, an oxide semiconductor film such as InGaZnO4 (approximately 30 nm thick) is formed by sputtering. Figure 12 As shown, a second semiconductor film 16 is formed.

[0088] Subsequently, the second semiconductor film 16 is patterned, such as... Figure 13 As shown, a second semiconductor layer 16a is formed thereon.

[0089] Next, on the surface of the substrate where the second semiconductor layer 16a is formed, for example by plasma CVD, a silicon oxide film (approximately 100 nm thick) is formed, thereby forming the second gate insulating film 17. Then, for example by sputtering, a molybdenum film (approximately 200 nm thick) is formed, etc. Figure 14 As shown, a second metal film 18 is formed.

[0090] Subsequently, the second metal film 18 and the second gate insulating film forming film 17 are patterned, such as... Figure 15 As shown, a second gate insulating film 17a and a second gate electrode 18a are formed.

[0091] Furthermore, on the surface of the substrate where the second gate electrode 18a is formed, for example, a silicon oxide film (approximately 300 nm thick) and a silicon nitride film (approximately 150 nm thick) are sequentially formed by plasma CVD. Figure 16 As shown, a second interlayer insulating film 19 is formed. In addition, through heat treatment after the formation of the second interlayer insulating film 19, a portion of the second semiconductor layer 16a is made conductive, and a third conductor region 16aa, a fourth conductor region 16ab, and a second channel region 16ac are formed in the second semiconductor layer 16a.

[0092] Next, relative to the substrate surface on which the second interlayer insulating film 19 is formed, the first gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 19 are patterned to form the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, the fourth contact hole Hd, etc.

[0093] Subsequently, on the substrate surface where the first contact hole Ha is formed, for example, a titanium film (thickness of about 50 nm) and an aluminum film (thickness of about 400 nm) are sequentially formed as a lower metal film and an intermediate metal film by sputtering. Then, the stacked film of the titanium film and aluminum film is patterned by dry etching to form a lower metal layer 6 and an intermediate metal layer 7 (first patterning process).

[0094] Furthermore, on the surface of the substrate where the lower metal layer 6 and the middle metal layer 7 are formed, for example, a titanium film (approximately 100 nm thick) is formed as the upper metal film by sputtering. Figure 17 As shown, a third metal film 20 is formed (the stack of the lower metal layer 6 and the middle metal layer 7 is covered by the upper metal film).

[0095] Subsequently, the upper metal film of the third metal film 20 is patterned by dry etching to form the upper metal layer 8, thereby... Figure 18As shown, a first terminal electrode 20a, a second terminal electrode 20b, a third terminal electrode 20c, and a fourth terminal electrode 20d are formed (second patterning process). Here, the substrate surface after the process of patterning the third metal film 20 is as follows: Figure 20 As shown, the surface elevation difference of the second interlayer insulating film 19 increases, but for the titanium / aluminum / titanium film stack, dry etching is performed twice, thus suppressing the formation of residue R on the third metal film 20. Furthermore, for example, although the source line 20f and power line 20g (formed simultaneously on the second interlayer insulating film 19 with the first terminal electrode 21a, etc.) are formed along... Figure 20 The X-direction extends adjacent to each other, but the generation of residue R in the third metal film 20 is suppressed, thus suppressing the short circuit between adjacent source lines 20f and power lines 20g.

[0096] Furthermore, on the surface of the substrate where the first terminal electrode 20a is formed, for example, a silicon oxide film (approximately 250 nm thick) is formed by plasma CVD, thereby forming a protective insulating film 21. Then, for example, an acrylic photosensitive resin film (approximately 2 μm thick) is coated by spin coating or slot coating. This coated film is then pre-baked, exposed, developed, and post-baked. Figure 19 As shown, a planarization film 22 with contact holes (not shown) is formed.

[0097] Finally, the protective insulating film 21 exposed from the contact hole of the planarization film 22 is removed, so that the contact hole reaches the second terminal electrode of the light-emitting control TFT 9f.

[0098] The TFT layer 30 can be formed as described above.

[0099] In addition, in this embodiment, a method is shown to form the upper metal layer 8 in such a way that it covers each end face of the lower metal layer 6 and the middle metal layer 7. However, the upper metal layer 8 may also be formed in such a way that each end face of the lower metal layer 6 and the middle metal layer 7 is exposed.

[0100] <Organic EL Component Layer Formation Process>

[0101] On the planarization film 22 of the TFT layer 30 formed in the above-mentioned TFT layer formation process, a first electrode 31, an edge mask 32, an organic EL layer 33 (hole injection layer 1, hole transport layer 2, light emission layer 3, electron transport layer 4, electron injection layer 5) and a second electrode 34 are formed using known methods to form an organic EL element layer 40.

[0102] <Sealing film formation process>

[0103] First, on the surface of the substrate on which the organic EL element layer 40 formed in the above-mentioned organic EL element layer formation process is formed, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by using a mask, for example, by plasma CVD, to form a first inorganic sealing film 41.

[0104] Next, on the surface of the substrate on which the first inorganic sealing film 41 is formed, for example, an organic resin material such as acrylic resin is formed by inkjet printing to form an organic sealing film 42.

[0105] Subsequently, on the substrate surface where the organic sealing film 42 is formed, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed using a mask, for example, by plasma CVD, to form a second inorganic sealing film 43, thereby forming a sealing film 45.

[0106] Finally, after a protective sheet (not shown) is attached to the surface of the substrate on which the sealing film 45 is formed, the glass substrate is peeled off from the lower surface of the resin substrate 10 by irradiating it with a laser from the glass substrate side of the resin substrate 10, and a protective sheet (not shown) is attached to the lower surface of the resin substrate 10 on which the glass substrate has been peeled off.

[0107] The organic EL display device 50 of this embodiment can be manufactured as described above.

[0108] As explained above, according to the organic EL display device 50 and its manufacturing method of this embodiment, each terminal electrode 20x of the first terminal electrode 20a and second terminal electrode 20b of the first TFT 9A and the third terminal electrode 20c and fourth terminal electrode 20d of the second TFT 9B comprises a lower metal layer 6, an intermediate metal layer 7, and an upper metal layer 8 stacked sequentially. Furthermore, at the ends of each terminal electrode 20x, the end faces of the lower metal layer 6 and the intermediate metal layer 7 are aligned, and the upper metal layer 8 is provided to cover these aligned end faces. To obtain the structure of the ends of the terminal electrodes 20x, in the first patterning process, a lower metal film forming the lower metal layer 6 and an intermediate metal film forming the intermediate metal layer 7 are sequentially formed on the second interlayer insulating film 19. The lower metal film and the intermediate metal film are patterned by dry etching to form the lower metal layer 6 and the intermediate metal layer 7 with aligned end faces. In the second patterning process following it, an upper metal film, which becomes the upper metal layer 8, is formed by covering the lower metal layer 6 and the intermediate metal layer 7. This upper metal film is patterned by dry etching, and the upper metal layer 8 is formed by covering the end faces of the lower metal layer 6 and the intermediate metal layer 7. According to this formation method, the lower metal film, the intermediate metal film, and the upper metal film are patterned by two dry etching processes. Therefore, the generation of metal film residue R, which is a concern when the lower metal film, the intermediate metal film, and the upper metal film are patterned by one dry etching process, is suppressed. As a result, the first gate electrode 14a, the second gate electrode 18a, and the third gate electrode 14b are formed in the lower layer. On the second interlayer insulating film 19 with a large surface height difference, the generation of residue R in the third metal film 20 is suppressed. Therefore, short circuits between adjacent terminal electrodes 20x (between the first terminal electrode 20a and the second terminal electrode 20b, and between the third terminal electrode 20c and the fourth terminal electrode 20d) can be suppressed. Furthermore, at the end of the terminal electrode 20x, the end face of the lower metal layer 6 and the end face of the intermediate metal layer 7 are aligned with each other, and the upper metal layer 8 is provided to cover the aligned end faces. Therefore, oxidation and corrosion of the intermediate metal layer 7 can be suppressed, and in particular, the characteristic degradation of the second TFT 9B using oxide semiconductor can be suppressed.

[0109] Furthermore, according to the organic EL display device 50 and its manufacturing method of this embodiment, the source line 20f and power line 20g are formed on the same layer as the first terminal electrode 20a, second terminal electrode 20b, third terminal electrode 20c, and fourth terminal electrode 20d using the same material. Therefore, similar to each terminal electrode 20x, a lower metal layer 6, an intermediate metal layer 7, and an upper metal layer 8 are sequentially stacked. Moreover, at both ends of the source line 20f and power line 20g, the end faces of the lower metal layer 6 and the intermediate metal layer 7 are aligned with each other, and the upper metal layer 8 is provided to cover these aligned end faces. Therefore, similar to each terminal electrode 20x, the generation of residue R of the third metal film 20 is suppressed on the second interlayer insulating film 19 with a large surface height difference, thus suppressing short circuits between adjacent source lines 20f and power lines 20g. Furthermore, at both ends of the source line 20f and the power line 20g, the end face of the lower metal layer 6 and the end face of the middle metal layer 7 are aligned with each other, and the upper metal layer 8 is provided to cover the aligned end faces. Therefore, oxidation and corrosion of the middle metal layer 7 are suppressed, and in particular, the characteristic degradation of the second TFT9B using oxide semiconductor is suppressed.

[0110] Furthermore, according to the organic EL display device 50 and its manufacturing method of this embodiment, in the second TFT 9B, a third gate electrode 14b is provided on the resin substrate 10 side of the second semiconductor layer 16a in a manner overlapping with the second channel region 16ac. Therefore, the diffusion of impurity ions contained in the resin substrate 10 into the second channel region 16ac and the incident light into the second channel region 16ac are suppressed respectively, and the characteristic degradation of the second TFT 9B can be suppressed.

[0111] Furthermore, according to the organic EL display device 50 and its manufacturing method of this embodiment, the second TFT9B has a second gate electrode 18a and a third gate electrode 14b, and has a dual gate structure, thus improving the driving capability of the second TFT9B.

[0112] Furthermore, according to the organic EL display device 50 and its manufacturing method of this embodiment, a base coating film 11 composed of an inorganic insulating film is provided between the resin substrate 10 and the first semiconductor layer 12a, thereby suppressing the film peeling of the first semiconductor layer 12a and the like.

[0113] Other Implementation Methods

[0114] In the above embodiments, an organic EL layer with a five-layer stacked structure of a hole injection layer, a hole transport layer, a light emission layer, an electron transport layer, and an electron injection layer is shown. However, the organic EL layer may also be a three-layer stacked structure of a hole injection layer that also serves as a hole transport layer, a light emission layer, and an electron transport layer that also serves as an electron injection layer.

[0115] Furthermore, in the above embodiments, an organic EL display device with a first electrode as the anode and a second electrode as the cathode is illustrated. However, the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed, with the first electrode as the cathode and the second electrode as the anode.

[0116] Furthermore, in the above embodiments, an organic EL display device was described as an example of a display device, but the present invention can be applied to display devices having multiple light-emitting elements driven by current, such as display devices having light-emitting elements using a layer containing quantum dots, i.e., QLED (Quantum-dot light emitting diode).

[0117] Industrial availability

[0118] As explained above, the present invention is useful for flexible display devices.

[0119] Explanation of reference numerals in the attached figures

[0120] D display area

[0121] P-subpixel

[0122] 6. Lower metal layer

[0123] 7 Intermediate Metal Layer

[0124] 8. Upper metal layer

[0125] 9A First TFT (First Thin Film Transistor)

[0126] 9B Second TFT (First Thin Film Transistor)

[0127] 9a Initialization TFT (Second Thin Film Transistor)

[0128] 9b compensation TFT (second thin-film transistor)

[0129] 9c write-in TFT (first thin-film transistor)

[0130] TFT (First Thin Film Transistor) for 9D Driving

[0131] 9e power supply TFT (first thin-film transistor)

[0132] 9F TFT (First Thin Film Transistor) for Light Emitting Control

[0133] 9g TFT (Second Thin Film Transistor) for Anode Discharge

[0134] 10. Resin substrate (base substrate)

[0135] 11 Primer film

[0136] 12 First Semiconductor Film

[0137] 12a First Semiconductor Layer

[0138] 12aa First Conductor Region

[0139] 12ab Second Conductor Region

[0140] 12ac First Channel Area

[0141] 13. First gate insulating film (first inorganic insulating film)

[0142] 14 First Metal Film

[0143] 14a First gate electrode

[0144] 14b Third gate electrode

[0145] 15. First interlayer insulating film (second inorganic insulating film)

[0146] 16 Second Semiconductor Film

[0147] 16a Second Semiconductor Layer

[0148] 16aa Third Conductor Region

[0149] 16ab fourth conductor region

[0150] 16ac Second Channel Area

[0151] 17a Second gate insulating film (third inorganic insulating film)

[0152] 18 Second Metal Film

[0153] 18a Second Gate Electrode

[0154] 19. Second interlayer insulating film (fourth inorganic insulating film)

[0155] 20 Third Metal Film

[0156] 20a First Terminal Electrode

[0157] 20b Second Terminal Electrode

[0158] 20c third terminal electrode

[0159] 20d fourth terminal electrode

[0160] 20f source line (conductive layer)

[0161] 20g power cord (conductive layer)

[0162] 20x terminal electrodes (conductive layer)

[0163] 30 TFT layers (thin-film transistor layers)

[0164] 35 Organic EL components (organic electroluminescent components, light-emitting components)

[0165] 40 Organic EL element layer (light-emitting element layer)

[0166] 45 sealing film

[0167] 50 Organic EL Display Device.

Claims

1. A display device comprising: Substrate; as well as A thin-film transistor layer is disposed on the substrate and consists of, in sequence, a first semiconductor film made of polycrystalline silicon, a first inorganic insulating film, a first metal film, a second inorganic insulating film, a second semiconductor film made of oxide semiconductor, a third inorganic insulating film, a second metal film, a fourth inorganic insulating film, and a third metal film. In the thin-film transistor layer, a first thin-film transistor and a second thin-film transistor are provided for each sub-pixel constituting the display area. The first thin-film transistor has a first semiconductor layer formed of the first semiconductor film, and the second thin-film transistor has a second semiconductor layer formed of the second semiconductor film. The first thin-film transistor includes: The first semiconductor layer defines a first conductor region and a second conductor region in a mutually separated manner, and defines a first channel region between the first conductor region and the second conductor region; The first gate electrode is disposed on the first semiconductor layer, separated by the first inorganic insulating film, and is formed of the first metal film; as well as The first terminal electrode and the second terminal electrode are disposed separately through the third metal film and are electrically connected to the first conductor region and the second conductor region, respectively. The second thin-film transistor includes: The second semiconductor layer defines a third conductor region and a fourth conductor region in a mutually separated manner, and defines a second channel region between the third conductor region and the fourth conductor region; The second gate electrode is disposed on the second semiconductor layer, separated by the third inorganic insulating film, and is formed of the second metal film; as well as The third terminal electrode and the fourth terminal electrode are disposed separately through the third metal film and are electrically connected to the third conductor region and the fourth conductor region, respectively. The display device is characterized in that... Each of the first terminal electrode, the second terminal electrode, the third terminal electrode, and the fourth terminal electrode has a lower metal layer, a middle metal layer, and an upper metal layer stacked sequentially. The intermediate metal layer has a lower electrical resistance and a lower melting point than the lower metal layer and the upper metal layer. At the ends of each terminal electrode, the end face of the lower metal layer and the end face of the middle metal layer are aligned with each other, and the upper metal layer is provided to cover the aligned end faces.

2. The display device according to claim 1, characterized in that, The second thin-film transistor has a third gate electrode disposed on the substrate side of the second semiconductor layer, separated by the second inorganic insulating film, and formed by the first metal film.

3. The display device according to claim 1 or 2, characterized in that, The third inorganic insulating film is configured to overlap with the second gate electrode.

4. The display device according to any one of claims 1 to 3, characterized in that, The lower metal layer and the upper metal layer are formed of titanium film or molybdenum film. The intermediate metal layer is formed of an aluminum film.

5. The display device according to any one of claims 1 to 4, characterized in that, The thin-film transistor layer has: Multiple source lines are arranged in a parallel manner and formed by the third metal film; as well as Multiple power lines are respectively disposed between the multiple source lines and are formed by the third metal film in a parallel manner. Each source line and each power line includes a lower metal layer, a middle metal layer, and an upper metal layer. At both ends of each source line and each power line, the end face of the lower metal layer and the end face of the middle metal layer are aligned with each other, and the upper metal layer is provided to cover the aligned end faces.

6. The display device according to any one of claims 1 to 5, characterized in that, The substrate is formed of an organic resin material.

7. The display device according to claim 6, characterized in that, A primer film is formed on the substrate. The first semiconductor layer is disposed on the base coating film.

8. The display device according to any one of claims 1 to 7, characterized in that, have: A light-emitting element layer is disposed on the thin-film transistor layer and a plurality of light-emitting elements are arranged thereon; and A sealing film is disposed on the light-emitting element layer.

9. The display device according to claim 8, characterized in that, Each of the light-emitting elements is an organic electroluminescent element.

10. A method for manufacturing a display device, comprising the method for manufacturing the display device according to any one of claims 1 to 9, characterized in that, The process of patterning the third metal film includes: In the first patterning process, after a lower metal film serving as the lower metal layer and an intermediate metal film serving as the intermediate metal layer are sequentially formed on the fourth inorganic insulating film, the lower metal film and the intermediate metal film are patterned by dry etching to form the lower metal layer and the intermediate metal layer; and In the second patterning process, after an upper metal film is formed to cover the lower metal layer and the intermediate metal layer formed in the first patterning process, the upper metal layer is formed by patterning the upper metal film through dry etching.

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