A method for extending a trusted execution environment boundary for an FPGA

Abstract

The application discloses a kind of FPGA-oriented trusted execution environment boundary extension method, including following three parts:1, for the control flow and data flow transmission of host end to FPGA device, construct system control path and data path, including system security start and identity authentication and trusted I / O channel construction;2, for the computing mode and security requirement of heterogeneous trusted computing task, implement computing and storage resource hierarchical isolation and sharing, including safe boundary physical strong isolation, inter-application memory isolation and inter-process memory isolation sharing;3, for the running characteristics of common application are counted and investigated, adopt the elastic extension scheme containing application characteristics, including application computing and memory access behavior research and investigation, hardware resource and computing mode packaging and high-frequency operator library construction.The application realizes the design of control and computing separation, establishes flexible, efficient heterogeneous trusted execution environment, solves the problem of processor trusted execution environment and heterogeneous computing device fragmentation.

Description

Technical Field

[0001] This invention belongs to the field of computer information security technology, specifically relating to a trusted execution environment boundary extension method for FPGA. Background Technology

[0002] With the development and application of heterogeneous computing technology, FPGA accelerator chips possess high computing performance and low power consumption characteristics. Due to these advantages, FPGA accelerator chips are now widely used in numerous fields, bringing significant improvements in computing performance to these applications.

[0003] However, in the face of emerging applications such as security-sensitive medical data processing and financial industry applications, heterogeneous computing lacks effective trusted computing technology support, which limits trusted environment technology from providing stronger and more fundamental system and data security capabilities for heterogeneous computing technology.

[0004] Traditional computing tasks primarily rely on the CPU. Therefore, the traditional Trusted Execution Environment (CPU-TEE) built on the CPU based on hardware-software isolation mechanisms can provide a trusted computing environment for user applications. However, CPU-based TEE solutions cannot be directly built and applied on heterogeneous chips, hindering heterogeneous computing from benefiting from the strong hardware-level security guarantees provided by the TEE. Therefore, research on building heterogeneous TEEs for heterogeneous computing scenarios based on general-purpose accelerator chips (FPGAs) is urgently needed. The FPGA-based TEE boundary extension method, based on the computing mode and special security model of heterogeneous computing, designs and builds a TEE suitable for heterogeneous computing scenarios where FPGAs are the primary devices. This TEE is flexible, efficient, and highly secure; moreover, its construction does not require modification of the hardware, thus exhibiting high adaptability.

[0005] The construction of a Trusted Execution Environment (TEE) involves creating a secure region within a central processing unit (CPU) using both hardware and software methods. This ensures the confidentiality and integrity of programs running and data loaded within the TEE. CPUs supporting TEE typically have their TEE control unit pre-integrated into the CPU chip, preventing its placement in the background. Therefore, only some CPU chips support TEE. Currently, mainstream CPUs utilize TEE technologies such as InterSGX and TDX based on the x86 instruction set architecture, and ARM's TrustZone. TEE technology is widely used for protecting confidential data and core programs, such as payment verification data and code protection in smartphones. TEE technology provides security at the hardware level. Summary of the Invention

[0006] This invention addresses the shortcomings of existing technologies by providing a trusted execution environment boundary extension method for FPGAs.

[0007] This invention is achieved through the following technical solution:

[0008] A trusted execution environment boundary extension method for FPGAs includes:

[0009] For the control and data flow transmission from the host to the FPGA device, a system control path and data path are constructed, including secure system startup and authentication, and the construction of a trusted I / O channel. Specifically, the system first ensures the secure startup and execution of the security boundary controller and system components through secure startup, while completing the device system authentication and sharing the I / O channel key. Finally, the control and data flows from the host are encrypted using an encryption key, and direct communication is achieved through the task queue of the security boundary controller, thus constructing an encrypted I / O channel from the host to the FPGA device, thereby realizing data protection of the I / O channel.

[0010] To address the computational patterns and security requirements of heterogeneous trusted computing tasks, a hierarchical isolation and sharing strategy for computing and storage resources is implemented. This includes strong physical isolation at security boundaries, memory isolation between applications, and memory isolation and sharing between processes. Specifically: For the boundary between the secure and insecure worlds, the inaccessibility of FPGA runtime to the outside world is utilized to ensure strong physical isolation at the security boundary of the trusted execution environment; for different applications running on the FPGA chip, application memory boundary checks are used to establish application-based memory isolation, ensuring the inaccessibility of memory data between applications and achieving data isolation between different applications within the trusted execution environment, thus ensuring application data security; for complex applications requiring frequent data interaction, process-level memory space isolation is provided, and an inter-process memory isolation mechanism is designed to achieve data isolation and minimize the overhead of data interaction between processes; through nested combinations of multi-level memory isolation mechanisms, an efficient memory sharing mode is established while ensuring data isolation between applications, guaranteeing data security.

[0011] This study statistically investigates and surveys the operational characteristics of commonly used applications, and adopts a flexible expansion scheme that incorporates application characteristics. This includes research and investigation of application computation and memory access behavior, encapsulation of hardware resources and computational modes, and construction of a high-frequency operator library. Specifically: First, research and investigation are conducted on the computation and memory access behavior characteristics of different types of applications; second, descriptions and abstractions of hardware resources and computational modes at different granularities are provided for applications with different characteristics, and resource description interfaces of different fine granularities are designed. For computational behaviors with high computational time overhead and high resource consumption, hardware resources are abstracted, organized, encapsulated, and corresponding operators are constructed; third, based on the different basic applications required by the usage scenarios, an application basic operator library is established, adapting to different basic applications and providing flexible and efficient modular application interfaces.

[0012] Furthermore, a secure boot process is achieved through a "root of trust". The secure boot process of the device is as follows: hardware integrity check, hardware boot, software decryption, software code integrity check, and system loading.

[0013] Furthermore, the AES-256 algorithm is used to encrypt the software and I / O channels, and the RSA-4096 algorithm is used to authenticate the software.

[0014] Furthermore, the hardware integrity check and hardware startup process is as follows: After the device is powered on, the PMU is responsible for detecting and waking up the system's required hardware. The PMU performs a PMU ROM pre-boot after a POR reset. The pre-boot operation is as follows: First, the PS SYSMON unit and PLL required for startup are initialized. Then, the PMU RAM and CSU RAM are reset. After the temporary storage unit is reset, the PLL lock is verified. If there is no PLL lock, the next step is to use the PS SYSMON unit to verify the LPD, AUX, and I / O supply range while clearing the low-power domain and the full-power domain. If no errors occur in all previous startup steps, the PMU releases the CSU reset, and the hardware integrity check and wake-up are completed. After that, the PMU enters service mode. If an error occurs during the hardware startup process, the device generates and marks a boot error, and the hardware startup fails.

[0015] Furthermore, after hardware integrity testing and wake-up, the software undergoes decryption, integrity testing, and system loading. Specifically, the software is decrypted using an eFuse pre-written with keys for decrypting the software code and for software authentication, configured on the FPGA device. If the device can decrypt the software and pass authentication, the system components and application design can start and be used normally on the device. If decryption fails or authentication fails, the device cannot start normally. The parts in the system that require encryption and authentication include FSBL, PMU Firmware, ARM TrustedFirmware, FPGABit File, U-boot, LinuxKernel, and User Data, which are loaded in the above order during the device's software startup process.

[0016] Furthermore, the software encryption and authentication process specifically involves: firstly generating the keys required for software encryption and authentication during secure boot and verifying the availability of the keys; then, after authenticating and encrypting components such as FSBL, PMU Firmware, ARM TrustedFirmware, FPGABit File, and U-boot, using a packaging tool to generate Boot.bin; and packaging Linux components such as Linux Kernel and User Data using a tool to generate image.ub. Finally, using a tool, Boot.bin and Image.ub are authenticated and encrypted as a whole, generating image.ub.bin; the generated image.ub.bin file is used for secure boot verification.

[0017] Furthermore, after the FPGA device undergoes secure boot, it generates encryption keys for I / O communication. Corresponding private and public keys are pre-distributed to the host and security boundary controller. When the host and security boundary controller exchange data and control flows, they first encrypt the transmitted data using the public key. After encryption, the encrypted data is transmitted to achieve control and data protection. Once the encrypted data reaches the destination, the destination decrypts it using the distributed private key and performs the corresponding operations. The system uses the security boundary controller to map and translate addresses across different memory spaces, thus forming a trusted I / O channel.

[0018] Furthermore, the aforementioned strong physical isolation of the security boundary specifically involves: establishing a physical isolation mechanism centered on PCIe; the security boundary controller utilizes the communication physical isolation mechanism of PCIe and the strong physical isolation characteristics of the FPGA device during operation; simultaneously, it sets up physical intrusion detection during FPGA device operation; it is configured to detect activity on the PS JTAG interface pins after the device starts up and activate the detection alarm; if the device detects the alarm information during operation, the device enters a locked state, and the application stops running to ensure data security.

[0019] Furthermore, the inter-application memory isolation is specifically as follows: based on the unified task description of the application, a single application is used as the basic isolation unit for execution. Before the system application runs, the available memory size and address space are pre-allocated for each application. Each application can only use the pre-accessed memory address space. When an application accesses memory, it first sends a request to the memory boundary checker, which includes the destination address of the application's memory access. The memory boundary checker performs an access compliance check based on the pre-allocated memory address space that the application can use. If the application's access address conforms to the pre-allocated address, the memory boundary checker performs the corresponding operation on the target address and returns the value in the corresponding address space to the application. If the application requests an access address that exceeds the predetermined range, the memory boundary checker returns an error message, thereby controlling the application's memory access permissions and achieving isolated execution between different applications.

[0020] Furthermore, the inter-process memory sharing specifically involves: for memory sharing behavior between different components of an application, the available memory address space of each application component is further divided within the memory address space allocated by the application; when dividing the available memory address space of the application component, a certain memory area is reserved as shared memory within the application, thereby enabling the interaction of memory data between processes running in isolation, reducing the memory sharing overhead between isolated processes, and improving the efficiency of data interaction between processes.

[0021] Compared with the prior art, the beneficial effects of this invention are as follows:

[0022] 1. This invention provides a method for extending the boundary of a trusted execution environment (TEE) for FPGAs, achieving a design that separates control and computation, thereby establishing a flexible and efficient heterogeneous trusted execution environment and solving the problem of separation between the processor trusted execution environment (CPU-TEE) and heterogeneous computing devices (FPGA devices). This method can build an isolated application execution environment on FPGA devices, providing hardware-level security for applications running on FPGA devices and improving data security capabilities during heterogeneous computing runtime.

[0023] 2. This invention provides a method for extending the boundaries of a trusted execution environment (TEE) for FPGAs, achieving separation of security control and computation, and establishing a flexible and efficient heterogeneous TEE, thus solving the problem of the disconnect between the processor's TEE and FPGA devices. Constructing a TEE for FPGA-based heterogeneous computing devices is of great significance for improving the security of heterogeneous computing and realizing its computational potential for security-sensitive applications. The TEE boundary extension scheme for FPGAs can incorporate heterogeneous devices into the heterogeneous TEE without modifying the chip hardware architecture, exhibiting good scalability. This characteristic allows for convenient large-scale deployment and application of existing widely used heterogeneous computing devices. Attached Figure Description

[0024] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0025] Figure 1 This is a schematic diagram illustrating the hierarchical isolation principle of the present invention;

[0026] Figure 2 This is a schematic diagram illustrating memory isolation between applications of the present invention. Detailed Implementation

[0027] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] This invention discloses a trusted execution environment boundary extension method for FPGAs, comprising three parts: a system control path and data path construction scheme, a hierarchical isolation and sharing scheme for computing and storage resources, and a flexible extension scheme incorporating application features. Specifically:

[0029] 1. System control path and data path construction scheme

[0030] For current control and data flow transmission from the host to the FPGA device, a system control path and data path construction scheme is proposed, which consists of system secure startup, device authentication and trusted I / O channel construction.

[0031] The system first ensures the secure startup and execution of the security boundary controller through secure boot and cryptographic verification. Then, it completes the identity authentication between the host and the security boundary controller, performs key sharing, and finally uses the encryption key to encrypt the control flow and data flow from the host. It then communicates directly through the task queue of the security boundary controller to build an encrypted I / O channel from the host to the FPGA device, thereby achieving data protection of the I / O channel.

[0032] 1.1 Device secure startup and authentication

[0033] The solution design implements a secure boot process using a "root of trust." The "root of trust" means that trust must begin at the root; to ensure the security and reliability of any boot step, all preceding steps must also be secure and reliable. The device's secure boot process includes: hardware integrity check, hardware boot, software decryption, software code integrity check, and system loading.

[0034] Hardware Integrity Detection and Hardware Boot: After the device is powered on, the Platform Management Unit (PMU) is responsible for detecting and waking up the system's required hardware. The PMU performs a pre-boot of the PMU ROM after a POR reset. The pre-boot operations include: first, initializing the PS SYSMON unit and PLL required for boot; then resetting the PMU RAM and CSU RAM; verifying the PLL lock after resetting the temporary storage unit; if no PLL lock is found, the next step uses the PS SYSMON unit to verify the LPD, AUX, and I / O supply ranges while clearing the low-power and full-power domains. If no errors occur during the previous boot steps, the PMU releases the CSU and resets, completing the hardware integrity detection and wake-up process. The PMU then enters service mode. If an error occurs during hardware boot, the device generates and marks a boot error, indicating a hardware boot failure.

[0035] After hardware integrity checks and wake-up, the software decryption, completion checks, and loading begin. To ensure the confidentiality and integrity of the software system, AES-256 encryption is used for the software, and RSA-4096 authentication is used to prevent malicious modification of the software code. The software decryption and authentication processes utilize hardware acceleration modules, thus minimizing the overall startup time overhead. The device's key storage and the eFuse (Electronic Fuse) configured on the device are fusible devices, belonging to one-time programmable memory. Before device use, the AES key for decrypting the software code and the RSA key for software authentication are written into the device's eFuse. The components requiring protection in a system include FSBL, PMU Firmware, ARMTrustedFirmware, FPGABit File, U-boot, Linux Kernel, and User Data, which are loaded in the above order during the device's software startup process.

[0036] Each system software component can be configured to perform either authentication and encryption simultaneously, authentication only, encryption only, or neither. Encryption and authentication are two independent operations. Encryption ensures the software is not cracked, while authentication ensures its integrity and tamper-proof nature, preventing the insertion of malicious code and security risks. To ensure high system security, encryption and authentication are performed on each component. Since MPSoC has a hardware-accelerated RSA authentication module, authentication has a relatively low impact on startup time, and the overhead of decryption and authentication processes on system startup time can be ignored.

[0037] When using secure boot, the necessary keys are first generated: RSA Private Key and Public Key AES Key. Key availability is verified, the software code is encrypted using the AES key, and the software components are authenticated using the RSA key. After authenticating and encrypting the FSBL, PMU Firmware, ARM TrustedFirmware, FPGABit File, and U-boot, a packaging tool is used to generate Boot.bin. The Linux Kernel and User Data components are packaged using a tool to generate image.ub. Then, a tool is used to authenticate and encrypt both Boot.bin and Image.ub, generating image.ub.bin. For system convenience, SD card booting is used, and the generated image.ub.bin file is saved to the SD card for booting. Next, the device key is written. The FPGA device is booted from JTAG mode, and a Standalone program is run to write the RSAPPK Hash and AES Key (red or black) into the eFuse of the FPGA chip, and the device boot verification function is initiated. After writing the key to the eFuse included in the device, start the device to enable the verification function. Insert the SD card containing the corresponding boot image into the device and set the device to boot from the SD card. If the device can decrypt the image and pass the authentication verification, the system components and applications contained in the image can start and be used normally in the device. If the image decryption fails or the authentication fails, it means that the software has been tampered with, and the device cannot start normally.

[0038] During the secure boot process, the device authenticates the software system by reading and parsing the pre-distributed RSA PrivateKey embedded in the software image.

[0039] 1.2 Construction of Trusted I / O Channels

[0040] After the FPGA device undergoes secure boot, an AES key for I / O communication is generated. Corresponding private and public keys are pre-distributed to the host and security boundary controller. When the host and security boundary controller exchange data and control flows, they first encrypt the transmitted data using the AES public key. After encryption, the encrypted data is transmitted, achieving control and data protection. Upon arrival at the destination, the destination decrypts the encrypted data using the distributed private key and performs corresponding operations such as addressing and data transmission. The system uses the security boundary controller to map and translate addresses across different memory spaces, thus forming a trusted I / O channel.

[0041] 2. Hierarchical Isolation and Sharing Scheme for Computing and Storage Resources

[0042] To address the computational patterns and security requirements of heterogeneous trusted computing tasks, a hierarchical isolation and sharing strategy for computing and storage resources is proposed, consisting of strong physical isolation at security boundaries, memory isolation between applications, and memory isolation and sharing between processes.

[0043] like Figure 1 , Figure 2 As shown, regarding the boundary between the secure and insecure worlds, the inaccessibility of FPGA runtime to the outside world ensures strong physical isolation of the secure boundary of the trusted execution environment. For different applications running on the FPGA chip, application memory boundary checks establish application-based memory isolation, ensuring the inaccessibility of memory data between applications and achieving data isolation between different applications within the trusted execution environment, thus guaranteeing application data security. For complex applications requiring frequent data interaction, process-level memory space isolation is provided, and an inter-process memory isolation mechanism is designed to achieve data isolation and minimize the overhead of data interaction between processes. Through the nested combination of multi-level memory isolation mechanisms, an efficient memory sharing mode is established while ensuring data isolation between applications, guaranteeing data security.

[0044] 2.1 Strong physical isolation at security boundaries

[0045] A PCIe-centric physical isolation mechanism is established. The security boundary controller leverages the communication isolation mechanism of PCIe and the strong physical isolation characteristics of the FPGA device during operation. Simultaneously, physical intrusion detection is configured for the FPGA device during operation. This involves detecting activity on the PS / JTAG interface pins after the device starts up, triggering an alarm, and if the device detects an alarm during operation, it enters a locked state, and the application stops running to ensure data security. The system utilizes the PCIe physical isolation mechanism combined with the strong physical isolation characteristics and physical intrusion detection capabilities of the FPGA device to achieve strong isolation between the secure and insecure worlds.

[0046] 2.2 Memory isolation between applications

[0047] Based on the unified task description of the application, and taking a single application as the basic isolation unit for execution, before the system application runs, the available memory size and address space are pre-allocated for each application. Each application can only use the pre-accessed memory address space. When an application accesses memory, it first sends a request to the memory boundary checker, which includes the destination address of the memory access. The memory boundary checker performs access compliance checks based on the pre-allocated memory address space that the application can use. If the application access address conforms to the pre-allocated address, the memory boundary checker performs the corresponding operation on the target address and returns the value in the corresponding address space to the application. If the application requests an access address that exceeds the predetermined range, the memory boundary checker returns an error message, thereby controlling the application's memory access permissions and achieving isolated execution between different applications.

[0048] 2.3 Inter-process memory sharing

[0049] To address memory sharing between different application components, the available memory address space is further partitioned within the application's allocated memory address space, taking each application component (process) as a unit. When partitioning the available memory address space of application components, a certain memory region is reserved as shared memory within the application. This enables memory data exchange between isolated processes within the application, reducing the overhead of memory sharing between isolated processes and improving the efficiency of data exchange between processes. Flexible memory isolation and interaction modes are provided by nesting strong memory data isolation between applications and soft memory data isolation between processes.

[0050] 3. Flexible expansion solutions incorporating application features

[0051] Based on statistical analysis and investigation of the operational characteristics of commonly used applications, a set of flexible expansion schemes incorporating application characteristics is proposed, consisting of research and investigation on application computing and memory access behavior, encapsulation of hardware resources and computing modes, and construction of a high-frequency operator library.

[0052] The heterogeneous computing trusted execution environment is designed with a security model that separates control and computation, allowing heterogeneous computing devices to maintain their original computing patterns. First, the computation and memory access behavior characteristics of different types of applications are studied and investigated. Second, different granularities of hardware resource and computation mode descriptions and abstractions are provided for applications with different characteristics, and different fine-grained resource description interfaces are designed. For computation behaviors with high computation time overhead and high resource consumption, hardware resources are abstracted, organized, encapsulated, and corresponding operators are constructed. Third, based on the different basic applications required by the usage scenarios, an application-based operator library is established, adapting to different basic applications and providing flexible and efficient modular application interfaces.

[0053] 3.1 Research and Survey on Application Computing and Memory Access Behavior

[0054] Application computing behavior research and investigation: First, it's necessary to collect data on application runtime, such as CPU utilization, memory usage, and I / O operation frequency. Analyzing this data reveals the application's operational characteristics. Based on the collected operational characteristics, applications can be categorized into different types, such as memory-intensive and compute-intensive. Then, through detailed performance analysis, the causes of performance bottlenecks in application operation are identified, such as insufficient memory allocation or unreasonable CPU time slicing.

[0055] Application Memory Access Behavior Research and Investigation: This involves detailed observation and research of the application's memory access behavior during runtime. Collected data includes the frequency and type of memory access, as well as data locality characteristics. Analysis of this data identifies hotspots in application memory access, reveals data access patterns, and assesses data locality. Further optimization of memory management strategies and cache utilization efficiency is then implemented, such as adjusting prefetching strategies, optimizing page scheduling algorithms, and improving cache replacement strategies, to specifically enhance memory usage efficiency and application performance.

[0056] 3.2 Hardware Resources and Computing Mode Encapsulation

[0057] For different computing device hardware resources, and in conjunction with the designed computing and storage resource isolation mechanism, a structured resource description method is designed: the computing power resources and storage resources of the device are divided into fine-grained parts, and hardware resources of different granularities are provided according to the application's operation and security requirements, such as memory blocks of different sizes, plaintext and ciphertext storage areas, and the computing resources that can be utilized, so as to provide a flexible resource requirement interface for application deployment and operation.

[0058] 3.3 Adaptation Feature Operators and Construction of Basic Operator Library

[0059] For heterogeneous computing applications that are used frequently on devices, we analyze their computation and memory access behavior, abstract, summarize and encapsulate the device hardware resources and computing modes, construct relevant operators, and establish a modular high-performance basic application operator library, such as encryption and decryption operators for trusted applications.

Claims

1. A method for extending the trusted execution environment boundary for FPGAs, characterized in that, include: For the control and data flow transmission from the host to the FPGA device, a system control path and data path are constructed, including secure system startup and authentication, and the construction of a trusted I / O channel. Specifically, the system first ensures the secure startup and execution of the security boundary controller and system components through secure startup, while completing the device system authentication and sharing the I / O channel key. Finally, the control and data flows from the host are encrypted using an encryption key, and direct communication is achieved through the task queue of the security boundary controller, thus constructing an encrypted I / O channel from the host to the FPGA device, thereby realizing data protection of the I / O channel. To address the computational patterns and security requirements of heterogeneous trusted computing tasks, a hierarchical isolation and sharing strategy for computing and storage resources is implemented, including strong physical isolation at security boundaries, memory isolation between applications, and memory isolation and sharing between processes. Specifically: for the boundary between the secure and insecure worlds, the inaccessibility of the FPGA runtime environment to the outside world is utilized to ensure strong physical isolation at the security boundaries of the trusted execution environment; for different applications running on the FPGA chip, memory isolation is established on an application-by-application basis through application memory boundary checks to ensure that memory data between applications cannot be accessed autonomously, and to achieve data isolation between different applications in the trusted execution environment, thereby ensuring application data security. For complex applications that require frequent data interaction, we provide process-level memory space isolation and design an inter-process memory isolation mechanism to achieve data isolation and minimize the overhead of data interaction between processes. By nesting and combining multi-level memory isolation mechanisms, an efficient memory sharing mode is established while ensuring data isolation between applications and guaranteeing data security. We conducted statistical analysis and investigations on the operational characteristics of commonly used applications, and adopted a flexible expansion scheme that incorporates application characteristics. This includes research and investigation on application computing and memory access behavior, encapsulation of hardware resources and computing modes, and construction of a high-frequency operator library. Specifically, we first conducted research and investigations on the computing and memory access behavior characteristics of different types of applications; secondly, we provided descriptions and abstractions of hardware resources and computing modes at different granularities for applications with different characteristics, designed resource description interfaces of different fine granularities, and abstracted, organized, encapsulated, and constructed corresponding operators for computing behaviors with high computing time overhead and high resource consumption. Furthermore, based on the different basic applications required by the usage scenarios, an application basic operator library is established to adapt to different basic applications and provide flexible and efficient modular application interfaces.

2. The trusted execution environment boundary extension method for FPGA according to claim 1, characterized in that, Secure boot is achieved through a "root of trust". The secure boot process of the device is as follows: hardware integrity check, hardware boot, software decryption, software code integrity check and system loading.

3. The trusted execution environment boundary extension method for FPGA according to claim 2, characterized in that, The software and I / O channels are encrypted using the AES-256 algorithm, and the software is authenticated using the RSA-4096 algorithm.

4. The trusted execution environment boundary extension method for FPGA according to claim 2, characterized in that, The hardware integrity check and hardware startup process is as follows: After the device is powered on, the PMU is responsible for detecting and waking up the system's required hardware. The PMU performs a PMU ROM pre-boot after a POR reset. The pre-boot operation is as follows: First, the PS SYSMON unit and PLL required for startup are initialized. Then, the PMU RAM and CSU RAM are reset. After the temporary storage unit is reset, the PLL lock is verified. If there is no PLL lock, the next step is to use the PS SYSMON unit to verify the LPD, AUX, and I / O supply range while clearing the low-power domain and full-power domain. If no errors occur in all previous startup steps, the PMU releases the CSU reset, and the hardware integrity check and wake-up are completed. After that, the PMU enters service mode. If an error occurs during the hardware startup process, the device generates and marks a booterror, and the hardware startup fails.

5. The trusted execution environment boundary extension method for FPGA according to claim 3, characterized in that, After hardware integrity detection and wake-up, the software is decrypted, integrity is checked, and the system is loaded. Specifically, the software is decrypted by using an eFuse configured on the FPGA device, which is pre-written with keys for decrypting the software code and keys for software authentication. If the device can decrypt the software and pass authentication, the system components and application design can start and be used normally in the device. If decryption fails or authentication fails, the device will not be able to start normally; The components requiring encryption and authentication in the system include FSBL, PMU Firmware, ARM Trusted Firmware, FPGA Bit File, U-boot, Linux Kernel, and UserData, which are loaded in the above order during the device's software startup process.

6. The trusted execution environment boundary extension method for FPGA according to claim 5, characterized in that, The software encryption and authentication process is as follows: When using secure boot, firstly, the keys required for software encryption and authentication are generated and their availability is verified; after authenticating and encrypting components such as FSBL, PMU Firmware, ARM Trusted Firmware, FPGA Bit File, and U-boot, a packaging tool is used to generate Boot.bin; Linux components such as Linux Kernel and User Data are packaged using a tool to generate image.ub; then, a tool is used to perform overall authentication and encryption on Boot.bin and Image.ub to generate image.ub.bin; the generated image.ub.bin file is used for secure boot verification.

7. The trusted execution environment boundary extension method for FPGA according to claim 1, characterized in that, After the FPGA device is securely booted, an encryption key for I / O communication is generated. The corresponding private and public keys are pre-distributed to the host and security boundary controller. When the host and security boundary controller exchange data and control flows, they first encrypt the transmitted data using the public key. After encryption, the encrypted data is transmitted to achieve the purpose of control and data protection. After the encrypted data arrives at the destination, the destination decrypts the encrypted data using the distributed private key and performs the corresponding operations. The system achieves address routing and translation across different memory spaces through security boundary controller mapping, thereby forming a trusted I / O channel.

8. The trusted execution environment boundary extension method for FPGA according to claim 1, characterized in that, The specific physical strong isolation of the security boundary is as follows: a physical isolation mechanism centered on PCIe is established. The security boundary controller uses the communication physical isolation mechanism of PCIe and the strong physical isolation characteristics of the FPGA device during operation. At the same time, physical intrusion detection is set during the operation of the FPGA device. After the device starts running, it is set to detect the activity on the PS JTAG interface pin and enable the detection alarm. If the device detects the alarm information during operation, the device enters a locked state and the application stops running to ensure data security.

9. The trusted execution environment boundary extension method for FPGA according to claim 1, characterized in that, The inter-application memory isolation is specifically as follows: Based on the unified task description of the application, a single application is used as the basic isolation unit for execution. Before the system application runs, the available memory size and address space are pre-allocated for each application. Each application can only use the pre-accessed memory address space. When an application accesses memory, it first sends a request to the memory boundary checker, which includes the destination address of the memory access. The memory boundary checker performs an access compliance check based on the pre-allocated memory address space that the application can use. If the application access address conforms to the pre-allocated address, the memory boundary checker performs the corresponding operation on the target address and returns the value in the corresponding address space to the application. If the application requests an access address that exceeds the predetermined range, the memory boundary checker returns an error message, thereby controlling the memory access permissions of the application and realizing isolated execution between different applications.

10. The trusted execution environment boundary extension method for FPGA according to claim 1, characterized in that, The inter-process memory isolation and sharing specifically refers to: for memory sharing behavior between different components of an application, the available memory address space of an application component is divided into two parts within the memory address space allocated by the application; when dividing the available memory address space of an application component, a certain memory area is reserved as shared memory within the application, thereby enabling the interaction of memory data between processes running in isolation, reducing the memory sharing overhead between isolated processes, and improving the efficiency of data interaction between processes.

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