基于单片三维集成的Transformer加速器架构
By employing a monolithic 3D integrated architecture in the Transformer accelerator, stacking silicon-based logic circuits, RRAM-CIM arrays, and CFET 2TOC-CIM arrays, and utilizing high-density interlayer dielectric vias for inter-module communication, the problem of data transport limitations is solved, enabling more efficient Transformer computation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TSINGHUA UNIVERSITY
- Filing Date
- 2024-05-14
- Publication Date
- 2026-07-17
AI Technical Summary
In the existing Transformer accelerator architecture, data transfer between fully static and semi-static weight modules limits system performance, making it difficult to completely overcome the von Neumann bottleneck and the slowdown of Moore's Law.
Employing a monolithically integrated Transformer accelerator architecture, this system utilizes a stack of silicon-based logic circuits, RRAM-CIM arrays, and CFET 2TOC-CIM arrays. High-density interlayer dielectric vias are used for inter-module communication, leveraging the advantages of different in-memory computing methods to achieve linear transformations and matrix multiplication operations.
It greatly reduces the amount of data transfer, overcomes the von Neumann bottleneck, continues Moore's Law, and achieves better Transformer acceleration.
Smart Images
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