Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises a plurality of pixel circuits and a plurality of light emitting devices; the pixel circuit comprises a driving transistor, a first light emitting control module and a second light emitting control module; one of the first light emitting control module and the second light emitting control module is connected between a first power supply end and a first electrode of the driving transistor, and the other is connected between a second electrode of the driving transistor and the light emitting device; at least one of the first light emitting control module and the second light emitting control module in the first pixel circuit is connected with the driving transistor through a cross-bridge line, and at least one of the first light emitting control module and the second light emitting control module in the second pixel circuit is directly connected with the driving transistor. The present application can reasonably arrange the positions of the two light emitting control modules in the pixel circuit, can realize the differentiated setting of the light emitting control modules in the two pixel circuits to receive the control signal, and can meet the line connection requirements in the pixel circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Micro LEDs (Micro light-emitting diodes) and Mini LEDs (Mini light-emitting diodes) are characterized by high luminous efficiency, high brightness, wide color gamut, and low power consumption, and are poised to become one of the mainstream technologies for future display products. Achieving color display requires red, green, and blue LED devices. Since different color devices have different luminous efficiencies, the pixel circuit structure used to drive the LEDs has a crucial impact on the display effect. Summary of the Invention

[0003] This invention provides a display panel and a display device to solve the technical problem of how to configure pixel circuits to improve display performance.

[0004] In a first aspect, embodiments of the present invention provide a display panel, comprising: a plurality of pixel circuits and a plurality of light-emitting devices; the pixel circuits include a driving transistor, a first light-emitting control module and a second light-emitting control module; wherein, in the first light-emitting control module and the second light-emitting control module, one is connected between a first power supply terminal and a first electrode of the driving transistor, and the other is connected between a second electrode of the driving transistor and a light-emitting device;

[0005] The pixel circuit includes a first pixel circuit and a second pixel circuit, and the display panel includes a bridge line;

[0006] In the first pixel circuit, at least one of the first light-emitting control module and the second light-emitting control module is connected to the driving transistor via a bridge line, and in the second pixel circuit, at least one of the first light-emitting control module and the second light-emitting control module is directly connected to the driving transistor.

[0007] Secondly, based on the same inventive concept, embodiments of the present invention provide a display device, including a display panel provided in any embodiment of the present invention.

[0008] The display panel and display device provided in this invention have the following beneficial effects: This invention differentiates the connection methods between the two light-emitting control modules and the driving transistors in the first and second pixel circuits, and rationally arranges the positions of the two light-emitting control modules in the pixel circuits. This enables differentiated settings for the light-emitting control modules receiving control signals in the two pixel circuits, while meeting the line connection requirements in the pixel circuits. It facilitates driving the first and second pixel circuits with different control methods, allowing for differentiated conduction durations of the light-emitting circuits in the first and second pixel circuits. This results in different durations of driving current provided to the light-emitting devices by different pixel circuits during the light-emitting phase, thus causing different light-emitting durations for the light-emitting devices driven by different pixel circuits. This compensates for differences in the luminous efficiency of the light-emitting devices and improves the display effect. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0011] Figure 2 A pixel circuit layout provided for an embodiment of the present invention;

[0012] Figure 3 for Figure 1 A timing diagram of a pixel circuit;

[0013] Figure 4 for Figure 2 A schematic diagram of the membrane layer disassembly;

[0014] Figure 5 A schematic diagram of a display panel provided in an embodiment of the present invention;

[0015] Figure 6 Another pixel circuit schematic diagram provided in an embodiment of the present invention;

[0016] Figure 7 A signal timing diagram provided in an embodiment of the present invention;

[0017] Figure 8 for Figure 5 A schematic diagram of a cross-section at the position of the tangent AA′;

[0018] Figure 9This is a schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0019] Figure 10A This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0020] Figure 10B This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0021] Figure 11 for Figure 5 Enlarged view of the central region at position Q1;

[0022] Figure 12 for Figure 5 Enlarged view of the Q2 position in the central region;

[0023] Figure 13 for Figure 12 A schematic diagram of a cross-section at the location of the tangent line BB′;

[0024] Figure 14 for Figure 11 A schematic diagram showing the semiconductor layer and the first metal layer retained in the middle;

[0025] Figure 15 for Figure 10A A schematic diagram showing the semiconductor layer and the first metal layer retained in the middle;

[0026] Figure 16 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0027] Figure 17 for Figure 16 A schematic diagram of a cross-section at the position of the tangent CC′;

[0028] Figure 18 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0029] Figure 19 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0030] Figure 20 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0031] Figure 21 Another pixel circuit schematic diagram provided in an embodiment of the present invention;

[0032] Figure 22 Another signal timing diagram provided in an embodiment of the present invention;

[0033] Figure 23 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0034] Figure 24 Another pixel circuit schematic diagram provided in an embodiment of the present invention;

[0035] Figure 25 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0036] Figure 26 A simplified schematic diagram of another display panel provided in an embodiment of the present invention;

[0037] Figure 27 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0038] Figure 28 Another pixel circuit schematic diagram provided in an embodiment of the present invention;

[0039] Figure 29 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0040] Figure 30 Another pixel circuit schematic diagram provided in an embodiment of the present invention;

[0041] Figure 31 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0044] Different colored LEDs require different luminescent materials, resulting in variations in luminous efficiency. The luminescent materials used in LEDs are significantly affected by temperature, leading to differences in luminous efficiency at different temperatures. Furthermore, the luminous efficiency of different colored LEDs is affected differently by temperature, causing color shifts in the display. For example, tests have shown that compared to a 25°C operating environment, the luminous efficiency of red, green, and blue LEDs decreases to varying degrees when operating at high temperatures (such as 85°C), resulting in color shifts and reduced brightness on the display panel.

[0045] To address the problems existing in related technologies, embodiments of the present invention provide a display panel that differentiates the layout of different pixel circuits, enabling different pixel circuits to be driven by different control methods. This allows the light-emitting devices coupled to different pixel circuits to have different light-emitting durations, thereby compensating for the differences in luminous efficiency of different light-emitting devices and improving the display effect of the display panel.

[0046] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 2 This is a pixel circuit layout provided as an embodiment of the present invention. For example... Figure 1 and Figure 2 As shown, the pixel circuit includes a driving transistor Tm, a first light-emitting control module 10, a second light-emitting control module 20, a gate reset module 30, an electrode reset module 40, a data writing module 50, and a storage capacitor Cst. The first electrode of the driving transistor Tm is coupled to the first power supply terminal Pvdd through the first light-emitting control module 10. The second electrode of the driving transistor Tm is coupled to one electrode of the light-emitting device LD through the second light-emitting control module 20. The other electrode of the light-emitting device LD is coupled to the second power supply terminal Pvee. One plate of the storage capacitor Cst is coupled to the first power supply terminal Pvdd, and the other plate is coupled to the gate of the driving transistor Tm. Figure 1 It can be seen that the gate reset module 30 is controlled by the first scan signal S1, the data writing module 50 and the electrode reset module 40 are controlled by the second scan signal S2, and the first light-emitting control module 10 and the second light-emitting control module 20 are controlled by the light-emitting control signal Emit. The light-emitting device LD is an LED device, such as Micro LED or Mini LED. In some embodiments, the light-emitting device LD can also be an organic light-emitting diode (OLED). Figure 2 As can be seen, the first light-emitting control module 10 is directly connected to the first electrode of the driving transistor Tm, and the second light-emitting control module 20 is directly connected to the second electrode of the driving transistor Tm.

[0047] Figure 3 for Figure 1 A timing diagram of a pixel circuit, such as Figure 3 As shown, the pixel circuit's operating cycle includes a gate reset phase t1, a data writing phase t2, and a light emission phase t3. In the gate reset phase t1, the gate reset module 30 is activated and writes the reset signal Ref (using the same label as its signal terminal) provided by the reset signal terminal Ref into the gate of the driving transistor Tm to reset the gate of the driving transistor Tm. In the data writing phase t2, the data writing module 50 is activated and writes the data voltage Data to the gate of the driving transistor Tm. Simultaneously, the electrode reset module 40 is activated and uses the reset signal Ref to reset the electrodes of the light-emitting device LD. In the light emission phase t3, the first light emission control module 10 and the second light emission control module 20 are activated. The driving transistor Tm is turned on under the control of its gate voltage, and the pixel circuit provides a driving current to the light-emitting device LD, causing the light-emitting device LD to emit light under the control of the driving current.

[0048] Optional, such as Figure 1 As shown, the data writing module 50 includes a data writing transistor T1 and a compensation transistor T2, the gate reset module 30 includes a gate reset transistor T3, the electrode reset module 40 includes an electrode reset transistor T4, the first light emission control module 10 includes a first light emission control transistor T5, and the second light emission control module 20 includes a second light emission control transistor T6. In some embodiments, the electrode reset transistor may not be provided in the pixel circuit.

[0049] Figure 1 The illustration assumes that all transistors in the pixel circuit are p-type transistors. In other embodiments, all transistors are n-type transistors. In other embodiments, at least one of the gate reset transistor T3 and the compensation transistor T2 is an n-type transistor, and the remaining transistors are p-type transistors. For example, the active layer of at least one of the gate reset transistor T3 and the compensation transistor T2 comprises metal oxide, while the active layer of the remaining transistors comprises silicon. When the compensation transistor T2 is an n-type transistor and the data write transistor T1 is a p-type transistor, it is understood that they need to be controlled by different signals. In the accompanying drawings of the following embodiments, the illustration only shows that the transistors in the pixel circuit are p-type transistors.

[0050] Figure 4 for Figure 2 A schematic diagram of the membrane layer disassembly. (Combined with...) Figure 1 The schematic circuit diagram illustrates the various structures in the pixel circuit and the film layers in which each structure resides. For example... Figure 2 and Figure 4As shown, the display panel includes a first scan line S1, a second scan line S2, an emission control line Emit, and a reset signal line Ref. The first scan line S1 provides the first scan signal S1, the second scan line S2 provides the second scan signal S2, and the emission control line Emit provides the emission control signal Emit. The reset signal line Ref serves as the reset signal terminal Ref, providing a reset signal.

[0051] In this embodiment of the invention, the signal lines and the signals they provide are represented by the same markings. For example, the first scan line and the first scan signal it provides are both marked with S1. The first power supply terminal and the first power supply voltage it provides are both marked with Pvdd. The markings for other signal lines, signal terminals, etc., are understood with reference to this description.

[0052] Combination Figure 4 The display panel comprises at least a semiconductor layer 000, a first metal layer 001, a second metal layer 002, a third metal layer 003, and a fourth metal layer 004, all located on a substrate. These layers are sequentially disposed away from the substrate. The active layer of each transistor is located on the semiconductor layer 000. Figure 4 The location of the active layer of each transistor is marked in semiconductor layer 000. Figure 4 As can be seen from the shape of the active layer at the location of the driving transistor Tm, the active layer at the location of the driving transistor Tm has a cutout LK. This allows the semiconductor layers on both sides of the cutout LK to serve as the active layers of the transistors, making the driving transistor Tm a parallel structure of two transistors in this embodiment. Because the output characteristic curve (Id-Vd) of the transistor exhibits a kink phenomenon, i.e., the output characteristic curve bends upwards, this phenomenon occurs when the leakage voltage exceeds a certain value. When the channel width of the driving transistor is too long, the kink phenomenon leads to a deterioration in display brightness uniformity. Compared with the solution of fabricating a single transistor in this area as the driving transistor, the parallel transistor design in this embodiment ensures that the channel width of a single transistor is not too large, avoids the kink phenomenon affecting brightness uniformity, and the driving transistor Tm composed of parallel transistors can have a larger aspect ratio, increasing the driving current.

[0053] The first scan line S1, the second scan line S2, and the light emission control line Emit are located in the first metal layer 001, and the gate of each transistor is located in the first metal layer 001. Figure 4The diagram illustrates the gate Tmg of the driving transistor Tm, which is multiplexed as one plate C1 of the storage capacitor Cst. The other plate C2 of the storage capacitor Cst is located on the second metal layer 002, and the reset signal line Ref is also located on the second metal layer 002. Several connection lines are arranged on the third metal layer 003. For example, the first connection line X1 connects the gate reset transistor T3 to the gate Tmg of the driving transistor Tm. The first connection line X1 has a large area, designed to increase the capacitance value of the storage capacitor. The second connection line X2 connects the gate reset transistor T3 to the reset signal line Ref; the third connection line X3 connects to the second light-emitting control transistor T6; and the fourth connection line X4 connects to the first light-emitting control transistor T5. The third connection line X3 is electrically connected to the connecting electrode X5 through a via O1 (a via refers to a hole penetrating the insulating layer). The connecting electrode X5 is connected to the light-emitting device LD, and the third connection line X3 is used to couple the second light-emitting control transistor T6 to the light-emitting device LD. The fourth connection line X4 is connected to the first power supply terminal Pvdd through a via O2. The first power supply terminal Pvdd and the connecting electrode X5 are located in the fourth metal layer 004.

[0054] Depend on Figure 1 and Figure 2 As can be seen, the pixel circuit provided in this embodiment of the invention includes two light-emitting control modules. One of these modules is connected between the first power supply terminal Pvdd and the first electrode of the driving transistor Tm, while the other is connected between the second electrode of the driving transistor Tm and the light-emitting device LD. The different names for the two light-emitting control modules are only for illustrative and understanding purposes of the pixel circuit structure. In fact, the names of the first light-emitting control module 10 and the second light-emitting control module 20 can be interchanged. That is, the first light-emitting control module 10 is connected between the second electrode of the driving transistor Tm and the light-emitting device LD, while the second light-emitting control module 20 is connected between the first power supply terminal Pvdd and the first electrode of the driving transistor Tm.

[0055] Figure 2 This illustrates a layout structure for a pixel circuit. Figure 2 In this embodiment, the first light-emitting control module 10 and the second light-emitting control module 20 are located on the same side of the driving transistor Tm. The first light-emitting control module 10 is directly connected to the first electrode of the driving transistor Tm, and the second light-emitting control module 20 is directly connected to the second electrode of the driving transistor Tm. Figure 3As shown in the schematic timing diagram, in the light-emitting stage t3, when both the first light-emitting control module 10 and the second light-emitting control module 20 are turned on, the light-emitting circuit formed by the first light-emitting control module 10, the driving transistor Tm, and the second light-emitting control module 20 is turned on, enabling the pixel circuit to provide driving current to the light-emitting device LD. In other words, the switching state of the first light-emitting control module 10 and / or the second light-emitting control module 20 affects the duration of providing driving current. Therefore, this embodiment of the invention considers different designs for the connection methods of the first light-emitting control module 10 and / or the second light-emitting control module 20 and the driving transistor Tm in different pixel circuits, so that the conduction duration of the light-emitting circuit in different pixel circuits is different, thereby making the duration of providing driving current different for different pixel circuits.

[0056] In a further embodiment of the present invention, the connection methods between the first light-emitting control module 10 and / or the second light-emitting control module 20 and the driving transistor Tm in different pixel circuits are designed differently, and a bridge line is set in the display panel. At least one of the first light-emitting control module 10 and the second light-emitting control module 20 in the first pixel circuit is connected to the driving transistor Tm via a bridge line, while at least one of the first light-emitting control module 10 and the second light-emitting control module 20 in the second pixel circuit is directly connected to the driving transistor Tm. This includes at least the following schemes:

[0057] Option 1: In the first pixel circuit, one of the two light-emitting control modules is connected to the driving transistor Tm via a bridge line, and the other is directly connected to the driving transistor Tm. In the second pixel circuit, the two light-emitting control modules are directly connected to the driving transistor Tm respectively.

[0058] Option 2: The two light-emitting control modules of the first pixel circuit are respectively connected to the driving transistor Tm through a bridge line; one of the two light-emitting control modules of the second pixel circuit is connected to the driving transistor Tm through a bridge line, and the other is directly connected to the driving transistor Tm.

[0059] Option 3: The two light-emitting control modules of the first pixel circuit are connected to the driving transistor Tm via a bridge line, and the two light-emitting control modules of the second pixel circuit are directly connected to the driving transistor Tm.

[0060] It should be noted that in the pixel circuit, both the first and second terminals of the driving transistor Tm are located on the semiconductor layer 000. Here, "direct connection" means that one terminal of the light-emitting control module is also located on the semiconductor layer 000, allowing the light-emitting control module to be directly connected to the driving transistor Tm. Taking the direct connection between the first light-emitting control module 10 and the first terminal of the driving transistor Tm as an example, the first light-emitting control module 10 includes a first light-emitting control transistor T5. The second terminal of the first light-emitting control transistor T5 and the first terminal of the driving transistor Tm are both located on the semiconductor layer 000, and the second terminal of the first light-emitting control transistor T5 and the first terminal of the driving transistor Tm are directly connected. Alternatively, the second terminal of the first light-emitting control transistor T5 and the first terminal of the driving transistor Tm are continuous structures (or integral structures).

[0061] In the pixel circuit, the first light-emitting control module 10, the driving transistor Tm, and the second light-emitting control module 20 form a light-emitting circuit. The switching state of the first light-emitting control module 10 and / or the second light-emitting control module 20 affects the conduction duration of the light-emitting circuit, and consequently, the duration of providing driving current. This embodiment of the invention differentiates the connection methods between the two light-emitting control modules and the driving transistor Tm in the first and second pixel circuits, and rationally arranges the positions of the two light-emitting control modules in the pixel circuit. This enables differentiated settings for the control signals received by the light-emitting control modules in the two pixel circuits, while meeting the line connection requirements in the pixel circuit. This facilitates driving the first and second pixel circuits with different control methods, allowing for differentiated conduction durations of the light-emitting circuits in the first and second pixel circuits. This results in different durations of driving current provided to the light-emitting devices by different pixel circuits during the light-emitting phase, thus compensating for differences in the luminous efficiency of the light-emitting devices and improving the display effect.

[0062] The above solution will be described in detail below with specific embodiments.

[0063] In this embodiment of the invention, the pixel circuit includes two light-emitting control modules: a first light-emitting control module 10 and a second light-emitting control module 20. Optionally, the first light-emitting control module 10 includes a first light-emitting control transistor T5, and the second light-emitting control module 20 includes a second light-emitting control transistor T6. In the following embodiments, the circuit diagram of the pixel circuit illustrates that the pixel circuit includes the first light-emitting control module 10 and the second light-emitting control module 20, and these are shown in the relevant figures. However, in embodiments involving a schematic diagram of the pixel circuit layout in a display panel, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are directly shown in the layout; that is, the first light-emitting control transistor T5 is shown as the first light-emitting control module 10, and the second light-emitting control transistor T6 is shown as the second light-emitting control module 20.

[0064] In some implementations... Figure 5 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 6 This is another pixel circuit schematic diagram provided in an embodiment of the present invention. Figure 7 This is a signal timing diagram provided for an embodiment of the present invention. Figure 8 for Figure 5 A schematic diagram of a cross-section at the location of the tangent AA′. Figure 5 The diagram illustrates the area where the first pixel circuit 01 is located. Figure 6 for Figure 5 The pixel circuit diagram corresponding to the middle layout.

[0065] Combination Figure 5 and Figure 6 In the first pixel circuit 01, the control terminal of the first light-emitting control module 10 receives the first control signal Emit1, and the control terminal of the second light-emitting control module 20 receives the second control signal Emit2. The effective pulse width of the first control signal Emit1 and the effective pulse width of the second control signal Emit2 are different. The effective pulse width refers to the width (or duration) of the effective pulse, also known as the duration of the effective pulse. Taking a low level as the effective level as an example, a low-level pulse is an effective pulse. Figure 5 It can be seen that the first light-emitting control module 10 includes a first light-emitting control transistor T5, and the second light-emitting control module 20 includes a second light-emitting control transistor T6. In the first pixel circuit 01, the first light-emitting control transistor T5 is directly connected to the driving transistor Tm, and the second light-emitting control transistor T6 is connected to the driving transistor Tm through a bridge line 90. Figure 6 As shown, the first pixel circuit 01 is coupled to the first light-emitting device LD1.

[0066] Combination Figure 7Let's take a low-level signal as the effective pulse signal, and the effective pulse width of the first control signal Emit1 being greater than the effective pulse width of the second control signal Emit2, as an example to illustrate the operating cycle of the first pixel circuit 01. The operating cycle of the first pixel circuit 01 includes a gate reset phase t1, a data writing phase t2, and a light emission phase t3. During the operating cycle of the first pixel circuit 01, the effective pulse periods of the second control signal Emit2 and the first control signal Emit1 overlap. Here, "overlapping periods" is understood as both the second control signal Emit2 and the first control signal Emit1 being effective pulses within the same time period. Figure 7 The diagram illustrates that the effective pulse width of the first control signal Emit1 is greater than the effective pulse width of the second control signal Emit2, and the second control signal Emit2 is an effective pulse during a portion of the effective pulse width of the first control signal Emit1. In other schemes involving the effective pulse width of the first control signal Emit1 being less than the effective pulse width of the second control signal Emit2, the effective pulse periods of the second control signal Emit2 and the first control signal Emit1 overlap, and the first control signal Emit1 is an effective pulse during a portion of the effective pulse width of the second control signal Emit2.

[0067] During the light-emitting phase t3 of the first pixel circuit 01, the overlap period between the effective pulses of the first control signal Emit1 and the second control signal Emit2 is t31. During t32, the first control signal Emit1 is active, and the second control signal Emit2 is inactive. During t31, both the first light-emitting control module 10 and the second light-emitting control module 20 in the first pixel circuit 01 are active, and the first pixel circuit 01 provides drive current to control the first light-emitting device LD1 to emit light. During t32, because the inactive level of the second control signal Emit2 controls the second light-emitting control module 20 to turn off, the first pixel circuit 01 cannot provide drive current. By setting different effective pulse widths for the first control signal Emit1 and the second control signal Emit2, the duration for which the first pixel circuit 01 provides drive current is related to the overlap period of the effective pulses of the two control signals, thereby achieving the regulation of the light-emitting duration of the first light-emitting device LD1 driven by the first pixel circuit 01. Figure 2 From the schematic pixel circuit layout, in Figure 2In the schematic layout design, two light-emitting control modules are directly connected to the driving transistor Tm, so that the control terminals of the two light-emitting control modules receive the same signal. However, in this embodiment of the invention, one of the two light-emitting control modules of the first pixel circuit 01 is connected to the driving transistor Tm via a bridge line 90, while the other is directly connected to the driving transistor Tm. This allows for the design of different effective pulse widths of the control signals received by the control terminals of the two light-emitting control modules. Consequently, the duration of the driving current provided by the first pixel circuit 01 is related to the overlap period of the effective pulses of the two control signals, thereby enabling the regulation of the duration of the driving current provided by the first pixel circuit 01.

[0068] Figure 7 The diagram illustrates a first control line (Emit1) providing a first control signal (Emit1) and a second control line (Emit2) providing a second control signal (Emit2). Optionally, a light-emitting driving circuit is arranged in the display panel, comprising multiple cascaded shift registers. For example, the first light-emitting driving circuit includes multiple cascaded shift registers, with the first control line (Emit1) connected to the output of the shift register in the first light-emitting driving circuit. Similarly, the second light-emitting driving circuit includes multiple cascaded shift registers, with the second control line (Emit2) connected to the output of the shift register in the second light-emitting driving circuit. This results in a difference between the effective pulse width of the first control signal (Emit1) and the effective pulse width of the second control signal (Emit2).

[0069] In other embodiments, the first control signal Emit1 and / or the second control signal Emit2 are provided by a pulse width modulation circuit. During the light emission stage, the pulse width modulation circuit provides control signals to turn off the light emission control module, thereby controlling the duration of the driving current supplied to the pixel circuit. The pulse width modulation circuit can be designed with reference to existing technology and is not illustrated in the accompanying drawings.

[0070] In some implementations, combined Figure 5 and Figure 8 As can be seen, the display panel has a first control line Emit1 and a second control line Emit2. The control terminal of the first light-emitting control module 10 is connected to the first control line Emit1, and the control terminal of the second light-emitting control module 20 is connected to the second control line Emit2; the second light-emitting control module 20 is connected between the driving transistor Tm and the light-emitting device LD. The bridge line 90 includes a first bridge line 91, and in the first pixel circuit 01, the second light-emitting control module 20 and the driving transistor Tm are connected through the first bridge line 91.

[0071] like Figure 8As shown, the display panel includes a substrate 00 and a semiconductor layer 000, a first metal layer 001, a second metal layer 002, a third metal layer 003, and a fourth metal layer 004 located on the substrate 00. For details on the devices and traces arranged in each layer, please refer to... Figure 2 and Figure 4 Corresponding implementation examples are described. (By...) Figure 8 It can be seen that the bridge line 90 is located in the third metal layer 003. This setting allows the original process of the display panel to be used to manufacture the bridge line 90, simplifying the manufacturing process.

[0072] In addition, by Figure 8 It can be seen that along the plane e (i.e., viewed from above), Figure 5 In the direction of the first power supply (Pvdd), the fourth connection line X4 located on the third metal layer 003 and the first power supply terminal Pvdd located on the fourth metal layer 004 overlap with the first light-emitting control transistor T5. The first power supply terminal Pvdd is connected to the fourth connection line X4 through the via O2, and the fourth connection line X4 is connected to the active layer of the first light-emitting control transistor T5 through the via penetrating the insulating layer, thus achieving coupling between the first light-emitting control transistor T5 and the first power supply terminal Pvdd.

[0073] Combination Figure 5 and Figure 8 As seen above, along direction e perpendicular to the plane of the display panel, the first bridge line 91 and the first control line Emit1 overlap insulated manner. During display panel fabrication, a semiconductor layer 000 is first fabricated on the substrate 00, followed by the sequential fabrication of a first metal layer 001, a second metal layer 002, a third metal layer 003, and a fourth metal layer 004. The gates of the transistors in the pixel circuit are located on the first metal layer 001. After the first metal layer 001 is formed using a patterning process, a doping process is performed on the semiconductor layer 000. The doped semiconductor layer 000 can then serve as a conductor in the pixel circuit. During the doping process, the patterned first metal layer 001 acts as a doping shielding layer; that is, along direction e perpendicular to the plane of the substrate 00, a portion of the semiconductor layer 000 structure overlaps with the first metal layer 001, while the remaining portion does not overlap. Direction e is also the direction perpendicular to the plane of the display panel after its fabrication is complete. The semiconductor layer 000 that does not overlap with the first metal layer 001 forms a conductive line after doping, while the semiconductor layer 000 that overlaps with the first metal layer 001 forms the channel region of the transistor after doping. The first metal layer 001 that overlaps with the semiconductor layer 000 serves as the gate of the transistor. Taking the first control line Emit1 located on the first metal layer 001 as an example, ... Figure 8As shown, at the location of the first light-emitting control transistor T5, the first control line Emit1 overlaps with the semiconductor layer 000, and a portion of the first control line Emit1 that overlaps with the semiconductor layer 000 is multiplexed as the gate of the first light-emitting control transistor T5.

[0074] In this embodiment of the invention, the first bridge line 91 and the first control line Emit1 are insulated and overlapped, for comparison. Figure 2 As can be seen, the semiconductor layer 000, which originally connected the second light-emitting control transistor T6 and the driving transistor Tm, can be cut off. The first bridge line 91 is connected to the semiconductor layer 000 through the first via V1, and then to the driving transistor Tm. The first bridge line 91 is connected to the semiconductor layer 000 through the second via V2, and then to the second light-emitting control transistor T6. In this way, the coupling between the second light-emitting control transistor T6 and the driving transistor Tm can be achieved using the first bridge line 91, and the first control line Emit1 can be routed along the horizontal direction x. No winding or other design is required for the first control line Emit1, which simplifies the routing method of the first control line Emit1. Furthermore, when the first control line Emit1 extends to the vicinity of the second light-emitting control transistor T6, it will not overlap with the semiconductor layer 000. This allows it to achieve the goal of not using a portion of the first control line Emit1 as the gate of the second light-emitting control transistor T6. In this way, the second light-emitting control transistor T6 and the first light-emitting control transistor T5 can be controlled by different control signals, thereby enabling the adjustment of the light-emitting duration of the light-emitting device driven by the first pixel circuit 01.

[0075] in addition, Figure 5 and Figure 8 The diagram illustrates that the first light-emitting control module 10 is connected between the driving transistor Tm and the first power supply terminal Pvdd, and the second light-emitting control module 20 is connected between the driving transistor Tm and the light-emitting device LD. The second light-emitting control module 20 is connected to the driving transistor Tm through a bridge line 90.

[0076] In other embodiments, the first light-emitting control module 10 may be connected between the driving transistor Tm and the first power supply terminal Pvdd, and the second light-emitting control module 20 may be connected between the driving transistor Tm and the light-emitting device LD. In this embodiment, the first light-emitting control module 10 and the driving transistor Tm are connected via a bridge line 90, and the second light-emitting control module 20 is directly connected to the driving transistor Tm. A first control line and a second control line are arranged in the display panel. The first control line is connected to the control terminal of the first light-emitting control module 10, and the second control line is connected to the control terminal of the second light-emitting module 20. In this embodiment, the bridge line and the second control line are insulated and overlap, and are not illustrated in the accompanying drawings.

[0077] Figures 5 to 8The embodiment illustrates a scheme where the two light-emitting control modules in the first pixel circuit 01 are controlled by different control signals. It explains the structure and operating cycle of the first pixel circuit 01, including the connection methods where the two light-emitting control modules are respectively connected to the driving transistor Tm. In the above-mentioned scheme one, the layout of the first pixel circuit can adopt... Figure 5 The design is as follows. Furthermore, the connection method between the two light-emitting control modules and the driving transistor in the second pixel circuit mentioned in Scheme 2 is the same as the connection method between the two light-emitting control modules and the driving transistor in the first pixel circuit of Scheme 1, and can be referred to... Figures 5 to 8 The embodiment designs the second pixel circuit in the above-mentioned Scheme 2 so that one of the two light-emitting control modules of the second pixel circuit is connected to the driving transistor Tm through a bridge line, and the other is directly connected to the driving transistor Tm.

[0078] In some implementations... Figure 9 This is a schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present invention. Figure 9 The diagram illustrates the first pixel circuit 01 and the second pixel circuit 02. The first pixel circuit 01 is coupled to the first light-emitting device LD1, and the second pixel circuit 02 is coupled to the second light-emitting device LD2. Figure 10A This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 10A The diagram illustrates a pixel region, which includes two first pixel circuits 01 and one second pixel circuit 02. Figure 10A The schematic diagram of the first pixel circuit 01 and Figure 9 The first pixel circuit 01 corresponds to, Figure 10A The schematic diagram of the second pixel circuit 02 and Figure 9 The second pixel circuit 02 corresponds to this. For Figure 10A The positions of the transistors in the first pixel circuit 01 and the second pixel circuit 02 can be referenced respectively. Figure 5 and Figure 2 To understand.

[0079] like Figure 9 As shown, in the first pixel circuit 01, the control terminal of the first light-emitting control module 10 receives the first control signal Emit1, and the control terminal of the second light-emitting control module 20 receives the second control signal Emit2. The effective pulse width of the first control signal Emit1 and the effective pulse width of the second control signal Emit2 are different. In the second pixel circuit 02, the control terminal of the first light-emitting control module 10 and the control terminal of the second light-emitting control module 20 both receive the first control signal Emit1.

[0080] like Figure 10AAs shown, in the first pixel circuit 01, one of the first light-emitting control module 10 and the second light-emitting control module 20 is connected to the driving transistor Tm via a bridge line 90, and the other is directly connected to the driving transistor Tm, so that the control terminals of the two light-emitting control modules can receive different signals. In the second pixel circuit 02, the two light-emitting control modules are each directly connected to the driving transistor Tm, so that the control terminals of the two light-emitting control modules can receive the same signal. Figure 10A The embodiment is a design that satisfies the above-mentioned Scheme 1.

[0081] like Figure 10A As shown, the display panel includes data lines (Data), scan lines (first scan line S1 and second scan line S2), light emission control lines (such as first control line Emit1 and second control line Emit2), and a first power line. Figure 10A Signal lines (not shown), such as the reset signal line Ref, are provided. The data line Data provides the data voltage Data, the first scan line S1 provides the first scan signal S1, the second scan line S2 provides the second scan signal S2, and the first power supply terminal Pvdd is connected to the first power supply line, providing the first power supply voltage Pvdd (the power supply terminal and the voltage signal it provides use the same designation). The first control signal Emit1 and the second control signal Emit2 are provided by their respective control lines. In the first pixel circuit 01, the control terminal of the first light-emitting control module 10 is coupled to the first control line Emit1, and the control terminal of the second light-emitting control module 20 is coupled to the second control line Emit2. That is, a portion of the first control line Emit1 is multiplexed as the gate of the first light-emitting control transistor T5, and a portion of the second control line Emit2 is multiplexed as the gate of the second light-emitting control transistor T6. In the second pixel circuit 02, the control terminals of both light-emitting control modules are coupled to the first control line Emit1. It can be understood that a portion of the first control line Emit1 is also multiplexed as the gate of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 in the second pixel circuit 02.

[0082] This invention includes multiple first pixel circuits 01 and multiple second pixel circuits 02. The first light-emitting devices LD1 and LD2 driven by the first pixel circuits 01 and 02 respectively can be located in the same pixel row (e.g., ...). Figure 10A(Illustrated in the diagram) These can also be located in different pixel rows. It can be understood that when the first pixel circuit 01 and the second pixel circuit 02 drive light-emitting devices located in the same pixel row, the first scan signal S1 received by both is valid for the same period, the second scan signal S2 received by both is valid for the same period, and the first control signal Emit1 received by both is valid for the same period. When the first pixel circuit 01 and the second pixel circuit 02 drive light-emitting devices located in different pixel rows, the duration of the valid level of the first scan signal S1 received by both is equal, but there is a time difference in the start time of the valid level. This is because the display panel typically drives multiple pixel rows line by line, with cascaded shift registers providing scan signals to multiple scan lines line by line. Therefore, there is a time difference in the effective level periods of the scan signals received by the pixel circuits driving different pixel rows. Correspondingly, for the first control signal Emit1, the effective level duration of the first control signal Emit1 received by the first pixel circuit 01 and the second pixel circuit 02 is equal, but there is a time difference in the start time of the effective level.

[0083] Figure 9 and Figure 10A The provided pixel circuit can be implemented using Figure 7 Driven by the provided signal timing. Combined with Figure 7 Let's understand the operating cycles of the first pixel circuit 01 and the second pixel circuit 02. Taking a low-level signal as the effective pulse signal and the effective pulse width of the first control signal Emit1 being greater than that of the second control signal Emit2 as an example, the operating cycles of both the first pixel circuit 01 and the second pixel circuit 02 include a gate reset phase t1, a data writing phase t2, and a light emission phase t3.

[0084] During the light-emitting phase t3 of the operating cycle of the first pixel circuit 01: the effective pulses of the first control signal Emit1 and the second control signal Emit2 overlap during time period t31, while during time period t32, the first control signal Emit1 is at an effective level and the second control signal Emit2 is at an ineffective level. During time period t31, both the first light-emitting control module 10 and the second light-emitting control module 20 in the first pixel circuit 01 are turned on, and the first pixel circuit 01 provides driving current to control the first light-emitting device LD1 to emit light.

[0085] During the operating cycle of the second pixel circuit 02, the first control signal Emit1 provides valid pulses in both time periods t31 and t32, and both the first light-emitting control module 10 and the second light-emitting control module 20 in the second pixel circuit 02 are turned on. Therefore, during time periods t31 and t32, the second pixel circuit 02 provides driving current to control the second light-emitting device LD2 to emit light. Figure 7When the signal timing provided in the embodiment is used for driving, the light emission duration of the second light-emitting device LD2 is greater than that of the first light-emitting device LD1.

[0086] In this embodiment, one of the two light-emitting control modules of the first pixel circuit 01 is connected to the driving transistor Tm via a bridge line, while the other is directly connected to the driving transistor Tm. The two light-emitting control modules of the second pixel circuit 02 are each directly connected to the driving transistor Tm. Therefore, the control terminals of the two light-emitting control modules in the first pixel circuit 01 can receive different signals, while the control terminals of the two light-emitting control modules in the second pixel circuit 02 receive the same signal. The first and second pixel circuits are driven by different control methods, enabling the conduction durations of the light-emitting circuits in the two pixel circuits to differ. In the light-emitting stage t3 of the first pixel circuit 01, the duration of the driving current provided to it is controlled by the overlap of the effective pulse width of the first control signal Emit1 and the effective pulse width of the second control signal Emit2. In the light-emitting stage t3 of the second pixel circuit 02, the duration of the driving current provided to it is controlled only by the effective pulse width of the first control signal Emit1. This allows the duration of the driving current provided by the second pixel circuit 02 to be greater than the duration of the driving current provided by the first pixel circuit 01. Consequently, the light-emitting duration of the second light-emitting device LD2 is greater than the light-emitting duration of the first light-emitting device LD1. This can compensate for the difference in luminous efficiency between different light-emitting devices and improve the display effect of the display panel.

[0087] In some implementations... Figure 9 In this embodiment, the first light-emitting device LD1 emits green or blue light, and the second light-emitting device LD2 emits red light. That is, the red light-emitting device in the display panel uses... Figure 9 The second pixel circuit 02 is driven, and the green and blue light-emitting devices can be respectively adopted as follows: Figure 9 The first pixel circuit 01 is driven. Corresponding to... Figure 10A From the example, that is Figure 10A In the middle, one of the two first pixel circuits 01 is coupled to the green light-emitting device, and the other is coupled to the blue light-emitting device. Figure 10A The second pixel circuit 02 is coupled to the red light-emitting device. The pixel circuit employs... Figure 7 When driven by the signal timing provided in the embodiment, the red light-emitting device can have a longer emission duration, compensating for the differences in luminous efficiency between different color light-emitting devices. Setting a red light-emitting device with lower luminous efficiency to have a longer emission duration can improve color shift and enhance display effects in applications.

[0088] In some implementations... Figure 10B This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 10B exist Figure 10A The diagram illustrates a red light-emitting device (RLED), a green light-emitting device (GLED), and a blue light-emitting device (BLED) within a pixel area. The pixel area includes red sub-pixels, green sub-pixels, and blue sub-pixels. The red sub-pixels include red light-emitting devices (RLED), the green sub-pixels include green light-emitting devices (GLED), and the blue sub-pixels include blue light-emitting devices (BLED). Figure 10B The first electrode 67 and the second electrode 68 in each sub-pixel are also illustrated. The first electrode 67 is connected to the connecting electrode X5 through the via O4 (e.g., Figure 4 (Illustrated in the diagram), and then connected to the pixel circuit via connecting electrode X5. Optionally, the anode of the light-emitting device is electrically connected to the first electrode 67, and the cathode of the light-emitting device is electrically connected to the second electrode 68. The second electrodes 68 of each sub-pixel within the pixel area are electrically connected to each other to form a laterally extending second auxiliary power line 68X. The second auxiliary power line 68X can serve as the second power terminal Pvee within the pixel area, and can be combined with the first power terminal Pvdd. Figure 10A Please refer to the relevant explanations for understanding. Optionally, the first electrode 67 and the second auxiliary power line 68X are located in the fifth metal layer 005, the first power terminal Pvdd is located in the fourth metal layer 004, and the fifth metal layer 005 is located on the side of the fourth metal layer 004 away from the substrate.

[0089] Optional, such as Figure 10B As shown, the size of the red LED (RLED) is larger than that of the green LED (GLED), and the size of the red LED (RLED) is also larger than that of the blue LED (BLED). Increasing the size of the red LED (RLED) can increase the brightness of the red sub-pixel, thereby compensating for the difference in luminous efficiency between the red LED (RLED) and the green LED (GLED) and blue LED (BLED).

[0090] Optionally, redundant positions can be set in the areas where green and blue sub-pixels are located. Taking the green sub-pixel as an example, one approach is to include a green light-emitting device (GLED) in the green sub-pixel area. When the green GLED fails to emit light, another green GLED is bound to its redundant position. Another approach is to directly bind two green GLEDs in the green sub-pixel area. When one LED fails to emit light, the other LED can work normally to ensure that the sub-pixel emits light. Figure 10B The illustration shows two green light-emitting devices (GLEDs) bonded to a green sub-pixel area and two blue light-emitting devices (BLEDs) bonded to a blue sub-pixel area.

[0091] In some implementations... Figure 11 for Figure 5 Enlarged view of the central region Q1 location, combined with Figure 5 and Figure 11 As can be seen, the first bridge line 91 is connected to the driving transistor Tm through the first via V1, and the first bridge line 91 is connected to the second light-emitting control module 20 through the second via V2. Figure 11 As shown, along the direction parallel to the plane of the display panel, i.e., parallel to the paper surface, the distance from the first via V1 to the first control line Emit1 is d1, and the distance from the second via V2 to the first control line Emit1 is d2; d1 ≥ 2.5 μm, and / or d2 ≥ 2.5 μm. This setting ensures a sufficiently large safety distance between the vias and the first control line Emit1, preventing short circuits between the metal inside the vias and the first control line Emit1 caused by errors in the manufacturing process.

[0092] Figure 11 The diagram illustrates the safe distance between the first control line Emit1 and the via on the first bridge line 91. When the first control line Emit1 is adjacent to a via on other structures, a sufficiently large safe distance can be set between the first control line Emit1 and the via to prevent short circuits. Additionally, the second control line Emit2 can be designed with reference to the first control line Emit1. When the second control line Emit2 is adjacent to a via, the distance between them should also be no less than 2.5 μm. In the related embodiments described below, when the control line and via are adjacent, the safe distance between them can be designed with reference to this section.

[0093] In some implementations... Figure 12 for Figure 5 Enlarged view of the Q2 position in the middle region. Figure 13 for Figure 12 A schematic diagram of a cross-section at the location of the tangent line BB′. (Combined with...) Figure 5 and Figure 12 Looking at it, the second control line Emit2 includes a first routing section 81, which is adjacent to the first light-emitting control module 10 in the first pixel circuit 01. Combined with... Figure 13 The first light-emitting control module 10 includes a first light-emitting control transistor T5. The active layer of the first light-emitting control transistor T5 is located on the semiconductor layer 000. The active layer of the first light-emitting control transistor T5 includes a first electrode region 82, which is located on the side of the active layer near the first trace portion 81. The fourth connection line X4 is connected to the first electrode region 82 through a via O3, and the first power supply terminal Pvdd is connected to the fourth connection line X4 through a via O2, thus connecting the first light-emitting control transistor T5 to the first power supply terminal Pvdd. In this embodiment, the fourth connection line X4 is located on the third metal layer 003, the first power supply terminal Pvdd is located on the fourth metal layer 004, and the first control line Emit1 and the second control line Emit2 are located on the first metal layer 001. Figure 12As can be seen, the fourth connecting line X4 is connected to the first electrode region 82 through two vias O3, and this setting can connect the impedance.

[0094] like Figure 12 and Figure 13 As illustrated, along a direction parallel to the plane of the display panel, the distance d3 between the first trace portion 81 and the first electrode region 82 in the second control line Emit2 is ≥ 1.5 μm. During display panel fabrication, a patterned semiconductor layer 000 is first fabricated, followed by a patterned first metal layer 001. Then, a doping process is performed on the semiconductor layer 000. After the doping process, the portion of the semiconductor layer 000 overlapping with the first metal layer 001 forms the transistor channel, while the portion not overlapping with the first metal layer 001 forms the conductive wire. When the distance between the first trace portion 81 and the first electrode region 82 is too close, a new channel may form in part of the first electrode region 82 after the doping process. In this embodiment of the invention, d3 is set to ≥ 1.5 μm, ensuring a sufficiently large safety distance between the first trace portion 81 and the first electrode region 82, preventing the formation of a new channel in the first electrode region 82, and guaranteeing manufacturing yield.

[0095] Figure 12 and Figure 13 The embodiment illustrates that when the second control line Emit2 and the structure in the semiconductor layer 000 are adjacent, a safe distance is required between them to prevent the formation of a new channel. Additionally, the first control line Emit1 can also be designed with reference to the second control line Emit2. When the first control line Emit1 and the semiconductor layer 00 are adjacent, a sufficiently large safe distance can also be set between the first control line Emit1 and the semiconductor layer 00 to prevent the formation of a new channel. In the related embodiments described below, when the control line located in the first metal layer 000 is adjacent to the semiconductor layer 000, this part can be used as a reference to design the safe distance between them.

[0096] In some implementations... Figure 14 for Figure 11 A schematic diagram showing the semiconductor layer and the first metal layer retained, combined with... Figure 11 and Figure 14 Looking at the first pixel circuit 01, the second light-emitting control module 20 includes a second light-emitting control transistor T6, which includes a gate T6g and an active layer w. The active layer w of the second light-emitting control transistor T6 is located in the semiconductor layer 000; the active layer w includes a second electrode region w1 arranged along the first direction a and a channel ( Figure 14(Not shown in the text) and the third electrode region w2, can be understood as a portion of the channel in the active layer w located between the second electrode region w1 and the third electrode region w2. A portion of the trace in the second control line Emit2 is multiplexed as the gate T6g of the second light-emitting control transistor T6, and the overlapping portion of the active layer w of the second light-emitting control transistor T6 and the gate T6g forms a channel.

[0097] Combination Figure 11 The display panel also includes a first connecting electrode 71. One end of the first connecting electrode 71 is connected to the second electrode area w1 through a third via V3. The other end of the first connecting electrode 71 covers the channel of the second light-emitting control transistor T6 and partially overlaps with the third electrode area w2. The length of the first connecting electrode 71 extending beyond the channel along the first direction a is d4, where d4 ≥ 1 μm. This arrangement allows the first connecting electrode 71 to act as a light shield, preventing light from shining onto the channel and causing leakage that could affect the performance of the pixel circuit.

[0098] The first connecting electrode 71 is part of the third connecting line X3. The third connecting line X3 is connected to the connecting electrode X5 through a via, and then connected to the light-emitting device through the connecting electrode X5, thus realizing the connection between the second light-emitting control transistor T6 and the light-emitting device.

[0099] In addition, by Figure 11 It can be seen that the first connecting electrode 71 is connected to the second electrode region w1 through two third vias V3, which reduces the connection impedance.

[0100] In some implementations, such as Figure 10A As shown, two first pixel circuits 01 and one second pixel circuit 02 are arranged within a pixel area. The display panel includes a first control line Emit1 and a second control line Emit2. The control terminal of the first light-emitting control module 10 in the first pixel circuit 01 is connected to the first control line Emit1, and the control terminal of the second light-emitting control module 20 in the first pixel circuit 01 is connected to the second control line Emit2. Both light-emitting control modules in the second pixel circuit 02 are connected to the first control line Emit1. The second control line Emit2 includes a second trace portion 83 and a third trace portion 84. The second trace portion 83 is adjacent to the second light-emitting control module 20 in the second pixel circuit 02; the third trace portion 84 is adjacent to the first light-emitting control module 10 in the second pixel circuit 02.

[0101] Figure 15 for Figure 10A A schematic diagram showing the semiconductor layer and the first metal layer retained. Figure 15 The location of the first light-emitting control module 10 and the second light-emitting control module 20 is indicated by the markings. For example... Figure 15As shown, the second light-emitting control module 20 in the second pixel circuit 02 includes a fourth electrode region 85 located on the semiconductor layer 000 and near the second trace portion 83. The first light-emitting control module 10 in the second pixel circuit 02 includes a fifth electrode region 86 located on the semiconductor layer 000 and near the third trace portion 84. The fifth electrode region 86 of the first light-emitting control module 10 in the second pixel circuit 02 and the first electrode region 82 of the first light-emitting control module 10 in the first pixel circuit 01 have substantially the same shape. The fourth electrode region 85 of the second light-emitting control module 20 in the second pixel circuit 02 is similar in shape to... Figure 11 Similar to the second electrode region w1 shown in the diagram, the fourth electrode region 85 also needs to be connected to the connecting electrode X5 through a via so that the second light-emitting control module 20 can be connected to the light-emitting device.

[0102] like Figure 15 As shown, along a direction parallel to the plane of the display panel, the distance from the second trace portion 83 to the fourth electrode region 85 is d5, and the distance from the third trace portion 84 to the fifth electrode region 86 is d6; wherein d5 ≥ 1.5 μm, and / or d6 ≥ 1.5 μm. This arrangement ensures a sufficiently large safety distance between the second trace portion 83 and the fourth electrode region 85, and / or between the third trace portion 84 and the fifth electrode region 86, preventing the formation of new channels within the fourth electrode region 85 and / or the fifth electrode region 86, thereby ensuring high manufacturing yield.

[0103] In some embodiments, the present invention also provides a transparent display panel, which includes a transparent area and a non-transparent area. Figure 16 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 17 for Figure 16 A schematic diagram of a cross-section at the position of the tangent CC′. Figure 16 The diagram illustrates the location of one pixel area; in reality, the display panel contains multiple pixel areas arranged in an array. For example... Figure 16 As shown, the pixel area includes the circuit area ( Figure 16 (Not shown in the image) and the transparent area TQ, the circuit area is the area where the pixel circuit is set, wherein the circuit area includes two first pixel circuits 01 and one second pixel circuit 02. Figure 16 It indicates that Figure 10A The same pixel area, the difference is, Figure 16 exist Figure 10A The transmission zone TQ and the first power line 70 are shown in the diagram.

[0104] like Figure 16As shown, the display panel includes a first control line Emit1 and a second control line Emit2. The control terminal of the first light-emitting control module 10 in the first pixel circuit 01 is connected to the first control line Emit1, and the control terminal of the second light-emitting control module 20 in the first pixel circuit 01 is connected to the second control line Emit2. The control terminals of both light-emitting control modules in the second pixel circuit 02 are connected to the first control line Emit1. The positions of the two light-emitting control modules in the pixel circuit can be understood with reference to the aforementioned related figures. In this embodiment, the first light-emitting control module 10 in the first pixel circuit 01 is directly connected to the driving transistor Tm, and the second light-emitting control module 20 is connected to the driving transistor Tm through a bridge line. The two light-emitting control modules in the second pixel circuit 02 are each directly connected to the driving transistor Tm.

[0105] Combination Figure 17 The display panel includes a substrate 00, a semiconductor layer 000, and multiple metal layers located on the substrate 00, such as... Figure 17 The diagram illustrates a first metal layer 001, a third metal layer 003, and a fourth metal layer 004, as well as a second metal layer (not shown). An insulating layer 72 is also provided between adjacent metal layers and between the semiconductor layer 000 and the first metal layer 001. At least one insulating layer 72 has a cutout within the transparent region TQ. During display panel manufacturing, an etching process is used to etch the insulating layer 72 to form the cutout. The cutout on the insulating layer 72 increases the light transmittance of the transparent region TQ, improving the display effect when applied to transparent displays.

[0106] The insulating layer 72 in the display panel includes organic and inorganic insulating layers, with the inorganic insulating layer having a greater impact on transmittance. For example... Figure 17 As illustrated, the insulating layer 72 between the semiconductor layer 000 and the first metal layer 001, and the insulating layer 72 between the first metal layer 001 and the second metal layer, have cutouts. Both of these insulating layers 72 are inorganic insulating layers. Optionally, the insulating layer 72 between the third metal layer 003 and the fourth metal layer 004, and the insulating layer 72 on the side of the fourth metal layer 004 away from the substrate 00, are organic insulating layers. Figure 17 The configuration of the embodiment enables the transmittance of the transmittance region TQ to be large, and retaining the organic insulating layer in the transmittance region TQ can prevent the step difference between the transmittance region TQ and the circuit region from being too large, thus avoiding affecting subsequent process manufacturing.

[0107] Figure 17The boundary of the transmittance zone TQ is indicated by a dashed line. At least one insulating layer 72 within the transmittance zone TQ has a cutout. During display panel manufacturing, the cutout within the transmittance zone TQ can be etched simultaneously with the insulating layer 72, or multiple insulating layers 72 can be etched simultaneously using a single etching process after the multiple metal film layers of the display panel are manufactured. The presence of the cutout in the insulating layer within the transmittance zone TQ creates a step difference between the transmittance zone TQ and the circuit area, forming a groove in the display panel. The location of this groove is the transmittance zone TQ. The boundary of the transmittance zone TQ can be defined at the location of this step difference in the display panel. Figure 17 As illustrated, the transparent area TQ is bounded by the bottom edge of the recess on the display panel. In the related embodiments described below, the distance from the transparent area TQ is calculated based on the distance from the bottom edge of the recess.

[0108] like Figure 16 As shown, the second control line Emit2 is adjacent to the transparent region TQ, and the distance between the second control line Emit2 and the transparent region TQ is d7, where d7 ≥ 5.5 μm. This embodiment sets the second control line Emit2 at a certain distance from the transparent region TQ to prevent excessive etching during the etching of the insulating layer 72 to avoid affecting the setting of the second control line Emit2.

[0109] like Figure 16 As shown, a first control line Emit1 and a second control line Emit2 are provided within the pixel area. The first control line Emit1 is located on the side of the second control line Emit2 closer to the first pixel circuit 01. By setting the first light-emitting control module 10 in the first pixel circuit 02 to be directly connected to the driving transistor Tm, and the second light-emitting control module 20 to be connected to the driving transistor Tm through a bridge line 90, it is possible to connect the control terminal of the first light-emitting control module 10 in the first pixel circuit 01 to the first control line Emit1, and the control terminal of the second light-emitting control module 20 to the second control line Emit2, so that the two light-emitting control modules of the first pixel circuit 01 are controlled by two control signals. Furthermore, positioning the first control line Emit1 on the side of the second control line Emit2 closer to the first pixel circuit 01 facilitates the connection between the two light-emitting control modules in the second pixel circuit 02 and the control line. When the control terminals of both light-emitting control modules in the second pixel circuit 02 are connected to the first control line Emit1, the two light-emitting control modules can be directly connected to the driving transistor Tm respectively. This eliminates the need for a bridge line connecting to the driving transistor Tm in the second pixel circuit 02, thus reducing the area occupied by the second pixel circuit 02. In transparent displays, this design helps increase the area of ​​the transmissive region TQ, improving the transparent display effect.

[0110] In some implementations, such as Figure 16As shown, three pixel circuits are arranged in the pixel area along the second direction b. The first control line Emit1 and the second control line Emit2 extend along the second direction b, and the data line Data and the first power line 70 extend along the first direction a. Since the control terminal of the second light-emitting control module 20 in the first pixel circuit 01 is connected to the second control line Emit2, the second light-emitting control module 20 needs to avoid the first control line Emit1. The second light-emitting control module 20 is connected to the driving transistor Tm through the bridge line 90. This arrangement causes the second light-emitting control module 20 to bulge outward along the first direction a. In this embodiment of the invention, the transmittance region TQ has a notch TQ1. The notch TQ1 is a shape feature of the transmittance region TQ when viewed from a top angle. The second light-emitting control module 20 in the first pixel circuit 01 is opposite to the notch TQ1. In addition, the first edge Y1 adjacent to the second control line Emit2 in the transmittance region TQ is set to be approximately parallel to the second control line Emit2. This implementation can adapt the shape of the transparent area TQ to the boundary shape of the circuit area, maximize the use of space to increase the area of ​​the transparent area TQ, and improve the display effect of transparent display.

[0111] like Figure 16 As shown, the second control line Emit2 is adjacent to the transmission area TQ, and the corner on the notch TQ1 adjacent to the second control line Emit2 is chamfered. Chamfering involves cutting the edge into a bevel. This design ensures that the distance d9 between the chamfer and the second control line Emit2 meets the safety distance requirement, preventing excessive etching of the transmission area TQ from affecting the arrangement of the second control line Emit2. Optionally, d9 ≥ 5.5 μm.

[0112] In addition, such as Figure 16 As shown, within a pixel area, the first power supply terminal Pvdd has a block structure, and it overlaps with the circuits of all three pixels. The block-shaped first power supply terminal Pvdd can also be referred to as the first power connection board. The first power supply terminal Pvdd connects to the first power lines 70 on its left and right sides. Figure 18 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 18 The diagram shows the first power line 70 and the first power terminal Pvdd within the four pixel regions SP, as well as the connection electrode X5 connecting each pixel circuit to the light-emitting device. Figure 18 It can be seen that multiple first power terminals Pvdd arranged along the second direction b can be interconnected to form a first auxiliary power line. The first auxiliary power line and the first power line 70 intersect and are electrically connected to form a grid-like trace, which can reduce the voltage drop of the transmitted power signal and improve in-plane uniformity.

[0113] In addition, the display panel also has multiple second power lines, which extend in the same direction as the first power line 70. The second power lines and the second auxiliary power line 68X (e.g.) Figure 10B (Illustrative diagram) Cross-connections form a mesh-like routing, thereby reducing the voltage drop of transmitted power signals. Optionally, the second power line and the second auxiliary power line 68X are located on the same layer.

[0114] In other implementations, Figure 19 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 19 This shows a top view of a pixel area. Figure 19 The pixel area shown in the diagram and Figure 16 The corresponding pixel areas in the text. Figure 19 China retains Figure 16 The semiconductor layer 000 in the middle. For example... Figure 19 As shown, the display panel also includes a light-shielding layer 73, which is located between the substrate and the semiconductor layer 000. The projection direction of the light-shielding layer 73 and the semiconductor layer 000 onto the substrate is the same in a top-view direction. Figure 19 As can be seen, the orthogonal projection of the light-shielding layer 73 onto the substrate covers the orthogonal projection of the semiconductor layer 000 onto the substrate. When applied to transparent displays, the light-shielding layer 73 can block light from the semiconductor layer 000 near the substrate, preventing ambient light from reaching the channels in the semiconductor layer 000 and causing transistor leakage, thus improving the performance and reliability of the transparent display.

[0115] like Figure 19 As shown, the light-shielding layer 73 includes a first portion 731, and a second light-emitting control module 20 in the first pixel circuit 01 (which can be combined with...). Figure 16 The location of the second light-emitting control module 20 is determined by a semiconductor layer 201, which is the active layer in the second light-emitting control module 20. Along a direction perpendicular to the plane of the display panel, the first portion 731 overlaps with the semiconductor layer 201 in the second light-emitting control module 20; a portion of the first portion 731 is opposite to the notch TQ1, and the distance between the first portion 731 and the transparent area TQ is d8, where d8 ≥ 4.7 μm. This arrangement ensures a sufficiently large safety distance between the transparent area TQ and the light-shielding layer 73, preventing excessive etching during the etching of the insulating layer within the transparent area TQ, which could affect the arrangement of the light-shielding layer 73.

[0116] In other implementations, Figure 20 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 21 This is another pixel circuit schematic diagram provided in an embodiment of the present invention. Figure 22 This is another signal timing diagram provided in an embodiment of the present invention. Figure 20The diagram illustrates the area where the first pixel circuit 01 is located. Figure 21 for Figure 20 The pixel circuit diagram corresponding to the middle layout.

[0117] Combination Figure 20 and Figure 21 The first pixel circuit 01 includes a first light-emitting control module 10, a second light-emitting control module 20, and a first functional module 61. The first functional module 61 is connected between the first terminal of the driving transistor Tm and the first signal terminal D1. The control terminal of the first light-emitting control module 10 receives a first control signal Emit1, the control terminal of the second light-emitting control module 20 receives a second control signal Emit2, and the control terminal of the first functional module 61 receives a third control signal K3. The first light-emitting control module 10, the second light-emitting control module 20, and the first functional module 61 in the first pixel circuit 01 receive different control signals. The first functional module 61 includes a first transistor T7, the gate of which is connected to the third control line K3, which provides a third control signal. The first terminal of the first transistor T7 is connected to the first signal terminal D1, and the second terminal is connected to the driving transistor Tm. Figure 20 As shown, the first light-emitting control module 10 is directly connected to the driving transistor Tm, and the bridge line 90 includes a first bridge line 91 and a second bridge line 92; the second light-emitting control module 20 is connected to the driving transistor Tm through the first bridge line 91, and the first functional module 61 is connected to the driving transistor Tm through the second bridge line 92.

[0118] Can be combined Figure 5 right Figure 20 To understand the illustrated layout structure, Figure 5 On this basis, Figure 20 The system adds a third control line K3, a first functional module 61, a first signal terminal D1, and a second bridge line 92. The first signal terminal D1 and the first power supply terminal Pvdd are located on the same film layer, and the second bridge line 92 and the first bridge line 91 are located on the same film layer. Figure 20 The diagram shows the fourth via V4, through which the first functional module 61 is connected to the first signal terminal D1.

[0119] Combination Figure 22 Let's look at the operating cycle of the first pixel circuit 01, which is... Figure 22 It can be seen that in the operating cycle of the first pixel circuit 01: the effective pulse width of the first control signal Emit1 is less than the effective pulse width of the second control signal Emit2; and during at least a portion of the time when the first control signal Emit1 is an ineffective pulse and the second control signal Emit2 is an effective pulse, the third control signal K3 is an effective pulse. Specifically, the operating cycle of the first pixel circuit 01 includes a gate reset phase t1, a data writing phase t2, and a light emission phase t3.

[0120] like Figure 22 As shown, during the t31 period of the light-emitting stage t3, the effective pulses of the first control signal Emit1 and the second control signal Emit2 overlap. During this period, both the first light-emitting control module 10 and the second light-emitting control module 20 are turned on, and the first pixel circuit 01 provides driving current to the first light-emitting device LD1. During at least a portion of the time when the first control signal Emit1 is an ineffective pulse and the second control signal Emit2 is an effective pulse, i.e. Figure 22 During the t33 period, the third control signal K3 provides an effective pulse to control the first functional module 61 to turn on and write the first signal Sg1 provided by the first signal terminal D1 into the first terminal of the driving transistor Tm. The t33 period is the overlapping period of the effective pulses of the second control signal Emit2 and the third control signal K3. The first signal Sg1 is a constant voltage signal; its voltage value can be equal to or different from the voltage value of the signal provided by the first power supply terminal Pvdd. During the t33 period, the first functional module 61 turns on and writes the first signal Sg1 into the first terminal of the driving transistor Tm, and the second light-emitting control module 20 is in the on state. Therefore, the driving transistor Tm can generate a driving current, and during this period, the first pixel circuit 01 provides a driving current to the first light-emitting device LD1. During the light-emitting stage t3, in the t31 and t33 periods, the first pixel circuit 01 provides a driving current to the first light-emitting device LD1, controlling the first light-emitting device LD1 to emit light.

[0121] In this embodiment, one of the two light-emitting control modules in the first pixel circuit 01 is connected to the driving transistor Tm via a bridge line 90, while the other is directly connected to the driving transistor Tm. This design allows for different effective pulse widths of the control signals received by the control terminals of the two light-emitting control modules. Furthermore, the first functional module 61 is connected to the driving transistor Tm via a second bridge line 92. By strategically arranging the position of the first functional module 61, different control signals are received by the control terminals of both light-emitting control modules. This implementation, by setting different effective pulse widths for the first control signal Emit1 and the second control signal Emit2, and by additionally including the first functional module 61, ensures that the duration of the driving current provided by the first pixel circuit 01 is related to the overlap period of the effective pulses of the first control signal Emit1 and the second control signal Emit2, as well as the overlap period of the effective pulses of the second control signal Emit2 and the third control signal K3. This achieves the regulation of the light-emitting duration of the first light-emitting device LD1 driven by the first pixel circuit 01. Figure 20As shown, the display panel includes a first control line Emit1 and a second control line Emit2. The control terminal of the first light-emitting control module 10 is connected to the first control line Emit1, and the control terminal of the second light-emitting control module 20 is connected to the second control line Emit2. Along the plane perpendicular to the display panel, the second bridge line 92 is insulated from and overlaps with both the first and second control lines Emit1 and Emit2. This arrangement allows the first functional module 61 to avoid the first and second control lines Emit1 and Emit2, ensuring that the control terminal of the first functional module 61 receives different control signals from the control terminals of the two light-emitting control modules, and maintaining the connection between the first functional module 61 and the driving transistor Tm.

[0122] In some implementations... Figure 23 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 24 This is another pixel circuit schematic diagram provided in an embodiment of the present invention. Figure 23 The diagram illustrates the area where the second pixel circuit 02 is located. Figure 24 for Figure 23 The pixel circuit diagram corresponding to the middle layout.

[0123] Combination Figure 23 and Figure 24 The second pixel circuit 02 includes a first light-emitting control module 10, a second light-emitting control module 20, and a second functional module 62. The second functional module 62 is connected between the first terminal of the driving transistor Tm and the first signal terminal D1. The control terminal of the second functional module 62 receives the same signal as the control terminal of the first functional module 61 in the first pixel circuit 01; that is, the control terminal of the second functional module 62 receives the third control signal K3. The second functional module 62 includes a second transistor T8, whose gate is connected to the third control line K3. The first terminal of the second transistor T8 is connected to the first signal terminal D1, and its second terminal is connected to the driving transistor Tm. In the second pixel circuit 02, the control terminals of both the first light-emitting control module 10 and the second light-emitting control module 20 receive the first control signal Emit1. Figure 23 As shown, in the second pixel circuit 02, the two light-emitting control modules are directly connected to the driving transistor Tm, and the bridge line 90 includes a third bridge line 93. The second functional module 62 is connected to the driving transistor Tm through the third bridge line 93.

[0124] Can be combined Figure 2 right Figure 23 To understand the illustrated layout structure, Figure 2 On this basis, Figure 23The system adds a second control line Emit2, a third control line K3, a second functional module 62, a first signal terminal D1, and a third bridge line 93. The first signal terminal D1 and the first power supply terminal Pvdd are located on the same film layer. Figure 23 The diagram shows the fifth via V5, through which the second functional module 62 is connected to the first signal terminal D1.

[0125] Figure 23 and Figure 24 The second pixel circuit 02 in the embodiment can employ Figure 22 The provided signal timing is used for driving. For example... Figure 22 As shown, the operating cycle of the second pixel circuit 02 includes a period when the first control signal Emit1 is an inactive pulse and the third control signal K3 is an active pulse. Specifically, the operating cycle of the second pixel circuit 02 includes a gate reset phase t1, a data writing phase t2, and a light emission phase t3.

[0126] During the operating cycle of the second pixel circuit 02, the first light-emitting control module 10 and the second light-emitting control module 20 are only activated during the t31 period when the first control signal Emit1 provides an effective pulse, causing the second pixel circuit 02 to provide a driving current to control the second light-emitting device LD2 to emit light. During the t33 period, the first control signal Emit1 is an ineffective pulse and the third control signal K3 is an effective pulse. During this period, the second functional module 62 is activated to write the first signal Sg1 provided by the first signal terminal D1 into the first terminal of the driving transistor Tm. During this period, the bias state of the driving transistor Tm can be adjusted using the second functional module 62. Compared with the operating cycle of the first pixel circuit 01, the duration for which the second pixel circuit 02 provides a driving current is shorter than the duration for which the first pixel circuit 01 provides a driving current. Therefore, the light-emitting duration of the second light-emitting device LD2 is shorter than the light-emitting duration of the first light-emitting device LD1.

[0127] In this embodiment, the two light-emitting control modules in the second pixel circuit 02 are directly connected to the driving transistor Tm, enabling the control terminals of the two light-emitting control modules to receive the same control signal. Additionally, the second functional module 62 is connected to the driving transistor Tm via a third bridge line 93. By strategically arranging the position of the second functional module 62, the control terminals of the second functional module 62 and the two light-emitting control modules can receive different control signals. In this implementation, the control terminals of the two light-emitting control modules in the second pixel circuit 02 receive the first control signal Emit1, and the effective pulse width of the first control signal Emit1 is less than the effective pulse width of the second control signal Emit2. This results in the second pixel circuit 02 providing driving current for a shorter duration than the first pixel circuit 01 providing driving current. Consequently, the light-emitting duration of the second light-emitting device LD2 is shorter than that of the first light-emitting device LD1, thereby compensating for the difference in luminous efficiency between the different light-emitting devices and improving the display effect of the display panel. A second functional module 62 is provided in the second pixel circuit 02. During the period when the first control signal Emit1 is an ineffective pulse and the third control signal K3 is an effective pulse, the second functional module 62 can adjust the bias state of the driving transistor Tm in the second pixel circuit 02, reduce the difference in bias state of the driving transistor Tm in the first pixel circuit 01 and the second pixel circuit 02, reduce the difference in characteristics of the driving transistor Tm in the two pixel circuits, and help improve display uniformity.

[0128] like Figure 24 As shown, the display panel includes a first control line Emit1 and a second control line Emit2. The control terminals of the first light-emitting control module 10 and the second light-emitting control module 20 in the second pixel circuit 02 are both connected to the first control line Emit1. (Combined with...) Figure 20 In the first pixel circuit 01, the control terminal of the first light-emitting control module 10 is connected to the first control line Emit1, and the control terminal of the second light-emitting control module 20 is connected to the second control line Emit2. Along a direction perpendicular to the plane of the display panel, the third bridge line 93 is insulated from and overlaps with the first control line Emit1 and the second control line Emit2. This arrangement allows the second functional module 62 to avoid the first control line Emit1 and the second control line Emit2, ensuring that the control terminal of the second functional module 62 receives different control signals from the control terminals of the two light-emitting control modules, and maintaining the connection between the second functional module 62 and the driving transistor Tm.

[0129] In some implementations... Figure 25 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 25 The diagram illustrates a pixel region, which includes a first pixel circuit 01 and two second pixel circuits 02. Figure 25The schematic diagram of the first pixel circuit 01 and Figure 20 The first pixel circuit 01 corresponds to, Figure 25 The schematic diagram of the second pixel circuit 02 and Figure 24 The second pixel circuit 02 corresponds to this.

[0130] like Figure 25 As shown, in the first pixel circuit 01, the control terminal of the first light-emitting control module 10 receives the first control signal Emit1, and the control terminal of the second light-emitting control module 20 receives the second control signal Emit2. The effective pulse widths of the first control signal Emit1 and the second control signal Emit2 are different. In the first pixel circuit 01, one of the first light-emitting control module 10 and the second light-emitting control module 20 is connected to the driving transistor Tm through a bridge line 90, and the other is directly connected to the driving transistor Tm. In the second pixel circuit 02, the control terminals of both the first light-emitting control module 10 and the second light-emitting control module 20 receive the first control signal Emit1, and the two light-emitting control modules of the second pixel circuit 02 are directly connected to the driving transistor Tm respectively. This embodiment is a design that satisfies the above-mentioned scheme one.

[0131] In addition, the second light-emitting control module 20 in the first pixel circuit 01 is connected to the driving transistor Tm via the first bridge line 91. The first pixel circuit 01 also includes a first functional module 61, which is connected to the driving transistor Tm via the second bridge line 92. The second pixel circuit 02 also includes a second functional module 62, which is connected to the driving transistor Tm via the third bridge line 93.

[0132] Figure 25 The medium pixel circuit can be adopted Figure 22 The provided signal timing enables the second pixel circuit 02 to provide driving current for a shorter duration than the first pixel circuit 01. Since the second pixel circuit 02 is coupled to the second light-emitting device LD2, and the first pixel circuit 01 is coupled to the first light-emitting device LD1, the light-emitting duration of the second light-emitting device LD2 is shorter than the light-emitting duration of the first light-emitting device LD1.

[0133] Optional, Figure 25 In this embodiment, within a pixel region: a first pixel circuit 01 is coupled to a red light-emitting device, and one of the two second pixel circuits 02 is coupled to a green light-emitting device and the other is coupled to a blue light-emitting device. The pixel circuit employs... Figure 22 When driven by the signal timing provided in the embodiment, the red light-emitting device can have a longer emission duration, compensating for the differences in luminous efficiency between different color light-emitting devices. Setting a red light-emitting device with lower luminous efficiency to have a longer emission duration can improve color shift and enhance display effects in applications.

[0134] like Figure 25 As shown, the pixel area includes a circuit area, which includes a first pixel circuit 01 and two second pixel circuits 02. The three pixel circuits within the pixel area are arranged along the second direction b. The pixel area includes a first power connection board P1 and a first signal connection board P2. The first power connection board P1 serves as the first power supply terminal Pvdd, and the first signal connection board P2 serves as the first signal terminal D1. The first power connection board P1 overlaps with and is electrically connected to the first light-emitting control module 10. The connection method between the first power connection board P1 and the first light-emitting control module 10 can be referred to... Figure 2 Description of the embodiment. The first signal connection board P2 and the first functional module 61 overlap and are electrically connected; the first signal connection board P2 also overlaps and is electrically connected to the second functional module 62. The first signal connection board P2 serves as the first signal terminal D1, and its connection method with the first functional module 61 can be referred to Figure 20 The connection method between the embodiment and the second functional module 62 can be referred to Figure 24 Description of the embodiments.

[0135] Figure 25 The diagram illustrates a data line (Data) extending along the first direction a. The display panel also includes a first power line and a first signal line extending along the first direction. Figure 25 It is not shown. Please refer to... Figure 26 To understand, Figure 26 This is a simplified schematic diagram of another display panel provided in an embodiment of the present invention. Figure 26 The diagram only shows the semiconductor layer 000, the first metal layer 001, and the fourth metal layer 004 at one pixel location, and also illustrates the first power connection board P1, the first signal connection board P2, the first power line 70, and the first signal line 74. Figure 26 As shown, the first power line 70 and the first signal line 74 extend along the first direction a. The first power connection board P1 is connected to the first power line 70, and the first signal connection board P2 is connected to the first signal line 74. Figure 18 As can be understood from the embodiment description, multiple first power connection boards P1 and multiple first signal connection boards P2 are provided in multiple pixel areas of the display panel. The multiple first power connection boards P1 can be interconnected with multiple first power lines 70 to form a grid-like trace, which can reduce the voltage drop of the transmitted power signal. Correspondingly, the multiple first signal connection boards P2 can be interconnected with multiple first signal lines 74 to form a grid-like trace, which can also reduce the voltage drop of the transmitted signal on the first signal lines 74.

[0136] Optional, such as Figure 26As shown, the first signal connection board P2, the first power connection board P1, and the first power line 70 are all located on the fourth metal layer 004. The first signal line 74 and the first signal connection board P2 are located on different layers, and the first signal line 74 and the first signal connection board P2 are connected by a connecting line 75. Optionally, the connecting line 75 can be located on the same layer as the reset signal line, that is, the connecting line 75 is located on the second metal layer 002 mentioned above.

[0137] In some embodiments, the first power line 70 and the first signal line 74 are located between adjacent pixel areas in the second direction b, and the first power line 70 and the first signal line 74 are located on different layers. A light-shielding layer is provided in the display panel, which can be referred to... Figure 19 The light-shielding layer is described in the embodiment. Located between the substrate 00 and the semiconductor layer 000, the light-shielding layer blocks light to prevent leakage current from the channels in the semiconductor layer 000. The first signal line 74 is on the same layer as the light-shielding layer. This embodiment can be applied to transparent display panels, where the first signal line 74 is fabricated on the same layer as the light-shielding layer without increasing the manufacturing process, and the placement of the first signal line 74 does not affect the wiring method of the original first power line 70.

[0138] In some embodiments, a light-shielding layer can be electrically connected to the first signal line 74. When the first signal line 74 transmits a constant voltage signal, the light-shielding layer can also act as a shield on the side of the semiconductor layer 000 closest to the substrate.

[0139] In some implementations... Figure 27 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 27 The diagram illustrates a pixel region, which includes a first pixel circuit 01 and two second pixel circuits 02. Figure 28 This is another pixel circuit schematic diagram provided in an embodiment of the present invention. Figure 27 for Figure 28 A layout design corresponding to the mid-pixel circuit. Figure 27 The structure of the first pixel circuit 01 and the second pixel circuit 02 is only simplified in the diagram, which only shows the semiconductor layer 000, the first metal layer 001 and the corresponding bridge line 90, and marks the position of each light-emitting control module.

[0140] like Figure 27 and Figure 28 As shown, in the first pixel circuit 01, the control terminal of the first light-emitting control module 10 and the control terminal of the second light-emitting control module 20 both receive the first control signal Emit1. In the second pixel circuit 02, the control terminal of the first light-emitting control module 10 receives the first control signal Emit1, and the control terminal of the second light-emitting control module 20 receives the second control signal Emit2. Figure 27As shown, in the first pixel circuit 01, the first light-emitting control module 10 and the second light-emitting control module 20 are respectively connected to the driving transistor Tm via a bridge line 90; in the second pixel circuit 02, the first light-emitting control module 10 is connected to the driving transistor Tm via a bridge line 90, and the second light-emitting control module 20 is directly connected to the driving transistor Tm. This embodiment is a design that satisfies the above-mentioned scheme two.

[0141] Figure 27 and Figure 28 The pixel circuits provided in the embodiments can be adopted Figure 7 The provided signal timing is used for driving. The effective pulse widths of the first control signal Emit1 and the second control signal Emit2 are different, and the effective pulse width of the first control signal Emit1 is greater than that of the second control signal Emit2. The operating cycles of both the first pixel circuit 01 and the second pixel circuit 02 include a gate reset phase t1, a data writing phase t2, and a light emission phase t3.

[0142] During the light-emitting phase t3 of the operating cycle of the second pixel circuit 02: the effective pulses of the first control signal Emit1 and the second control signal Emit2 overlap during time period t31, while during time period t32, the first control signal Emit1 is at an effective level and the second control signal Emit2 is at an ineffective level. Therefore, during time period t31, both the first light-emitting control module 10 and the second light-emitting control module 20 in the second pixel circuit 02 are turned on, and the second pixel circuit 02 provides driving current to control the second light-emitting device LD2 to emit light.

[0143] During the operating cycle of the first pixel circuit 01, the first control signal Emit1 provides valid pulses in both time periods t31 and t32, and both the first light-emitting control module 10 and the second light-emitting control module 20 in the first pixel circuit 01 are turned on. Therefore, during time periods t31 and t32, the first pixel circuit 01 provides a driving current to control the first light-emitting device LD1 to emit light. Figure 7 When the signal timing provided in the embodiment is used for driving, the light emission duration of the first light-emitting device LD1 is greater than the light emission duration of the second light-emitting device LD2.

[0144] This embodiment differentiates the connection methods between the two light-emitting control modules and the driving transistor Tm in the first pixel circuit 01 and the second pixel circuit 02, and rationally arranges the positions of the two light-emitting control modules in the pixel circuits, enabling differentiated settings for the control signals received by the light-emitting control modules in the two pixel circuits. Furthermore, by setting different effective pulse widths for the first control signal Emit1 and the second control signal Emit2, the duration of the driving current provided by the second pixel circuit 02 is related to the overlap period of the effective pulses of the two control signals, while the duration of the driving current provided by the first pixel circuit 01 is only related to the effective pulse width of the first control signal Emit1. This allows the duration of the driving current provided by the first pixel circuit 01 to be greater than the duration of the driving current provided by the second pixel circuit 02. Consequently, the light-emitting duration of the first light-emitting device LD1 driven by the first pixel circuit 01 is greater than the light-emitting duration of the second light-emitting device LD2 driven by the second pixel circuit 02, thereby compensating for the difference in luminous efficiency of the light-emitting devices and improving the display effect. In some embodiments, Figure 27 In this embodiment, the first pixel circuit 01 is coupled to the red light-emitting device, and one of the two second pixel circuits 02 is coupled to the green light-emitting device and the other is coupled to the blue light-emitting device. That is... Figure 28 In this embodiment, the first light-emitting device LD1 emits red light, and the first light-emitting device LD2 emits green or blue light. In the pixel circuit... Figure 7 When driven by the signal timing provided in the embodiment, the red light-emitting device can have a longer emission duration, compensating for the differences in luminous efficiency between different color light-emitting devices. Setting a red light-emitting device with lower luminous efficiency to have a longer emission duration can improve color shift and enhance display effects in applications.

[0145] like Figure 27 As shown, the display panel includes a first control line Emit1 and a second control line Emit2. The control terminal of the first light-emitting control transistor T5 in the second pixel circuit 02 is connected to the first control line Emit1, and the control terminal of the second light-emitting control transistor T6 in the second pixel circuit 02 is connected to the second control line Emit2. In the first pixel circuit 01, the control terminals of both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the first control line Emit1. The first control line Emit1 is located on the side of the second control line Emit2 furthest from the driving transistor Tm.

[0146] The bridge line 90 includes a fourth bridge line 94, a fifth bridge line 95, and a sixth bridge line 96. In the first pixel circuit 01, the first light-emitting control module 10 is connected to the driving transistor Tm via the fourth bridge line 94, and the second light-emitting control module 20 is connected to the driving transistor Tm via the fifth bridge line 95. In the second pixel circuit 02, the first light-emitting control module 10 is connected to the driving transistor Tm via the sixth bridge line 96. Along the direction perpendicular to the plane of the display panel, the fourth bridge line 94 is insulated from and overlaps with the second control line Emit2, the fifth bridge line 95 is insulated from and overlaps with the second control line Emit2, and the sixth bridge line 96 is insulated from and overlaps with the second control line Emit2. This arrangement allows the first light-emitting control transistor T5 in the second pixel circuit 02 to avoid the second control line Emit2, so that the two light-emitting control modules in the second pixel circuit 02 are controlled by the first control line Emit1 and the second control line Emit2, respectively. Furthermore, both light-emitting control transistors in the first pixel circuit 01 avoid the second control line Emit2, ensuring that both light-emitting control modules in the first pixel circuit 01 are controlled by the first control line Emit1. By differentiating the connection methods between the two light-emitting control modules and the driving transistor Tm in the first pixel circuit 01 and the second pixel circuit 02, and by rationally arranging the positions of the two light-emitting control modules in the pixel circuit, differentiated settings for receiving control signals by the light-emitting control modules in the two pixel circuits can be achieved, while meeting the line connection requirements in the pixel circuit.

[0147] In some implementations... Figure 29 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 29 The diagram illustrates a pixel region, which includes two first pixel circuits 01 and one second pixel circuit 02. Figure 30 This is another pixel circuit schematic diagram provided in an embodiment of the present invention. Figure 29 for Figure 30 A layout design corresponding to the mid-pixel circuit. Figure 29 The structure of the first pixel circuit 01 and the second pixel circuit 02 is only simplified in the diagram, which only shows the semiconductor layer 000, the first metal layer 001 and the corresponding bridge line 90, and marks the position of each light-emitting control module.

[0148] like Figure 29 and Figure 30As shown, in the first pixel circuit 01, the control terminal of the first light-emitting control module 10 receives the first control signal Emit1, and the control terminal of the second light-emitting control module 20 also receives the first control signal Emit1; in the second pixel circuit 02, the control terminal of the first light-emitting control module 10 receives the second control signal Emit2, and the control terminal of the second light-emitting control module 20 also receives the second control signal Emit2. The effective pulse widths of the first control signal Emit1 and the second control signal Emit2 are different.

[0149] like Figure 29 As shown, in the first pixel circuit 01, the first light-emitting control module 10 is connected to the driving transistor Tm via a bridge line 90, and the second light-emitting control module 20 is also connected to the driving transistor Tm via a bridge line 90. In the second pixel circuit 02, the first light-emitting control module 10 and the driving transistor Tm are directly connected, and the second light-emitting control module 20 and the driving transistor Tm are also directly connected. The first light-emitting control module 10 includes a first light-emitting control transistor T5, and the second light-emitting control module 20 includes a second light-emitting control transistor T6. This embodiment is a design that satisfies the above-mentioned scheme three.

[0150] Figure 29 and Figure 30 The pixel circuits provided in the embodiments can be adopted Figure 7 The provided signal timing is used for driving. The effective pulse widths of the first control signal Emit1 and the second control signal Emit2 are different, and the effective pulse width of the first control signal Emit1 is greater than that of the second control signal Emit2. The operating cycles of both the first pixel circuit 01 and the second pixel circuit 02 include a gate reset phase t1, a data writing phase t2, and a light emission phase t3.

[0151] During the operating cycle of the first pixel circuit 01, in the light-emitting phase t3, the period when the first control signal Emit1 is an effective pulse controls both the first light-emitting control module 10 and the second light-emitting control module 20 in the first pixel circuit 01 to be turned on. The first pixel circuit 01 provides driving current to control the first light-emitting device LD1 to emit light. During the operating cycle of the second pixel circuit 02, in the light-emitting phase t3, the period when the second control signal Emit2 is an effective pulse controls both the first light-emitting control module 10 and the second light-emitting control module 20 in the second pixel circuit 02 to be turned on. The second pixel circuit 02 provides driving current to control the second light-emitting device LD2 to emit light. Since the effective pulse width of the first control signal Emit1 is greater than the effective pulse width of the second control signal Emit2, the following is adopted: Figure 7 When the signal timing provided in the embodiment is used for driving, the duration of the driving current provided by the first pixel circuit 01 is greater than the duration of the driving current provided by the second pixel circuit 02, and the duration of the light emission of the first light-emitting device LD1 is greater than the duration of the light emission of the second light-emitting device LD2.

[0152] This embodiment differentiates the connection methods between the two light-emitting control modules and the driving transistor Tm in the first pixel circuit 01 and the second pixel circuit 02, and rationally arranges the positions of the two light-emitting control modules in the pixel circuits, enabling differentiated settings for the control signals received by the light-emitting control modules in the two pixel circuits. Furthermore, by setting different effective pulse widths for the first control signal Emit1 and the second control signal Emit2, the duration of the driving current provided by the second pixel circuit 02 is related to the effective pulse width of the second control signal Emit2, while the duration of the driving current provided by the first pixel circuit 01 is only related to the effective pulse width of the first control signal Emit1. This allows the duration of the driving current provided by the first pixel circuit 01 to be greater than the duration of the driving current provided by the second pixel circuit 02. Consequently, the light-emitting duration of the first light-emitting device LD1 driven by the first pixel circuit 01 is greater than the light-emitting duration of the second light-emitting device LD2 driven by the second pixel circuit 02, thereby compensating for the difference in luminous efficiency of the light-emitting devices and improving the display effect. In some embodiments, Figure 29 In this embodiment, the first pixel circuit 01 is coupled to the red light-emitting device, and one of the two second pixel circuits 02 is coupled to the green light-emitting device and the other is coupled to the blue light-emitting device. That is... Figure 30 In this embodiment, the first light-emitting device LD1 emits red light, and the first light-emitting device LD2 emits green or blue light. In the pixel circuit... Figure 7 When driven by the signal timing provided in the embodiment, the red light-emitting device can have a longer emission duration, compensating for the differences in luminous efficiency between different color light-emitting devices. Setting a red light-emitting device with lower luminous efficiency to have a longer emission duration can improve color shift and enhance display effects in applications.

[0153] In some implementations, such as Figure 29As shown, the display panel includes a first control line Emit1 and a second control line Emit2. The control terminals of the first light-emitting control module 10 and the second light-emitting control module 20 in the first pixel circuit 01 are both connected to the first control line Emit1. Similarly, the control terminals of the first light-emitting control module 10 and the second light-emitting control module 20 in the second pixel circuit 02 are both connected to the second control line Emit2. The bridge line 90 includes a seventh bridge line 97 and an eighth bridge line 98. In the first pixel circuit 01, the first light-emitting control module 10 is connected to the driving transistor Tm via the seventh bridge line 97, and the second light-emitting control module 20 is connected to the driving transistor Tm via the eighth bridge line 98. Along a direction perpendicular to the plane of the display panel, the seventh bridge line 97 and the second control line Emit2 are insulated and overlap, and the eighth bridge line 98 and the second control line Emit2 are also insulated and overlap. This configuration allows the first light-emitting control transistor T5 and the second light-emitting control transistor T6 in the first pixel circuit 01 to avoid the second control line Emit2, ensuring that both light-emitting control modules in the first pixel circuit 01 are controlled by the first control line Emit1, and both light-emitting control modules in the second pixel circuit 02 are also controlled by the first control line Emit1. By differentiating the connection methods between the two light-emitting control modules and the driving transistor Tm in the first pixel circuit 01 and the second pixel circuit 02, and by rationally arranging the positions of the two light-emitting control modules in the pixel circuit, differentiated settings for receiving control signals by the light-emitting control modules in the two pixel circuits can be achieved, while meeting the line connection requirements in the pixel circuits.

[0154] In other embodiments, in the first pixel circuit 01, the control terminal of the first light-emitting control module 10 receives the first control signal Emit1, and the control terminal of the second light-emitting control module 20 also receives the first control signal Emit1; in the second pixel circuit 02, the control terminal of the first light-emitting control module 10 receives the second control signal Emit2, and the control terminal of the second light-emitting control module 20 also receives the second control signal Emit2. The effective pulse width of the first control signal Emit1 is different from the effective pulse width of the second control signal Emit2. Specifically, the effective pulse width of the first control signal Emit1 is smaller than the effective pulse width of the second control signal Emit2. Therefore, the duration for which the driving current is provided in the working cycle of the first pixel circuit 01 is shorter than the duration for which the driving current is provided in the working cycle of the second pixel circuit 02. In applications, if the first light-emitting device coupled to the first pixel circuit 01 emits green or blue light, and the light-emitting device coupled to the second pixel circuit 02 emits red light, the light-emitting duration of the red light-emitting device can be longer, compensating for the difference in luminous efficiency between different color light-emitting devices. In applications, this can improve color shift and enhance display effects.

[0155] Based on the same inventive concept, embodiments of the present invention provide a display device. Figure 31This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 31 As shown, the display device includes a display panel 100 provided in any embodiment of the present invention. The structure of the display panel has been described in the above embodiments and will not be repeated here. The display device provided in the embodiments of the present invention can be, for example, an electronic device such as a mobile phone, computer, tablet, television, or transparent display device.

[0156] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0157] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes multiple pixel circuits and multiple light-emitting devices; the pixel circuit includes a driving transistor, a first light-emitting control module and a second light-emitting control module; of the first light-emitting control module and the second light-emitting control module, one is connected between a first power supply terminal and a first electrode of the driving transistor, and the other is connected between a second electrode of the driving transistor and the light-emitting device; The pixel circuit includes a first pixel circuit and a second pixel circuit, which are respectively coupled to light-emitting devices of different colors; the display panel includes a bridge line. In the first pixel circuit, at least one of the first light-emitting control module and the second light-emitting control module is connected to the driving transistor through the bridge line, and the bridge line is connected to the driving transistor and one of the first light-emitting control module and the second light-emitting control module through vias; in the second pixel circuit, at least one of the first light-emitting control module and the second light-emitting control module is directly connected to the driving transistor. The display panel includes a first control line and a second control line, wherein the first control line provides a first control signal and the second control line provides a second control signal; The display panel satisfies at least one of the following: The first control line is located between the second control line and the driving transistor of the pixel circuit; in the first pixel circuit, the control terminal of the first light-emitting control module receives the first control signal, and the control terminal of the second light-emitting control module receives the second control signal; the first light-emitting control module is directly connected to the driving transistor, and the second light-emitting control module is connected to the driving transistor through the bridge line; in the second pixel circuit, both the control terminals of the first and second light-emitting control modules receive the first control signal; in the second pixel circuit, the first light-emitting control module is directly connected to the driving transistor, and the second light-emitting module is directly connected to the driving transistor. or, The first control line is located on the side of the second control line away from the driving transistor of the pixel circuit. In the first pixel circuit, the control terminals of both the first and second light-emitting control modules receive a first control signal. Both the control terminals of the first and second light-emitting control modules are connected to the first control line. The first and second light-emitting control modules are respectively connected to the driving transistor via the bridge line. In the second pixel circuit, the control terminal of the first light-emitting control module receives the first control signal, and the control terminal of the second light-emitting module receives a second control signal. The control terminal of the first light-emitting control module is connected to the first control line, and the control terminal of the second light-emitting module is connected to the second control line. In the second pixel circuit, the first light-emitting control module is connected to the driving transistor via the bridge line, and the second light-emitting control module is directly connected to the driving transistor. or, The first control line is located on the side of the second control line away from the driving transistor of the pixel circuit; in the first pixel circuit, the control terminal of the first light-emitting control module receives a first control signal, and the control terminal of the second light-emitting control module receives the first control signal; in the second pixel circuit, the control terminal of the first light-emitting control module receives a second control signal, and the control terminal of the second light-emitting control module receives the second control signal; in the first pixel circuit, the first light-emitting control module is connected to the driving transistor through the bridge line, and the second light-emitting control module is connected to the driving transistor through the bridge line; in the second pixel circuit, the first light-emitting control module is directly connected to the driving transistor, and the second light-emitting control module is directly connected to the driving transistor.

2. The display panel according to claim 1, characterized in that, In the first pixel circuit, the control terminal of the first light-emitting control module receives the first control signal, and the control terminal of the second light-emitting control module receives the second control signal; the effective pulse width of the first control signal and the effective pulse width of the second control signal are different. In the first pixel circuit, the first light-emitting control module is directly connected to the driving transistor, and the second light-emitting control module is connected to the driving transistor through the bridge line.

3. The display panel according to claim 2, characterized in that, The control terminal of the first light-emitting control module is connected to the first control line, and the control terminal of the second light-emitting control module is connected to the second control line; The bridge line includes a first bridge line, in which the second light emission control module and the driving transistor are connected through the first bridge line in the first pixel circuit.

4. The display panel according to claim 3, characterized in that, Along a plane perpendicular to the display panel, the first bridge line and the first control line are insulated from each other and overlap.

5. The display panel according to claim 4, characterized in that, The first bridge line is connected to the driving transistor through a first via, and the first bridge line is connected to the second light-emitting control module through a second via; Along a direction parallel to the plane of the display panel, the distance between the first via and the first control line is d1, and the distance between the second via and the first control line is d2; d1 ≥ 2.5 μm, and / or d2 ≥ 2.5 μm.

6. The display panel according to claim 3, characterized in that, The second control line includes a first trace portion, which is adjacent to the first light-emitting control module in the first pixel circuit; the display panel includes a semiconductor layer, and the first light-emitting control module in the first pixel circuit includes a first electrode region located on the semiconductor layer and close to the first trace portion. Along a direction parallel to the plane where the display panel is located, the distance between the first trace portion and the first electrode area is d3, where d3 ≥ 1.5 μm.

7. The display panel according to claim 3, characterized in that, The second light-emitting control module in the first pixel circuit includes a gate and an active layer; The display panel includes a semiconductor layer, and the active layer is located on the semiconductor layer; the active layer includes a second electrode region, a channel, and a third electrode region arranged along a first direction; a portion of the second control line is multiplexed as the gate, and the portion of the active layer that overlaps with the gate forms the channel; The display panel further includes a first connecting electrode, one end of which is connected to a via in the second electrode area, and the other end of which covers the channel and partially overlaps with the third electrode area. The length of the first connecting electrode extending beyond the channel in the first direction is d4, where d4 ≥ 1 μm.

8. The display panel according to claim 2, characterized in that, In the second pixel circuit, both the control terminal of the first light-emitting control module and the control terminal of the second light-emitting control module receive the first control signal; In the second pixel circuit, the first light-emitting control module is directly connected to the driving transistor, and the second light-emitting control module is also directly connected to the driving transistor.

9. The display panel according to claim 8, characterized in that, In the first pixel circuit, the control terminal of the first light-emitting control module is connected to the first control line, and the control terminal of the second light-emitting control module is connected to the second control line. The second control line includes a second routing section and a third routing section. The second routing section is adjacent to the second light-emitting control module in the second pixel circuit; the third routing section is adjacent to the first light-emitting control module in the second pixel circuit. The display panel includes a semiconductor layer. The second light-emitting control module in the second pixel circuit includes a fourth electrode region located on the semiconductor layer and close to the second trace portion. The first light-emitting control module in the second pixel circuit includes a fifth electrode region located on the semiconductor layer and close to the third trace portion. Along a direction parallel to the plane of the display panel, the distance between the second trace portion and the fourth electrode region is d5, and the distance between the third trace portion and the fifth electrode region is d6. Wherein, d5 ≥ 1.5 μm, and / or d6 ≥ 1.5 μm.

10. The display panel according to claim 8, characterized in that, The effective pulse width of the first control signal is greater than the effective pulse width of the second control signal; During the operating cycle of the first pixel circuit, the effective pulse period of the second control signal overlaps with the effective pulse period of the first control signal.

11. The display panel according to claim 8, characterized in that, In the first pixel circuit, the control terminal of the first light-emitting control module is connected to the first control line, and in the second pixel circuit, the control terminal of the second light-emitting control module is connected to the second control line. The display panel includes a pixel area, which includes a circuit area and a transparent area. The circuit area includes two first pixel circuits and one second pixel circuit. The display panel includes a substrate and a plurality of insulating layers located on one side of the substrate, wherein at least one of the insulating layers has a cutout in the transparent area; wherein the second control line is adjacent to the transparent area, and the distance between the second control line and the transparent area is d7, where d7 ≥ 5.5 μm.

12. The display panel according to claim 8, characterized in that, The display panel includes a pixel area, which includes a circuit area and a transparent area. The circuit area includes two first pixel circuits and one second pixel circuit. The display panel includes a substrate and a plurality of insulating layers located on one side of the substrate, wherein at least one of the insulating layers has a cutout in the transparent area; The transparent area has a notch, and the second light-emitting control module in the first pixel circuit is opposite to the notch.

13. The display panel according to claim 12, characterized in that, The display panel further includes a light-shielding layer and a semiconductor layer, wherein the light-shielding layer is located between the substrate and the semiconductor layer; the orthogonal projection of the light-shielding layer onto the substrate covers the orthogonal projection of the semiconductor layer onto the substrate; The light-shielding layer includes a first portion; along a direction perpendicular to the plane of the display panel, the first portion overlaps with the semiconductor layer in the second light-emitting control module of the first pixel circuit; a portion of the first portion is opposite to the notch, and the distance of the first portion from the transparent area is d8, wherein d8 ≥ 4.7 μm.

14. The display panel according to claim 12, characterized in that, In the first pixel circuit, the control terminal of the first light-emitting control module is connected to the first control line, and the control terminal of the second light-emitting control module is connected to the second control line. The second control line is adjacent to the transmission area, and the corner of the notch adjacent to the second control line is chamfered.

15. The display panel according to claim 12, characterized in that, The display panel includes a first control line and a second control line. The first control line is located on the side of the second control line closer to the first pixel circuit.

16. The display panel according to claim 2, characterized in that, The first pixel circuit includes a first functional module, which is connected between the first pole and the first signal terminal of the driving transistor in the first pixel circuit. The bridge line includes a second bridge line; The first functional module is connected to the driving transistor via the second bridge line.

17. The display panel according to claim 16, characterized in that, In the first pixel circuit, the control terminal of the first light-emitting control module is connected to the first control line, and the control terminal of the second light-emitting control module is connected to the second control line. Along a plane perpendicular to the display panel, the second bridge line is insulated from and overlaps with the first control line, and is also insulated from and overlaps with the second control line.

18. The display panel according to claim 16, characterized in that, The display panel includes a third control line, the control terminal of the first functional module is connected to the third control line, and the third control line provides a third control signal; During the operating cycle of the first pixel circuit: the effective pulse width of the first control signal is less than the effective pulse width of the second control signal; during at least a portion of the time when the first control signal is an ineffective pulse and the second control signal is an effective pulse, the third control signal is an effective pulse.

19. The display panel according to claim 16, characterized in that, The display panel includes a pixel area, the pixel area includes a circuit area, and the circuit area includes a first pixel circuit and two second pixel circuits; The pixel area includes a first power connection board and a first signal connection board, wherein the first power connection board and the first light-emitting control module overlap and are electrically connected, and the first signal connection board and the first functional module overlap and are electrically connected; the display panel includes a first power line and a first signal line extending along a first direction. The three pixel circuits within the pixel area are arranged along a second direction; the second direction intersects the first direction; the first power connection board is connected to the first power line, and the first signal connection board is connected to the first signal line.

20. The display panel according to claim 19, characterized in that, The first power line and the first signal line are located between adjacent pixel areas in the second direction; the first power line and the first signal line are located on different layers; The display panel includes a substrate, a light-shielding layer, and a semiconductor layer. The light-shielding layer is located between the substrate and the semiconductor layer, and the orthogonal projection of the light-shielding layer on the substrate covers the orthogonal projection of the semiconductor layer on the substrate. The first signal line is in the same layer as the light-shielding layer.

21. The display panel according to claim 16, characterized in that, In the second pixel circuit, both the control terminal of the first light-emitting control module and the control terminal of the second light-emitting control module receive the first control signal; The second pixel circuit includes a second functional module, which is connected between the first pole of the driving transistor and the first signal terminal. The control terminal of the second functional module and the control terminal of the first functional module receive the same signal. The bridge line includes a third bridge line; the second functional module is connected to the driving transistor through the third bridge line.

22. The display panel according to claim 21, characterized in that, In the first pixel circuit, the control terminal of the first light-emitting control module is connected to the first control line, and the control terminal of the second light-emitting control module is connected to the second control line; in the second pixel circuit, both the control terminals of the first light-emitting control module and the control terminals of the second light-emitting module are connected to the first control line. Along a direction perpendicular to the plane where the display panel is located, the third bridge line is insulated from and overlaps with the first control line and the second control line.

23. The display panel according to claim 1, characterized in that, In the first pixel circuit, both the control terminal of the first light-emitting control module and the control terminal of the second light-emitting control module receive a first control signal. In the second pixel circuit, the control terminal of the first light-emitting control module receives the first control signal, and the control terminal of the second light-emitting control module receives a second control signal. In the first pixel circuit, the first light-emitting control module and the second light-emitting control module are respectively connected to the driving transistor through the bridge line; In the second pixel circuit, the first light-emitting control module is connected to the driving transistor through the bridge line, and the second light-emitting control module is directly connected to the driving transistor.

24. The display panel according to claim 23, characterized in that, In the second pixel circuit, the control terminal of the first light-emitting control module is connected to the first control line, and the control terminal of the second light-emitting control module is connected to the second control line. The bridge line includes the fourth bridge line, the fifth bridge line, and the sixth bridge line; In the first pixel circuit, the first light-emitting control module is connected to the driving transistor via the fourth bridge line, and the second light-emitting control module is connected to the driving transistor via the fifth bridge line. In the second pixel circuit, the first light-emitting control module is connected to the driving transistor via the sixth bridge line. Along a plane perpendicular to the display panel, the fourth bridge line is insulated from and overlaps with the second control line, the fifth bridge line is insulated from and overlaps with the second control line, and the sixth bridge line is insulated from and overlaps with the second control line.

25. The display panel according to claim 1, characterized in that, In the first pixel circuit, the control terminal of the first light-emitting control module receives a first control signal, and the control terminal of the second light-emitting control module receives the first control signal; in the second pixel circuit, the control terminal of the first light-emitting control module receives a second control signal, and the control terminal of the second light-emitting control module receives the second control signal. In the first pixel circuit, the first light-emitting control module is connected to the driving transistor through the bridge line, and the second light-emitting control module is connected to the driving transistor through the bridge line. In the second pixel circuit, the first light-emitting control module is directly connected to the driving transistor, and the second light-emitting control module is also directly connected to the driving transistor.

26. The display panel according to claim 25, characterized in that, In the first pixel circuit, the control terminal of the first light-emitting control module is connected to the first control line, and the control terminal of the second light-emitting control module is connected to the first control line; in the second pixel circuit, the control terminal of the first light-emitting control module is connected to the second control line, and the control terminal of the second light-emitting module is connected to the second control line. The bridge line includes the seventh bridge line and the eighth bridge line; In the first pixel circuit, the first light-emitting control module is connected to the driving transistor via the seventh bridge line, and the second light-emitting control module is connected to the driving transistor via the eighth bridge line. Along a direction perpendicular to the plane where the display panel is located, the seventh bridge line is insulated from and overlaps with the second control line, and the eighth bridge line is insulated from and overlaps with the second control line.

27. The display panel according to claim 1, characterized in that, The display panel includes a substrate, a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer; the semiconductor layer, the first metal layer, the second metal layer, and the third metal layer are disposed sequentially away from the substrate; The active layer of the driving transistor is located on the semiconductor layer, and the gate of the driving transistor is located on the first metal layer; the pixel circuit further includes a storage capacitor, one plate of the storage capacitor is located on the first metal layer, and the other plate is located on the second metal layer; the bridge line is located on the third metal layer.

28. The display panel according to claim 2, characterized in that, The light-emitting device includes a first light-emitting device and a second light-emitting device, wherein the first light-emitting device is coupled to the first pixel circuit, and the second light-emitting device is coupled to the second pixel circuit; wherein... The first light-emitting device emits green light or blue light, and the second light-emitting device emits red light.

29. The display panel according to claim 16 or 23, characterized in that, The light-emitting device includes a first light-emitting device and a second light-emitting device, wherein the first light-emitting device is coupled to the first pixel circuit, and the second light-emitting device is coupled to the second pixel circuit; wherein... The first light-emitting device emits red light, and the second light-emitting device emits green light or blue light.

30. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 29.

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