Method, device and system for taming a local clock

Abstract

The application provides a method, device and system for taming a local clock, the method is applied to an MCU; the MCU takes the local clock as a frequency source and outputs a local second pulse signal through a timer; the method comprises the following steps: receiving a satellite second pulse signal output by a GPS / Beidou receiver, determining a first frequency difference between a clock frequency output by the local clock and a satellite standard frequency; performing a preliminary cyclic adjustment on the clock frequency of the local clock according to the first frequency difference, so that the error of the adjusted clock frequency meets a preset requirement; synchronizing the local second pulse signal and the satellite second pulse signal through the timer; detecting the phase difference between the local second pulse signal and the satellite second pulse signal within a specified time, and converting to obtain a second frequency difference between the clock frequency output by the local clock and the satellite standard frequency; performing a secondary cyclic adjustment on the clock frequency of the local clock according to the second frequency difference, so that the local clock outputs a high-precision frequency, thereby taming the local clock.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method, apparatus and system for disciplining a local clock. Background Technology

[0002] The current common clock discipline scheme involves acquiring the satellite second pulse signal through a satellite receiver, and then using an FPGA or TDC (time-to-frequency converter) to quantize the second pulse signal in a local clock discipline system. Since the accuracy of the second pulse signal output by the GPS / BeiDou satellite receiver is typically ±50ns, the second pulse data quantized by the FPGA will also have a jitter error of ±50ns. This necessitates complex filtering algorithms to improve data accuracy, resulting in high costs. Summary of the Invention

[0003] The purpose of this application is to provide a method, apparatus, and system for taming a local clock. The local clock is coarsely tuned by detecting the satellite second pulse signal of a GPS / BeiDou receiver, and then finely tuned by detecting the phase difference between the satellite second pulse signal and the local second pulse signal, thereby taming the local clock to enable it to output a high-precision frequency while reducing costs.

[0004] In a first aspect, this application provides a method for disciplining a local clock, which is applied to an MCU. The MCU is connected to a GPS / BeiDou receiver and a local clock. The MCU uses the local clock as a frequency source and outputs a local second pulse signal through a timer. The method includes: receiving a satellite second pulse signal output by the GPS / BeiDou receiver; determining a first frequency difference between the clock frequency output by the local clock and the satellite standard frequency based on the satellite second pulse signal; performing a preliminary cyclic adjustment on the clock frequency of the local clock based on the detected first frequency difference to ensure that the error of the adjusted clock frequency meets a preset requirement; synchronizing the local second pulse signal with the satellite second pulse signal through a timer; detecting the phase difference between the local second pulse signal and the satellite second pulse signal within a specified time period, and converting it to obtain a second frequency difference between the clock frequency output by the local clock and the satellite standard frequency; and performing a secondary cyclic adjustment on the clock frequency of the local clock based on the converted second frequency difference to ensure that the local clock outputs a high-precision frequency.

[0005] Furthermore, the step of determining the first frequency difference between the clock frequency output by the local clock and the satellite standard frequency based on the satellite second pulse signal includes: detecting the satellite second pulse period corresponding to the satellite second pulse signal; and converting according to the satellite second pulse period to obtain the first frequency difference between the clock frequency output by the local clock and the satellite standard frequency.

[0006] Furthermore, the step of performing preliminary cyclic adjustment of the local clock frequency based on the detected first frequency difference to ensure that the error of the adjusted clock frequency meets the preset requirements includes: obtaining the current first frequency difference detected at the current moment; adjusting the local clock frequency based on the current first frequency difference; determining whether the difference between the adjusted clock frequency and the satellite standard frequency is less than a first preset threshold; if not, continuing to execute the step of obtaining the current first frequency difference detected at the current moment; if yes, determining that the error of the adjusted clock frequency meets the preset requirements.

[0007] Furthermore, the step of adjusting the clock frequency of the local clock based on the current first frequency difference includes: determining a first frequency calibration voltage based on the current first frequency difference; adjusting the voltage value output by the built-in DAC to the local clock based on the first frequency calibration voltage, thereby adjusting the clock frequency of the local clock.

[0008] Furthermore, the step of determining the first frequency calibration voltage based on the current first frequency difference includes: calculating the first frequency calibration voltage ΔU according to the following formula:

[0009] △U=△f / VF;

[0010] Where △f represents the current first frequency difference between the clock frequency output by the local clock and the satellite standard frequency; VF represents the frequency-voltage controlled voltage of the local clock.

[0011] Furthermore, the above-mentioned step of synchronizing the local second pulse signal with the satellite second pulse signal via a timer includes: entering an interrupt when the rising edge of the satellite second pulse signal is detected; adjusting the timer count value in the interrupt handling so that the local second pulse signal output by the timer is synchronized with the satellite second pulse signal.

[0012] Furthermore, the step of performing a second-cycle adjustment of the local clock frequency based on the converted second frequency difference to enable the local clock to output a high-precision frequency includes: obtaining the current second frequency difference obtained based on the phase difference between the local second pulse signal and the satellite second pulse signal, and performing the following adjustment steps: determining a second frequency calibration voltage based on the current second frequency difference; adjusting the voltage value output by the built-in DAC to the local clock based on the second frequency calibration voltage, thereby adjusting the local clock frequency; determining whether the phase difference between the local second pulse and the satellite second pulse is less than a second preset threshold; if yes, outputting the adjusted clock frequency through the local clock; if no, continuing to synchronize the local second pulse signal with the satellite second pulse signal through a timer, and detecting the second frequency difference and adjustment steps again.

[0013] Secondly, this application also provides a local clock discipline device, which is applied to an MCU; the MCU is connected to a GPS / BeiDou receiver and a local clock respectively; the MCU uses the local clock as a frequency source and outputs a local second pulse signal through a timer; the device includes: a first detection module, used to receive the satellite second pulse signal output by the GPS / BeiDou receiver, and determine a first frequency difference between the clock frequency output by the local clock and the satellite standard frequency based on the satellite second pulse signal; a first adjustment module, used to perform preliminary cyclic adjustment of the clock frequency of the local clock according to the detected first frequency difference, so that the error of the adjusted clock frequency meets a preset requirement; a synchronization module, used to synchronize the local second pulse signal with the satellite second pulse signal through a timer; a second detection module, used to detect the phase difference between the local second pulse signal and the satellite second pulse signal within a specified time, and convert it to obtain a second frequency difference between the clock frequency output by the local clock and the satellite standard frequency; and a second adjustment module, used to perform secondary cyclic adjustment of the clock frequency of the local clock according to the converted second frequency difference, so that the local clock outputs a high-precision frequency.

[0014] Thirdly, this application also provides a local clock discipline system, the system including an MCU, a GPS / BeiDou receiver, and a local clock; the MCU is connected to the GPS / BeiDou receiver and the local clock respectively; the MCU uses the local clock as a frequency source to output a local second pulse signal through a timer; the MCU is used to execute the local clock discipline method as described in the first aspect.

[0015] Fourthly, this application also provides a computer-readable storage medium storing computer-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the method described in the first aspect above.

[0016] The local clock discipline method, apparatus, and system provided in this application are applied to an MCU. The MCU is connected to a GPS / BeiDou receiver and a local clock. The MCU uses the local clock as a frequency source and outputs a local second pulse signal through a timer. The method includes: receiving the satellite second pulse signal output by the GPS / BeiDou receiver; determining a first frequency difference between the clock frequency output by the local clock and the satellite standard frequency based on the satellite second pulse signal; performing a preliminary cyclic adjustment on the clock frequency of the local clock based on the detected first frequency difference to ensure that the error of the adjusted clock frequency meets a preset requirement; synchronizing the local second pulse signal with the satellite second pulse signal through a timer; detecting the phase difference between the local second pulse signal and the satellite second pulse signal within a specified time period, and converting it to obtain a second frequency difference between the clock frequency output by the local clock and the satellite standard frequency; and performing a secondary cyclic adjustment on the clock frequency of the local clock based on the converted second frequency difference to ensure that the local clock outputs a high-precision frequency. This application performs coarse frequency adjustment of the local clock by detecting the satellite second pulse signal of the GPS / BeiDou receiver, and then performs fine frequency adjustment of the local clock by detecting the phase difference between the satellite second pulse signal and the local second pulse signal, thereby taming the local clock so that the local clock outputs a high-precision frequency while reducing costs. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a local clock discipline system in the prior art;

[0019] Figure 2 A schematic diagram of clock jitter provided for an embodiment of this application;

[0020] Figure 3 A flowchart illustrating a local clock discipline method provided in this application embodiment;

[0021] Figure 4 A schematic diagram of a local clock discipline system provided in an embodiment of this application;

[0022] Figure 5 A schematic diagram illustrating a local clock discipline process provided in an embodiment of this application;

[0023] Figure 6 This is a structural block diagram of a local clock discipline device provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions of this application will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] With the development of the times, traditional industries such as power and finance, as well as emerging industries such as 5G base station construction and urban rail transit, have all shown a huge demand for clock synchronization. Currently, the main clock synchronization solutions are NTP network clock synchronization and synchronization using 1pps-second pulse signals based on GPS / BeiDou satellites. NTP network clock synchronization typically has millisecond-level accuracy due to varying network latency, while synchronization using 1pps-second pulse signals based on GPS / BeiDou satellites has nanosecond-level accuracy.

[0026] The local OCXO (Oven-Oven Crystal Oscillator) or rubidium clock input frequency is tamped to match the satellite's built-in clock frequency by using a 1pps second pulse output from a GPS / BeiDou satellite receiver. Because the local clock also has high stability, it can maintain consistency with the satellite's standard second signal for a period of time (typically ±1µs for 24 hours) even after the satellite signal is lost. This solution has been widely used in the field of clock synchronization due to its excellent performance.

[0027] See Figure 1 As shown, the currently common clock discipline scheme involves acquiring the satellite second pulse signal through a satellite receiver, and then using an FPGA or TDC (time-to-frequency converter) to quantize the second pulse signal in the local clock discipline system. Since the accuracy of the second pulse signal output by the GPS / BeiDou satellite receiver is typically ±50ns, ... Figure 2 As shown, the second pulse data quantized by the FPGA will also have a jitter error of ±50ns, which requires complex filtering algorithms to improve the data accuracy. Then, the quantized second pulse data is converted into a local clock frequency difference signal, and the local clock output frequency accuracy is adjusted by a DAC.

[0028] To address the high cost of the aforementioned methods, this application provides a local clock taming method, apparatus, and system. This method coarsely adjusts the local clock frequency by detecting the satellite second pulse signal from a GPS / BeiDou receiver, and then finely adjusts the local clock frequency by detecting the phase difference between the satellite second pulse signal and the local second pulse signal. This tames the local clock, enabling it to output a high-precision frequency while reducing costs.

[0029] To facilitate understanding of this embodiment, a method for taming a local clock disclosed in this application will first be described in detail.

[0030] Figure 3 A flowchart illustrating a method for disciplining a local clock, as provided in this application embodiment, is shown. This method is applied to an MCU; the MCU is connected to a GPS / BeiDou receiver and a local clock, respectively. Figure 4 As shown, the MCU uses its local clock as a frequency source to output a local second pulse signal through a timer. For example, the MCU counts at a local clock frequency of 10MHz; when the count reaches 10,000,000, it outputs a local second pulse signal. When the local clock frequency is inaccurate, the period of the local second pulse signal will differ from that of the satellite second pulse signal. Therefore, the MCU will acquire the satellite second pulse signal to calibrate the local clock frequency and synchronize the local second pulse signal, ensuring that the local clock frequency of 10MHz is consistent with the satellite's internal 10MHz standard frequency, and that the rising edge of the local second pulse signal is consistent with that of the satellite second pulse signal. The specific implementation process is as follows... Figure 1 As shown, the method specifically includes the following steps:

[0031] Step S302: Receive the satellite second pulse signal output by the GPS / BeiDou receiver, and determine the first frequency difference between the clock frequency output by the local clock and the satellite standard frequency based on the satellite second pulse signal;

[0032] The process of determining the first frequency difference between the local clock output frequency and the satellite standard frequency using the satellite second pulse signal is essentially a process of detecting the period of the satellite second pulse signal and then performing data conversion. Because the satellite second pulse signal experiences jitter during propagation between the satellite and the satellite signal receiver, the period of the satellite second pulse signal received by the MCU is not the standard 1 second. Directly converting this to the local clock output frequency results in a significant error compared to the standard 10MHz frequency. Therefore, period detection of the satellite second pulse signal can only be used for coarse adjustment of the local clock output frequency.

[0033] Step S304: Perform preliminary cyclic adjustment of the local clock frequency based on the detected first frequency difference, so that the error of the adjusted clock frequency meets the preset requirements.

[0034] In practice, the frequency calibration voltage corresponding to the DAC can be determined based on the first frequency difference to further control the output voltage of the DAC, thereby adjusting the clock frequency of the local clock. The above adjustment process is repeated until the clock frequency error meets the preset requirements, such as the difference between the clock frequency and the standard frequency of the satellite being less than a preset threshold.

[0035] Step S306: Synchronize the local second pulse signal with the satellite second pulse signal using a timer;

[0036] Synchronization is to ensure that the rising edge phase of the local second pulse signal is consistent with that of the satellite second pulse signal, so that the data obtained by the user using the local second pulse signal is at the same moment as the data obtained based on the satellite second pulse signal.

[0037] In practice, synchronization can be achieved in the following way: Utilize the interrupt function of the MCU, enter the interrupt after detecting the rising edge of the second pulse, and adjust the count value of the MCU's internal timer TIMR in the interrupt handling so that the local second pulse signal output by TIMR is in phase with the rising edge of the satellite second pulse signal.

[0038] Step S308: Detect the phase difference between the local second pulse signal and the satellite second pulse signal within a specified time period, and convert it to obtain the second frequency difference between the clock frequency output by the local clock and the satellite standard frequency.

[0039] In a preferred embodiment, the specified time can be set to 100-500 seconds.

[0040] Step S310: The clock frequency of the local clock is adjusted twice in a loop according to the second frequency difference obtained by conversion, so that the local clock outputs a high-precision frequency.

[0041] The adjustment principle here is the same as the principle of the preliminary adjustment mentioned above. The frequency calibration voltage corresponding to the DAC can also be determined based on the second frequency difference to further control the output voltage of the DAC, thereby adjusting the clock frequency of the local clock. The above adjustment process is repeated until the phase difference between the local second pulse signal and the satellite second pulse signal is less than the preset threshold.

[0042] The local clock taming method provided in this application embodiment performs coarse frequency adjustment of the local clock by detecting the satellite second pulse signal of the GPS / BeiDou receiver, and then performs fine frequency adjustment of the local clock by detecting the phase difference between the satellite second pulse signal and the local second pulse signal, thereby taming the local clock so that the local clock outputs a high-precision frequency while reducing costs.

[0043] This application also provides another method for disciplining a local clock, which is implemented based on the above embodiments; this embodiment focuses on describing the frequency modulation process.

[0044] The steps described above for determining the first frequency difference between the local clock output frequency and the satellite standard frequency based on the satellite second pulse signal include: detecting the satellite second pulse period corresponding to the satellite second pulse signal; and converting the satellite second pulse period to obtain the first frequency difference between the local clock output frequency and the satellite standard frequency.

[0045] Assuming the local clock frequency minus the voltage-controlled voltage VF = 1Hz / V, the standard frequency f0 = 10,000,000Hz, and the period C = 1 / f0 = 100ns, neglecting satellite second pulse jitter error, the sampling count value for one cycle is: 1 / C = f0 = 10,000,000 times. Assuming the current MCU collects 9,999,999 counts of the satellite second pulse over one cycle, and given the current local clock frequency f1 = 9,999,999, the first frequency difference between the local clock output frequency and the satellite standard frequency is: Δf = 10,000,000 - 9,999,999 = 1Hz.

[0046] Furthermore, the step of performing preliminary cyclic adjustment of the local clock frequency based on the detected first frequency difference to ensure that the error of the adjusted clock frequency meets the preset requirements includes:

[0047] (1) Obtain the current first frequency difference detected at the current moment;

[0048] (2) Adjust the clock frequency of the local clock according to the current first frequency difference;

[0049] In practice, the first frequency calibration voltage is first determined based on the current first frequency difference; for example, the first frequency calibration voltage ΔU is calculated according to the following formula:

[0050] △U=△f / VF;

[0051] Where △f represents the current first frequency difference between the clock frequency output by the local clock and the satellite standard frequency; VF represents the frequency-voltage controlled voltage of the local clock.

[0052] Assuming the local clock frequency - voltage-controlled voltage VF = 1Hz / V, the standard frequency f0 = 10000000Hz, the period C = 1 / f0 = 100ns, and without considering satellite second pulse jitter error, the sampling count value for one period is: 1 / C = f0 = 10000000 times.

[0053] Assume that the current MCU collects the count value of the satellite's second pulse cycle 9,999,999 times, and knows that the current local clock frequency f1 = 9,999,999, and the difference between it and the satellite standard frequency is Δf = 10,000,000 - 9,999,999 = 1Hz; the frequency calibration voltage ΔU = Δf / VF = 1Hz / (1Hz / V) = 1V.

[0054] Then, based on the first frequency calibration voltage, the voltage value output by the built-in DAC to the local clock is adjusted, thereby adjusting the clock frequency of the local clock.

[0055] If the frequency calibration voltage ΔU = 1V, increase the output voltage of the DAC by 1V.

[0056] (3) Determine whether the difference between the adjusted clock frequency and the satellite standard frequency is less than the first preset threshold;

[0057] (4) If not, continue to execute the step of obtaining the current first frequency difference detected at the current time; if yes, determine that the error of the adjusted clock frequency meets the preset requirements.

[0058] Furthermore, the above-mentioned step of synchronizing the local second pulse signal with the satellite second pulse signal using a timer includes:

[0059] An interrupt is triggered when the rising edge of the satellite second pulse signal is detected. The timer count value is adjusted in the interrupt handler to synchronize the local second pulse signal output by the timer with the satellite second pulse signal.

[0060] That is, by utilizing the interrupt function of the MCU, an interrupt is entered after the rising edge of the second pulse is detected. In the interrupt handling, the count value of the internal timer TIMR is adjusted so that the local second pulse signal output by TIMR is in phase with the rising edge of the satellite second pulse signal.

[0061] Furthermore, the step of performing a second-cycle adjustment of the local clock frequency based on the converted second frequency difference to enable the local clock to output a high-precision frequency includes:

[0062] (1) Obtain the current second frequency difference value based on the phase difference conversion between the local second pulse signal and the satellite second pulse signal, and perform the following adjustment steps:

[0063] (2) Determine the second frequency calibration voltage based on the current second frequency difference;

[0064] (3) Adjust the voltage value output by the built-in DAC to the local clock according to the second frequency calibration voltage, and adjust the clock frequency of the local clock.

[0065] (4) Determine whether the phase difference between the local second pulse and the satellite second pulse is less than the second preset threshold;

[0066] (5) If yes, output the adjusted clock frequency through the local clock; if no, continue to synchronize the local second pulse signal with the satellite second pulse signal through the timer, and check the second frequency difference and adjustment steps again.

[0067] In this embodiment, a lower-cost MCU (microprocessor) solution is used to acquire the second pulse signal. After synchronizing the local second pulse signal with the satellite second pulse signal, the phase difference between the satellite second pulse signal from the GPS / BeiDou satellite receiver and the local second pulse signal is acquired at a set time interval. The clock frequency is adjusted based on this phase difference. Assuming a time interval of 10 seconds, since there is no error accumulation in the satellite second pulse signal output by the GPS / BeiDou satellite receiver, the error of the satellite pulse signal over a 10-second time interval is still ±50nS. After quantization, the average error of each satellite second pulse signal is 5nS, effectively reducing the impact of GPS / BeiDou satellite receiver second pulse signal jitter error on the accuracy of the acquired data.

[0068] See Figure 5 As shown, this embodiment provides a method for disciplining a local clock based on the cumulative phase difference between the second pulse of a GPS / BeiDou satellite receiver and a local second pulse. The method includes: outputting a local second pulse signal using an MCU (microprocessor); synchronizing the local second pulse signal with the satellite second pulse output by the GPS / BeiDou satellite receiver; detecting the cumulative phase difference between the local second pulse signal and the satellite second pulse signal output by the GPS / BeiDou satellite receiver per unit time; and calibrating the local clock frequency using the cumulative phase difference. This scheme can significantly improve the accuracy of the acquired data and enhance the frequency accuracy of disciplining the local clock.

[0069] Preferably, the local clock is tamed by collecting and processing the cumulative phase difference between the GPS / BeiDou satellite receiver's second pulse and the local second pulse within a unit time into a frequency calibration voltage for the local clock.

[0070] For example, the phase difference detected in a 100-second time interval is ΔT = 10ns, the average phase difference per second is ΔT' = ΔT / 100 = 0.1ns, the frequency difference is calculated as Δf = (0.1 × 1E-9) * 10E6 = 0.001Hz, and then calculated using the frequency-voltage control voltage VF = 1Hz / V: ΔU = Δf / VF = 0.001Hz / (1Hz / V) = 0.001V = 1mV.

[0071] The local clock taming method provided in this application involves rapidly adjusting the accuracy of the local clock by collecting the phase difference between the satellite second pulse signal and the local second pulse signal within an interval; synchronization between the local second pulse and the GPS / BeiDou satellite receiver's second pulse edge is triggered by the rising edge of the GPS / BeiDou satellite receiver's second pulse; a frequency calibration voltage is determined based on the phase difference between the GPS / BeiDou satellite receiver's second pulse and the local second pulse within a unit interval; the impact of GPS / BeiDou satellite receiver's second pulse jitter on data is reduced by averaging the accumulated phase difference; and the local clock is tamed and costs are reduced by processing the accumulated phase difference into a DAC-based frequency calibration voltage for the local clock.

[0072] Based on the above method embodiments, this application also provides a local clock discipline device, which is applied to an MCU; the MCU is connected to a GPS / BeiDou receiver and a local clock respectively; the MCU uses the local clock as a frequency source to output a local second pulse signal through a timer; see also Figure 6 As shown, the device includes: a first detection module 602, used to receive satellite second pulse signals output by a GPS / BeiDou receiver, and determine a first frequency difference between the clock frequency output by the local clock and the satellite standard frequency based on the satellite second pulse signals; a first adjustment module 604, used to perform preliminary cyclic adjustment of the clock frequency of the local clock according to the detected first frequency difference, so that the error of the adjusted clock frequency meets a preset requirement; a synchronization module 606, used to synchronize the local second pulse signal with the satellite second pulse signal through a timer; a second detection module 608, used to detect the phase difference between the local second pulse signal and the satellite second pulse signal within a specified time, and convert it to obtain a second frequency difference between the clock frequency output by the local clock and the satellite standard frequency; and a second adjustment module 610, used to perform secondary cyclic adjustment of the clock frequency of the local clock according to the converted second frequency difference, so that the local clock outputs a high-precision frequency.

[0073] Furthermore, the aforementioned first detection module 602 is used to detect the satellite second pulse period corresponding to the satellite second pulse signal; and to convert the satellite second pulse period to obtain the first frequency difference between the clock frequency output by the local clock and the satellite standard frequency.

[0074] Furthermore, the aforementioned first adjustment module 604 is used to obtain the current first frequency difference detected at the current moment; adjust the clock frequency of the local clock according to the current first frequency difference; determine whether the difference between the adjusted clock frequency and the satellite standard frequency is less than a first preset threshold; if not, continue to execute the step of obtaining the current first frequency difference detected at the current moment; if yes, determine that the error of the adjusted clock frequency meets the preset requirements.

[0075] Furthermore, the aforementioned first adjustment module 604 is used to determine a first frequency calibration voltage based on the current first frequency difference; adjust the voltage value output by the built-in DAC to the local clock based on the first frequency calibration voltage, and adjust the clock frequency of the local clock.

[0076] Furthermore, the aforementioned first adjustment module 604 is used to calculate the first frequency calibration voltage ΔU according to the following formula:

[0077] △U=△f / VF;

[0078] Where △f represents the current first frequency difference between the clock frequency output by the local clock and the satellite standard frequency; VF represents the frequency-voltage controlled voltage of the local clock.

[0079] Furthermore, the aforementioned synchronization module 606 is used to enter an interrupt when the rising edge of the satellite second pulse signal is detected; in the interrupt handling, the count value of the timer is adjusted so that the local second pulse signal output by the timer is synchronized with the satellite second pulse signal.

[0080] Further, the aforementioned second adjustment module 610 is used to obtain the current second frequency difference value obtained by converting the phase difference between the local second pulse signal and the satellite second pulse signal, and to perform the following adjustment steps: determine the second frequency calibration voltage according to the current second frequency difference value; adjust the voltage value output by the built-in DAC to the local clock according to the second frequency calibration voltage, and adjust the clock frequency of the local clock; determine whether the phase difference between the local second pulse and the satellite second pulse is less than a second preset threshold; if yes, output the adjusted clock frequency through the local clock; if no, continue to synchronize the local second pulse signal with the satellite second pulse signal through a timer, and detect the second frequency difference value and the adjustment steps again.

[0081] The device provided in this application embodiment has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts of the device embodiment not mentioned can be referred to the corresponding content in the aforementioned method embodiment.

[0082] Based on the above method embodiments, this application also provides a local clock discipline system, see [link to relevant documentation]. Figure 4 As shown, the system includes an MCU, a GPS / BeiDou receiver, and a local clock; the MCU is connected to the GPS / BeiDou receiver and the local clock respectively; the MCU uses the local clock as a frequency source to output a local second pulse signal through a timer; the MCU is used to execute the local clock taming method as described in the aforementioned method embodiments.

[0083] The system provided in this application embodiment has the same implementation principle and technical effects as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the system embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0084] This application also provides a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the above-described method. For specific implementation details, please refer to the foregoing method embodiments, which will not be repeated here.

[0085] The computer program products of the methods, apparatus, and electronic devices provided in the embodiments of this application include a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementations, please refer to the method embodiments, which will not be repeated here.

[0086] Unless otherwise specifically stated, the relative steps, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application.

[0087] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0088] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0089] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the technical scope disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A method for taming a local clock, characterized in that, The method is applied to an MCU; the MCU is connected to a GPS / BeiDou receiver and a local clock; the MCU uses the local clock as a frequency source to output a local second pulse signal through a timer; the method includes: Receive the satellite second pulse signal output by the GPS / BeiDou receiver, and determine the first frequency difference between the clock frequency output by the local clock and the satellite standard frequency based on the satellite second pulse signal; The clock frequency of the local clock is initially cyclically adjusted based on the detected first frequency difference so that the error of the adjusted clock frequency meets the preset requirements. The local second pulse signal is synchronized with the satellite second pulse signal using the timer. Within a specified time period, the phase difference between the local second pulse signal and the satellite second pulse signal is detected, and after conversion, a second frequency difference value is obtained between the clock frequency output by the local clock and the standard frequency of the satellite. The clock frequency of the local clock is adjusted twice in a loop based on the second frequency difference obtained from the conversion, so that the local clock outputs a high-precision frequency.

2. The method according to claim 1, characterized in that, The step of determining the first frequency difference between the clock frequency output by the local clock and the satellite standard frequency based on the satellite second pulse signal includes: Detect the satellite second pulse period corresponding to the satellite second pulse signal; The first frequency difference between the clock frequency output by the local clock and the standard frequency of the satellite is obtained by converting the clock frequency based on the satellite's second pulse period.

3. The method according to claim 1, characterized in that, The steps of performing preliminary cyclic adjustment of the local clock frequency based on the detected first frequency difference, so that the error of the adjusted clock frequency meets the preset requirements, include: Obtain the current first frequency difference detected at the current moment; Adjust the clock frequency of the local clock according to the current first frequency difference; Determine whether the difference between the adjusted clock frequency and the satellite standard frequency is less than a first preset threshold; If not, continue with the step of obtaining the current first frequency difference detected at the current moment; If so, confirm that the error of the adjusted clock frequency meets the preset requirements.

4. The method according to claim 3, characterized in that, The step of adjusting the clock frequency of the local clock based on the current first frequency difference includes: The first frequency calibration voltage is determined based on the current first frequency difference. The built-in DAC outputs a voltage value to the local clock based on the first frequency calibration voltage, thereby adjusting the clock frequency of the local clock.

5. The method according to claim 4, characterized in that, The step of determining the first frequency calibration voltage based on the current first frequency difference includes: Calculate the first frequency calibration voltage ΔU using the following formula: △U = △f / VF; Wherein, △f represents the current first frequency difference between the clock frequency output by the local clock and the satellite standard frequency; VF represents the frequency-voltage controlled voltage of the local clock.

6. The method according to claim 1, characterized in that, The step of synchronizing the local second pulse signal with the satellite second pulse signal using the timer includes: An interrupt is initiated upon detection of the rising edge of the satellite's second pulse signal; In the interrupt handling, the count value of the timer is adjusted so that the local second pulse signal output by the timer is synchronized with the satellite second pulse signal.

7. The method according to claim 3, characterized in that, The step of performing a second-cycle adjustment of the local clock frequency based on the converted second frequency difference to enable the local clock to output a high-precision frequency includes: Obtain the current second frequency difference value obtained by converting the phase difference between the local second pulse signal and the satellite second pulse signal, and perform the following adjustment steps: Based on the current second frequency difference, a second frequency calibration voltage is determined; based on the second frequency calibration voltage, the voltage value output by the built-in DAC to the local clock is adjusted, thereby adjusting the clock frequency of the local clock; Determine whether the phase difference between the local second pulse and the satellite second pulse is less than a second preset threshold; If so, the adjusted clock frequency is output via the local clock; If not, continue with the process of synchronizing the local second pulse signal with the satellite second pulse signal using the timer, and then checking the second frequency difference and adjusting the steps again.

8. A device for taming a local clock, characterized in that, The device is applied to an MCU; the MCU is connected to a GPS / BeiDou receiver and a local clock; the MCU uses the local clock as a frequency source to output a local second pulse signal through a timer; the device includes: The first detection module is used to receive the satellite second pulse signal output by the GPS / BeiDou receiver, and based on the satellite second pulse signal, determine the first frequency difference between the clock frequency output by the local clock and the satellite standard frequency; The first adjustment module is used to perform preliminary cyclic adjustment of the clock frequency of the local clock based on the detected first frequency difference, so that the error of the adjusted clock frequency meets the preset requirements. The synchronization module is used to synchronize the local second pulse signal with the satellite second pulse signal through the timer; The second detection module is used to detect the phase difference between the local second pulse signal and the satellite second pulse signal within a specified time, and after conversion, obtain the second frequency difference between the clock frequency output by the local clock and the standard frequency of the satellite. The second adjustment module is used to perform a second cyclic adjustment on the clock frequency of the local clock based on the converted second frequency difference, so that the local clock outputs a high-precision frequency.

9. A local clock taming system, characterized in that, The system includes an MCU, a GPS / BeiDou receiver, and a local clock; the MCU is connected to the GPS / BeiDou receiver and the local clock respectively; the MCU uses the local clock as a frequency source to output a local second pulse signal through a timer; the MCU is used to execute the local clock taming method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions that, when invoked and executed by a processor, cause the processor to implement the method for disciplining a local clock as described in any one of claims 1 to 7.

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