Convolutional neural network computing acceleration circuit structure after hybrid-granularity pruning

Abstract

A kind of computing acceleration circuit structure for fine-grained pruning and compressed convolutional neural network model, it includes: input data distribution unit, computing unit, pooling unit, fully connected unit and bus controller, the present application deeply participates in each cycle in convolution calculation, can participate in optimization from the bottom logic of calculation in multiple angles, cooperate with pruning method, compression index, improve the compression rate of neural network model, reduce the transmission and access amount of data, reduce the demand of storage space, reduce total computing time, the efficiency and accuracy of hardware calculation are guaranteed.

Description

Technical Field

[0001] This invention belongs to the field of sparse neural network acceleration, specifically a computation acceleration circuit structure for sparse neural networks after mixed-granularity pruning. Background Technology

[0002] Thanks to their excellent feature extraction capabilities, convolutional neural networks (CNNs) have been widely used in image recognition, speech processing, and other fields in recent years. The number of model parameters has also increased significantly with the addition of functionality and improved accuracy. However, hardware accelerators responsible for network inference face numerous limitations in resources and computing power. Therefore, it is necessary to identify the sparse components in the network model, compress the network, and simultaneously accelerate computation within the compressed network. Existing compression and computation acceleration methods can be broadly categorized into two types: one involves directly inputting unprocessed data, with the hardware identifying the sparse components and planning a new computational data flow; the other involves pre-compressing the data and generating a compressed index, then adding a data decompression circuit in the hardware to retrieve the original data based on the index and perform computation according to the normal data flow. However, the first type of method involves highly complex convolutional kernel zero-value lookup circuits, multiplier input rearrangement circuits, and timing control logic. The second type of method delegates compression to a host computer, typically using methods such as sparse column compression to generate a compressed index. This type of method can effectively improve the model compression ratio, but it has additional compression coding for each convolution kernel. The number and length of the coding depend on the sparsity. The transmission time and decompression time of the neural network model compression coding need to be considered during the calculation. Summary of the Invention

[0003] This invention addresses the shortcomings of existing technologies, such as the lack of support for mixed-granularity model pruning and acceleration, the inability of existing neural network hardware accelerators to efficiently support fine-grained model computation, and the high data storage and transmission requirements of existing technologies. It proposes a circuit structure for accelerating convolutional neural network computation after mixed-granularity pruning. This structure deeply participates in each loop of the convolution computation, optimizing from multiple angles at the underlying computational logic level. Combined with pruning methods and compressed indexes, it improves the compression ratio of the neural network model, reduces data transmission and access volume, lowers storage space requirements, and reduces total computation time, ensuring both hardware computation efficiency and accuracy.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a circuit structure for accelerating computation in convolutional neural networks after mixed-granularity pruning, comprising: an input data allocation unit, a computation unit, a pooling unit, a fully connected unit, and a bus controller. The bus controller receives instruction streams, input feature maps, and model weights from a host computer via an AXI bus, parses the instruction streams, and outputs the input feature maps and model weights to the data allocation unit. The bus controller also receives the computed output feature maps from the pooling unit or the fully connected unit and outputs them to off-chip memory via the AXI bus. The input data allocation unit, based on the commands obtained from parsing the instruction streams by the bus controller, allocates... The input feature map, model weights, and compressed index are stored in the input feature map buffer, model weight buffer, and compressed index buffer, respectively. They are rearranged by the corresponding rearrangement unit and then input into the computation unit. The computation unit performs parallel multiplication-addition calculations based on the rearranged data and the instructions of the compressed index decoded by the input data allocation unit to obtain the convolution calculation result. The pooling unit determines whether to perform max pooling or average pooling operations on the output feature map based on the commands obtained by the bus controller parsing the instruction stream. The fully connected unit determines whether to perform a fully connected operation on the output feature map based on the commands obtained by the bus controller parsing the instruction stream.

[0006] The input data allocation unit includes: an input feature map buffer, a model weight buffer, a compressed index buffer, an input feature map rearrangement unit, a model weight rearrangement unit, and a compressed index decoding unit. The input feature map buffer, model weight buffer, and compressed index buffer are used to buffer the input feature map, model weights, and compressed index, respectively. The input feature map rearrangement unit and the model weight rearrangement unit, based on information such as the resolution of the current network layer obtained from the bus controller, expand the input feature map and model weights into a single-row format and output them to the computation unit. The compressed index decoding unit decodes the control signal used to accelerate the convolution operation after mixed-granularity channel pruning / column pruning according to the encoding method of the compressed index.

[0007] The computational unit includes: a dot product result reconnection module, a row vector part, and an accumulation control module. The dot product result reconnection module performs parallel computation using two computational arrays based on the rearranged feature map and weights of the input data allocation unit to obtain the dot product result. Then, it outputs the result to the row vector part and the accumulation control module according to the relative position in the pruned convolution kernel. At the same time, it performs zero-padding on the parts that exceed the edge of the feature map. The row vector part and the accumulation control module count the number of accumulations of the row vector part sums and outputs the accumulated convolution kernel part sum to the subsequent unit when the number of accumulations equals the number indicated in the index.

[0008] Technical effect

[0009] This invention flexibly distributes the dot product results produced by the computation array through a dot product result reconnection technique, skipping the invalid calculation of redundant weights in the convolution kernel. The number of accumulations of the reconnected dot product results is controlled by the row vector portion and accumulation to match the number of vectors pruned by the convolution kernel. Compared with existing technologies, this invention can optimize the computational data flow of the model after column vector pruning. At the same time, the special compressed index it relies on has high data reusability, avoiding the cumbersome read and decode operations of traditional compressed indexes and not introducing significant additional overhead to the overall accelerator time. Attached Figure Description

[0010] Figure 1 This is a flowchart of the present invention;

[0011] Figure 2 A schematic diagram of the four computational loops unfolding the convolution operation in a neural network model;

[0012] Figure 3 A schematic diagram of fine-grained column pruning in mixed-grained pruning;

[0013] Figure 4 This is a schematic diagram of the system of the present invention;

[0014] Figure 5 This is a schematic diagram of the compressed index decoding unit;

[0015] Figure 6 A schematic diagram of the module reconnection for the dot product result;

[0016] Figure 7 This is a schematic diagram of the row vector section and the accumulation control module;

[0017] Figure 8 This is a schematic diagram illustrating the acceleration of the model after mixed-size pruning according to the present invention. Detailed Implementation

[0018] like Figure 1 As shown in this embodiment, a method for accelerating the computation of a convolutional neural network after mixed-granularity pruning is proposed. The method includes: a host computer pruning the convolutional neural network model to obtain a compressed model, generating an instruction stream and a compressed index, and then outputting them to a bus controller located at the terminal via an AXI bus; the bus controller loading the control instruction stream, reading the input feature map, model weights, and compressed index, caching them in corresponding buffers, and rearranging the input feature map and model weights before computation and decoding the compressed index; the computation unit performing convolution operations on the rearranged input feature map and model weights to obtain a dot product result, and controlling the selection and accumulation number of the dot product result based on the signal obtained from the compressed index decoding to obtain the final convolution result; after pooling and / or fully connected processing, the output feature map is written back to off-chip memory via the bus controller.

[0019] like Figure 2 As shown, the convolution operations in the convolutional layers of the computation unit, pooling unit, and fully connected unit all include four nested loops: the fourth loop (LOOP4) iterates through all output channels; the third loop (LOOP3) iterates through each pixel of the input feature map; the second loop (LOOP2) iterates through all input channels; and the first loop (LOOP1) iterates through all convolutional kernels. As shown in the figure, N if N represents the input channel. of Represents the output channel, and the size of the convolution kernel is N. kx Multiply by N ky The size of the input feature map is N. ix Multiply by N iy The size of the output feature map is N. ox Multiply by N oy The convolution kernel performs a horizontal convolution operation with the input feature map and generates a corresponding output feature map, which can be summarized as the four loops shown in the figure.

[0020] like Figure 3 As shown, the hybrid granularity pruning refers to the pruning of redundant parameters in the vector scale of the convolution kernel based on channel pruning, i.e., column pruning. Specifically, it involves recording and sorting the L1 norm of the column vectors of each convolution kernel, and, according to the pruning rate setting, performing the following operations on each column vector in the convolution kernel: no pruning, pruning the rightmost column, pruning the middle column, pruning the leftmost column, pruning the middle and rightmost columns, pruning the leftmost and rightmost columns, and pruning the middle and leftmost columns. Since the position and number of columns that can be pruned vary for different convolution kernels, the pruning granularity is significantly finer than channel pruning, thus constituting hybrid granularity pruning together with channel pruning.

[0021] The compressed index, comprising a sequence portion and a core portion, specifically: {Index feeder Index kernel}, where: the sequence part Index feeder Includes: the second cycle calculation period T loop2 The core components include the convolution kernel dimension and P. channel The first cycle calculation period T loop1 The relative position index P of the effective column vector row .

[0022] The sequence portion Index feederThis is used to control the behavior of the input data allocation unit. Because the mixed-granularity pruning of the convolutional kernel affects not only the behavior of the computation unit but also the behavior of the input data allocation unit. The input feature map data required for computation needs to be read in advance via the AXI bus and stored in the input feature map buffer, and in each second loop, the input channels, i.e., n... if Each iteration requires pre-fetching the feature map of the next input channel. For an unpruned convolutional kernel, the second loop computation period T... loop2 =N of ×N ky ×N kx That is, the total number of output channels of the current convolutional layer × kernel length × kernel width; after the convolutional kernels undergo mixed-granularity pruning, the kernel widths of the convolutional kernels corresponding to different channels will be different, causing the iteration interval of the input channels in the second loop to change from a fixed value of N. of ×N ky ×N kx Transform into Here, different 'i's refer to different channels. This refers to the kernel length and kernel width of the i-th channel.

[0023] The core part Index kernel In the middle, the part of the convolution kernel dimension and P channel = Current output channel × Total input channels – (Total input channels – Current input channels) – 1; First loop calculation period T loop1 This refers to the number of times the convolution kernel corresponding to the current channel actually needs to accumulate column vectors, with a value ranging from 1 to 3; the relative position index P of the effective column vector. row This refers to the specific position of the retained column vector within the convolution kernel corresponding to the current channel. There are a total of 6 possible configurations for a convolution kernel that undergoes column vector pruning, such as... Figure 3 As shown on the right, the value range is from 1 to 6.

[0024] like Figure 4 As shown, this embodiment relates to a circuit structure for accelerating the computation of a convolutional neural network after mixed-granularity pruning, which includes: an input data allocation unit, a computation unit, a pooling unit, a fully connected unit, and a bus controller.

[0025] The input data allocation unit includes: an input feature map buffer, a model weight buffer, a compressed index buffer, an input feature map rearrangement unit, a model weight rearrangement unit, and a compressed index decoding unit.

[0026] like Figure 5As shown, the compressed index decoding unit includes: an input feature map buffer counter and an input / output channel counter, wherein: the input feature map buffer counter counts the total number of cycles that the input feature map of the current input channel has participated in the calculation in the calculation unit, and sets the input compressed index index... feeder Partial decoding involves the input feature map corresponding to each input channel participating in computation within a clock cycle T of the computation array. loop2 Then, it is compared with the count value provided by the input feature map buffer counter; the input and output channel counters count the number of channels in the array that have completed the convolution calculation, and the count is equal to the clock period T. loop2 At the same time, the compressed index decoding unit will send a control signal to the input feature map buffer to switch the channel of the current input feature map, and will also send the input compressed index to the buffer. kernel Partial decoding is performed as a partial sum of the convolution kernel dimension, the relative position index of the effective column vector, and the first loop calculation cycle. When the count value provided by the input and output channel counters is consistent with the partial sum of the convolution kernel dimension, the compressed index decoding unit will send the relative position index of the effective column vector and the first loop calculation cycle to the partial sum processing unit respectively, which is used to control the two behaviors of dot product result reconnection and row vector partial sum accumulation.

[0027] like Figure 6 As shown, the dot product result reconnection module of the computing unit outputs the dot product result from the correct computing array position to the subsequent adder. The dot product result reconnection module includes: 256 three-to-one selectors and 256 boundary judges, wherein: the three-to-one selector selects one dot product from the chip select signal from the compressed index decoding unit for output according to the chip select signal from the compressed index decoding unit; when the boundary judge determines that the current dot product is the boundary of the feature map, it replaces the dot product result with a zero value.

[0028] For convolution operations with an unpruned 3×3 convolution kernel, each 3-to-1 selector sequentially takes the corresponding dot product input from left to right, determines whether to replace zero values ​​via a boundary checker, and then outputs it to the subsequent adder. For the hybrid-granularity pruned convolution kernel used in this invention, the dot product input at each time step no longer corresponds to the relative column position of the convolution kernel. Therefore, the 3-to-1 selector is controlled by the relative position index signal of the effective column vector sent by the compressed index decoding unit, selecting the dot product at the correct position from the three input dot products and outputting it to the subsequent adder. The dot product data after reconnection according to the above method will be output to... Figure 7 The row vector section and the accumulation control module are shown.

[0029] For convolution operations with an unpruned 3×3 convolution kernel, each row requires three summations of the dot product results to obtain the row vector partial sum. However, for the hybrid-granularity pruned convolution kernel used in this invention, the actual number of summations required for the row vector partial sum is no longer fixed at 3, but varies depending on the actual pruning. In the row vector partial sum accumulation control module, the accumulator has a counter that continuously compares with the first loop calculation cycle signal from the compressed index decoding unit. When the accumulated number equals the first loop calculation cycle signal, the row vector partial sum is calculated and output to the subsequent adder, ultimately obtaining the partial sum of the convolution kernel dimension.

[0030] like Figure 8 The diagram illustrates the optimized convolution computation process: When a convolutional layer to be computed has only two output channels and one row of input feature maps, the rightmost column of the convolutional kernel corresponding to the first output channel is pruned, and the middle column of the convolutional kernel corresponding to the second output channel is pruned. The black dashed boxes in the diagram represent the input data allocation unit, the blue dashed boxes represent the two computation arrays in the computation unit, and the red dashed boxes represent the partial sum processing unit in the computation unit. After the dot product operation of the computation arrays, the dot product result is output to the partial sum processing unit. The compression index decoding unit, based on the indices corresponding to the convolution kernels under different pruning conditions, instructs the dot product result reconnection module to correctly reconnect the valid dot product result and replace zero values, and instructs the row vector dimension partial sum accumulation module to correctly accumulate the row vector dimension partial sum according to the actual number of accumulations required, and outputs it to the subsequent ReLU unit. After the dot product operation of the computation arrays, the dot product result is output to the partial sum processing unit in the hardware accelerator (marked by the red dashed box). The compressed index decoding unit will, based on the index corresponding to the convolution kernel under different pruning conditions, instruct the dot product result reconnection module to correctly reconnect the valid dot product result and replace the zero value, and instruct the row vector dimension part sum accumulation module to correctly accumulate the row vector dimension part sum according to the actual number of accumulations required, and output it to the subsequent ReLU unit.

[0031] by Figure 8 For example, by pruning the convolution kernel by 1 / 3, the convolution calculation cycle can be reduced to 2 / 3 of the original, and the acceleration effect will also increase in tandem with the increase of the pruning rate.

[0032] Through specific practical experiments, VGG16 was used as the neural network model and Cifar-10 as the dataset. This invention, relying on optimized compressed indexing and computational data flow, after incorporating the impact of reading compressed indexes, requires only 71% of the total computation time of the mixed-granularity pruning model with a column vector pruning rate of 33% compared to the model using only channel pruning; and 45% of the total computation time of the mixed-granularity pruning model with a column vector pruning rate of 66%. Meanwhile, when the column vector pruning rate is set to 55%, the accuracy of the mixed-granularity pruning model is at the same level as the model using only channel pruning, with no significant accuracy loss, but the former's model parameter count is only 45% of the latter.

[0033] Compared with existing technologies, this invention deeply participates in each loop of convolution calculation, and can participate in optimization from multiple perspectives from the underlying logic of the calculation. It can efficiently read and decode compressed indexes, and perform reconnection and acceleration operations on the partial sums generated in each step of the convolution operation, ensuring the reduction of calculation time and the correctness of calculation results. In conjunction with pruning methods and compressed indexes, it can improve the compression ratio of neural network models, reduce the amount of data transmission and access, reduce storage space requirements, and reduce the total calculation time, thus ensuring the efficiency and accuracy of hardware calculation.

[0034] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A circuit structure for accelerating computation in a convolutional neural network after mixed-granularity pruning, characterized in that, include: The system comprises an input data allocation unit, a computation unit, a pooling unit, a fully connected unit, and a bus controller. The bus controller receives instruction streams, input feature maps, and model weights from a host computer via an AXI bus. It parses the instruction streams and outputs the input feature maps and model weights to the data allocation unit. The bus controller also receives the computed output feature maps from the pooling unit or the fully connected unit and outputs them to off-chip memory via the AXI bus. The input data allocation unit, based on the commands obtained from the instruction stream parsed by the bus controller, stores the input feature maps, model weights, and compressed indexes in an input feature map buffer, a model weight buffer, and a compressed index buffer, respectively. These are then rearranged by the corresponding rearrangement units and input to the computation unit. The computation unit performs parallel multiplication-addition calculations based on the rearranged data and the compressed indexes decoded by the input data allocation unit to obtain the convolution result. The pooling unit, based on the commands obtained from the instruction stream parsed by the bus controller, determines whether to perform max pooling or average pooling operations on the output feature map. The fully connected unit, based on the commands obtained from the instruction stream parsed by the bus controller, determines whether to perform a fully connected operation on the output feature map. The compressed index includes a sequence portion and a core portion for controlling the behavior of the input data allocation unit, specifically: { }, where: sequence part Includes: the second cycle of calculation The core part includes the kernel dimension and First cycle calculation period Relative position index of valid column vectors ; The second cycle calculation period That is, all output channels of the current convolutional layer. kernel length Kernel width; after mixed-granularity pruning, the kernel width of the convolutional kernels for different channels will be different, causing the iteration interval of the input channels in the second loop to change from a fixed value. Transform into Among them: different Referring to different channels, , Refers to the first The kernel length and kernel width of each channel; The core part In the middle, the partial sum of the convolution kernel dimension =Current output channel Total input channels – (Total input channels – Current input channel) – 1; First cycle calculation period This refers to the number of times the convolution kernel corresponding to the current channel actually needs to accumulate column vectors, with a value ranging from 1 to 3; the relative position index of the effective column vector. This refers to the specific position of the column vector that is retained in the convolution kernel corresponding to the current channel. There are a total of 6 possible cases for the convolution kernel that undergoes column vector pruning.

2. The computing acceleration circuit structure according to claim 1, characterized in that, The aforementioned hybrid granularity pruning refers to the pruning of redundant parameters in the vector scale of the convolution kernel based on channel pruning, i.e., column pruning. Specifically, it involves recording and sorting the L1 norm of the column vectors of each convolution kernel, and, according to the pruning rate setting, performing the following operations on each column vector in the convolution kernel: no pruning, pruning the rightmost column, pruning the middle column, pruning the leftmost column, pruning the middle and rightmost columns, pruning the leftmost and rightmost columns, and pruning the middle and leftmost columns. Since the position and number of columns pruned are different for different convolution kernels, the pruning granularity is significantly finer than channel pruning, thus constituting hybrid granularity pruning together with channel pruning.

3. The computing acceleration circuit structure according to claim 1 or 2, characterized in that, The input data allocation unit includes: an input feature map buffer, a model weight buffer, a compressed index buffer, an input feature map rearrangement unit, a model weight rearrangement unit, and a compressed index decoding unit. The input feature map buffer, model weight buffer, and compressed index buffer are used to buffer the input feature map, model weights, and compressed index, respectively. The input feature map rearrangement unit and the model weight rearrangement unit expand the input feature map and model weights into a single-row format and output them to the computation unit based on the resolution information of the current network layer obtained from the bus controller. The compressed index decoding unit decodes the control signal used to accelerate the convolution operation after mixed-granularity channel pruning / column pruning according to the encoding method of the compressed index.

4. The computing acceleration circuit structure according to claim 1 or 2, characterized in that, The computational unit includes: a dot product result reconnection module, a row vector part, and an accumulation control module. The dot product result reconnection module performs parallel computation using two computational arrays based on the rearranged feature map and weights of the input data allocation unit to obtain the dot product result. Then, it outputs the result to the row vector part and the accumulation control module according to the relative position in the pruned convolution kernel. At the same time, it performs zero-padding on the parts that exceed the edge of the feature map. The row vector part and the accumulation control module count the number of accumulations of the row vector part sums and outputs the accumulated convolution kernel part sum to the subsequent unit when the number of accumulations equals the number indicated in the index.

5. The computing acceleration circuit structure according to claim 1 or 2, characterized in that, The convolution operations of the convolutional layers in the computation unit, pooling unit, and fully connected unit all involve four sequentially nested cyclic horizontal convolution operations with the input feature map through the convolution kernel to generate the corresponding output feature map. These include: the fourth loop LOOP4 traversing all output channels, the third loop LOOP3 traversing each pixel of the input feature map, the second loop LOOP2 traversing all input channels, and the first loop LOOP1 traversing all convolution kernels.

6. The computing acceleration circuit structure according to claim 3, characterized in that, The compressed index decoding unit includes: an input feature map buffer counter and an input / output channel counter, wherein: the input feature map buffer counter counts the total number of cycles that the input feature map of the current input channel has participated in the calculation in the calculation unit, and stores the input compressed index... Partial decoding involves the clock cycles during which the input feature map corresponding to each input channel participates in computation within the computation array. Then, it is compared with the count value provided by the input feature map buffer counter; the input and output channel counters count the number of channels in the array that have completed the convolution calculation, and when the count is equal to... At the same time, the compressed index decoding unit will send a control signal to the input feature map buffer to switch the channel of the current input feature map, and will also send the input compressed index... Partial decoding is performed as a partial sum of the convolution kernel dimension, the relative position index of the effective column vector, and the first loop calculation cycle. When the count value provided by the input and output channel counters is consistent with the partial sum of the convolution kernel dimension, the compressed index decoding unit will send the relative position index of the effective column vector and the first loop calculation cycle to the partial sum processing unit respectively, which is used to control the two behaviors of dot product result reconnection and row vector partial sum accumulation.

7. The computing acceleration circuit structure according to claim 4, characterized in that, The dot product result reconnection module outputs the dot product result from the correct computation array position to the subsequent adder. The dot product result reconnection module includes: 256 three-to-one selectors and 256 boundary judges, wherein: the three-to-one selector selects one dot product from the chip select signal from the compressed index decoding unit for output according to the chip select signal from the compressed index decoding unit; when the boundary judge determines that the current dot product is the boundary of the feature map, it replaces the dot product result with a zero value. For unpruned branches In the convolution operation of the convolution kernel, each 3-to-1 selector will take the corresponding dot product input from left to right, and the boundary judge will determine whether to replace the zero value before outputting it to the subsequent adder. For the convolution kernel after mixed granularity pruning, the dot product input at each time step is no longer related to the relative column position of the convolution kernel. Therefore, the 3-to-1 selector will be controlled by the relative position index signal of the effective column vector sent by the compressed index decoding unit, select the dot product at the correct position from the three input dot products and output it to the subsequent adder. The dot product data after reconnection will be output to the row vector part and the accumulation control module. For unpruned branches The convolution operation of the convolution kernel requires the sum of the dot product results three times for each row to obtain the partial sum of the row vector. For convolution kernels with mixed granularity pruning, the actual number of times the partial sum of the row vector needs to be accumulated is no longer fixed at 3, but varies with the actual pruning situation. In the row vector partial sum accumulation control module, the accumulator has a counter, which will continuously compare with the first cycle calculation period signal from the compressed index decoding unit. When the number of accumulated counts equals the first cycle calculation period signal, the partial sum of the row vector is calculated and will be output to the subsequent adder to finally obtain the partial sum of the convolution kernel dimension.

8. A computational acceleration circuit method based on the computational acceleration circuit structure described in any one of claims 1-7, characterized in that, include: The host computer prunes the convolutional neural network model to obtain a compressed model and generates an instruction stream and compressed index, which are then output to the bus controller located at the terminal via the AXI bus. The bus controller loads the control command stream, reads the input feature map, model weights and compressed index and caches them in the corresponding buffers, and rearranges the input feature map and model weights before calculation and decodes the compressed index; The computing unit performs convolution operations on the rearranged input feature map and model weights to obtain the dot product result. It then controls the selection and accumulation number of the dot product result based on the signal obtained from the compressed index decoding to obtain the final convolution result. After pooling and / or fully connected processing, the output feature map is written back to the off-chip memory through the bus controller.

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