A linear DC regulated power supply circuit

Abstract

The invention discloses a linear DC voltage-stabilized power supply, comprising a first triode, a first operational amplifier, a fifth operational amplifier, a sixth operational amplifier, a first potentiometer, a third resistor, a fourth resistor, a sixth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a sixteenth resistor and a seventeenth resistor, wherein one end of the first potentiometer is connected to a power supply, the collector of the first triode is connected to an input voltage Vin_1, the base of the first triode is connected to an amplified signal Vin_2, the emitter of the first triode is connected to an output voltage Qut_1, the other end of the first potentiometer, the tap end of the first potentiometer, one end of the sixth resistor and a non-inverting end of the fifth operational amplifier are connected, the inverting end of the fifth operational amplifier is connected to one end of the ninth resistor, the output end of the fifth operational amplifier is connected to the other end of the ninth resistor and one end of the sixteenth resistor, and the other end of the sixteenth resistor is connected to one end of the seventeenth resistor and the non-inverting end of the first operational amplifier.

Description

Technical Field

[0001] The invention relates to the technical field of switching power supplies, and in particular to a linear direct current regulated power supply circuit. Background Art

[0002] Linear regulated power supplies can adjust the current flowing into the load by controlling the amplification parameters of the power tube to achieve the purpose of voltage stabilization. Unlike switching regulated power supplies, linear regulated power supplies have small output ripple, low noise, and a smaller input and output range, so they have a better adjustable range. However, the current linear regulated power supply can only be regulated under the condition of fixed input voltage supply. Since voltage stabilization requires preset amplification parameters of the power tube, after the power supply voltage fluctuates or changes, the output power supply changes must be limited to the voltage stabilization range of the reference signal, so the amplification parameters of the power tube remain unchanged, and the input voltage changes will result in the original input power supply voltage. The preset output voltage output by adjusting the amplification parameters of the power tube will change with the new input power supply voltage. Summary of the invention

[0003] In view of the above technical problems, the purpose of the present invention is to provide a linear DC regulated power supply, including a first transistor Q1, a first operational amplifier U1, a fifth operational amplifier U5, a sixth operational amplifier U6, a first potentiometer RV1, a third resistor R3, a fourth resistor R4, a sixth resistor R6, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a sixteenth resistor R16, and a seventeenth resistor R17, wherein one end of the first potentiometer RV1 is connected to a power supply, the collector of the first transistor Q1 is connected to an input voltage Vin_1, the base of the first transistor Q1 is connected to an amplified signal Vin_2, the emitter of the first transistor Q1 is connected to an output voltage Qut_1, the other end of the first potentiometer RV1, the tap end of the first potentiometer RV1 and one end of the sixth resistor R6 and the in-phase end of the fifth operational amplifier U5 are connected, and the inverting end of the fifth operational amplifier U5 and the ninth One end of the resistor R9 is connected, the output end of the fifth operational amplifier U5 is connected to the other end of the ninth resistor R9 and one end of the sixteenth resistor R16, the other end of the sixteenth resistor R16 is connected to one end of the seventeenth resistor R17 and the same-phase end of the first operational amplifier U1, the inverting end of the first operational amplifier U1 is connected to one end of the third resistor R3 and one end of the fourth resistor R4, the output end of the first operational amplifier U1 is connected to the other end of the third resistor R3 and the amplified signal Vin_2, one end of the eleventh resistor R11 is connected to the bias signal Vin_3, the same-phase end of the sixth operational amplifier U6 is connected to the other end of the eleventh resistor R11, the inverting end of the sixth operational amplifier U6 is connected to one end of the tenth resistor R10, the output end of the sixth operational amplifier U6 is connected to the other end of the tenth resistor R10 and the other end of the seventeenth resistor R17, the other end of the fourth resistor R4, the other end of the sixth resistor R6 and the ground end are connected.

[0004] Furthermore, it also includes a third operational amplifier U3, a fourth digital potentiometer U4, a seventh operational amplifier U7, a ninth inverter U9, a fourteenth operational amplifier U14, a first resistor R1, a second resistor R2, a seventh resistor R7, an eighth resistor R8, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, and a first switch SW1, wherein one end of the first switch SW1 is connected to a power supply, the other end of the first switch SW1 is connected to an input end of a ninth inverter U9, an output end of the ninth inverter U9 is connected to one end of the first resistor R1 and a seventh pin of the fourth digital potentiometer U4, a second pin of the fourth digital potentiometer U4 is connected to one end of the second resistor R2 and an output end of the third operational amplifier U3, an inverting end of the third operational amplifier U3 is connected to a sampling voltage Out_2, a non-inverting end of the third operational amplifier U3 and one end of the twenty-first resistor R21, an output end of the first operational amplifier U1 The second end of the eighth resistor R8 is connected to the emitter of the first transistor Q1, the other end of the eighth resistor R8 is connected to one end of the seventh resistor R7 and the sampling voltage Out_2, the other end of the first resistor R1, the other end of the second resistor R2, the other end of the seventh resistor R7, the non-inverting end of the seventh operational amplifier U7, the non-inverting end of the fourteenth operational amplifier U14 and the ground are connected.

[0005] Furthermore, it also includes an eighth trigger U8, a tenth thyristor U10, an eleventh inverter U11, a twelfth thyristor U12, a thirteenth AND gate U13, a second triode Q2, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a first diode D1, and a second switch SW2, wherein one end of the second switch SW2, a first pin of the eighth trigger U8, a fourth pin of the eighth trigger U8, and a collector of the second triode Q2 are connected to a power supply, a second pin of the eighth trigger U8 is connected to a sixth pin of the eighth trigger U8, a third pin of the eighth trigger U8 is connected to the other end of the second switch SW2, one end of the twelfth resistor R12, and an output end of the thirteenth AND gate U13, a fifth pin of the eighth trigger U8 is connected to a base of the second triode Q2, and an anode of the first diode D1 The cathode of the first diode D1 is connected to the input end of the ninth inverter U9, the emitter of the second triode Q2 is connected to the anode of the tenth thyristor U10 and the anode of the twelfth thyristor U12, the control electrode of the twelfth thyristor U12 is connected to the output end of the eleventh inverter U11 and one end of the fourteenth resistor R14, the cathode of the twelfth thyristor U12 is connected to the first input end of the thirteenth AND gate U13 and one end of the fifteenth resistor R15, the control electrode of the tenth thyristor U10 is connected to the input end of the eleventh inverter U11 and the output end of the third operational amplifier U3, the cathode of the tenth thyristor U10 is connected to the second input end of the thirteenth AND gate U13 and one end of the thirteenth resistor R13, the other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15 and the ground are connected.

[0006] Furthermore, it also includes a second voltage stabilizing chip U2, a fifth resistor R5, an eighteenth resistor R18, and a nineteenth resistor R19. One end of the fifth resistor R5, one end of the eighteenth resistor R18, and the cathode of the second voltage stabilizing chip U2 are connected to the power supply, the other end of the fifth resistor R5 is connected to the collector of the first transistor Q1, the control electrode of the second voltage stabilizing chip U2 is connected to the other end of the eighteenth resistor R18 and one end of the nineteenth resistor R19, and the anode of the second voltage stabilizing chip U2 and the other end of the nineteenth resistor R19 are connected to the ground.

[0007] Furthermore, a twentieth resistor R20 is included, one end of the twentieth resistor R20 is connected to the in-phase terminal of the sixth operational amplifier U6, and the other end of the twentieth resistor R20 is connected to the ground terminal.

[0008] Furthermore, it also includes a first capacitor C1, one end of the first capacitor C1 is connected to one end of the eighth resistor R8, and the other end of the first capacitor C1 is connected to the ground.

[0009] Furthermore, it also includes a sampling circuit and a differential circuit. The sampling circuit is used to collect the output voltage Out_1 and feed back the sampled voltage to the differential circuit. The differential circuit generates a bias signal after performing a differential operation on the sampled voltage and the output voltage of the first operational amplifier U1.

[0010] Furthermore, the eighteenth resistor R18 is an adjustable resistor, and the power supply voltage of the subsequent circuit is adjusted by the eighteenth resistor R18.

[0011] Furthermore, the first switch SW1 is a self-locking switch.

[0012] The beneficial effects of the present invention compared with the prior art are:

[0013] Secondary voltage regulation can be performed when the input power supply voltage changes to ensure that the previously preset output voltage remains stable after the power supply voltage changes. The secondary voltage regulation parameters after the output voltage adjustment can be reconfigured, and the reconfigured parameters can be automatically detected and stopped. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 This is a circuit diagram of a linear DC regulated power supply provided by the present invention. DETAILED DESCRIPTION

[0016] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0017] The present invention discloses a linear DC regulated power supply, comprising a first transistor Q1, a first operational amplifier U1, a fifth operational amplifier U5, a sixth operational amplifier U6, a first potentiometer RV1, a third resistor R3, a fourth resistor R4, a sixth resistor R6, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a sixteenth resistor R16, and a seventeenth resistor R17, wherein one end of the first potentiometer RV1 is connected to a power supply, the collector of the first transistor Q1 is connected to an input voltage Vin_1, the base of the first transistor Q1 is connected to an amplified signal Vin_2, the emitter of the first transistor Q1 is connected to an output voltage Qut_1, the other end of the first potentiometer RV1, the tap end of the first potentiometer RV1, one end of the sixth resistor R6, and the in-phase end of the fifth operational amplifier U5 are connected, and the inverting end of the fifth operational amplifier U5 is connected to one end of the ninth resistor R9 The output end of the fifth operational amplifier U5 is connected to the other end of the ninth resistor R9 and one end of the sixteenth resistor R16, the other end of the sixteenth resistor R16 is connected to one end of the seventeenth resistor R17 and the same-phase end of the first operational amplifier U1, the inverting end of the first operational amplifier U1 is connected to one end of the third resistor R3 and one end of the fourth resistor R4, the output end of the first operational amplifier U1 is connected to the other end of the third resistor R3 and the amplified signal Vin_2, one end of the eleventh resistor R11 is connected to the bias signal Vin_3, the same-phase end of the sixth operational amplifier U6 is connected to the other end of the eleventh resistor R11, the inverting end of the sixth operational amplifier U6 is connected to one end of the tenth resistor R10, the output end of the sixth operational amplifier U6 is connected to the other end of the tenth resistor R10 and the other end of the seventeenth resistor R17, the other end of the fourth resistor R4, the other end of the sixth resistor R6 and the ground end are connected.

[0018] Specifically, it also includes a third operational amplifier U3, a fourth digital potentiometer U4, a seventh operational amplifier U7, a ninth inverter U9, a fourteenth operational amplifier U14, a first resistor R1, a second resistor R2, a seventh resistor R7, an eighth resistor R8, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, and a first switch SW1, wherein one end of the first switch SW1 is connected to a power supply, the other end of the first switch SW1 is connected to an input end of a ninth inverter U9, an output end of the ninth inverter U9 is connected to one end of the first resistor R1 and a seventh pin of the fourth digital potentiometer U4, a second pin of the fourth digital potentiometer U4 is connected to one end of the second resistor R2 and an output end of the third operational amplifier U3, an inverting end of the third operational amplifier U3 is connected to a sampling voltage Out_2, a non-inverting end of the third operational amplifier U3 and one end of the twenty-first resistor R21, an output end of the first operational amplifier U1 The second end of the eighth resistor R8 is connected to the emitter of the first transistor Q1, the other end of the eighth resistor R8 is connected to one end of the seventh resistor R7 and the sampling voltage Out_2, the other end of the first resistor R1, the other end of the second resistor R2, the other end of the seventh resistor R7, the non-inverting end of the seventh operational amplifier U7, the non-inverting end of the fourteenth operational amplifier U14 and the ground are connected.

[0019] Specifically, it also includes an eighth trigger U8, a tenth thyristor U10, an eleventh inverter U11, a twelfth thyristor U12, a thirteenth AND gate U13, a second triode Q2, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a first diode D1, and a second switch SW2. One end of the second switch SW2, a first pin of the eighth trigger U8, a fourth pin of the eighth trigger U8, and a collector of the second triode Q2 are connected to a power supply. The second pin of the eighth trigger U8 is connected to the sixth pin of the eighth trigger U8. The third pin of the eighth trigger U8 is connected to the other end of the second switch SW2, one end of the twelfth resistor R12, and an output end of the thirteenth AND gate U13. The fifth pin of the eighth trigger U8 is connected to the base of the second triode Q2 and the anode of the first diode D1. The cathode of the first diode D1 is connected to the input end of the ninth inverter U9, the emitter of the second triode Q2 is connected to the anode of the tenth thyristor U10 and the anode of the twelfth thyristor U12, the control electrode of the twelfth thyristor U12 is connected to the output end of the eleventh inverter U11 and one end of the fourteenth resistor R14, the cathode of the twelfth thyristor U12 is connected to the first input end of the thirteenth AND gate U13 and one end of the fifteenth resistor R15, the control electrode of the tenth thyristor U10 is connected to the input end of the eleventh inverter U11 and the output end of the third operational amplifier U3, the cathode of the tenth thyristor U10 is connected to the second input end of the thirteenth AND gate U13 and one end of the thirteenth resistor R13, the other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15 and the ground are connected.

[0020] Specifically, it also includes a second voltage stabilizing chip U2, a fifth resistor R5, an eighteenth resistor R18, and a nineteenth resistor R19. One end of the fifth resistor R5, one end of the eighteenth resistor R18, and the cathode of the second voltage stabilizing chip U2 are connected to the power supply, the other end of the fifth resistor R5 is connected to the collector of the first transistor Q1, the control electrode of the second voltage stabilizing chip U2 is connected to the other end of the eighteenth resistor R18 and one end of the nineteenth resistor R19, and the anode of the second voltage stabilizing chip U2 and the other end of the nineteenth resistor R19 are connected to the ground.

[0021] Specifically, a twentieth resistor R20 is also included, one end of the twentieth resistor R20 is connected to the in-phase terminal of the sixth operational amplifier U6, and the other end of the twentieth resistor R20 is connected to the ground terminal.

[0022] Specifically, it also includes a first capacitor C1, one end of the first capacitor C1 is connected to one end of the eighth resistor R8, and the other end of the first capacitor C1 is connected to the ground.

[0023] Specifically, it also includes a sampling circuit and a differential circuit. The sampling circuit is used to collect the output voltage Out_1 and feed back the sampled voltage to the differential circuit. The differential circuit generates a bias signal after performing a differential operation on the sampled voltage and the output voltage of the first operational amplifier U1.

[0024] Specifically, the eighteenth resistor R18 is an adjustable resistor, and the power supply voltage of the subsequent circuit is adjusted by the eighteenth resistor R18.

[0025] Specifically, the first switch SW1 is a self-locking switch.

[0026] In the first embodiment, it is considered that after the linear power supply is stabilized and regulated, its output voltage is equal to the voltage regulation signal multiplied by the amplification factor of the power tube. However, when the input voltage changes, since the voltage regulation signal and the power tube do not change, the preset output voltage amplitude will change with the input voltage, and the voltage regulation signal needs to be changed to make its output reach the preset value. Therefore, in the embodiment, the voltage regulation signal is divided into two parts: a reference voltage regulation signal and a bias signal, wherein Vin_1 is the input voltage, Out_1 is the output voltage, and Vin_2 is the amplified signal. After adjusting the first potentiometer RV1 knob to change the voltage divider ratio of the sixth resistor R6, the reference voltage regulation signal is output, and the signal is fed back to the in-phase terminal of the fifth operational amplifier U5. After the ninth resistor R9 is connected to the fifth operational amplifier U5, it is output to the sixteenth resistor R16 to prevent the bias signal from changing the reference voltage regulation signal, and the seventeenth resistor R17 is used for input bias regulation. The signal, the reference voltage adjustment signal and the bias signal are all fed back to the in-phase terminal of the first operational amplifier U1. The output of the first operational amplifier U1 is superimposed by the third resistor R3 and the fourth resistor R4 and then output to the base of the first transistor Q1 for driving and amplification. When the input voltage of Vin_1 changes, the bias signal amount input by the seventeenth resistor R17 is changed. The initial bias signal amount needs to be preset with a certain amplitude to facilitate the reduced input after the input voltage Vin_1 is reduced. Among them, the sixth operational amplifier U6 and the tenth resistor R10 are used for bias signal following. The in-phase terminal of the sixth operational amplifier U6 and the eleventh resistor R11 are connected to input the bias signal. The bias signal can be obtained by sampling the output voltage, and then the sampling voltage and the output voltage of the first operational amplifier U1 are differentiated by the differential circuit. This solution has low cost and can perform secondary voltage stabilization power supply for the output voltage that needs to be not less than the bias signal amount to prevent the output from following the change when the input voltage changes.

[0027] In the second embodiment, the power supply mode requiring the minimum output voltage and automatic callback are considered, so a low-voltage power supply mode is additionally provided on the basis of the first embodiment. In this embodiment, the amplified signal Vin_2 originally outputted by the first operational amplifier U1 to the base of the first transistor Q1 is changed to the output of the fourteenth operational amplifier U14. Since the low-voltage power supply amplitude is small, it can be completed by a step adjustment method. Therefore, the output of the first operational amplifier U1 is inputted to the sixth pin of the fourth digital potentiometer U4 and the inverting end of the seventh operational amplifier U7 through the twenty-first resistor R21, and the eighth resistor R8 and the seventh resistor R7 feed back the sampling voltage Out_2 to the inverting end of the third operational amplifier U3. When the first potentiometer RV1 is adjusted, the first switch SW1 is closed, and the fourth digital potentiometer U4 is started. Assuming that the current sampling voltage is greater than the output of the first operational amplifier U1, the third operational amplifier U3 outputs a signal to the second pin of the fourth digital potentiometer U4, otherwise the third operational amplifier U3 is cut off, and the fourth digital potentiometer U4 is adjusted up or down when the third operational amplifier U3 outputs. When there is no output, the second pin of the fourth digital potentiometer U4 is adjusted down or up through the second resistor R2 loop to change the resistance coefficient of the twenty-first resistor R21 and the fourth digital potentiometer U4. After the adjustment is completed, the first switch SW1 is disconnected, the fourth digital potentiometer U4 is cut off, and the signal output by the first operational amplifier U1 is calculated by the seventh operational amplifier U7 and then outputs a negative voltage signal to the inverting terminal of the fourteenth operational amplifier U14. The twenty-third resistor R23 and the twenty-second resistor R22 have the same resistance value. The fourteenth operational amplifier U14 outputs a positive voltage signal to the base of the first transistor Q1 after proportional inversion, thereby completing automatic callback to prevent the output voltage from changing after the input voltage changes. When it is necessary to change the output voltage again to adjust the first potentiometer RV1, press the first switch SW1 again to reconfigure the fourth digital potentiometer U4 and the twenty-first resistor R21. Both schemes can stably control the high output voltage. This scheme can be used when a secondary voltage regulation control is required for a lower output voltage. When combined, the twentieth resistor R20 needs to be added to prevent the sixth operational amplifier U6 from being virtual short.

[0028] In the third embodiment, the automatic detection and stop control after reconfiguration of the startup is considered. The original method of controlling the startup of the fourth digital potentiometer U4 by shutting off the first switch SW1 is replaced by the output of the first diode D1. When the first potentiometer RV1 is readjusted, the second switch SW2 is activated, and the power supply feeds back a switch signal to the third pin of the eighth trigger U8 through the second switch SW2. The fifth pin of the eighth trigger U8 is cut off in the initial state. When the second switch SW2 is activated, the fifth pin of the eighth trigger U8 outputs a signal, which is fed back to the ninth inverter U9 through the first diode D1. The ninth inverter U9 is cut off, and the fourth digital potentiometer U4 is started. Assuming that the current input voltage is higher than the previous input voltage, the third operational amplifier U3 is cut off, and the eleventh inverter U11 outputs a signal through the control electrode of the twelfth thyristor U12 and the loop of the fifteenth resistor R15. After the output of the fourteenth operational amplifier U14 is changed by the fourth digital potentiometer U4, the output of the third operational amplifier U3 is output, and the eleventh inverter U11 The eighth trigger U8 is cut off, and the output signal of the eighth trigger U8 is fed back to the second triode Q2, and the second triode Q2 is turned on. When the third operational amplifier U3 outputs, the power signal of the second triode Q2 passes through the twelfth thyristor U12 and the fifteenth resistor R15 circuit. The tenth thyristor U10 is turned on when the third operational amplifier U3 outputs. At this time, the thirteenth AND gate U13 outputs a signal back to the third pin of the eighth trigger U8, and the fifth pin of the eighth trigger U8 is cut off. Conversely, when the output voltage is lower than the previous input voltage, the output signal of the third operational amplifier U3 passes through the control electrode of the tenth thyristor U10 and the thirteenth resistor R13 circuit. After the third operational amplifier U3 is cut off, the eleventh inverter U11 is outputting, and the voltages at the fifteenth resistor R15 and the fourteenth resistor R14 are fed back to the thirteenth AND gate U13, and the thirteenth AND gate U13 still outputs a signal back to the eighth trigger U8. That is to say, no matter how the input power changes, the fourth digital potentiometer U4 stops after the output of the third operational amplifier U3 jumps. The second voltage stabilizing chip U2, the fifth resistor R5, the eighteenth resistor R18, and the nineteenth resistor R19 are used to stabilize the voltage and supply power to the subsequent circuit.

[0029] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A linear DC regulated power supply, characterized in that: The invention comprises a first triode, a first operational amplifier, a fifth operational amplifier, a sixth operational amplifier, a first potentiometer, a third resistor, a fourth resistor, a sixth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a sixteenth resistor and a seventeenth resistor, wherein one end of the first potentiometer is connected to a power supply, the collector of the first triode is connected to an input voltage Vin_1, the base of the first triode is connected to an amplified signal Vin_2, the emitter of the first triode is connected to an output voltage Qut_1, the other end of the first potentiometer, the tap end of the first potentiometer and one end of the sixth resistor and the in-phase end of the fifth operational amplifier are connected, the inverting end of the fifth operational amplifier is connected to one end of the ninth resistor, and the fifth operational amplifier is connected to one end of the ninth resistor. The output end is connected to the other end of the ninth resistor and one end of the sixteenth resistor, the other end of the sixteenth resistor is connected to one end of the seventeenth resistor and the non-inverting end of the first operational amplifier, the inverting end of the first operational amplifier is connected to one end of the third resistor and one end of the fourth resistor, the output end of the first operational amplifier is connected to the other end of the third resistor and the amplified signal Vin_2, one end of the eleventh resistor is connected to the bias signal Vin_3, the non-inverting end of the sixth operational amplifier is connected to the other end of the eleventh resistor, the inverting end of the sixth operational amplifier is connected to one end of the tenth resistor, the output end of the sixth operational amplifier is connected to the other end of the tenth resistor and the other end of the seventeenth resistor, and the other end of the fourth resistor, the other end of the sixth resistor and the ground end are connected; The present invention also includes a third operational amplifier, a fourth digital potentiometer, a seventh operational amplifier, a ninth inverter, a fourteenth operational amplifier, a first resistor, a second resistor, a seventh resistor, an eighth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, and a first switch, wherein one end of the first switch is connected to a power supply, the other end of the first switch is connected to an input end of the ninth inverter, an output end of the ninth inverter is connected to one end of the first resistor and a seventh pin of the fourth digital potentiometer, a second pin of the fourth digital potentiometer is connected to one end of the second resistor and an output end of the third operational amplifier, an inverting end of the third operational amplifier is connected to a sampling voltage Out_2, a non-inverting end of the third operational amplifier is connected to one end of the twenty-first resistor and an output end of the first operational amplifier, and a first switch is connected to the output end of the twenty-third resistor. The other end of the first resistor is connected to the sixth pin of the fourth digital potentiometer and the inverting end of the seventh operational amplifier, the third pin of the fourth digital potentiometer, the fifth pin of the fourth digital potentiometer, the output end of the seventh operational amplifier and one end of the twenty-second resistor are connected, the other end of the twenty-second resistor is connected to one end of the twenty-third resistor and the inverting end of the fourteenth operational amplifier, the output end of the fourteenth operational amplifier and the other end of the twenty-third resistor are connected to the amplified signal Vin_2, one end of the eighth resistor is connected to the emitter of the first transistor, the other end of the eighth resistor is connected to one end of the seventh resistor and the sampling voltage Out_2, the other end of the first resistor, the other end of the second resistor, the other end of the seventh resistor, the non-inverting end of the seventh operational amplifier, the non-inverting end of the fourteenth operational amplifier and the ground are connected.

2. The linear DC regulated power supply according to claim 1, characterized in that: It also includes an eighth trigger, a tenth thyristor, an eleventh inverter, a twelfth thyristor, a thirteenth AND gate, a second triode, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a first diode, and a second switch. One end of the second switch, the first pin of the eighth trigger, the fourth pin of the eighth trigger, and the collector of the second triode are connected to the power supply. The second pin of the eighth trigger is connected to the sixth pin of the eighth trigger. The third pin of the eighth trigger is connected to the other end of the second switch, one end of the twelfth resistor, and the output end of the thirteenth AND gate. The fifth pin of the eighth trigger is connected to the base of the second triode and the anode of the first diode. The cathode of the diode is connected to the input end of the ninth inverter, the emitter of the second triode is connected to the anode of the tenth thyristor and the anode of the twelfth thyristor, the control electrode of the twelfth thyristor is connected to the output end of the eleventh inverter and one end of the fourteenth resistor, the cathode of the twelfth thyristor is connected to the first input end of the thirteenth AND gate and one end of the fifteenth resistor, the control electrode of the tenth thyristor is connected to the input end of the eleventh inverter and the output end of the third operational amplifier, the cathode of the tenth thyristor is connected to the second input end of the thirteenth AND gate and one end of the thirteenth resistor, and the other end of the twelfth resistor, the other end of the thirteenth resistor, the other end of the fourteenth resistor, the other end of the fifteenth resistor and the ground are connected.

3. The linear DC regulated power supply according to claim 1, characterized in that: It also includes a second voltage stabilizing chip, a fifth resistor, an eighteenth resistor, and a nineteenth resistor. One end of the fifth resistor, one end of the eighteenth resistor, and the cathode of the second voltage stabilizing chip are connected to the power supply, the other end of the fifth resistor is connected to the collector of the first transistor, the control electrode of the second voltage stabilizing chip is connected to the other end of the eighteenth resistor and one end of the nineteenth resistor, and the anode of the second voltage stabilizing chip and the other end of the nineteenth resistor are connected to the ground.

4. The linear DC regulated power supply according to claim 1, characterized in that: It also includes a twentieth resistor, one end of the twentieth resistor is connected to the in-phase terminal of the sixth operational amplifier, and the other end of the twentieth resistor is connected to the ground terminal.

5. The linear DC regulated power supply according to claim 1, characterized in that: It also includes a first capacitor, one end of which is connected to one end of the eighth resistor, and the other end of the first capacitor is connected to the ground.

6. The linear DC regulated power supply according to claim 1, characterized in that: It also includes a sampling circuit and a differential circuit. The sampling circuit is used to collect the output voltage Out_1 and feed back the sampled voltage to the differential circuit. The differential circuit generates a bias signal after performing a differential operation on the sampled voltage and the output voltage of the first operational amplifier.

7. The linear DC regulated power supply according to claim 3, characterized in that: The eighteenth resistor is an adjustable resistor, and the power supply voltage of the subsequent circuit is adjusted by the eighteenth resistor.

8. The linear DC regulated power supply according to claim 1, characterized in that: The first switch is a self-locking switch.

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