Method, computer equipment and medium for automatic generation of top-level code

CN118502730BActive Publication Date: 2025-01-07XIN YAOHUI TECH CO LTD
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Patent Information

Application Number
CN202410681084.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-05-29
Publication Date
2025-01-07
Estimated Expiration
2044-05-29

AI Technical Summary

Technical Problem

In the prior art, the development and maintenance of intelligent attribute core (IP) codes are inefficient and have high integration complexity, resulting in high labor costs and prone to errors.

Method used

Through the method of automatically generating top-level code, the global control information, sub-layer module interface control information and sub-layer module interface information are analyzed using the table format in the architecture document, and the connection relationship between modules, interface signal correspondence relationships and automation scripts and artificial intelligence models are used to realize the connection relationship between modules and interface signals. Automated processing of naming specifications.

Benefits of technology

It improves the efficiency of intelligent attribute core (IP) integration, reduces labor costs, reduces the probability of errors, and adapts to the development progress and iterative needs of chip design.

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Abstract

The present application provides a method, computer device and medium for automatic generation of top-level code. The method includes: determining the table format for filling in the architecture document based on the top-level code specification associated with the chip design; executing the associated architecture document filling in accordance with the table format to obtain the architecture document associated with the chip design; determining the associated global control information, sub-layer module interface control information and sub-layer module interface information set by parsing the architecture document; traversing each sub-layer module, determining the corresponding sub-layer module interface information, the associated top-level interface information, and the associated module interface interconnection information, and instantiating the sub-layer module to generate the top-level code. In this way, the automation efficiency is improved.
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Citation Information

Patent Citations

  • Method for completing chip design integrated functions by forms

    CN103049619A

  • Method for realizing automatic instantiation of top layer of chip system based on python

    CN112861454A

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