Chip processing apparatus and method, device, medium, program product and chip

Abstract

The present disclosure provides a processing device and method for a chip, an electronic device, a non-transitory computer-readable storage medium, a computer program product, and a chip. The processing device for the chip comprises a receiving module configured to receive a first instruction; a selecting module configured to: in response to the receiving module not receiving an instruction of a computing task, output the first instruction, and execute the first instruction by a computing unit; and in response to the receiving module receiving the instruction of the computing task, output the instruction of the computing task, and stop executing the first instruction by the computing unit and execute the instruction of the computing task. In this way, the amount of instantaneous current change can be reduced, and the chip can be protected from being easily damaged.

Description

Technical Field

[0001] The embodiments of this disclosure relate to the field of artificial intelligence technology, and more specifically to processing apparatus for chips, processing methods for chips, electronic devices, non-transitory computer-readable storage media, computer program products, and chips. Background Technology

[0002] Artificial intelligence (AI) chips are typically dedicated to graphics processing and image rendering. They possess massively parallel processing capabilities and dedicated computing cores, enabling them to rapidly handle graphics computation tasks, particularly tensor operations and convolution tasks in machine learning. AI chips can include Graphics Processing Units (GPUs), General-Purpose Computing on Graphics Processing Units (GPGPUs), Tensor Processing Units (TPUs), Data Processing Units (DPUs), and Artificial Intelligence (AI) accelerators. Summary of the Invention

[0003] According to one aspect of this disclosure, at least one embodiment provides a processing apparatus for a chip, comprising: a receiving module configured to receive a first instruction; and a selection module configured to: output a first instruction in response to the receiving module not receiving an instruction for a computing task, and have a computing unit execute the first instruction; and output an instruction for a computing task in response to the receiving module receiving an instruction for a computing task, and have the computing unit stop executing the first instruction and execute the instruction for the computing task.

[0004] According to one aspect of this disclosure, at least one embodiment provides a processing method for a chip, comprising: receiving a first instruction; executing the first instruction in response to not receiving an instruction for a computing task; and stopping the execution of the first instruction and executing the instruction for the computing task in response to receiving an instruction for a computing task.

[0005] According to another aspect of this disclosure, at least one embodiment provides an electronic device, including: a memory for storing computer instructions; and a processor for reading the computer instructions from the memory and performing a method according to at least one embodiment of this disclosure.

[0006] According to another aspect of this disclosure, at least one embodiment provides a non-transitory computer-readable storage medium having computer instructions stored thereon, wherein, when executed by a processor, the computer instructions cause the processor to perform a method according to at least one embodiment of this disclosure.

[0007] According to another aspect of this disclosure, at least one embodiment provides a computer program product including computer instructions, wherein, when executed by a processor, the computer instructions cause the processor to perform a method according to at least one embodiment of this disclosure.

[0008] According to another aspect of this disclosure, at least one embodiment provides a chip, including: a processing apparatus for the chip according to at least one embodiment of this disclosure; and one or more computing units. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A block diagram of a computing system according to at least one embodiment of the present disclosure is shown.

[0011] Figure 2 A block diagram of a processing apparatus for a chip according to at least one embodiment of the present disclosure is shown.

[0012] Figure 3 A scene block diagram of a chip according to at least one embodiment of the present disclosure is shown.

[0013] Figure 4 A flowchart of a processing method for a chip according to at least one embodiment of the present disclosure is shown.

[0014] Figure 5 A block diagram of an exemplary electronic device according to at least one embodiment of the present disclosure is shown.

[0015] Figure 6 A block diagram of a chip according to at least one embodiment of the present disclosure is shown.

[0016] Figure 7 A schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the present disclosure is shown. Detailed Implementation

[0017] Referring now to specific embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. Although this application will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit this application to the described embodiments. Rather, it is intended to cover variations, modifications, and equivalents included within the spirit and scope of this disclosure. It should be noted that the method steps described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0018] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0019] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0020] The method provided in at least one embodiment of this disclosure is generally executed by a computing device with a certain computing capability.

[0021] Artificial intelligence chips require massive computations to train and infer large models, resulting in significant power consumption. The computational units of an AI chip, performing matrix multiplication or convolution operations, consume more than half of the chip's total power.

[0022] When a computing unit initiates or terminates matrix multiplication or convolution operations, the instantaneous current (power consumption) changes dramatically, sometimes even damaging the entire chip. Therefore, it is necessary to reduce this instantaneous current fluctuation. Using numerous analog devices on the printed circuit board of an AI chip, such as connecting a large number of capacitors in parallel near the DC power supply, can reduce the instantaneous current of the entire circuit through the charging and discharging of these capacitors. However, this method requires a large number of capacitors of different specifications to achieve this reduction, leading to a larger printed circuit board and increased engineering complexity. This disclosure proposes a new technical solution that effectively addresses the aforementioned problems.

[0023] Figure 1 A block diagram of a computing system 100 according to at least one embodiment of the present disclosure is shown.

[0024] The computing system 100 includes an artificial intelligence chip 110 and a host computer 120. The artificial intelligence chip 110 is capable of rapidly processing graphics computing tasks. The host computer 120 includes a central processing unit (CPU) 1210 and memory 1220. The central processing unit 1210 is the core of the host computer's operation and control, responsible for executing instructions, processing data, and controlling multiple components of the computer. It possesses broad general-purpose computing capabilities and is suitable for performing various types of general-purpose tasks.

[0025] The AI ​​chip 110 can be referred to as the device side, and the host 120 can be referred to as the host side. The AI ​​chip 110 and the host 120 are interconnected through the bus 130 to transmit code, data, addresses, control signals, etc.

[0026] The artificial intelligence chip 110 includes a command processor (CP) 1110 for receiving commands sent by the central processing unit 1210. The AI ​​chip 110 also includes multiple computing units (CUs) 1120 for executing instructions sent by the host 120 to perform data computation. The computing units may include tensor cores for performing tensor operations, etc., and the embodiments disclosed herein are not limited thereto. The AI ​​chip 110 also includes memory 1140, such as high-bandwidth memory (HBM), for storing data required for data computation.

[0027] For example, in handling tensor operations and convolution tasks in machine learning, computation unit 1120 pre-loads the data to be operated on (e.g., matrices A and B to be multiplied) from host 120 into memory 1140. During operation, it reads matrices A and B from memory 1140 into register 1130. Computation unit 1120 performs, for example, matrix multiplication on matrices A and B in register 1130 and stores the result in memory 1140. The result can be sent to memory 1220 of host 120 via bus 130.

[0028] The artificial intelligence chip 110 can work with the host 120 to perform computing tasks such as speech recognition, image recognition, text recognition, video recognition, and intelligent human-computer dialogue with large language models.

[0029] Figure 2 A block diagram of a processing apparatus 200 for, for example, the chip described above, according to at least one embodiment of the present disclosure is shown.

[0030] The various modules in the processing device 200 can be implemented in software, hardware, or a combination of both. For example, the processing device 200 can be implemented as at least part of a command processor, or provided independently of a command processor, and the embodiments of this disclosure do not limit this.

[0031] like Figure 2 As shown, the processing device 200 for the above-mentioned chip includes a receiving module 210 and a selection module 220.

[0032] The receiving module 210 is configured to receive a first instruction for execution by the computing unit.

[0033] Here, the first instruction may include at least one of the preset matrix multiplication, convolution, or other operations. It may not be the actual exemplary computational task instruction that the host requires the chip to execute as described above, but rather a simulated instruction. The term "first" here is for distinguishing purposes only and is not limited to the first one.

[0034] The selection module 220 is configured to: in response to the receiving module 210 not receiving an instruction for a computing task, output a first instruction to be executed by the computing unit.

[0035] Here, the instructions for the computing task can be the actual computing task instructions that the host requires the chip to perform the computing.

[0036] Here, the computing unit executes a first instruction, thereby putting the chip into an operating state, which enables the chip to have a first current value and consume a first power consumption.

[0037] In some embodiments, the receiving module 210 may also be configured to receive a first instruction in response to the chip being started, for execution by the computing unit.

[0038] Here, startup may include powering on. The method described in this embodiment of the present disclosure can be started from the initial power-on of the chip, thereby executing the first instruction, or the execution of the first instruction can begin some time after the initial power-on of the chip.

[0039] In some embodiments, the receiving module 210 may also be configured to receive a first instruction for execution by the computing unit between receiving instructions for a computing task.

[0040] In some embodiments, the receiving module 210 may also be configured to: receive a first instruction for execution by the computing unit in response to the receiving module not receiving an instruction for a computing task for a predetermined time. The predetermined time may be a few milliseconds, etc., and the embodiments of this disclosure do not limit this.

[0041] Here, the first instruction can be executed only after a predetermined time, so that the chip already has the first current value before the second current value caused by the instruction to execute the calculation task, thereby reducing the instantaneous current change and saving power consumption at the same time.

[0042] The selection module 220 is configured to: in response to the receiving module 210 receiving the instruction of the computing task, output the instruction of the computing task, stop the execution of the first instruction by the computing unit, and execute the instruction of the computing task.

[0043] Here, the instruction of the computing task is the actual computing task instruction that the host needs the chip to execute. In some embodiments, the execution priority of the instruction of the computing task is higher than the execution priority of the first instruction. Therefore, once the receiving module 210 receives the instruction of the computing task, the selection module 220 outputs the instruction of the computing task, and the computing unit stops executing the first instruction and executes the instruction of the computing task.

[0044] At this time, the instructions executed by the computing unit to perform the computing task will cause the chip to have a second current value and consume a second power consumption.

[0045] Since the chip already has a first current value before executing the received computational task instructions, when the unit executes the computational task instructions, the chip reaches a second current value. The instantaneous current change from the first current value to the second current value is smaller than the change from 0 to the second current value. This reduces the instantaneous current change and protects the chip from damage.

[0046] In some embodiments, the receiving module 210 may also be configured to receive a first instruction before receiving the instruction for the computing task, for repeated execution by the computing unit.

[0047] Thus, to prevent the current value in the chip from becoming zero, the receiving module 210 can receive a first instruction for execution by the computing unit, and the selection module 220 can output the first instruction for the computing unit to repeatedly execute, so that the chip still has the first current value until a computing task instruction is received and executed by the computing unit. This ensures that the instantaneous current change is small during chip power-on, protecting the chip from damage.

[0048] In these embodiments, the chip can be kept near a first current value. Of course, the first instruction can also include multiple repeating or non-repeating sub-instructions, so that executing the first instruction is equivalent to executing multiple sub-instructions to keep the chip at a certain current value.

[0049] In some embodiments, the selection module 220 is further configured to: in response to the receiving module not receiving an instruction for a computing task for a predetermined time, the computing unit executes the first instruction.

[0050] Thus, after the predetermined time, the selection module 220 continues to output the first instruction for the computing unit to execute, until the receiving module 210 receives an instruction for a new computing task. At this point, the computing unit stops executing the first instruction and executes the instruction for the new computing task. This ensures that the instantaneous current change is small during chip power-on, protecting the chip from damage.

[0051] If the receiving module 210 does not receive a new computing task instruction and continues to receive the first instruction until the chip finishes executing the computing task instruction and is powered off, then from the state of executing the first instruction to the complete power off, its power consumption value changes from low power consumption to 0 power consumption, which also reduces the instantaneous current change.

[0052] In some embodiments, the current value or power consumption value generated by the computing unit executing the first instruction is less than or equal to the current value or power consumption value generated by the instruction of the computing unit executing the computing task.

[0053] Therefore, if the current or power consumption generated by executing the first instruction is small, the total current or power consumption consumed by the chip during power-on can be reduced.

[0054] On the other hand, to minimize the instantaneous current change, the current generated by the computing unit executing the first instruction can be increased by modifying the computational data of the first instruction. This makes the current value closer to the current value generated by the computing unit executing the computational task instruction. However, this also leads to a higher power consumption by the computing unit executing the first instruction, thus increasing the chip's total power consumption. Therefore, in practice, a trade-off can be struck between the instantaneous current change and the chip's total power consumption to set an appropriate first instruction.

[0055] In some embodiments, changing the current value generated by the computing unit executing the first instruction can be achieved by setting configuration information to change the computation data of the first instruction.

[0056] In some embodiments, the processing device 200 may further include an instruction generation module and a pattern generation module.

[0057] The instruction generation module is configured to generate a first instruction based on configuration information and provide the first instruction to the receiving module. The pattern generation module is configured to generate a data sequence corresponding to the configuration information, which is required by the computing unit when executing the first instruction, based on the first instruction output by the selection module.

[0058] Here, the configuration information can be pre-stored in a configuration information storage module in the processing device 200 (e.g., before the chip leaves the factory). Once the chip is initially powered on, the instruction generation module can read the configuration information stored in the configuration information storage module and generate a first instruction based on the information included in the configuration information. Alternatively, the configuration information can be sent from the host to the configuration information storage module in the processing device 200 after the chip is powered on. The configuration information storage module may include registers, HBM, etc.

[0059] For example, configuration information can be customized and may include one of several data formats. The data format represents the format of the data to be processed by the first instruction, such as integer (INT) 8 (8 bits), INT 16 (16 bits), INT 32 (32 bits), INT 64 (64 bits), floating-point (FP) 8 (8 bits), FP 16 (16 bits), FP32 (32 bits), FP 64 (64 bits), brain floating-point (BF) 8 (8 bits), BF 16 (16 bits), BF 32 (32 bits), BF 64 (64 bits), and so on. The higher the precision of the data format and the more bits it occupies, the greater the current or power consumption generated when processing data in that format.

[0060] In some embodiments, the configuration information may also include one of several power consumption modes. Different power consumption modes can be implemented using the toggle rate. The toggle rate refers to the number of times a signal level (including 0 and 1) flips per unit time, that is, the frequency with which the signal changes from high to low or from low to high.

[0061] For example, if the data being operated on is 01 or 10, fetching 0 and 1 or 1 and 0 from the register sequentially will cause the bits in the register to flip from 0 to 1 or from 1 to 0, resulting in power consumption. However, if the data being operated on is 00 or 11, fetching 0 and 0 or 1 and 1 from the register sequentially will not require bit flipping between data fetches, thus incurring no power consumption. It is clear that the different proportions of 0 and 1 flips in the data sequence being operated on, i.e., the different flip rates, lead to different power consumption levels.

[0062] Thus, the higher the toggle ratio, the greater the current or power consumption. For example, a high toggle ratio can be assigned to a high-power mode, such as using an INT8 format data sequence of 01010101; a medium toggle ratio can be assigned to a medium-power mode, such as using an INT8 format data sequence of 00100100; and a low toggle ratio can be assigned to a low-power mode, such as using an INT8 format data sequence of 00000001.

[0063] It's understandable that, under the same power consumption mode, higher data format precision results in higher power consumption. For example, the power consumption of an INT16 data sequence of 01010101010101 in high power consumption mode is higher than that of an INT8 data sequence of 01010101 in high power consumption mode. Similarly, under the same data format precision, higher power consumption modes result in higher power consumption. For instance, the power consumption of a high power consumption INT8 data sequence of 01010101 is higher than that of a low power consumption INT8 data sequence of 00000001.

[0064] The pattern generation module is configured to generate a data sequence corresponding to at least one of a plurality of data formats and / or a plurality of power consumption modes, which is to be processed by the computing unit. For example, if the configuration information specifies that one of the plurality of data formats is INT 32 format and one of the plurality of power consumption modes is high power consumption, then the pattern generation module generates a data sequence to be processed by the computing unit, such as 01010101010101010101010101010101 (INT 32 format, high power consumption), for the computing unit to process. Of course, the configuration information can also specify only one of the plurality of data formats without specifying one of the plurality of power consumption modes, or only specify one of the plurality of power consumption modes without specifying one of the plurality of data formats, or both, and the pattern generation module can generate a data sequence accordingly.

[0065] Note that the pattern generation module can pre-record the data sequences corresponding to different data formats and / or different power consumption modes so that the corresponding data sequences can be generated without real-time calculation.

[0066] In this way, the current / power consumption generated by executing the first instruction can be flexibly set based on configuration information including one of multiple data formats and / or one of multiple power consumption modes.

[0067] Thus, according to at least one embodiment of this disclosure, the chip generates a certain current value when executing the first instruction between the instructions that the host actually wants the chip to execute. Therefore, when the computing unit executes the actual computing task instructions, its instantaneous current change is smaller than the change starting from 0, which can protect the chip from damage. Moreover, the current / power consumption generated by executing the first instruction can be flexibly set based on configuration information including one of multiple data formats and / or one of multiple power consumption modes.

[0068] The above-described at least one embodiment will be described below with reference to specific scenario diagrams.

[0069] Figure 3A scene block diagram of a chip 300 according to at least one embodiment of the present disclosure is shown.

[0070] The various modules associated with chip 300 can be implemented using software, hardware, firmware, or any combination thereof.

[0071] like Figure 3 As shown, when chip 300 starts up and powers on, host 310 can send configuration information to chip 300 in various ways. For example, host 310 can use a memory-mapped I / O (MMIO) interface to store configuration information in register 340 of chip 300, or host 310 can use a design for test (DFT) interface to store configuration information in register 340 of chip 300. Alternatively, the configuration information may be pre-stored in register 340 before the chip leaves the factory, or pre-stored in register 340 in other ways.

[0072] The configuration information may include one of multiple data formats, one of multiple power consumption modes, and a function switch indicating whether the execution of the first instruction is enabled. If the function switch indicates that the instruction generation module 330 is off, the instruction generation module 330 does not generate the first instruction. If the function switch indicates that the instruction generation module 330 is on, the instruction generation module 330 generates a first instruction corresponding to at least one of the multiple data formats and / or multiple power consumption modes based on at least one of the multiple data formats and / or multiple power consumption modes in the configuration information in register 340.

[0073] This first instruction only needs to be generated once based on the configuration information, and it can be stored in register 340 indefinitely. The receiving module 350 can obtain the first instruction from register 340, thus, the receiving module 350 can continuously receive the first instruction during chip power-on.

[0074] The host 310 can also send actual computation task instructions that the host 310 needs the chip to execute to the instruction sending module 320 in the chip 300. The receiving module 350 can receive both the actual computation task instructions that the host 310 needs the chip to execute and the first instruction sent by the instruction sending module 320. The execution priority of the actual computation task instructions is higher than the execution priority of the first instruction.

[0075] In response to the receiving module 350 not receiving an actual computation task instruction, the selection module 360 ​​outputs a first instruction, which is then executed by the computing unit. Conversely, in response to the receiving module 350 receiving an actual computation task instruction from the instruction issuing module 320 that the host 310 requires the chip to execute, the selection module 360 ​​outputs the actual computation task instruction, so that the computing unit stops executing the first instruction and executes the actual computation task instruction.

[0076] The data storage module 370 can pre-store computational data.

[0077] When the selection module 360 ​​outputs the actual calculation task instruction, it can read the A calculation data and B calculation data required by the calculation unit 390 to perform the actual calculation task instruction from the data storage module 370 and send them to the calculation unit 390 for calculation.

[0078] When the selection module 360 ​​outputs the first instruction, the mode generation module 380 can generate the A' data sequence and B' data sequence corresponding to the configuration information (i.e., one of multiple data formats and one of multiple power consumption modes) based on the information of the first instruction, and send them to the calculation unit 390 for calculation.

[0079] For example, if the configuration information specifies that one of the multiple data formats is INT 32 format and one of the multiple power consumption modes is high power consumption, then the mode generation module 380 generates the data sequence required when executing the first instruction, such as 01010101010101010101010101010101, so that the calculation unit 390 can perform operations on the data sequence.

[0080] Thus, when chip 300 starts up and powers on, instruction issuing module 320 typically does not immediately receive the actual computation task instruction from host 310. Therefore, selection module 360 ​​outputs the first instruction, which is executed by computation unit 390, causing chip 300 to initially operate at a certain current value. When instruction issuing module 320 issues the actual computation task instruction from host 310, selection module 360 ​​outputs the actual computation task instruction, which is then executed by computation unit 390. At this time, the current of chip 300 will reach its maximum operating value. Since the initial current value of chip 300 is not zero, the instantaneous current change will not be too large and is controllable. The first instruction can still be stored in register 340 and will not be lost.

[0081] If a predetermined time is reached in response to the failure to receive a computing task instruction, the selection module 360 ​​continues to output the first instruction, which is then executed by the computing unit 390. The chip 300 continues to operate at a certain current value until the instruction issuing module 320 issues the actual computing task instruction from the host 310, and then the computing unit 390 executes the actual computing task instruction. This continuously reduces the instantaneous current change.

[0082] Of course, during the normal operation of the chip 300, if there is a long interval between two actual computing task instructions, the first instruction can be executed between the arrival of the actual computing task instructions. In this way, the power consumption caused by continuously executing the first instruction can be reduced, and the instantaneous current change can also be reduced.

[0083] Thus, according to at least one embodiment of this disclosure, a first instruction can be repeatedly executed to generate a certain current value before the actual instructions the host wants the chip to execute. Therefore, when the computing unit executes the actual computing task instructions, its instantaneous current change is smaller than the change starting from 0, which can protect the chip from damage. Moreover, the current / power consumption generated by executing the first instruction can be flexibly set based on configuration information including one of multiple data formats and / or one of multiple power consumption modes.

[0084] The defects and problems existing in the above-mentioned prior art solutions are also the result of the inventor's careful research after practical and creative labor. The discovery process of the above problems and the solutions proposed by at least one embodiment disclosed below for the above problems are all creative contributions of the inventor during the invention process.

[0085] Figure 4 A flowchart of a processing method for a chip according to at least one embodiment of the present disclosure is shown.

[0086] like Figure 4 As shown, the processing method for the chip includes steps 410, 420, and 430, where the chip corresponds to, for example, [the chip is described in the original text]. Figure 2 or Figure 3 The chip shown.

[0087] In step 410, the first instruction is received.

[0088] In step 420, in response to the absence of a computation task instruction, the first instruction is executed. At this time, the chip's computing unit executes the first instruction, thereby putting the chip into, for example, a low-power state to avoid subsequent large instantaneous changes in operating current.

[0089] In step 430, in response to receiving the instruction for the computing task, the execution of the first instruction is stopped, and the instruction for the computing task is executed. At this time, the chip's computing unit stops executing the first instruction and executes the corresponding instruction for the actual computing task, thereby putting the chip into a normal power consumption state.

[0090] In some embodiments, step 410 may include: receiving a first instruction in response to the chip being powered on, and executing the first instruction.

[0091] In some embodiments, step 410 may include: receiving a first instruction between receiving instructions for a computing task, to execute the first instruction.

[0092] In some embodiments, step 410 may include: receiving a first instruction to repeatedly execute the first instruction before receiving the instruction for the computing task.

[0093] In some embodiments, executing the first instruction in response to not receiving an instruction for a computing task includes: executing the first instruction in response to a predetermined time elapsed since no instruction for a computing task has been received.

[0094] In some embodiments, the execution priority of the instructions for the computation task is higher than the execution priority of the first instruction.

[0095] In some embodiments, the current value or power consumption value generated by executing the first instruction is less than or equal to the current value or power consumption value generated by the instruction that executes the computing task.

[0096] In some embodiments, the method may further include: generating a first instruction based on configuration information to receive the first instruction; and generating a data sequence corresponding to the configuration information required when executing the first instruction based on the first instruction.

[0097] In some embodiments, the configuration information includes at least one of a variety of data formats and / or a variety of power consumption modes.

[0098] In some embodiments, the method may further include generating a data sequence required when executing a first instruction, corresponding to at least one of a plurality of data formats and / or a plurality of power consumption modes, for performing operations on the data sequence.

[0099] Thus, according to at least one embodiment of this disclosure, the chip can generate a certain current value by executing a first instruction before executing the actual instructions that the host wants the chip to execute. Therefore, when executing the actual computing task instructions, the instantaneous current change is smaller than the change starting from 0, which can protect the chip from damage. Moreover, the current / power consumption generated by executing the first instruction can be flexibly set based on configuration information including one of multiple data formats and / or one of multiple power consumption modes.

[0100] Figure 5 A block diagram of an exemplary electronic device according to at least one embodiment of the present disclosure is shown.

[0101] An electronic device may include a processor 510 and a memory 520, the memory 520 being coupled to the processor 510 and storing computer instructions and / or data therein.

[0102] The processor 510 may include, but is not limited to, one or more processors or microprocessors, such as the chip included in any embodiment of this disclosure, which may be used independently or in cooperation with a central processing unit (CPU) to perform computational tasks for implementing, for example, speech recognition, image recognition, text recognition, video recognition, intelligent human-computer dialogue with large language models, etc.

[0103] The memory 520 may include, but is not limited to, random access memory (RAM), read-only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, computer storage media (such as hard disks, floppy disks, solid-state drives, removable disks, CD-ROMs, DVD-ROMs, Blu-ray discs, etc.).

[0104] In addition, the electronic device may also include (but is not limited to) a data bus 530, an input / output (I / O) bus 540, a display 550, and input / output devices 560 (e.g., a keyboard, mouse, speaker, etc.).

[0105] The processor 510 can communicate with external displays 550 and input / output devices 560 via the I / O bus 540.

[0106] In one embodiment, the at least one computer instruction may also be compiled into or comprise a computer program product or software product, wherein one or more computer instructions, when executed by a processor, perform the various functions in the embodiments described herein.

[0107] Figure 6 A block diagram of a chip 600 according to at least one embodiment of the present disclosure is shown.

[0108] Chip 600 includes: a processing device 610 for the chip according to embodiments of the present disclosure; and one or more computing units 620. The processing device 610 for the chip has been described above and will not be repeated here. In different embodiments, the chip 600 may also include, for example, memory, shared cache, etc.

[0109] Figure 7 A schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the present disclosure is shown.

[0110] like Figure 7As shown, the non-transitory computer-readable storage medium 720 stores instructions, such as computer instructions 710. When the computer instructions 710 are executed by a processor, the various methods described above can be performed. Non-transitory computer-readable storage media include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, computer storage media (e.g., hard disks, floppy disks, solid-state drives, removable disks, CD-ROMs, DVD-ROMs, Blu-ray discs, etc.). For example, the non-transitory computer-readable storage medium 720 can be connected to a computing device such as a computer, and then, when the computing device executes the computer instructions 710 stored on the computer-readable storage medium 720, the various methods described above can be performed.

[0111] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The term “such as / for example” as used herein refers to the phrase “such as / for example but not limited to,” and is used interchangeably with it.

[0112] The flowcharts and method descriptions in this disclosure are merely illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the given order. As those skilled in the art will recognize, the steps in the above embodiments can be performed in any order. Words such as "then," "next," etc., are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods. Furthermore, any reference to a singular element, such as the use of the articles "a," "one," or "the," is not to be construed as limiting that element to the singular.

[0113] Furthermore, the steps and apparatus in the various embodiments herein are not limited to any one embodiment. In fact, new embodiments can be conceived by combining relevant steps and apparatus in the various embodiments herein based on the concepts of this disclosure, and these new embodiments are also included within the scope of this disclosure.

[0114] The above methods can be implemented in hardware, software, firmware, or any combination thereof.

[0115] This disclosure may also include a computer program product capable of performing the methods, steps, and operations given herein. For example, such a computer program product may be a computer software package, computer code instructions, or a computer-readable tangible medium having computer instructions tangibly stored (and / or encoded) thereon, which can be executed by a processor to perform the operations described herein. The computer program product may include packaging materials.

[0116] Furthermore, modules and / or other suitable means for carrying out the methods and techniques described herein can be downloaded from a server wirelessly when appropriate. Alternatively, the various methods described herein can be provided via a storage component so that the various methods are available when coupled to the storage component. Additionally, any other suitable techniques for providing the methods and techniques described herein to the device can be utilized.

[0117] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit at least one embodiment of the present disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A processing apparatus for a chip, comprising: The receiving module is configured to receive a first instruction from a register for repeated execution by the computing unit before receiving instructions for a computing task in response to the chip being started. The selected module is configured as follows: In response to the receiving module not receiving the instruction for the computing task for a predetermined time, the first instruction is output and executed by the computing unit; In response to the receiving module receiving the instruction of the computing task, the receiving module outputs the instruction of the computing task, and the computing unit stops executing the first instruction and executes the instruction of the computing task. The instruction generation module is configured to generate the first instruction based on configuration information and provide the first instruction to the receiving module. The configuration information includes multiple power consumption modes, which are implemented using a toggle rate, where the toggle rate is the number of times the signal level toggles per unit time. The first instruction is generated once according to the configuration information and is always stored in the register. The pattern generation module is configured to generate, based on the first instruction, a data sequence required by the computing unit when executing the first instruction, corresponding to the configuration information.

2. The apparatus of claim 1, wherein, The receiving module is further configured to: Between receiving instructions for the computing task, the first instruction is received for execution by the computing unit.

3. The apparatus of claim 1, wherein, The current value or power consumption value generated by the computing unit executing the first instruction is less than or equal to the current value or power consumption value generated by the computing unit executing the instruction of the computing task.

4. The apparatus according to claim 1, further comprising: The configuration information storage module is configured to store the configuration information.

5. A method for processing a chip, comprising: In response to the chip being started, before receiving instructions for computing tasks, a first instruction is received from a register for repeated execution by the computing unit, wherein the first instruction is generated based on configuration information, wherein the configuration information includes multiple power consumption modes, wherein the multiple power consumption modes are implemented using a toggle rate, wherein the toggle rate is the number of times the signal level toggles per unit time, wherein the first instruction is generated once according to the configuration information, and the first instruction is always stored in the register; Based on the first instruction, generate a data sequence corresponding to the configuration information required by the computing unit when executing the first instruction; If no instruction for the computing task is received for a predetermined time, the first instruction is executed; In response to receiving the instruction from the computing task, the execution of the first instruction is stopped, and the instruction from the computing task is executed.

6. The treatment method of claim 5, wherein, The receiving of the first instruction further includes: Between receiving instructions for the computing task, the first instruction is received for execution.

7. An electronic device, comprising: Memory, used to store computer instructions; At least one processor is configured to read computer instructions from the memory and execute the processing method according to any one of claims 5-6.

8. A non-transitory computer-readable storage medium having computer instructions stored thereon, in, When the computer instructions are executed by the processor, the processor performs the processing method according to any one of claims 5-6.

9. A chip, comprising: Processing apparatus for a chip according to any one of claims 1-4; as well as One or more of the aforementioned computing units.

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