Synchronous write aggregation

Abstract

The present disclosure relates to synchronous write aggregation. A memory system includes a firmware unit and a cache module including a cache controller and a cache memory. The cache controller receives an I / O message including a local message ID (LMID) and data to be written to a logical drive (LD), stores the data in a cache segment (CS) row of the cache memory, and sends an ID of the CS row to the firmware unit. The firmware unit, in response to receiving the ID of the CS row, acquires a timestamp and stores the timestamp for the CS row for checking against a cache flush timeout. The firmware unit periodically checks a cache flush timeout and, in response to detecting the cache flush timeout, sends a flush command to the cache controller with the ID of the CS row. The cache controller, in response to receiving the flush command, flushes first data of the CS row.

Description

Technical Field

[0001] This description generally relates to cache controllers, and more specifically, to write aggregation of write-through I / O. Background Technology

[0002] When executing I / O messages to write data to a drive, write aggregation is used to execute two or more I / O message requests in one step to write data together to the same row of the same drive. The data for two or more data writes to the same row of the same drive can be stored by the cache controller in a cache segment (CS) row in the cache memory. Additionally, each I / O message has a timeout. The firmware unit communicating with the cache controller checks the timeout. When the timeout is nearing its end, the firmware unit provides instructions to the cache controller to flush the data to the drive. When a CS row becomes completely dirty, for example, when it is filled with new data, the cache controller performs an active flush of the CS row to the drive. Maintaining synchronization between the cache controller and the firmware unit and resolving stale data are highly desirable. Summary of the Invention

[0003] In one aspect, this disclosure provides a memory system comprising: a firmware unit; and a cache module including a cache controller and a cache memory, the cache controller being configured to: receive a first I / O message including a Local Message ID (LMID) and first data, store the first data in a cache segment (CS) line of the cache memory, and send an ID of the CS line to the firmware unit; and wherein the firmware unit is configured to provide firmware instructions to: in response to receiving the ID of the CS line, obtain a timestamp of the ID of the CS line; store the timestamp, and periodically check for cache refresh timeouts, and in response to detecting a cache refresh timeout, send a refresh command having the ID of the CS line to the cache controller, wherein in response to receiving the refresh command, the cache controller is configured to refresh the first data of the CS line.

[0004] In another aspect, this disclosure provides a memory system comprising: a firmware unit; and a cache module including a cache controller and a cache memory; wherein the cache controller is configured to: receive an I / O message including data and a Local Message ID (LMID); store the data of the I / O message in a cache segment (CS) row of the cache memory; generate a Parity Independent Redundancy Array Request (PRRQ) with an active refresh bit set to 1 in response to the CS row being completely dirty; store the PRRQ in an LM buffer corresponding to the LMID such that the LMID is a PRRQ LMID; refresh the data in the CS row; and send a refresh complete message having the PRRQ LMID to the firmware unit in response to the active refresh bit being set to 1.

[0005] In another aspect, this disclosure provides a memory system comprising: a firmware unit; and a cache module including a cache controller, a cache memory, and an I / O dispatcher module; wherein the cache controller is configured to: receive a first I / O message to be written to a logical drive (LD), wherein the first I / O message includes a first local message ID (LMID) and first data; retrieve the LD and its row number from the first LMID of the first I / O message to be written to the LD; store the first data of the first I / O message in a cache segment (CS) row of the cache memory; merge the ID of the CS row and the LMID into a write pending list corresponding to the CS row; and send a message including the ID of the CS row... Send to the firmware unit; and wherein the firmware unit is configured to provide firmware instructions to: in response to receiving the ID of the CS line, save a timestamp for the CS line to check for cache refresh timeout, periodically check the cache refresh timeout, in response to an active refresh of the CS line of the cache memory by the cache controller, and before detecting the cache refresh timeout, receive a refresh completion message and the first LMID from the I / O dispatcher module, and in response to receiving the refresh completion message, extract the ID of the CS line based on the first LMID, clean the firmware context, and send a cache update message containing the first LMID to the cache controller to: clean the CS line, and generate an I / O completion message. Attached Figure Description

[0006] Certain features of the present technology are set forth in the appended claims. However, for purposes of explanation, several aspects of the present technology are depicted in the following figures.

[0007] Figure 1A and1B Explain the memory system and the Local Message (LM) buffer.

[0008] Figure 2 This describes a memory system based on various aspects of the present technology.

[0009] Figure 3A and 3B This describes the message passing of modules in a memory system according to various aspects of this technology. Detailed Implementation

[0010] The detailed description set forth below is intended to describe various configurations of the present technology and is not intended to represent the only configuration in which the present technology can be practiced. The accompanying drawings are incorporated herein and form part of the detailed description, which contains specific details for providing a thorough understanding of the present technology. However, the present technology is not limited to the specific details set forth herein and can be practiced without one or more of the specific details. In some instances, structures and components are shown in block diagram form to avoid obscuring the concepts of the present technology.

[0011] When an element is referred to herein as “connected” or “coupled” to another element, it should be understood that the element may be directly connected to the other element, or that there may be an intermediary element between the elements. In contrast, when an element is referred to as “directly connected” or “directly coupled” to another element, it should be understood that there is no intermediary element in the “direct” connection between the elements. However, the presence of a direct connection does not preclude the possibility of other connections in which there may be intermediary elements.

[0012] When performing I / O messaging to write data to a driver, write aggregation is used to gather data from multiple writes to a single row and perform the write in one step to save time. In some embodiments, the data of a row is stored in a CS line of cache memory, where one CS line corresponds to a row in the driver, before being written to the driver. In some embodiments, the CS line of cache memory is allocated before being written to the cache memory. Additionally, since each I / O message has a timeout, and the hardware (e.g., the cache controller) does not have a timer, the timer is implemented by a firmware unit that communicates with the cache controller. The firmware unit checks that the timeout has not expired, for example, and confirms that it has not expired. Approximately when the timeout expires, the firmware unit commands the cache controller to flush the data in the CS line to the driver. Additionally, when the CS line becomes completely dirty, for example, when the CS line is filled with new data, the data in the CS line is also flushed to the driver. The cache controller then performs an active flush of the CS line to the driver and notifies the firmware unit that the data in the CS line has been flushed to the driver. Because hardware operations are faster than firmware operations performed based on command / message queues, synchronization between the cache module and the firmware unit is lost in some embodiments. In some embodiments, the data in the CS line is committed, for example, written to the drive, by flushing the CS line to the drive. In some embodiments, after the data in the CS line is committed to the drive, the CS line is cleaned up, for example, the CS line is marked as clean so that new data can be rewritten in the CS line.

[0013] Additionally, if the cache controller performs CS line cleanup after the CS line is flushed to the driver, the firmware unit can access data that is not present in the cache memory. Furthermore, the host (e.g., the processor) is unaware of the CS line, and therefore, I / O messages refer to logical drives (LDs) and their line numbers. To detect I / O message timeouts, the firmware unit receives the LD and its line number, and monitors for timeouts based on the LD (e.g., two bytes) and its line number (e.g., eight bytes). Therefore, timeout data can easily fill the memory associated with the firmware unit, and context exhaustion may occur and write aggregation may stop.

[0014] In the embodiments described below, instead of using the LD and its 10-byte row number to track timeouts for multiple I / O messages, a two-byte Local Message ID (LMID) is used because the number of LM buffers is limited, for example, with 8k LM buffers, and the LM buffer ID can conform to two bytes. In some embodiments, as described above, the CS row ID is added to the LM buffer, which can be accessed (e.g., retrieved) based on the LMID associated with (e.g., involving) a local message buffer or an LM buffer. In some embodiments, a CS row ID conforming to one or more bytes (e.g., three bytes) is used to track timeouts.

[0015] Because the number of LM buffers and CS lines is limited, in some embodiments, LM buffers and CS lines are reused, and therefore, synchronization between the firmware unit and the cache module is addressed below. Although the cache controller can actively flush CS lines when they are completely dirty, the cache controller or any other module of the cache module may not initiate CS line cleanup. In some embodiments, the cache controller sends a message to the firmware unit, and the firmware unit sends instructions for CS line cleanup to the cache module, as described below.

[0016] Figure 1A and 1B This describes memory system 100 and LM buffer 150. Memory system 100 includes cache module 104, memory 106, LM memory 130, and firmware unit 120 including processor 125 and firmware memory 126. In some embodiments, host 102 communicates with firmware unit 120 via a storage controller (not shown) by sending messages containing firmware unit 120 and cache controller 110. In addition to processor 111, host 102 also includes memory 113, such as random access memory. Cache module 104 includes cache controller 110 and cache memory 112. In some embodiments, firmware unit 120 is non-volatile memory or non-volatile memory containing stored firmware instructions. In some embodiments, cache controller 110 sends a request via link 127 to be executed by processor 125 through instructions from firmware unit 120. In some embodiments, firmware unit 120 sends a response back to cache controller 110 via link 127. In some embodiments, memory 106 is a physical drive. In some embodiments, memory 106 is an LD.

[0017] In some embodiments, the cache memory is a collection of cache segment units of 16 kilobytes (kB), 32kB, 48kB, or 64kB. The cache controller 110 includes a cache refresh hardware module 114 (e.g., a cache refresh module), a cache update hardware module 116 (e.g., a cache update module), and an I / O dispatcher module 118. In some embodiments, the cache controller 110 receives and responds to I / O messages via a link 122 to the host 102. In some embodiments, messages or commands from the cache controller 110 require a series of firmware instructions to be executed on the processor 125 of the firmware unit 120. Therefore, the firmware unit 120 and the host 102 execute instructions on separate processors. The firmware unit 120 serves I / O messages from the host 102 via the processor 125 and sends status back to the host 102.

[0018] In some embodiments, messages sent to firmware unit 120 are queued in firmware unit 120's message queue (e.g., instruction queue) and executed one after another. In some embodiments, firmware unit 120 and host 102 have separate memories, such as firmware memory 126 and memory 113. Host 102 sends I / O messages from memory 113, which are received by the storage controller and sent by cache controller 110 to cache memory 112 and / or LM memory 130. In some embodiments, cache controller 110 is part of storage controller, and I / O messages sent from host 102 reach cache memory 112 via link 122, which may include other hardware units that translate host messages.

[0019] like Figure 1A As shown, the I / O dispatcher module 118 sends and receives data to and from the memory 106 via link 124. In some embodiments, the I / O dispatcher module 118 transmits and / or sends commands to the cache update hardware module 116. Furthermore, the cache controller 110 and firmware unit 120 communicate via link 127 and send and receive data. The memory system 100 further shows the firmware unit 120 communicating with and sending and receiving data to the LM memory 130 via link 132, and the cache controller 110 communicating with and sending and receiving data to the LM memory 120 via link 134.

[0020] Figure 1BLM buffers 150, i.e., individual memory cells, are shown within LM memory 130. In some embodiments, each LM buffer has 64 bytes, 128 bytes, or more, and the LM buffers are encapsulated one after another within LM memory 130. Thus, the first LM buffer 150 begins at address 0 (e.g., the beginning) of LM memory 130, and the Nth LM buffer 150 begins at address 128*(N-1) of LM memory 130. In some embodiments, the number of LM buffers 150 in LM memory 130 is 8k or 16k. In some embodiments, LMID is an index of the address or location of LM buffer 150, and therefore, LMID is no more than two bytes. In some embodiments, when cache controller 110 receives an I / O message via link 122, the I / O message contains the LMID and the data to be written to memory 106. Cache controller 110 uses the LMID to access the corresponding LM buffer 150 of LM memory 130 and retrieve (e.g., fetch) the contents of LM buffer 150. The retrieved LM buffer 150 contains the ID (LDID) of the LD at memory location 152 of the LM buffer 150, for example, the address of the LD. Additionally, the retrieved LM buffer 150 contains the row number of the LD at memory location 154. In some embodiments, the LM memory 130 is used by the cache module 104 and the firmware unit 120 communicating with the cache module 104, and therefore, the LM memory 130 is a local memory for messages. Therefore, the LM buffer 150 of the LM memory 130 is a local buffer for messages communicating with the stacked cache modules 104. Therefore, the ID (or LMID) of the LM buffer 150 is an index of the LM buffer 150 in the LM memory 130. Furthermore, the LMID refers to the memory location of the LM buffer in the LM memory 130. Thus, assuming the LM buffer has 128 bytes, the first 128 bytes of the LM memory 130 have IDs of 0, and the Mth 128th bytes of the LM memory 130 are between IDs of M-1.

[0021] In some embodiments, data in an I / O message is copied to the CS line of cache memory 112. In some embodiments, the row ID (e.g., row number) of the CS line is copied to memory location 156 of LM buffer 150. In some embodiments, each LM buffer 150 contains the address (e.g., LMID) of another LM buffer 150, for example, the LMID corresponding to a previous I / O message containing data stored in the CS line. Therefore, based on the tail LMID and the head LMID, a list of links from the last data stored in the CS line to the LMIDs of the first data stored in the CS line can be generated, and the LMIDs of all data in the CS line are accessible. In some embodiments, the LM buffer 150 corresponding to the first LMID does not contain the LMID corresponding to a previous I / O message containing data stored in the CS line, and therefore, the first LMID is the head LMID. In some embodiments, the list of links of LMIDs may be generated based solely on the tail LMID. In some embodiments, the LM buffer 150 in LM memory 130 contains the LDID and the row number of the LD to be accessed in response to receiving an I / O message. In some embodiments, physical memory is accessed based on the row number of the LD. In some embodiments, the cache controller 110 and firmware unit 120 can access the cache memory 112. Therefore, the message 246 to the cache refresh hardware module 114 to refresh data includes a tail LMID, and based on the tail LMID, the entire LMID of the data stored in the CS line is accessible.

[0022] In some embodiments, the write command is loaded by host 102 and executed by processor 111 of host 102, and processor 111 sends the write command to cache refresh hardware module 114. In some embodiments, cache controller 110 receives a first I / O message to write data to a driver having a first LDID and a first row number. As mentioned, the first data in the first I / O message is copied to a CS row (having the ID of the CS row) of cache memory 112, and the LMID of LM buffer 150 of LM memory 130 is added to the write pending list corresponding to the CS row. Then, cache controller 110 receives one or more second I / O messages to write data having the first LDID and the first row number, such that the first I / O message and one or more second I / O messages have the same (e.g., the same) LDID and the same (e.g., the same) row number. The second data in the second one or more I / O messages is copied, for example, by cache controller 110 to the same CS row of cache memory 112 and appended to the first data. A cache refresh timeout occurs before the CS row becomes completely dirty. In response to a cache refresh timeout, a refresh command (e.g., message 246) is sent to the cache refresh hardware module 114 to refresh the data in the CS line to the driver. In some embodiments, a write pending list is generated and maintained for each CS line containing data. The write pending list may contain LMIDs associated with the data in the CS line, such as the LMIDs of a first I / O message and one or more second I / O messages. In some embodiments, a write pending list for each CS line is generated and maintained. In some embodiments, the write pending list for each CS line includes a tail LMID and a head LMID. The tail LMID refers to the LM buffer 150 corresponding to the last data stored in the CS line, and the head LMID refers to the LM buffer 150 corresponding to the first data stored in the CS line. In some embodiments, the timestamp associated with the first I / O message (e.g., the timestamp associated with the CS line) becomes associated with one or more second I / O messages. In some embodiments, commands or messages between the firmware unit 120 and the cache module 104 are transmitted via link 127.

[0023] Figure 2The memory system 200 according to various aspects of the present technology is described. The memory system 200 shows a cache module 104, which includes a cache refresh hardware module 114, a cache update hardware module 116, a cache memory 112, and an I / O dispatcher module 118. Received I / O messages contain an LMID and data to be written to a logic drive 206. As described above, the cache controller 110 receives an I / O message 242 from the host 102, and the data in the I / O message is copied to CS line 226. Based on the LMID, the LM buffer 150 in the LM memory 130 can be accessed, and the LDID and the line number of the LD can be accessed. The cache controller 110 checks whether CS line 226 is completely dirty. If it is not completely dirty, then another I / O message is received. If CS line 226 is completely dirty, then the cache controller 110 sends a publish refresh command 252 and sends the publish refresh command 252 to the I / O dispatcher module 118.

[0024] Upon receiving an I / O message, message 262, along with the ID of the CS line corresponding to CS line 226, is sent to firmware unit 120 to instruct firmware unit 120 to retrieve the timestamp of CS line 226 and store the timestamp in firmware memory 126 of firmware unit 120. Therefore, for each first received I / O message on a new line of LD, the timestamp is associated with the ID of the CS line. The LMID and the corresponding ID of the CS line are stored in an item in the write-pending list managed by the cache. In some embodiments, the CS line has a timeout, through which the timeout data must be flushed and the I / O must be completed and returned to the host, for example, a cache flush timeout. The timestamp of the CS line of the I / O message is periodically (e.g., repeated at constant intervals) checked by firmware unit 120 for timeouts.

[0025] In some embodiments, the issue refresh command 252 includes a Parity Redundant Array of Independent Disks (RAID) Request (PRRQ) containing an active refresh bit. In response to the issue refresh command 252 initiated by cache controller 110, the active refresh bit is set to 1 by cache controller 110 because CS line 226 is completely dirty. Upon I / O completion, I / O dispatcher module 118 checks whether the active refresh bit 222 is set to 1. If the active refresh bit 222 is set to 1, then I / O dispatcher module 118 sends a refresh completion message 256 (e.g., a command) to firmware unit 120. If the active refresh bit 222 is not set to 1, for example, if it is set to 0, then the I / O dispatcher module 118 sends a cache update message 254 (e.g., a command) to the cache update hardware module 116 to clean up the CS line 226 and generate an I / O completion message 244, and sends the I / O completion message 244 to the host 102 to indicate that the I / O message 242 is complete and the data has been committed to the logical drive 206. Regardless of whether the active refresh bit 222 is 0 or 1, the I / O dispatcher module 118 sends the data to the logical drive 206 via the communication link 263 for writing to the drive. In some embodiments, the I / O dispatcher module 118 stores the PRRQ in the LM buffer 150 corresponding to the LMID and changes the type to PRRQ LMID.

[0026] In some embodiments, when the active refresh bit 222 is not set in the refresh message, the cache update hardware module 116 receives the cache update message 254 from the I / O dispatcher. In this aspect of the technology, the cache controller further receives one or more second I / O messages. The LDID and row number of the second I / O message are the same as the LDID and row number of the first I / O message. The cache controller also stores the second data of the one or more second I / O messages in the CS row of the cache memory. A cache refresh timeout is detected before the CS row becomes completely dirty, and in response to the detection of the cache refresh timeout, a refresh command is sent to the cache controller.

[0027] Firmware unit 120 receives message 262 from cache module 104 and creates context 216. As described, message 262 contains the ID of the CS row storing I / O message 242. In some embodiments, context 216 is a table containing the IDs of the CS rows of I / O message 242, and the table is created in firmware memory 126. For each entry, the table also contains one or more timestamps associated with the CS row ID (e.g., the ID of the CS row), for example, the time when one or more I / O messages were received. Therefore, the one or more I / O messages associated with the CS row are the I / O messages stored in the CS row. Firmware unit 120 checks (e.g., periodically checks) the timestamps associated with the CS row ID, which contain expired (e.g., expired or timed out) data. In response to the expiration of the timestamp associated with the ID of CS line 226, firmware unit 120 sends a message 246 containing the tail (e.g., last) LMID in the write pending list of the ID of CS line 226 associated with (e.g., related to) the expiration timestamp. Firmware unit 120 instructs cache refresh hardware module 114 to refresh the data in CS line 226 of cache memory 112. In some embodiments, when more than one piece of data in an I / O message is in CS line 226, the expiration timestamp is used for the earliest received I / O message; however, the entire data in CS line 226 is refreshed. In some embodiments, the earliest timestamp of the data in CS line 226 is either the timestamp of CS line 226 or the timestamp associated with CS line 226.

[0028] In some embodiments, cache refresh hardware module 114 derives the ID of LD (e.g., LDID) and the ID of CS line 226 from LMID, generates a message 258 containing a Parity Redundancy Array of Independent Disks (PRRQ) request with an active refresh bit 222 set to 0, and sends message 258 to I / O dispatcher module 118. Because the active refresh bit 222 is set to 0, I / O dispatcher module 118 sends cache update message 254 to cache update hardware module 116, as described above. In some embodiments, firmware unit 120 periodically checks the timestamp approximately every 80 milliseconds (msec) to approximately every 150 msec, within approximately 5%. In some embodiments, Redundancy Array of Independent Disks (RAID) is configured to use disk striping with parity. Because data and parity are striped uniformly across all disks, no single disk is a bottleneck. Striping also allows users to reconstruct data in the event of disk failure. Therefore, the PRRQ instructs the I / O dispatcher module 118 on how to allocate the data to be stored on the disk array and how to generate parity. In some embodiments, the PRRQ is stored in the LM buffer 150 and accessed based on the LMID of the LM buffer 150 (e.g., the PRRQ LMID). In some embodiments, the LMID has a different type depending on the data in the LM buffer 150 to which the LMID relates. Therefore, the LMID of the LM buffer 150 containing the PRRQ can be a PRRQ LMID, for example, an LMID of type PRRQ. In some embodiments, receiving a command containing a PRRQ is receiving a command containing a PRRQ LMID, and the PRRQ is accessible in the LM buffer 150 associated with the PRRQ LMID.

[0029] When the ID of a CS line has been waiting for longer than the cache refresh timeout in firmware unit 120, or when refresh completion message 256 is received by firmware unit 120, the cleanup module 214 of the firmware unit is instructed to clean up the firmware context corresponding to the CS line ID, for example, CS line 226. In the case where refresh completion message 256 is received by firmware unit 120, when an active refresh is performed via cache controller 110, the cleanup module 214 sends a message or command (e.g., cache update message 248) to cache update hardware module 116. In response, cache update hardware module 116 cleans up CS line 226 and generates I / O completion message 244, and sends I / O completion message 244 to host 102 to indicate that I / O message 242 is complete and data has been committed to logical driver 206.

[0030] Figure 3A and 3B This describes the message passing of modules in a memory system according to various aspects of this technology. Figure 3A and 3B and Figure 2 Consistent. Figure 3A The steps arranged in time 324 are shown, corresponding to the detection of a timeout (e.g., cache refresh timeout) in firmware unit 120, and I / O message 242 from host 102 to cache module 104 is shown. Then, at step 306, cache module 104 sends message 262 (write aggregation message) to firmware unit 120 to monitor the timeout. As previously mentioned, commands or messages between firmware unit 120 and cache module 104 are transmitted via link 127. After the timeout, for example, when the timestamp of the ID of the CS row wait time in the firmware has exceeded the cache refresh timeout, for example, when a timeout has occurred, firmware unit 120 sends message 246 to cache refresh hardware module 114 to refresh the data. In step 310, firmware unit 120 cleans up a portion of the firmware memory 126 associated with firmware unit 120 and removes the contents of the table associated with the ID of the CS row of the refreshed data. At step 320, the I / O dispatcher module 118 sends data to the logic driver 206 via communication link 263 for writing to the driver. Again, the I / O dispatcher module 118 sends a cache update message 254 to the cache update hardware module 116 of the cache module 104 and sends an I / O completion message 244 to the host 102 to indicate that I / O message 242 has completed. In some embodiments, the cache refresh timeout is 30 to 40%, shorter than the I / O timeout.

[0031] Figure 3B The steps arranged in time 324 are also shown, corresponding to the condition that the CS line becomes completely dirty, for example, when all data is new and has been committed to the drive. Firmware unit 120 shows I / O message 242 from host 102 to cache module 104. When the data in I / O message 242 is stitched into the cache, the cache module checks whether the CS line is completely dirty in step 332 and refreshes the CS line in step 320, for example, through active refresh by cache controller 110. Since the active refresh bit is set to 1, refresh complete message 256 is sent by I / O dispatcher module 118 to firmware unit 120 for cleanup, and in response, firmware unit sends cache update message 248, as described above.

[0032] The technique discussed above reduces the context exhaustion of the firmware unit's memory. Furthermore, this technique resolves the synchronization problem between the firmware unit and the cache module, and addresses the issue of stale data because the firmware unit performs cache cleanup.

[0033] According to an aspect of this technology, a memory system includes a firmware unit and a cache module including a cache controller and a cache memory. The cache controller receives a first I / O message containing an LMID and first data. The cache controller also stores the first data in a CS row of the cache memory and sends the ID of the CS row to the firmware unit. The firmware unit provides firmware instructions that, in response to receiving the CS row ID, acquire and store a timestamp of the CS row ID. The timestamp is periodically checked for cache refresh timeouts. In response to detecting a cache refresh timeout, a refresh command with the CS row ID is sent to the cache controller to instruct the cache controller to refresh the first data in the CS row.

[0034] In this aspect of the technology, the cache controller further extracts the LMID and first data of the first I / O message, allocates a CS line for the first data, and stores the LMID and the ID of the CS line in a write pending list, wherein the LMID can be accessed based on the ID of the CS line. In this aspect of the technology, a periodic check for cache refresh timeout is performed approximately every 100ms, and when the cache refresh timeout expires, a refresh command is provided to the cache controller via firmware instructions, wherein the firmware instructions contain the ID of the CS line and an active refresh bit set to 0. In this aspect of the technology, the cache controller module further includes an I / O dispatcher module and a cache refresh module. The cache refresh module receives a refresh command with the ID of the CS line from the firmware and sends the refresh command with the ID of the CS line to the I / O dispatcher module to refresh the first data in the CS line. The refresh command contains the LMID of a Parity Redundant Array of Independent Disks (PRRQ) type. In this aspect of the technology, the cache module further includes an I / O dispatcher module, which extracts the PRRQ LMID from the refresh command, retrieves the ID of the logical drive (LD) and the row number of the LD based on the PRRQ LMID as the location to which the first data is refreshed, and refreshes the first data in the CS row to the physical destination disk based on the row number of the LD. In this aspect of the technology, the cache module further includes a cache update module. In response to receiving a refresh complete message from the I / O dispatcher module, the I / O dispatcher module detects the active refresh bit based on the PRRQ LMID. In response to detecting that the active refresh bit is set to 0, the I / O dispatcher module sends a cache update message to the cache update module. In response to the cache update message, the cache update module indeed cleans up the CS row and generates an I / O complete message.

[0035] According to this technology, a memory system includes a firmware unit and a cache module including a cache controller and a cache memory. The cache controller receives I / O messages containing data and a Local Message ID (LMID), stores the data of the I / O message in a CS row of the cache memory, and in response to a CS row being completely dirty, generates a Parity Redundancy Array Request (PRRQ) with an active refresh bit set to 1 and a PRRQ LMID, stores the PRRQ in an LM buffer corresponding to the PRRQ LMID, and refreshes the data in the CS row. Furthermore, in response to the active refresh bit being set to 1, a refresh complete message with the PRRQ LMID is sent to the firmware unit.

[0036] In this aspect of the technology, the cache module further includes a cache update hardware module. In response to receiving a refresh complete message, the firmware unit extracts the PRRQ LMID and provides a cache update message and the PRRQ LMID to the cache update module via firmware instructions executable by the firmware unit's processor, requests cleanup of CS lines, and generates an I / O complete message. In this aspect of the technology, the firmware unit receives the ID of the CS line from the cache module, stores a timestamp for the CS line in response to receiving the CS line ID for checking for cache refresh timeout, periodically checks for cache refresh timeout based on the timestamp, and receives a refresh complete message from the I / O dispatcher before detecting a cache refresh timeout. In this aspect of the technology, the cache module further includes an I / O dispatcher module. The I / O dispatcher receives a refresh command, retrieves the PRRQ LMID, retrieves the PRRQ and logical driver (LD) ID and the LD's row number as the location for refreshing data based on the PRRQ LMID, and refreshes the data in the CS line to the LD's row number. Furthermore, in response to the completion of the refresh, a refresh completion message with a PRRQ LMID is sent to the firmware unit. In this aspect of the technology, the I / O dispatcher module extracts the PRRQ LMID corresponding to the CS line, retrieves the logical drive (LD) ID and the LD's row number from the PRRQ LMID as the location of the refresh data, determines the destination disk, and refreshes the data in the CS line to the physical destination based on the LD's row number. In this aspect of the technology, the cache controller generates and maintains a write pending list in the cache memory. The write pending list contains a list of LMIDs associated with one or more I / O messages for each CS line. In this aspect of the technology, the I / O message is the writing of data to the LD.

[0037] According to an aspect of this technology, a memory system includes a firmware unit and a cache module including a cache controller, a cache memory, and an I / O dispatcher module. The cache controller receives a first I / O message to be written to an LD. The first I / O message includes a first LMID and first data. The cache controller further retrieves the LD and its row number from the first LMID of the first I / O message to be written to the LD, stores the data of the first I / O message in a CS row of the cache memory, merges the CS row ID and LMID into a write pending list corresponding to the CS row, sends a message containing the CS row ID to the firmware unit, and the firmware unit provides firmware instructions to save a timestamp for the CS row in response to receiving the first CS row ID, and to check for cache refresh timeout in response to receiving the CS row ID. The cache refresh timeout is checked periodically, and in response to an active refresh of the CS row of the cache memory by the cache controller and before a cache refresh timeout is detected, a refresh completion message and the first LMID are received from the I / O dispatcher module. In addition, in response to receiving the refresh completion message, the ID of the CS line is extracted based on the first LMID, the firmware context is cleaned up, and a cache update message containing the first LMID is sent to the cache controller to clean up the CS line, and an I / O completion message is generated.

[0038] In this aspect of the technology, the cache module further includes a cache update hardware module. The cache update hardware module cleans up the CS line and generates an I / O completion message. In this aspect of the technology, the cache controller receives one or more second I / O messages to write to a drive containing one or more second LMIDs and second data. The one or more second LMIDs contain the same LD and the same row number as the first LMID, and a write pending list corresponding to the CS line is generated and maintained, which contains a list of one or more LMIDs associated with the first I / O message and one or more second I / O messages of the CS line, the list containing first data of the first I / O message and second data of one or more second I / O messages corresponding to the same row number of the same LD. In one aspect of this technology, the I / O dispatcher module receives a PRRQ with the active refresh bit set to 1, retrieves the LMID, retrieves the logical driver (LD) ID and the row number of the LD from the first LMID as the location to refresh the first data, and refreshes the first data in the CS row to the row number of the LD. Upon completion of the refresh, it sends a refresh completion message with the first LMID related to the PRRQ to the firmware unit. In another aspect of this technology, in response to the CS row being completely dirty, the cache controller generates a PRRQ with the active refresh bit set to 1 and sends the PRRQ and data to the I / O dispatcher module to refresh the data in the CS row. In yet another aspect of this technology, the I / O dispatcher module receives a PRRQ with the active refresh bit set to 0 and sends a cache update message to the cache update hardware module to clean the CS row and generate an I / O completion message.

[0039] Those skilled in the art will understand that the various illustrative blocks, modules, elements, components, memory systems, and algorithms described herein can be implemented as electronic hardware, computer software, or a combination of both. To illustrate this hardware-software interchangeability, the various illustrative blocks, modules, elements, components, memory systems, and algorithms have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the overall system. Skilled technicians can implement the described functionality in different ways for each specific application. Various components and blocks can be arranged differently (e.g., in different orders or divided in different ways), all without departing from the scope of this art.

[0040] It should be understood that any particular order or hierarchy of blocks in the disclosed process is a specification of the example method. Based on design preferences, it should be understood that a particular order or hierarchy of blocks in the process may be rearranged, or all specified blocks may be executed. Any of the blocks may be executed simultaneously. In one or more embodiments, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together as a single software product or packaged as multiple software products.

[0041] As used in this specification and any claim of this application, the terms "base station," "receiver," "computer," "server," "processor," and "memory" refer to electronic or other technological devices. These terms exclude persons or groups of people. For the purposes of this specification, the term "display" means displaying on an electronic device.

[0042] As used herein, the phrase “at least one of…” preceding a series of items, where the terms “and” or “or” are used to separate any of the items, modifies the list as a whole, not each member of the list (i.e., each item). The phrase “at least one of…” does not require selection of at least one of every listed items; rather, the phrase allows for the inclusion of at least one of any of the items, and / or at least one of any combination of items, and / or at least one of each of the items. For example, the phrases “at least one of A, B, and C” and “at least one of A, B, or C” respectively refer to only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.

[0043] The predicates “configured to,” “operable to,” and “programmed to” do not imply any specific tangible or intangible modification of the subject, but are intended to be used interchangeably. In one or more embodiments, a processor configured to monitor and control operation or components may also mean a processor programmed to monitor and control operation or an operable processor to monitor and control operation. Similarly, a processor configured to execute code can be interpreted as a processor programmed to execute code or an operable processor to execute code.

[0044] Phrases such as “aspect,” “the aspect,” “on the other hand,” “some aspects,” “one or more aspects,” “implementation,” “the implementation,” “another implementation,” “some implementations,” “one or more implementations,” “embodiment,” “the embodiment,” “another embodiment,” “some embodiments,” “one or more embodiments,” “configuration,” “the configuration,” “another configuration,” “some configurations,” “one or more configurations,” “the technology,” “the disclosure,” “this disclosure,” and other variations and similar expressions are used for convenience and do not imply that disclosures associated with such phrases are essential to the technology or that such disclosures apply to all configurations of the technology. Disclosures associated with such phrases may apply to all configurations or one or more configurations. Disclosures associated with such phrases may provide one or more instances. For example, the phrase “aspect” or “some aspects” may refer to one or more aspects, and vice versa, and this similarly applies to other foregoing phrases.

[0045] The term “exemplary” as used herein means “serving as an example, illustration, or description.” Any embodiment described herein as “exemplary” or “example” is not necessarily to be construed as being more preferred or advantageous than other embodiments. Furthermore, where the terms “comprising,” “having,” or similar are used in the description or claims, such terms are intended to be comprehensive in a manner similar to how the term “comprising” is interpreted when used as a transitional word in the claims.

[0046] All structural and functional equivalents of elements throughout the various aspects described herein that are known or subsequently known to a person skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be made public, whether or not such disclosure is expressly stated in the claims. No claim element will be interpreted in accordance with 35 U.S.SC §112(f) unless the element is expressly stated using the phrase “component for…” or, in the case of a memory system claim, the element is stated using the phrase “step for…”.

[0047] The foregoing description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects presented herein, but should conform to the full scope consistent with the language of the claims, wherein elements referred to in the singular are not intended to mean “one and only one,” but rather “one or more,” unless expressly stated otherwise. Unless expressly stated otherwise, the term “some” refers to one or more. Masculine pronouns (e.g., his) include feminine and neuter pronouns (e.g., her and its), and vice versa. Titles and subtitles (if any) are used for convenience only and do not limit this disclosure.

Claims

1. A memory system comprising: Firmware unit; and A cache module includes a cache controller and a cache memory, wherein the cache controller is configured to: Receive the first I / O message, which includes the local message ID (LMID) and the first data. The first data is stored in the cache segment CS line of the cache memory, and Send the ID of the CS line to the firmware unit; and The firmware unit is configured to provide firmware instructions to: In response to receiving the ID of the CS row, obtain the timestamp of the ID of the CS row; Store the timestamp, and Periodically check cache refresh timeout. In response to detecting the cache refresh timeout, a refresh command having the ID of the CS row is sent to the cache controller, wherein in response to receiving the refresh command, the cache controller is configured to refresh the first data of the CS row; and The cache controller is configured to extract the LMID and the first data of the first I / O message, allocate a CS line for the first data, and store the LMID and the ID of the CS line in a write pending list of the CS line, wherein the LMID can be accessed based on the ID of the CS line.

2. The memory system of claim 1, wherein the periodic check for cache refresh timeout is performed approximately every 100 milliseconds, wherein upon the expiration of the cache refresh timeout, the refresh command is provided to the cache controller via firmware instructions, and wherein the firmware instructions include the ID of the CS line and an active refresh bit set to 0.

3. The memory system according to claim 1, wherein the cache module further comprises an I / O dispatcher module and a cache refresh module, wherein the cache refresh module is configured to: Receive the refresh command including the ID of the CS row, and The refresh command having the ID of the CS row is sent to the I / O dispatcher module to refresh the first data of the CS row, wherein the refresh command includes an LMID of type Parity Independent Redundant Array of Disks Request (PRRQ).

4. The memory system of claim 3, wherein the I / O dispatcher module is configured to: Extract the PRRQ LMID from the refresh command. Based on the PRRQ LMID, the ID of the logic driver LD and the row number of the LD are retrieved as the position to which the first data is refreshed. The first data in the CS row is refreshed to the physical destination based on the row number of the LD.

5. The memory system of claim 4, wherein the cache module further comprises a cache update module, wherein in response to receiving a refresh completion message by the I / O dispatcher module, an active refresh bit is detected based on the PRRQ LMID, wherein in response to detecting that the active refresh bit is set to 0, the I / O dispatcher module further sends a cache update message to the cache update module, and wherein in response to the cache update message, the cache update module is configured to: Clean up the CS line, and Generate an I / O completion message.

6. The memory system of claim 1, wherein the cache controller is further configured to receive one or more second I / O messages, and wherein the LDID and row number of the second I / O message are the same as the LDID and row number of the first I / O message; and The cache controller is further configured to store the second data of the one or more second I / O messages in the CS line of the cache memory, wherein the cache refresh timeout is detected before the CS line becomes completely dirty, and wherein in response to the detection of the cache refresh timeout, the refresh command is sent to the cache controller.

7. A memory system comprising: Firmware unit; and A cache module, which includes a cache controller and a cache memory; The cache controller is configured to: Receive I / O messages including data and Local Message ID (LMID). The data of the I / O message is stored in the cache segment CS line of the cache memory. In response to the CS row being completely dirty, a Parity Independent Redundancy Array Request (PRRQ) with an active refresh bit set to 1 and a PRRQ LMID are generated. The PRRQ is stored in an LM buffer corresponding to the PRRQ LMID, and the data in the CS row is refreshed. In response to the active refresh bit being set to 1, a refresh complete message with the PRRQ LMID is sent to the firmware unit.

8. The memory system of claim 7, wherein the cache module further includes a cache update module, and wherein the firmware unit is configured to: In response to receiving the refresh completion message, the PRRQ LMID is extracted, and a cache update message and the PRRQ LMID are provided to the cache update module via firmware instructions executable by the processor of the firmware unit, and a request is made: Clean up the CS line, and Generate an I / O completion message.

9. The memory system of claim 7, wherein the firmware unit is further configured to: Receive the ID of the CS line from the cache module. In response to receiving the ID of the CS line, a timestamp is stored for the CS line to check for cache refresh timeout. The cache refresh timeout is periodically checked based on the timestamp, and Before the cache refresh timeout is detected, the refresh complete message is received from the I / O dispatcher.

10. The memory system of claim 7, wherein the cache module further comprises an I / O dispatcher module, and the I / O dispatcher module is configured to: Receive the publish refresh command. Retrieve the PRRQ LMID, and based on the PRRQ LMID, retrieve the PRRQ, the logic driver LD ID, and the row number of the LD as the location to refresh the data. The data in the CS row is refreshed to the row number of the LD, and In response to the completion of the refresh, a refresh completion message with the PRRQ LMID is sent to the firmware unit.

11. The memory system of claim 10, wherein the I / O dispatcher module is configured to: Extract the PRRQ LMID corresponding to the CS row. Retrieve the logical drive LD ID and the row number of the LD from the PRRQ LMID as the location to refresh the data and determine the destination disk. The data in the CS row is refreshed to the physical destination based on the row number of the LD.

12. The memory system of claim 7, wherein the cache controller is further configured to generate and maintain a write pending list in the cache memory, wherein the write pending list includes a list of LMIDs associated with one or more I / O messages for each CS line.

13. The memory system of claim 7, wherein the I / O message is writing data to a logic driver.

14. A memory system comprising: Firmware unit; and The cache module includes a cache controller, a cache memory, and an I / O dispatcher module; The cache controller is configured to: Receive a first I / O message to be written to the logic drive LD, wherein the first I / O message includes a first local message ID (LMID) and first data. Retrieve the LD and its row number from the first LMID of the first I / O message to be written to the LD. The first data of the first I / O message is stored in the cache segment CS line of the cache memory. The ID of the CS line and the LMID are merged into the write pending list corresponding to the CS line, and a message including the ID of the CS line is sent to the firmware unit; and The firmware unit is configured to provide firmware instructions to: In response to receiving the ID of the CS line, a timestamp is saved for the CS line for checking for cache refresh timeout. Periodically check the cache refresh timeout. In response to an active refresh of the CS line of the cache memory by the cache controller, and before a cache refresh timeout is detected, a refresh completion message and the first LMID are received from the I / O dispatcher module. In response to receiving the refresh complete message, the ID of the CS line is extracted based on the first LMID, the firmware context is cleaned, and a cache update message containing the first LMID is sent to the cache controller to: Clean up the CS line, and Generate an I / O completion message.

15. The memory system of claim 14, wherein the cache module further includes a cache update module, and wherein the cache update module is configured to clean the CS line and generate the I / O completion message.

16. The memory system of claim 14, wherein the cache controller is further configured to: Receive one or more second I / O messages to write to a driver including one or more second LMIDs and second data, wherein the one or more second LMIDs include the same LD corresponding to the ID of the CS row of the first LMID and the same row number of the LD; and Generate and maintain the write pending list corresponding to the CS row, which includes a list of one or more LMIDs associated with the first I / O message and the one or more second I / O messages of the CS row, the list including the first data of the first I / O message and the second data of the one or more second I / O messages corresponding to the same row number of the same LD.

17. The memory system of claim 14, wherein the I / O dispatcher module is further configured to: Receive a Parity Independent Redundancy Array Request (PRRQ) with the Active Refresh bit set to 1. Retrieve the first LMID, retrieve the logic driver LD ID and the row number of the LD from the first LMID as the position to refresh the first data, and The first data in the CS row is refreshed to the row number of the LD, and when the refresh is complete, the refresh completion message having the first LMID involving the PRRQ is sent to the firmware unit.

18. The memory system of claim 17, wherein the cache controller is further configured to: In response to the CS line being completely dirty, a PRRQ is generated with the active refresh bit set to 1, and The PRRQ and the first data are sent to the I / O dispatcher module to refresh the first data in the CS line.

19. The memory system of claim 17, wherein the I / O dispatcher module is further configured to: Receive a Parity Independent Redundancy Array Request (PRRQ) with the Active Refresh bit set to 0, and The cache update message is sent to the cache update module to clean up the CS line and generate the I / O completion message.

Images