Systems and methods for improving operating characteristics of a display

Abstract

Systems and methods for improving operating characteristics of displays such as silicon-based liquid crystal displays.

Description

[0001] This application is a divisional application of Chinese patent application "System and method for improving the operating characteristics of a display" (application number: 201980034984.6), filed on May 24, 2019. Technical Field

[0002] The technical field generally relates to systems and methods for silicon-based liquid crystal displays. Background Technology

[0003] Liquid crystal on silicon (LCOS) displays typically come in two types. The main characteristic of each type lies in the type of circuitry under each pixel of the display: analog and digital.

[0004] In analog displays, the circuitry under each pixel primarily consists of storage capacitors. During operation, analog voltage sources are sequentially connected to the storage capacitors in each pixel to store an analog voltage in the capacitors of each pixel. These stored voltages are also connected to the pixel electrodes corresponding to the pixel.

[0005] The variable voltage on these pixel electrodes then determines the response of the liquid crystal (LC) directly above each of these pixels, and thus ultimately determines (for amplitude displays) the amount of polarization change in the light reflected from that pixel, or (for phase displays) the amount of phase shift applied to the light reflected from that pixel. This variable voltage is an analog quantity, so the resulting modulation of the polarization or phase shift in the LC also varies as an analog quantity.

[0006] For such displays, the reproduction of grayscale images or variable phase shifts is straightforward. Early LCOS displays were essentially analog. However, as pixel sizes decreased, building analog displays became increasingly difficult. This is because very small pixels mean very small pixel capacitors. Since leakage current changes voltage over time, small capacitors cannot maintain the accurate charge for a sufficiently long period for successful display operation.

[0007] Digital LCOS displays are a relatively recent development. They integrate digital memory within each pixel, which can store "1" or "0" states. The pixel electrodes can be set to one of two possible voltages, corresponding to a fully "on" or fully "off" LC state. These "1" or "0" states can be written to the pixel very quickly, and the voltage does not change due to leakage.

[0008] Digital LCOS displays typically achieve grayscale by rapidly writing a series of 1s and 0s to each pixel, causing the LC to alternate between these fully on and fully off states. These changes occur much faster than the eye can process. Therefore, the eye averages the duty cycles of these "off" and "on" conditions to obtain the equivalent grayscale.

[0009] In use, digital LCOS displays typically use some variant of duty cycle modulation (DCM) or pulse width modulation (PWM) encoding to write multiple times during each frame using a “bit plane” of 1s and 0s to achieve the desired equivalent grayscale value.

[0010] Digital pixel designs can be made very small and do not suffer from leakage problems. However, they tend to require more complex pixel circuitry with more transistors. Furthermore, they tend to require higher external data rates for writing large amounts of bit planes per frame.

[0011] Of particular relevance to phase-mode displays is that averaging by the human eye is ineffective because voltage errors at pixels correspond to positional shifts in the image that the human eye cannot average. Therefore, using digital LCOS displays for phase-mode displays is more challenging.

[0012] The phase-mode display can send a sequence of 1 & 0 bit planes fast enough to keep the LC in an intermediate state between fully off and fully on, corresponding to the desired phase shift. Here, the LC does not have time to fully reach either the off or on state.

[0013] However, this method approximates the desired constant phase shift. Furthermore, in reality, various nonlinearities and minimum voltage durations within the system (especially within the LC itself) result in “phase ripple” in the LC’s response to such rapidly changing bit planes. Figure 1 A simulation example of a typical waveform 100 with phase ripple 110 is shown.

[0014] Here, for waveform 100, the first 2ms of the frame are required to reach a phase shift value close to the desired value 120. Then, the phase level of waveform 100 nominally alternates back and forth around the desired phase shift value 120 (phase ripple 110).

[0015] Furthermore, phase-mode digital LCOS displays typically operate with a fixed Vpix equivalent power supply. This assumes that the voltage across all bit planes should be identical, and this assumption is used in the design of digital LCOS displays. Summary of the Invention

[0016] Various embodiments of this disclosure provide a driving scheme for a display that reduces phase ripple, phase switching noise and phase instability, and improves other operating characteristics.

[0017] Embodiments of this disclosure utilize a driving scheme having an optimal number of on / off bits and their distribution for each grayscale / phase level. By distributing a desired number of on and off values ​​for grayscale or phase values ​​within a frame or subframe, the binary value sequence used to achieve the desired grayscale or phase value during that frame or subframe is optimized such that the on duration occurs substantially equally at intervals throughout the duration of the frame or subframe.

[0018] Therefore, the systems and methods described herein determine optimized sequences of "1" and "0" bit planes that, when sent to a digital LCOS display driven by a phase-mode bit plane, result in grayscale values ​​or phase shift values ​​with minimal phase ripple. For example, for a 6-bit phase-mode display, the systems and methods determine optimized sequences that are applied to each of 64 possible phase shift values ​​defined by a 6-bit phase resolution.

[0019] Embodiments of this disclosure utilize optimized cyclic rotation of bit sequences to minimize 1 / 0 and 0 / 1 transition glitches.

[0020] The embodiments of this disclosure utilize different voltages for each bit plane.

[0021] Specifically, the systems and methods described herein allow for fine-tuning of individual bit-plane voltages, thereby optimizing display performance to minimize phase ripple and thus reduce noise in phase displays. This fine-tuning is accomplished by changing the pixel electrode power supply (Vpix) or by changing the cover glass transparent electrode voltage (Vcom). Changing the Vcom voltage may introduce complications that need to be addressed. Therefore, fine-tuning can be performed solely by adjusting Vpix. However, it is possible to achieve the same purpose by adjusting Vpix, Vcom, or both.

[0022] In all these cases, these adjustments are made by modifying the driving sequence.

[0023] Embodiments of this disclosure can utilize: different voltages for positive and negative Vcom polarities; very high Vcom switching frequencies; latch release synchronized with LC using actual Vcom conjugate flipping; and DC balancing by using an odd number of on / off bits in combination with inter-frame Vcom conjugate and on / off bits (including their rotation) for frame matching for each grayscale / phase level.

[0024] The foregoing has broadly outlined some aspects and features of various embodiments, which should be construed as merely illustrating various potential applications of this disclosure. Other beneficial results can be obtained by applying the disclosed information in different ways or by combining various aspects of the disclosed embodiments. Therefore, in addition to the scope defined by the claims, other aspects and a more complete understanding can be obtained by referring to the detailed description of exemplary embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0025] Figure 1 It is a graphical illustration of the waveform of phase ripple, including existing technologies.

[0026] Figure 2 This is a schematic diagram of a display system including a display driver and a display according to an embodiment of the present invention.

[0027] Figure 3 It is shown that according to the present invention Figure 2 The flowchart shows an exemplary driver process for displaying the driver.

[0028] Figure 4 It is shown that according to the present invention Figure 2 A flowchart illustrating an exemplary display process for a display.

[0029] Figure 5 This is a flowchart illustrating an exemplary bit plane generation process for generating a bit plane sequence table according to the present invention.

[0030] Figure 6A and Figure 6B According to the present invention Figure 5 A graphical illustration of an exemplary bit-plane sequence table generated by the bit-plane sequence process.

[0031] Figure 7 This is a flowchart illustrating an exemplary bit plane voltage adjustment method according to the present invention.

[0032] Figure 8 This is a graphical illustration of an exemplary baseline bit plane sequence list.

[0033] Figure 9 and Figure 10 This is a graphical illustration of an exemplary modified bit plane sequence list.

[0034] Figure 11 This is a graphical illustration of an exemplary amplitude pattern.

[0035] Figure 12 This is a graphical illustration of an exemplary phase mode. Detailed Implementation

[0036] In the following detailed description, reference is made to the accompanying drawings, which form a part of the invention, in which illustrative embodiments that may be practiced are shown. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope. Therefore, the following detailed description should not be considered limiting, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0037] Various operations can be described sequentially as multiple discrete operations in a manner that aids in understanding the embodiments. However, the order of description should not be interpreted as implying that these operations are sequentially related.

[0038] The terms “coupling” and “connection”, as well as their derivatives, may be used. It should be understood that these terms are not intended to be synonyms. Rather, in certain embodiments, “connection” may be used to indicate that two or more elements are in direct physical contact with each other. “Coupling” may indicate that two or more elements are in direct physical contact with each other. However, “coupling” may also indicate that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0039] The description may use the term "embodiment" or "multiple embodiments," which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "containing," "having," etc., used with respect to embodiments are synonymous and are generally intended to be "open" terms (e.g., the term "comprising" should be interpreted as "including but not limited to," the term "having" should be interpreted as "at least having," the term "containing" should be interpreted as "including but not limited to," etc.).

[0040] Regarding the use of any plural and / or singular terms in this document, those skilled in the art can convert plural to singular and / or singular to plural depending on the applicable context and / or application. For clarity, various singular / plural substitutions may be explicitly described herein.

[0041] Various embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals may be used to denote the same elements throughout. In the following description, several specific details are set forth for illustrative purposes in order to facilitate a thorough understanding of one or more embodiments. However, it may be apparent in some or all of these instances that any of the embodiments described below may be practiced without employing the specific design details described below.

[0042] Embodiments of the methods, processes, or techniques disclosed herein can be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of this disclosure can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0043] As used in any embodiment herein, the term "logic" can refer to an application, software, firmware, and / or circuit configured to perform any of the foregoing operations. Software can be embodied as a software package, code, instructions, instruction sets, and / or data recorded on a non-transitory computer-readable storage medium. Firmware can be embodied as hard-coded (e.g., non-volatile) code, instructions, or instruction sets and / or data in a memory device. As described above, a software module can include logic executed by a processor.

[0044] The term "logic" can also refer to any information in the form of instruction signals and / or data that can be applied to affect the operation of a processor. Software is an example of such logic. Examples of processors are computer processors (processing units), microprocessors, digital signal processors, controllers, and microcontrollers. Logic can be formed by computer-executable instructions stored on a non-transitory computer-readable medium such as memory or storage devices, including, for example, random access memory (RAM), read-only memory (ROM), erasable / electrically erasable programmable read-only memory (EPROMs / EEPROMS), flash memory, etc. Logic can also include digital and / or analog hardware circuitry, for example, hardware circuitry including logical AND, OR, XOR, NAND, NOR, and other logical operations. Logic can be formed by a combination of software and hardware. On a network, logic can be programmed on a server or a series of servers. A particular logical unit is not limited to a single logical location on a network.

[0045] As used in any embodiment herein, "circuit" may include, for example, hardwired circuitry, programmable circuitry, state machine circuitry, logic, and / or firmware storing instructions executed by the programmable circuitry, either alone or in any combination. The circuit may be embodied as an integrated circuit, such as an integrated circuit chip, a system-on-a-chip (SoC), etc. In some embodiments, the circuit may be formed at least partially by at least one processor executing code and / or instruction sets (e.g., software, firmware, etc.) corresponding to the functions described herein, thereby transforming a general-purpose processor into a dedicated processing environment to perform one or more of the operations described herein.

[0046] Processors may include commercially available processors such as Celeron, Core, or Pentium processors manufactured by Intel Corporation, SPARC processors manufactured by Sun Microsystems, Athlon, Sempron, Phenom, or Opteron processors manufactured by AMD Corporation, other commercially available processors, and / or other available or soon-to-be-available processors.

[0047] Some embodiments of the processor may include processors referred to as multi-core processors and / or processors capable of employing parallel processing techniques in single-core or multi-core configurations. For example, a multi-core architecture typically includes two or more processor "execution cores." In this example, each execution core may execute as an independent processor pad, thereby enabling the parallel execution of multiple threads. Furthermore, those skilled in the art will understand that the processor may be configured in architectures commonly referred to as 32-bit or 64-bit architectures, or other architectural configurations now known or potentially developed in the future. The processor typically runs an operating system, which may be, for example, a Windows-type operating system from Microsoft Corporation; a Mac OS X operating system from Apple Computer Corporation; a Unix-type or Linux-type operating system available from many vendors, or a so-called open-source operating system; another or future operating system; or some combination thereof.

[0048] An operating system interfaces with firmware and hardware in a known manner and facilitates the processor's coordination and execution of the functions of various computer programs that can be written in various programming languages. Typically, the operating system, working in conjunction with the processor, coordinates and executes the functions of other computer components. The operating system also provides scheduling, input / output control, file and data management, memory management, and communication control and related services, all based on known technologies.

[0049] System memory may include any of a variety of known or future memory storage devices that can be used to store required information and are accessible by a computer. Computer-readable storage media include non-transitory, volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Examples include any generally available random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), digital versatile disk (DVD), magnetic media (e.g., resident hard disks or magnetic tapes), optical media (e.g., read-write compact disks), and / or other memory storage devices.

[0050] Storage devices can include any of a variety of known or future devices, including compact disk drives, tape drives, removable hard disk drives, USB or flash drives, or floppy disk drives. This type of storage device typically reads from and / or writes to program storage media, such as compact disks, tapes, removable hard disks, USB or flash drives, or floppy disks. Any of these program storage media, or other media currently in use or that may be developed in the future, can be considered a computer program product.

[0051] It will be understood that these program storage media typically store computer software programs and / or data. Computer software programs, also known as computer control logic, are typically stored in system memory and / or program storage devices used in conjunction with memory storage devices. In some embodiments, a computer program product is described that includes a computer-usable medium in which control logic (computer software programs, including program code) is stored. When executed by a processor, the control logic causes the processor to perform the functions described herein. In other embodiments, some functions are implemented primarily in hardware using, for example, a hardware state machine. Implementing a hardware state machine to perform the functions described herein will be apparent to those skilled in the art. Input / output controllers may include any of a variety of known devices for receiving and processing information from a user (whether human or machine, local or remote).

[0052] Such devices include, for example, modem cards, wireless cards, network interface cards, sound cards, or other types of controllers for any of a variety of known input devices. Output controllers may include controllers for any of a variety of known display devices to present information to a user (whether human or machine, local or remote).

[0053] In the embodiments described herein, the functional elements of the computer communicate with each other via a system bus. Some embodiments of the computer may use a network or other types of remote communication to communicate with some of the functional elements. It will be apparent to those skilled in the art that if instrument control and / or data processing applications are implemented in software, they can be loaded into and executed from system memory and / or memory storage devices.

[0054] All or part of the instrument control and / or data processing application may also reside in a read-only memory or similar device of a memory storage device, such a device not requiring the instrument control and / or data processing application to be loaded first via an input / output controller. Those skilled in the art will understand that the instrument control and / or data processing application, or a portion thereof, may be loaded by a processor into system memory or cache memory, or both, in a known manner for execution.

[0055] In addition, the computer may include one or more library files, experimental data files, and an internet client stored in system memory. For example, experimental data may include data related to one or more experiments or measurements, such as detected signal values, or other values ​​related to one or more sequencing-by-synthesis (SBS) experiments or processes. Furthermore, the internet client may include applications capable of accessing remote services on another computer using a network, and may include, for example, applications commonly referred to as "web browsers." Some commonly used web browsers include Microsoft Internet Explorer (available from Microsoft Corporation), Mozilla Firefox (from Mozilla Corporation), Safari (from Apple Computer Corporation), Google Chrome (from Google Corporation), or other types of web browsers currently known or to be developed in the art.

[0056] Furthermore, in the same or other embodiments, the Internet client may include a dedicated software application capable of accessing remote information via a network, or an element that may be a dedicated software application, such as a data processing application for biological applications.

[0057] A computer or processor may be part of a network. A network may include one or more of a variety of network types known to those skilled in the art. For example, a network may include a local area network (LAN) or a wide area network (WAN) that communicates using a protocol stack commonly known as the TCP / IP protocol stack. A network may include a global system of interconnected computer networks commonly known as the Internet, or it may also include various intranet architectures.

[0058] Those skilled in the art will also understand that some users in a network environment may prefer to use firewalls, commonly known as “firewalls” (sometimes also called packet filters or perimeter protection devices), to control information traffic to and from hardware and / or software systems. For example, a firewall may include hardware or software components or some combination thereof, and is typically designed to enforce security policies established by users (e.g., network administrators, etc.).

[0059] Although certain embodiments have been shown and described herein, those skilled in the art will understand that various alternative and / or equivalent embodiments or implementations calculated to achieve the same purpose may replace the embodiments shown and described without departing from the scope.

[0060] Those skilled in the art will readily understand that embodiments can be implemented in a very wide variety of ways. This application is intended to cover any modifications or variations of the embodiments discussed herein. Therefore, it is clearly intended that the embodiments be limited only by the claims and their equivalents. It will be apparent to those skilled in the art that various modifications and variations can be made to the invention without departing from the spirit or scope of the invention. Therefore, this invention is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

[0061] Embodiments of the operations described herein can be implemented in a computer-readable storage device having instructions stored thereon that, when executed by one or more processors, at least partially perform the method. The processor may include, for example, a processing unit and / or programmable circuitry. The storage device may include a machine-readable storage device comprising: any type of tangible, non-transitory storage device, such as any type of disk including floppy disks, optical disks, compact disc read-only memory (CD-ROM), compact disc rewritable (CD-RW), and magneto-optical disks; semiconductor devices, such as read-only memory (ROM), random access memory (RAM) such as dynamic and static RAM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic cards, or optical cards; or any type of storage device suitable for storing electronic instructions.

[0062] Detailed embodiments are disclosed herein as needed. It must be understood that the disclosed embodiments are merely examples of various and alternative forms. As used herein, the term "exemplary" is broadly used to refer to embodiments used as illustrations, samples, models, or patterns. Drawings are not necessarily to scale, and some features may be enlarged or reduced to show detail of specific components. In other instances, well-known components, systems, materials, or methods known to those skilled in the art have not been described in detail to avoid obscuring this disclosure. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting, but merely as the basis for the claims and as a representative basis for teaching those skilled in the art.

[0063] Embodiments of this disclosure are described in the context of phase mode operation of digital LCoS (Liquid Crystal on Silicon) devices; however, it will be apparent to those skilled in the art that, with appropriate and necessary modifications, the described processes can also be selectively applied to amplitude mode and mixed mode LC devices, as well as to other types of LC devices, including, for example, transmissive LC devices.

[0064] Overview

[0065] In the embodiments described in more detail below, the digitally driven LCoS microdisplay operates substantially in phase mode and uses a driving scheme having one or more features as described herein, which reduces phase ripple, phase switching noise and phase instability, and increases phase accuracy and device lifespan.

[0066] refer to Figure 2 This paper describes certain systems and methods within the context of a microcode-driven architecture. This architecture utilizes downloaded event tables and data lookup tables (e.g., Figure 6A and Figure 6B A bit-plane sequence table (600) is used to define all actions that occur during the frame sequence. The behavior of the driving algorithm can be changed by downloading a new set of tables. This means that the same driver chip can drive the display as an amplitude device or a phase-shifting device, depending on the downloaded tables used.

[0067] Display systems and methods

[0068] exist Figure 2 A high-level block diagram of a display system 200 is shown. The display system 200 includes a display driver 210, a display 220, and a mixed-signal chip 230.

[0069] Bit plane sequence table 600 (for example, see...) Figure 6A and Figure 6B These are stored in the memory 202 of the display system 200 or in memory accessible to the system software. For example, the CPU obtains the bit plane sequence list 600 and sends it to the display driver 210 via the SPI interface.

[0070] exist Figure 2 In the diagram, imager video data arrow 240 indicates a connection used to transfer video data from display driver 210 to display 220 (e.g., a 64-bit DDR bus). Imager arrow 250 indicates a connection used to send configuration commands to display 220 (e.g., a serial data bus in SPI format).

[0071] Arrow 260 indicates a connection (e.g., a serial data bus in SPI format) used to send control commands to mixed-signal chip 230, which uses these commands to set the values ​​of Vpix output voltage 270 and Vcom output voltage 280. The arrows for Vpix output voltage 270 and Vcom output voltage 280 are connected to display 220 to establish “high” or fully on voltage and “low” or fully off voltage as seen across display pixels.

[0072] Vpix and Vcom conjugate

[0073] In some embodiments, the Vcom and Vpix values ​​used in each Vcom conjugation segment are adjusted for each such segment before their conjugation, rather than using the same values, thereby reducing performance fluctuations associated with a particular conjugation. For example, adjusting the voltage during the first and last conjugation in each frame or subframe, during which, for example, reset and latch transients may cause undesirable voltage offsets and / or drift.

[0074] In some embodiments, different Vcom and Vpix values ​​are used before their conjugation in the positive and negative Vcom conjugate segments, instead of using the same values, to compensate for performance differences in analog voltage circuits with, for example, two opposite conjugate polarities.

[0075] In some embodiments, the Vcom switching frequency is increased to reduce, for example, current leakage during the Vcom conjugation phase or any other time-dependent drift that occurs during the Vcom conjugation phase. Leakage or drift can cause undesirable voltage variations or fluctuations during the conjugation phase. The Vcom conjugation frequency can be high enough to result in Vcom conjugation for each bit plane load of LcoS, or even several conjugations between one bit plane load and the next bit plane load.

[0076] Accurate and efficient DC balancing can be achieved over a duration of two or more frames or subframes by: (a) selecting an odd number of Vcom conjugates during the frame or subframe such that the inter-frame or subframe conjugates ensure that the polarity of the final Vcom conjugate segment in the frame or subframe is opposite to the polarity of the first Vcom conjugate segment of the matched frame or subframe, wherein the matching of pairs is performed with the next frame or subframe or with frames or subframes that subsequently occur an integer number of frames or subframes; and (b) rotating each of the matched frames or subframes by the same rotation value using the same sequence of b-on and b-off values.

[0077] In some embodiments, an integer number of bit-plane loads are used for each Vcom conjugated segment, where the integer can advantageously be as low as 1, such that at substantially the same moment when Vcom is actually conjugated at the liquid crystal in the LCoS, the bit-plane load operates directly or from each pixel latch at the liquid crystal in the LCoS. This allows for a design or measured delay between the time when the bit-plane load and Vcom conjugation are sent, issued, switched, executed, or commanded by the LCoS software, firmware, and hardware, as well as its driver circuitry and software, and the time when the corresponding bit-plane load and Vcom conjugation actually occur at the liquid crystal, including design or measured delays for special cases and other performance characteristics, e.g. For example, the first and / or last Vcom conjugate segment and / or the first and / or last bit plane load of these first and / or last Vcom conjugate segments and the first and / or last bit plane load of other Vcom conjugate segments, substantially before, during or after them, may be required by the driver circuitry of LCoS and / or its associated firmware and / or software to perform various initializations, resets and cache loads, which may additionally cause undesirable changes or fluctuations in timing and / or voltage during or temporarily adjacent to the bit plane load and the Vcom conjugate.

[0078] Display driver process

[0079] exist Figure 3 The diagram shows a basic flowchart of the driving process 300 of display driver 210. According to the first step 310, display driver 210 downloads an event table and a LUT table (e.g., bit plane sequence table 600) from memory 202. According to the second step 320, display driver 210 writes non-default display settings to display 220 via a connection. According to the third step 330, display driver 210 waits for Vsync 332 from a video source (not shown) that marks the start of a video frame. After receiving Vsync 332, according to the fourth step 340, display driver 210 executes the event sequence according to the downloaded tables.

[0080] Specifically, the fourth step 340 includes: at the first sub-step 342, starting a frame timer and loading a first event time; at the second sub-step 344, waiting for the event time; at the third sub-step 346, executing the bit plane (LCOS sent to the display 220) or other events; and determining whether the event is the last event according to the fourth sub-step 348. If the event is not the last event, a new event time is loaded according to the sub-step 350, and sub-steps 344, 346, 348, and 350 are repeated until the event is determined to be the last event at the fourth sub-step 348.

[0081] Display process

[0082] exist Figure 4 The diagram shows a basic flowchart of the rendering process 400 on display 220. When in idle state 410, display 220 receives image data from display driver 210. According to the first step 412, display 220 parses the received image data via a parallel interface to determine if a valid LCoS header has been received. If not, frame timer 414 is updated, and display 220 returns to idle state 410. If yes, the header is stored in internal register 416 within display 220, and then display 220 transitions to bit plane receive state 420.

[0083] Display 220 receives 128 column bits via a parallel interface and stores them in the master triggers 422 of the appropriate pixels. After reception, column selection counter 424 is incremented, with 422 and 424 repeated until all column data 426 is received. After column reception is complete, before receiving the first column data 422 of the next row, row selection counter is incremented 430 and column selection counter is cleared. These steps are repeated until the last row and last column data 432 are received, at which point display 220 transitions to a loading state 440. While in loading state 440, display 220 sends a loading pulse to move the master trigger data of the entire column group to the slave triggers 450, then delays for a predetermined number of periods 452, then increments the column group counter 454, and repeats this process for all remaining column groups. After repeating this process 456 for all column groups, a level shift trigger 460 is sent to simultaneously update all slave trigger data to the electrodes, and the display returns to idle state 410.

[0084] Bit Plane Table Method

[0085] The system and method described in this paper determine the optimal sequence of "1" and "0" bit planes (see, for example, [link to relevant documentation]). Figure 6A and Figure 6B The optimized sequence (bit plane sequence table 600) sent by the display driver 210 to the phase mode bit plane driven digital LCOS display 220 results in a waveform 100 with minimum phase ripple 110 at the desired phase shift value 120.

[0086] Phase mode and amplitude mode

[0087] For context, the differences between operating the digital LCOS display 220 in phase and amplitude modes are briefly described. Typically, in amplitude mode, the display system 200 operates with PWM. Here, for a given pixel in a given frame to be displayed at a specific grayscale level, the pixel is turned on at the beginning of the frame and rewritten with a "1" value so that it remains on in every bit plane until the desired percentage of "full scale" is reached.

[0088] Therefore, for example, pixels with a grayscale value of "0" are never turned on. For 50% grayscale, typically for the first half of the frame, the pixel remains on, and for the second half it remains off. For nearly 100% grayscale, the pixel remains on for almost the entire frame. Therefore, typically, each pixel is written with a long series of "1" values ​​at each bit plane until a specific point in time, and then from then until the end of the frame, it is written with a long series of "0" values.

[0089] Figure 11 The results are shown for various grayscale values. For these amplitude mode cases, only 4 bit planes are written, corresponding to the example number of possible grayscale levels (2^3). 2 The Vsync pulse begins at the start of each frame, followed by the pixel voltage waveform and the corresponding LC response. On this graph, there are four dashed boxes; one for each possible grayscale value, representing the voltage and LC response for four different pixels, which need to be four different grayscale levels. At 60Hz, the entire sequence will take 16.67ms to complete and will be repeated in the next frame (but with the opposite polarity to achieve DC balance).

[0090] Here, it should be understood that (except for some grayscale values ​​close to 0), the LC 222 of the display 220 always has time to reach a fully on state before the PWM pulse ends, and (again, except for some grayscale values ​​close to full scale) then reaches a fully off state.

[0091] In terms of bit-plane timing (which is affected by, but not dependent on, the desired gamma), the average bit-plane spacing is approximately the frame time divided by the number of possible gray levels. This number is typically much longer than the minimum possible bit-plane time, and depending on the desired gamma value, the spacing increases further up to the obtained frame time.

[0092] The operation of the display system 200 in phase mode is different. Here, the display system 200 is designed so that the LC 222 of the display 220 does not reach a "fully on" or "fully off" state. Instead, the display driver 210 sends a pattern of 1s and 0s, causing the LC state of the LC 222 to move back and forth in a sawtooth pattern to keep it at the desired percentage of "fully on" corresponding to the desired phase shift value 120.

[0093] Figure 12 The results are shown for various phase values. Here, there are 16 bit-plane writes, and it can be understood that a bit-plane write occurs whenever the voltage needs to change. With 60µs between bit-plane writes, this figure only depicts the first 960µs, or less than 1 / 16 of a frame. The dashed line roughly represents the averaging over the LC states, which determines the desired phase shift.

[0094] Whenever a "1" bit plane is transmitted, the LC state begins to ramp towards "fully on," and whenever a "0" bit plane is transmitted, the LC state begins to ramp towards "fully off." The LC state always ramps in one direction or the other. The greater the time interval between these bit plane transmissions, the longer the ramp movement in one direction, and therefore the larger the amplitude of phase ripple 110 or the sawtooth pattern of waveform 100.

[0095] The display system 200 writes bit plane 610 very close together to minimize phase ripple 110. The shortest interval between writes to bit plane 610 can be limited to, for example, approximately 60 µs.

[0096] Depending on the temperature, the rise and fall times of the current material used for phase mode LC 222 can be, for example, about 3 ms. In this case, even a fairly long sequence of the same pattern of bit plane 610 (e.g., a series of 1s or a series of 0s) will not necessarily cause the LC state to saturate (“fully on” or “fully off”).

[0097] As an example, to obtain 60% of the LC state as "fully on", a pattern of "1" bit plane 610 and "0" bit plane 610 with 60% "1" and 40% "0" could potentially achieve the desired result. However, a specific pattern is important in order to minimize the phase ripple 110 around the phase shift value 120.

[0098] The selected pattern applies the correct duty cycle to achieve an improved phase shift value of 120°, and also minimizes the time required for the system to continuously transmit several "on" or "off" bit planes (because, as mentioned above...). Figure 1As described above, this tends to increase phase ripple (110). The method 500 for determining the optimal pattern to achieve these two objectives will now be described in further detail.

[0099] Bit plane table generation method

[0100] Typically, a sequence of binary values ​​achieves the desired grayscale or phase value during a frame or subframe, and is determined by scattering a desired number of “on” and “off” values ​​for that grayscale or phase value within the frame or subframe, such that the “on” duration occurs at substantially equal intervals within the duration of the frame or subframe.

[0101] We divide each frame or subframe into b = m × (2 n -1) such on or off values, where n is the integer raw bit depth of the frame or subframe, and m is the chosen integer multiplier, such that b bit plane loads can occur substantially equally in time during the frame or subframe without requiring the bit plane loads to occur at a rate higher than that achievable by LCoS and its driving circuitry.

[0102] Method 500 determines, based on each possible phase shift value 620 (rows of bit plane sequence list 600), how many patterns of “on” or “1” bit planes 610 (columns of bit plane sequence list 600) will exist within a time interval, and distributes the “on” or “1” bit planes 610 as uniformly as possible over the duration of that time interval. The remaining bit plane time will then be “off” or “0” bit planes 610. Method 500 is described below and in Figure 5 The diagram in the middle is shown.

[0103] For example, for a 6-bit phase mode display 220, the system and method 500 determine an optimized sequence for each of 64 possible phase shift values ​​120 defined by a 6-bit phase resolution (the probability of a phase shift value is represented by rows in a bit plane sequence table 600, and the bit plane is indicated by columns in the bit plane sequence table 600; each row is a bit plane sequence for a phase shift value).

[0104] Method 500 includes a first step 510 of determining the frame time and the number of bits for the phase shift resolution. For example, in terms of duration, a 60Hz frame has a frame time of 16.667ms. Various phase shift resolutions are considered. For example, if a 6-bit phase shift resolution is chosen, then there are 64(2) bits in the basic modulation sequence. 6 The phase shift resolution of the bits is determined, and the pattern is determined to support the possibility of 0 in 64 to 63 in 64 being "1".

[0105] Continuing with this example, the minimum modulation time is 64 * 60 μs = 3.84 ms. According to step 520, determine the number of times the 64-bit planar sequence (modulation time) repeats within the frame. Here, the frame time is 16.667 ms, therefore the 64-bit planar sequence repeats 4.34 times.

[0106] The time for each bit plane 610 is then adjusted so that the number of repetitions is an integer. For example, the time for bit plane 610 is adjusted to 65.1 µs so that the 64-bit plane sequence (modulation mode) has exactly 4 repetitions within the time frame.

[0107] Method 500 continues with a series of sub-steps to select a bit pattern for each of the 64 possible phase shift values.

[0108] According to step 3, 530, the phase shift value is normalized and rounded from the original 0-2p phase shift value 120 to 0 / 64, 1 / 64, 2 / 64, 3 / 64, ..., 63 / 64. In each case, the numerator (P) is the number of "on" or "1" bit planes out of 64 possibilities. It should be understood that, if necessary, each of these fractions can be converted back to a phase shift value (in radians) by multiplying by 2p.

[0109] According to step 440, for a phase shift of 0, all 64 bit planes are "0". P is set to start from the value 1.

[0110] According to step 550, the average “on” bit plane spacing (D) is determined by dividing 64 by the numerator value (P). For example, for a phase shift (0.785 radians) corresponding to 8 / 64, 64 is divided by 8 to obtain a result of 8.0. This means that every 8th bit plane will require an “on” bit plane.

[0111] According to substep 552 of step 550, for each of the D value and the associated P value, determine whether D is an integer.

[0112] According to step 6.560, for phase shift values ​​where the division result is even (D produces an integer result), a pattern is determined. In this pattern, the "on" or "1" bit planes are 0 (first), 8, 16, 24, 32, 40, 48, and 56. For a phase shift of 2p (full scale), all 64 bit planes are "1". For a phase shift of 1p (middle scale), the pattern is 1 and 0 (32 each) alternating to "10101010...".

[0113] However, for most phase shift values ​​(associated with numerator P), the division in step 552 of step 550 will not produce integer results. For example, for a phase shift corresponding to 3 / 64 (0.295 radians), the division result is 64 / 3 = 21.3. This would correspond to one “connected” bit plane for every 21.3 bit planes. However, “connected” bit planes cannot have fractional or non-integer positions in the bit plane sequence list 600. Instead, according to a series of sub-steps 570, 572, 574, 576, 578, the non-fractional positions of the three “connected” bit planes are determined to be as uniform as possible, such that the average spacing between the “connected” bit planes 610 is as close as possible to 21.3.

[0114] Typically, for each non-integer interval, the system enumerates the patterns closest to the desired interval, calculates the average interval for each pattern, and eliminates all patterns except the one whose average interval is closest to the desired average interval. If there are more than one pattern with the same closest average interval (as in the example above), the system selects the pattern with the earliest “extra” connected bit plane.

[0115] Here, according to substep 570, for each non-integer D value, the system determines the spacing to be either int(D) or int(D)+1. For the example above, the spacing will be 21 or 22 (int(21.3) or int(21.3)+1).

[0116] According to substep 570, the system additionally forms a list of all possible sequences (associated with molecule P). For example, if each repeat starts from 0 in the “on” bit plane, the choices for continuing the example above are {0, 21, 42}, {0, 21, 43}, {0, 22, 43}, or {0, 22, 44}.

[0117] According to substep 572, for each sequence, the system calculates the average difference between adjacent elements. This includes the "wrap-around" difference between the last element and "64". For the example sequences, the average spacing for each series is 21.3, 21.3, 21.3, and 21.7, respectively.

[0118] According to substep 574, the system compares each mean interval with the D value and determines which sequences are associated with the minimum difference. Continuing the example above, among the calculated mean intervals, the last one is eliminated because it is furthest from the target of 21.3. {0, 21, 42}, {0, 21, 43}, and {0, 22, 43} are selected and any one of them is a valid selection.

[0119] According to substep 576, the system uses the determined sequence or selects from the remaining sequences. For example, it selects from the remaining example sequences, choosing the second choice {0, 21, 42} because it places the “on” bit plane earlier in the frame, which will speed up the process of reaching the desired phase value earlier.

[0120] According to substep 578, at each phase shift value (P), the bit plane sequence table 600 is filled with bit plane values ​​according to the selected sequence. This sequence indicates the bit plane 610 with an "on" value for a given P value.

[0121] Based on sub-steps 580 and 582, the steps of method 500 are repeated for the additional value.

[0122] Figure 6A and Figure 6B A diagram is shown illustrating an example where each bit plane in the possible 64 phase shift stages would be "on" in the exemplary 6-bit system described above. Note that each row represents a different phase shift; the green cells are the "on" bit planes.

[0123] Circular rotation

[0124] As mentioned above, each frame or subframe is divided into b = m × (2 n -1) such “on” or “off” values, where n is the integer raw bit depth of the frame or subframe, and m is the chosen integer multiplier, such that b bit plane loads can occur at substantially uniform intervals in time during the frame or subframe, without requiring the bit plane loads to occur at a rate higher than that achievable by LCoS and its driving circuitry.

[0125] For each desired grayscale or phase value, the system cyclically rotates an integer value over a sequence of b on and off values ​​for that grayscale or phase value. For example, the system selects a set of integer rotation values ​​(one for each phase or grayscale value) that collectively result in a substantially equal number of on-to-off transitions in each of the b bit-plane loads and a substantially equal number of off-to-on transitions in each of the b bit-plane loads. Therefore, within a frame or subframe, the on-to-off transition rate and the off-to-on transition rate remain substantially constant.

[0126] As another example, the system selects a set of integer rotation values, which are chosen from the set of possible unique rotation values ​​(where only b rotation values ​​exist, m=2). n ×b unique choices, which result in b distinct sequences of on and off values. The choice is determined by numerically evaluating some or all of m possible sets to minimize or maximize one or more numerically defined good-value functions.

[0127] For example, the selection can be determined with regard to the uniformity of the time distribution of the on-to-off transitions. Alternatively, the selection can be determined to prevent a large number of off-to-on transitions from occurring at or near certain times in a frame or subframe (e.g., at the beginning or end of a frame or subframe).

[0128] Alternatively, the selection can be experimentally determined by measuring one or more figure-of-fact functions of the LCoS one at a time using some or all of the m possible sets. Here, the measured figure-of-fact function could be, for example, the diffraction efficiency of the LCoS operated on using that set of rotational values. As another example, the figure-of-fact function could be the ratio between the optical power measured in a first substantially bright region of a first-order diffraction pattern produced by the LCoS operated on using that set of rotational values ​​and the optical power measured in a second substantially dark region of a first-order diffraction pattern produced by the LCoS operated on using that set of rotational values; or it could be measured in corresponding regions in the conjugate space of the first-order diffraction pattern.

[0129] In addition, a hybrid approach can be used to determine the selection, in which a candidate set is digitally selected from the possible set and then these candidates are experimentally evaluated.

[0130] In reality, each bit plane simultaneously sets the value of every pixel in the display, and the near-simultaneous transformation of millions of pixels can lead to system-level interaction. If we consider... Figure 6A and Figure 6B The number of phase shift values ​​by which a pixel changes state (from 0 to 1 or from 1 to 0) between one bit plane and the next can be as few as 20 or as many as 41. By applying an image containing a wide range of phase shift values ​​to an imager containing millions of pixels, visible artifacts can be produced as the activity level changes with the bit planes being executed throughout the frame.

[0131] The target phase shift is achieved through the mixing and expansion of a series of pixel 1 and 0 states during the framing process. These states are independent of starting the sequence of 1s and 0s at any specific point in the sequence. Therefore, the system performs an optimization step that calculates the number of pixel state changes between each bit plane and adjusts the starting point of each series of 1s and 0s associated with each target phase state value to minimize the range between the minimum and maximum number of pixel state changes between consecutive bit planes. Applying this optimization significantly reduces artifacts and improves phase contrast.

[0132] Variable voltage per bit plane

[0133] Figure 8 This is an exemplary baseline bit plane sequence list, while Figure 9 and Figure 10It is the modified bit plane sequence list (a set of bit planes, which is obtained by applying the following optimizations). Figure 8 (Obtained from the baseline set of the bit plane depicted in the text).

[0134] Refer again Figure 2 The microcode driving architecture of display system 200 can change the details of the bit plane sent to display 220 independently of other bit planes. One of these details is the voltage applied to the pixel electrodes for a given bit plane. In this example embodiment, this voltage (display voltage Vpix 270) is provided to display 220 from external mixed-signal chip 230, where the actual voltage from display driver 210 to mixed-signal chip 230 is set by writing via SPI interface.

[0135] Initiating a write operation on the SPI interface is called, and the value written is determined by commands that have been inserted into or presented in the downloaded event table. Therefore, by downloading a new event table, the Vpix voltage 270 for each bit plane can be adjusted individually.

[0136] According to voltage adjustment method 700, small empirical voltage adjustments are typically made continuously for each bit plane starting from the first bit plane transmitted, and phase ripple 110 is measured after each adjustment.

[0137] For example, applying a small voltage adjustment, typically only 0.1 or 0.2V, to only one or two bit planes within a frame (or sequence / line) can very effectively reduce the average amount of phase ripple 110. Specifically, these voltage adjustments are most effective when applied to the first bit plane or the last bit plane (or both) in a frame.

[0138] This effect is most easily understood as a partial “correction” or “compensation” for the asymmetry caused by inactive periods before and after the bit-plane sequence that occurs during the frame process. These adjustments should be made in such a way that the overall DC balance for the display 220 is maintained during continuous operation, since any residual DC voltage present on the LCOS display 220 could cause flickering and image retention artifacts.

[0139] refer to Figure 7 The exemplary voltage adjustment method 700 will now be described in further detail. According to the first step 710, a baseline phase pattern sequence table is downloaded to the display driver 210. The phase pattern sequence table has a bit plane Vpix voltage 270 set as the baseline value.

[0140] According to the second step 720, the display system 200 uses the baseline sequence list to measure the phase ripple 110 and saves the result as a baseline (#0) for that bit plane.

[0141] According to step 730, the display system 200 modifies the baseline sequence table to apply a +100mV Vpix offset (relative to the "baseline" value) only to the first bit plane. The modified phase pattern sequence table is downloaded to the display driver 210, and the display system 200 uses the new sequence to measure the phase ripple 110 and saves the result as (#1).

[0142] According to step 740, the display system 200 modifies the baseline sequence table to apply a Vpix offset of -100mV (relative to the "baseline" value) only to the first bit plane. The modified phase pattern sequence table is downloaded to the display driver 210, and the display system 200 uses the new sequence to measure the phase ripple 110 and saves the result as (#2).

[0143] According to step 750, the display system 200 compares the phase ripple 110 of result #0 with the phase ripple 110 of results #1 and #2. If the phase ripple of #1 or #2 is lower than that of #0, the baseline Vpix voltage 270 in the baseline sequence of the first bit plane is replaced with a modified Vpix voltage (Vpix voltage 270 and Vpix offset) that gives a smaller phase ripple 110 value.

[0144] Steps 710, 720, 730, 740, and 750 are repeated for each bit plane in the sequence. In each case, if a voltage offset of the Vpix voltage 270 for a particular bit plane is found to give a lower phase ripple 110 value than the previous “low” phase ripple 110 value, the Vpix voltage 270 value is replaced in the baseline sequence for that bit plane with the value that results in a lower overall phase ripple 110. This new “modified sequence” is then used for the remaining steps.

[0145] These values ​​can interact, so repeating the steps more than once for each bit plane 610 in the sequence can be advantageous. Repeating the algorithm with a voltage offset of less than 100mV to fine-tune the final result can also be advantageous. Other offsets should also be considered.

[0146] According to step 760, the display system 200 modifies subframes of opposite polarity and rechecks the phase ripple 110 on the combined positive and negative subframes. The modifications to the positive and negative subframes are equal in magnitude and opposite in polarity to ensure that DC balance is maintained. It may be advantageous to repeat the voltage adjustment method 700 on these combined subframes to further minimize the phase ripple 110.

[0147] According to step 770, the display system 200 saves and stores the “baseline” sequence that incorporates the final modifications of the Vpix offset.

[0148] Voltage regulation method 700 is part of an engineering optimization for a specific drive sequence and LC configuration.

[0149] Summarize

[0150] Analog designs have historically been favored because digital designs were thought unable to produce the accurate low-ripple phase shift required for holography. However, in many respects, digital phase-mode LCOS displays are at least competitive, and often superior to analog designs in several aspects. Digital phase-mode LCOS displays have phase ripple that rivals analog versions—typically 3% or less for 6-bit resolution. Each of the “droop” and charge transfer inaccuracies in digital phase-mode LCOS displays is minimal or nonexistent, issues even for analog displays—especially at smaller pixel sizes. Because digital phase-mode LCOS displays do not require the minimum size of the storage capacitors used to fit each pixel, they can be implemented with much smaller pixels. For example, digital phase-mode LCOS displays can use a pixel pitch of 3.015µm, and even smaller pixels are possible. No analog phase-mode displays with such small pixels have yet been demonstrated.

[0151] Digital architecture significantly improves immunity to noise, offset voltage, ground bounce, PSRR issues, and other artifacts that make the design of analog LCOS displays challenging.

[0152] This system and method allow for the display of phase images with higher contrast than those created by prior art displays. Contrast is improved by providing a method for operating a display with reduced phase ripple. This makes displays created using the systems and methods described herein better (because they produce higher quality images) and more suitable for end-customer use.

[0153] The terms and expressions used herein are descriptive rather than limiting, and in using such terms and expressions, no equivalents of the features shown and described (or parts thereof) are intended to be excluded, and it should be understood that various modifications may be made within the scope of the claims. Therefore, the claims are intended to cover all such equivalents.

[0154] Various features, aspects, and embodiments have been described herein. As those skilled in the art will understand, the features, aspects, and embodiments are readily combined with each other, and can be varied and modified. Therefore, it should be considered that this disclosure covers such combinations, variations, and modifications.

[0155] The above embodiments are merely illustrative examples of implementations set forth for the purpose of clearly understanding the principles. Variations, modifications, and combinations of the above embodiments may be made without departing from the scope of the claims. All such variations, modifications, and combinations are included herein within the scope of this disclosure and the appended claims.

Claims

1. A display system, comprising: A liquid crystal display includes a plurality of pixels, each pixel being configured to generate a phase shift of light applied to that pixel in response to an applied voltage; A display table comprising multiple rows, each row of the display table comprising a bit plane sequence associated with one of multiple phase shift values ​​for each of the pixels in the display, each bit plane sequence being: Includes multiple 1 values ​​and multiple 0 values; Having the 1 and 0 values ​​spaced apart within the sequence to reduce phase ripple in pixels among the plurality of pixels to which the bit plane sequence is applied; as well as Having at least one 1 value, said at least one 1 value comprising one or more groups of 1 values, said one or more groups of 1 values ​​having substantially the same number of bit planes, Each of the one or more groups of 1 values ​​is spaced apart from each other by one or more groups of 0 values ​​within the bit plane sequence, and Each of the one or more groups of 0 values ​​has substantially the same number of bit planes; as well as A display driver is configured to apply a bit plane sequence as a voltage to each of the plurality of pixels, the bit plane sequence for each of the plurality of pixels corresponding to one of the rows in the display table, and one of the rows in the display table being determined by a corresponding phase shift value for each of the plurality of pixels.

2. The display system of claim 1, wherein, The plurality of phase shift values ​​are 2 n There are 1 phase shift values, and among them, the number of values ​​for 1 is greater than 1 and less than 2. n For each bit plane sequence of -2, the plurality of 1 values ​​are distributed across the length of the bit plane sequence such that one or more groups of one or more 1 values ​​are spaced apart from each other by one or more groups of one or more 0 values.

3. The display system of claim 1, wherein, The number of values ​​of 1 is greater than 1 and less than 2. n -2 for each bit plane sequence, each of the one or more groups of one or more 1 values ​​is the same or within a bit plane of each of the one or more groups of one or more 1 values.

4. The display system of claim 1, wherein, The number of values ​​of 1 is greater than 1 and less than 2. n -2 for each bit plane sequence, each of the one or more groups of 0 values ​​is the same or within a bit plane of each of the one or more groups of 0 values.

5. The display system of claim 1, wherein, For each bit plane sequence, the quantity P represents the number of 1 values ​​in the bit plane sequence associated with one of the plurality of phase shift values, where the quantity P of 1 values ​​is greater than 1 and less than 2. n -2, the plurality of 1 values ​​are distributed according to a spacing D across the length of the bit plane sequence, the spacing D being determined to be 2. n / P, where the length of the bit plane sequence is 2. n And P represents the number of 1 values ​​in the bit plane sequence.

6. The display system of claim 5, wherein, Each of the plurality of phase shift values ​​is related to the values ​​at 0, 1, ..., 2. n The quantity P in the range of -1 is associated with, where 2 n -P represents the number of 0 values ​​in the bit plane sequence associated with one of the plurality of phase shift values.

7. The display system of claim 1, wherein, The bit plane sequence is applied to the display during a frame with a relevant frame time, wherein the time of each bit plane in the bit plane sequence has a value that causes the bit plane sequence to be repeated an integer number of times during the frame time.

8. The display system of claim 1, wherein, The display table includes baseline voltage values ​​for each bit plane in each bit plane sequence.

9. The display system of claim 8, wherein, For at least one baseline voltage value in at least one bit plane sequence, the display table also includes an offset voltage value added to the baseline voltage value.

10. A display system, comprising: A display, comprising multiple pixels; Display tables, including: Multiple rows, each row of the display table includes a bit plane sequence associated with one of a plurality of phase shift values ​​for one of the pixels in the display, each bit plane sequence including a plurality of 1 values ​​and a plurality of 0 values; Each bit plane sequence has at least one 1 value, said at least one 1 value comprising one or more groups of 1 values, said one or more groups of 1 values ​​having substantially the same number of bit planes; and Each of the one or more groups of 1 values ​​is spaced apart from each other by one or more groups of 0 values ​​within the bit plane sequence, each of the one or more groups of 0 values ​​having substantially the same number of bit planes; and A display driver is configured to send a bit plane sequence to the pixel of the display according to the phase shift value for the pixel and the corresponding row of the display table. Wherein, the plurality of phase shift values ​​are 2 n There are 1 phase shift values, and among them, the number of values ​​for 1 is greater than 1 and less than 2. n For each bit plane sequence of -2, the plurality of 1 values ​​are distributed across the length of the bit plane sequence such that one or more groups of one or more 1 values ​​are spaced apart from each other by one or more groups of one or more 0 values.

11. The display system of claim 10, wherein, The number of values ​​of 1 is greater than 1 and less than 2. n -2 for each bit plane sequence, each of the one or more groups of one or more 1 values ​​is the same or within a bit plane of each of the one or more groups of one or more 1 values.

12. The display system of claim 10, wherein, The bit plane sequence is applied to the display during a frame with a relevant frame time, wherein the time of each bit plane in the bit plane sequence has a value that causes the bit plane sequence to be repeated an integer number of times during the frame time.

13. The display system of claim 10, wherein, The display table includes the baseline voltage value for each bit plane in each bit plane sequence.

14. The display system of claim 10, wherein, For each bit plane sequence, the quantity P represents the number of 1 values ​​in the bit plane sequence associated with one of the plurality of phase shift values, where the quantity P of 1 values ​​is greater than 1 and less than 2. n -2, the plurality of 1 values ​​are distributed according to a spacing D across the length of the bit plane sequence, the spacing D being determined to be 2. n / P, where the length of the bit plane sequence is 2. n And P represents the number of 1 values ​​in the bit plane sequence.

15. The display system of claim 14, wherein, each of the plurality of phase shift values is associated with a number P in the range of 0, 1,..., 2 n -1, wherein 2 n P represents the number of 0 values in the bit plane sequence associated with one of the plurality of phase shift values.

16. The display system of claim 13, wherein, For at least one baseline voltage value in at least one bit plane sequence, the display table also includes an offset voltage value added to the baseline voltage value.

17. A method for driving a display, comprising: A display table is generated comprising multiple bit-plane sequences, each bit-plane sequence being associated with one of multiple phase shift values ​​for each of a plurality of pixels in the display, the display table comprising: Multiple rows, each row of the display table including a bit plane sequence associated with one of the multiple phase shift values ​​for one of the pixels in the display; Each bit plane sequence includes a plurality of 1 values ​​and a plurality of 0 values, and has the 1 values ​​and 0 values ​​spaced apart within the sequence to reduce phase ripple in the pixels of the plurality of pixels to which the bit plane sequence is applied; Determine the phase shift value for each of the plurality of pixels in the display; and The bit plane sequence corresponding to the determined phase shift value for the pixel is applied to each of the plurality of pixels in the display. Determining the phase shift value for each of the plurality of pixels in the display includes determining 2 n A number of phase shift values, wherein each of the phase shift values ​​is related to the values ​​at 0, 1, ..., 2. n The quantity P in the range -1 is associated with, where P represents the number of 1 values ​​in the bit plane sequence associated with one of the plurality of phase shift values, and 2 n -P represents the number of 0 values ​​in the bit plane sequence associated with one of the phase shift values.

18. The method of claim 17, further comprising: Regarding the cases in 2, ..., 2 n For each phase shift value associated with the quantity P in the range -2, the spacing D is determined to be 2. n / P and determine the bit plane sequence such that the plurality of 1 values ​​are distributed across the length of the bit plane sequence according to the spacing D.

19. The method of claim 17, wherein, It also includes adjusting the timing of each bit plane in each bit plane sequence so that the bit plane sequence is repeated an integer number of times in each frame of the display.

20. The method of claim 17, further comprising: Calculate the average difference between adjacent 1 values ​​in each of the plurality of bit-plane sequences, wherein the average difference between adjacent 1 values ​​includes the difference between the last 1 value in the bit-plane sequence and the first 1 value in a subsequently repeated bit-plane sequence; and Select the bit plane sequence with the lowest average difference from the plurality of bit plane sequences.

Images