A semiconductor power device and a method for manufacturing the same

Abstract

The present invention discloses a semiconductor power device and a method for preparing the same. The method for preparing the semiconductor power device comprises: providing a substrate; forming a semiconductor epitaxial layer on a first surface of the substrate; forming a gate structure layer on a side of the semiconductor epitaxial layer away from the substrate, and forming an opening in the gate structure layer to expose a portion of a heavily doped region of the first conductive type; forming a first supporting layer on a side of the gate structure layer away from the substrate, and thinning the substrate based on the first supporting layer; forming a second supporting layer on a second surface of the substrate, and thinning or removing the first supporting layer based on the second supporting layer; wherein the resistivity of the second supporting layer is lower than the resistivity of the substrate; forming a contact hole to expose a portion of the heavily doped region of the first conductive type, and forming a first electrode in the contact hole. The technical solution provided by the present invention reduces the on-resistance of the semiconductor power device.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of semiconductor devices, and in particular to a semiconductor power device and a method for manufacturing the same. Background Art

[0002] As a representative of the third generation of semiconductor materials, silicon carbide (SiC) has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large bandgap, high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios.

[0003] At present, the preparation process of SiC power devices is usually to grow an epitaxial layer on a SiC substrate with a certain doping concentration, and perform a front process on it to form the front structure of the SiC power device. After the front structure is completed, the substrate is thinned on the back to reduce a certain thickness. The thinned substrate will retain a thickness of 100um to 200um to ensure that subsequent processes will not cause wafer splits or fragments. However, the material of the substrate is doped SiC with a resistivity of about 0.02Ω·cm. A thicker substrate will cause the on-resistance of the SiC power device to increase. In SiC vertical devices, the on-resistance brought by the retained substrate cannot be ignored when the chip current level is large. Taking the chip active area as 20mm 2 , the substrate thickness is 150um, the resistance of the substrate itself is about 1.5mΩ, and the device on-resistance level corresponding to the active area is about 12mΩ~18mΩ. The resistance of the substrate accounts for about 8%~12.5% ​​of the overall on-resistance of the device. Therefore, in chips with large current levels, the on-resistance brought by the substrate cannot be ignored. Summary of the invention

[0004] The embodiment of the present invention provides a semiconductor power device and a method for manufacturing the same, so as to reduce the on-resistance of the semiconductor power device.

[0005] According to one aspect of the present invention, there is provided a method for preparing a semiconductor power device, comprising:

[0006] Providing a substrate; the substrate comprising a first surface and a second surface opposite to each other;

[0007] A semiconductor epitaxial layer is formed on the first surface of the substrate; wherein the semiconductor epitaxial layer comprises a first conductive type first doping region, a second conductive type doping region and a first conductive type second doping region which are sequentially away from the substrate; and the second conductive type doping region covers the bottom and sidewalls of the first conductive type second doping region, and the first conductive type first doping region covers the bottom and sidewalls of the second conductive type doping region;

[0008] forming a gate structure layer on a side of the semiconductor epitaxial layer away from the substrate, and forming an opening in the gate structure layer that exposes a portion of the first conductive type second doped region;

[0009] forming a first supporting layer on a side of the gate structure layer away from the substrate;

[0010] Based on the support and protection of the semiconductor epitaxial layer by the first supporting layer, the substrate is thinned so that the substrate reaches a preset thickness;

[0011] forming a second supporting layer on the second surface of the substrate; wherein the resistivity of the second supporting layer is lower than the resistivity of the substrate, and the substrate of the preset thickness and the second supporting layer are used to constitute a target substrate;

[0012] Based on the support and protection of the semiconductor epitaxial layer by the second supporting layer, the first supporting layer is thinned or removed;

[0013] A contact hole is formed to expose a portion of the first conductive type second doping region, and a first electrode is formed in the contact hole.

[0014] Optionally, the preset thickness ranges from 2um to 5um; and the thickness range of the second supporting layer is from 80um to 200um.

[0015] Optionally, the material of the second supporting layer includes metal, and the second supporting layer is also reused as a second electrode;

[0016] The first electrode is a source electrode, and the second electrode is a drain electrode; or the first electrode is a drain electrode, and the second electrode is a source electrode.

[0017] Optionally, forming a first supporting layer on a side of the gate structure layer away from the substrate includes:

[0018] Forming a first supporting layer on a surface of the gate structure layer on a side away from the substrate and in the opening by a deposition process;

[0019] The thinning or removing of the first supporting layer includes:

[0020] The first supporting layer is thinned or removed by at least one of wet etching, dry etching and chemical mechanical polishing.

[0021] Optionally, forming a first supporting layer on a side of the gate structure layer away from the substrate includes:

[0022] Forming a first supporting layer on a side of the gate structure layer away from the substrate by a bonding process;

[0023] The thinning or removing of the first supporting layer includes:

[0024] The first supporting layer is thinned or removed through a debonding process.

[0025] Optionally, the material of the first supporting layer includes a dielectric material or a conductive material;

[0026] In the case where the material of the first supporting layer is a conductive material, removing the first supporting layer;

[0027] In the case that the material of the first supporting layer is a dielectric material, the first supporting layer is thinned.

[0028] Optionally, if the first supporting layer is removed, forming a contact hole exposing a portion of the first conductive type second doping region includes:

[0029] forming an interlayer insulating layer on a side of the gate structure layer away from the substrate and in the opening;

[0030] forming a contact hole in the interlayer insulating layer exposing a portion of the first conductive type second doping region;

[0031] Based on thinning the first supporting layer, a contact hole exposing a portion of the first conductive type second doping region is formed, including:

[0032] A contact hole exposing a portion of the first conductive type second doping region is formed in the thinned first supporting layer; the first supporting layer is used as an interlayer insulating layer isolating the first electrode from the gate structure.

[0033] Optionally, the substrate is subjected to a thinning process, comprising:

[0034] Thinning the substrate by dry etching combined with chemical mechanical polishing;

[0035] Alternatively, the substrate is thinned by laser lift-off combined with chemical mechanical polishing.

[0036] Optionally, forming a second supporting layer on the second surface of the substrate includes:

[0037] forming an ohmic contact layer on the second surface of the substrate;

[0038] An electrode metal layer is formed on a side of the ohmic contact layer away from the substrate.

[0039] Optionally, after the substrate is thinned, the method further comprises:

[0040] The substrate and the semiconductor epitaxial layer are annealed, and the second surface of the substrate is planarized.

[0041] According to another aspect of the present invention, there is provided a semiconductor power device, characterized in that it is formed by the method for preparing a semiconductor power device according to any embodiment of the present invention; the semiconductor power device comprises:

[0042] A target substrate; the target substrate comprises a substrate of a preset thickness and a second supporting layer located on a second surface of the substrate; the resistivity of the second supporting layer is lower than the resistivity of the substrate;

[0043] A semiconductor epitaxial layer, located on the first surface of the substrate; wherein the semiconductor epitaxial layer comprises a first conductive type first doping region, a second conductive type doping region and a first conductive type second doping region, which are sequentially away from the substrate; and the second conductive type doping region covers the bottom and side walls of the first conductive type second doping region, and the first conductive type first doping region covers the bottom and side walls of the second conductive type doping region;

[0044] a gate structure layer, located at a side of the semiconductor epitaxial layer away from the target substrate, the gate structure layer including an opening exposing a portion of the second doped region of the first conductivity type;

[0045] an interlayer insulating layer, located on a surface of the gate structure layer away from the target substrate and a sidewall of the gate structure layer; wherein the interlayer insulating layer comprises a contact hole exposing a portion of the first conductive type second doping region;

[0046] The first electrode is located on a surface of the interlayer insulating layer away from the target substrate and in the contact hole.

[0047] Optionally, the preset thickness ranges from 2um to 5um; and the thickness range of the second supporting layer is from 80um to 200um.

[0048] Optionally, the material of the second supporting layer includes metal, and the second supporting layer is also reused as a second electrode;

[0049] The first electrode is a source electrode, and the second electrode is a drain electrode; or the first electrode is a drain electrode, and the second electrode is a source electrode.

[0050] The technical solution provided by the present invention forms a first supporting layer on a side of the gate structure layer away from the substrate. Based on the support and protection of the semiconductor epitaxial layer by the first supporting layer, the substrate can be thinned to prevent the wafer from warping or even breaking due to being too thin; and a second supporting layer is formed on the second side of the thinned substrate, and the second supporting layer is used as a partial substrate to form a target substrate together with the second supporting layer. Based on the support and protection of the semiconductor epitaxial layer by the second supporting layer, the first supporting layer is thinned or removed, and the subsequent preparation process is completed, which also prevents the wafer from warping or even breaking due to being too thin; the resistivity of the second supporting layer is set to be lower than the resistivity of the substrate, and under the same substrate thickness (the thickness of the SiC substrate in the prior art is the same as the thickness of the target substrate in the present application), the resistance of the substrate can be reduced, thereby reducing the resistance ratio of the substrate and the on-resistance of the semiconductor power device.

[0051] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 is a flow chart of a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0054] Figure 2 is a schematic structural cross-sectional diagram corresponding to step S211 in a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0055] Figure 3 is a schematic structural cross-sectional diagram corresponding to step S212 in a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0056] Figure 4 is a schematic structural cross-sectional diagram corresponding to step S311 in a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0057] Figure 5 is a schematic structural cross-sectional diagram corresponding to step S312 in a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0058] Figure 6is a schematic structural cross-sectional diagram corresponding to step S411 in a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0059] Figure 7 is a schematic structural cross-sectional diagram corresponding to step S150 in a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0060] Figure 8 is a schematic structural cross-sectional diagram corresponding to step S160 in a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0061] Fig. 9 It is a schematic diagram of a structural cross-section after the first supporting layer is thinned in step S170 in a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0062] Fig.10 It is a schematic diagram of a structural cross-section after the first supporting layer is removed in step S170 in a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0063] Fig.11 is a schematic structural cross-sectional diagram corresponding to step S811 in a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0064] Fig.12 is a schematic structural cross-sectional diagram corresponding to step S821 in a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0065] Fig.13 is a schematic structural cross-sectional diagram corresponding to step S822 in a method for preparing a semiconductor power device provided by an embodiment of the present invention;

[0066] Fig.14 It is a schematic structural cross-sectional diagram of forming a first electrode in step S180 in a method for preparing a semiconductor power device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0067] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0068] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0069] The embodiment of the present invention provides a method for preparing a semiconductor power device. Figure 1 is a flow chart of a method for preparing a semiconductor power device provided by an embodiment of the present invention, with reference to Figure 1 , the preparation method of the semiconductor power device comprises:

[0070] S110 , providing a substrate.

[0071] S120. Form a semiconductor epitaxial layer on the first surface of the substrate; wherein the semiconductor epitaxial layer includes a first conductive type first doping region, a second conductive type doping region and a first conductive type second doping region which are sequentially away from the substrate; and the second conductive type doping region covers the bottom and the wall side of the first conductive type second doping region, and the first conductive type first doping region covers the bottom and the side wall of the second conductive type doping region.

[0072] Specifically, the substrate includes a first surface and a second surface relative to each other. The material of the substrate may be the same as or different from the material of the semiconductor epitaxial layer. In an embodiment of the present invention, the material of the substrate is the same as the material of the semiconductor epitaxial layer, and both may be SiC. That is, the trench power device in the embodiment of the present invention may be a SiC power device. SiC has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large bandgap, and have the advantages of high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios.

[0073] The first conductive type first doping region located below the second conductive type doping region is used to form a drift region of a SiC power device; the first conductive type first doping regions located on both sides of the second conductive type doping region are used to form a JFET region of a SiC power device. The second conductive type doping region is used to form a well region of a trench SiC power device. The first conductive type second doping region is used to form a contact source region or a contact drain region of a trench SiC power device.

[0074] S130, forming a gate structure layer on a side of the semiconductor epitaxial layer away from the substrate, and forming an opening in the gate structure layer to expose a portion of the first conductivity type second doped region.

[0075] S140 , forming a first supporting layer on a side of the gate structure layer away from the substrate.

[0076] S150, based on the support and protection of the semiconductor epitaxial layer by the first supporting layer, the substrate is thinned so that the substrate reaches a preset thickness.

[0077] Specifically, the material of the first support layer may include a dielectric material. The dielectric material may be a conventional dielectric material, such as SiO 2 , Si 3 N 4 The first support layer can also be made of conductive material (non-insulating material), and can be removed in subsequent steps.

[0078] S160, forming a second supporting layer on the second surface of the substrate; wherein the resistivity of the second supporting layer is lower than the resistivity of the substrate, and the substrate with a preset thickness and the second supporting layer are used to constitute a target substrate.

[0079] S170, based on the support and protection of the semiconductor epitaxial layer by the second supporting layer, the first supporting layer is thinned or removed.

[0080] Specifically, the main functions of the second supporting layer include supporting the wafer, preventing the first supporting layer from being thinned or removed, and preventing the problem of broken fragments after the thinning or removal process; at the same time, the second supporting layer, as a partial substrate, together with the thinned and thickened substrate, constitutes the target substrate. Therefore, the resistivity of the second supporting layer is set lower than the resistivity of the substrate, such as metal material, which can reduce the resistance of the substrate under the same substrate thickness (the thickness of the SiC substrate in the prior art is the same as the thickness of the target substrate in this application), thereby reducing the resistance ratio of the substrate and the on-resistance of the semiconductor power device.

[0081] Furthermore, the thickness of the thin substrate formed by thinning the substrate is in the range of 2um to 5um. By thinning the substrate to 2um to 5um, the high doping concentration of the substrate itself can be used as an electric field buffer layer during reverse withstand voltage, ensuring that the electric field does not extend to the metal below when the device withstands reverse voltage. Compared with the SiC substrate in the prior art, the thickness is reduced by about 150um, and the on-resistance of the semiconductor power device can be greatly reduced. The thickness of the second support layer ranges from 80um to 200um, which can prevent the thickness of the second support layer from being too low, affecting the support of the second support layer.

[0082] S180, forming a contact hole exposing a portion of the first conductivity type second doping region, and forming a first electrode in the contact hole.

[0083] Specifically, the first electrode contacts the second doping region of the first conductivity type, so that the first electrode can be electrically connected to the second doping region of the first conductivity type. A second electrode is formed on the side of the second supporting layer away from the substrate, and the second electrode contacts the second supporting layer, so that the second electrode is electrically connected to the second supporting layer. Optionally, the material of the second supporting layer includes metal, and the second supporting layer can also be reused as the second electrode, without depositing metal material on the surface of the second supporting layer to prepare the electrode, thereby simplifying the preparation process of the semiconductor device. Among them, the first electrode is a source electrode, and the second electrode is a drain electrode; or, the first electrode is a drain electrode, and the second electrode is a source electrode.

[0084] The technical solution provided by the present invention forms a first supporting layer on a side of the gate structure layer away from the substrate. Based on the support and protection of the semiconductor epitaxial layer by the first supporting layer, the substrate can be thinned to prevent the wafer from warping or even breaking due to being too thin; and a second supporting layer is formed on the second side of the thinned substrate, and the second supporting layer is used as a partial substrate to form a target substrate together with the second supporting layer. Based on the support and protection of the semiconductor epitaxial layer by the second supporting layer, the first supporting layer is thinned or removed, and the subsequent preparation process is completed, which also prevents the wafer from warping or even breaking due to being too thin; the resistivity of the second supporting layer is set to be lower than the resistivity of the substrate, and under the same substrate thickness (the thickness of the SiC substrate in the prior art is the same as the thickness of the target substrate in the present application), the resistance of the substrate can be reduced, thereby reducing the resistance ratio of the substrate and the on-resistance of the semiconductor power device.

[0085] The above is the core inventive concept of the present invention. For ease of understanding, the specific implementation of each of the above steps will be described in detail below.

[0086] Based on the above embodiments, in one embodiment of the present invention, Figure 2is a schematic structural cross-sectional diagram corresponding to step S211 in a method for preparing a semiconductor power device provided in an embodiment of the present invention, Figure 3 is a schematic diagram of a structural cross-section corresponding to step S212 in a method for preparing a semiconductor power device provided in an embodiment of the present invention, with reference to Figure 2 and Figure 3 Step S120 of forming a semiconductor epitaxial layer 20 on the first surface of the substrate 10 may specifically include:

[0087] S211, growing a SiC material layer on the first surface of the substrate 10 to form an initial semiconductor epitaxial layer 20';

[0088] S212 , ion implantation is performed on the initial semiconductor epitaxial layer 20 ′ to form a semiconductor epitaxial layer 20 having a first conductivity type first doping region 21 , a second conductivity type doping region 22 and a first conductivity type second doping region 23 .

[0089] Among them, reference Figure 3 , N-type doping ions are injected into the first conductive type first doping region 21 and the first conductive type second doping region 23; P-type doping ions are injected into the second conductive type doping region 22 and the second conductive type heavily doped region; P+ and N+ shown in the figure indicate that the ion doping concentration in the region is high, and P- and N- indicate that the ion doping concentration in the region is low. Among them, the N-type doping ions can be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions can be Al (aluminum) ions or B (boron) ions.

[0090] Alternatively, P-type doping ions may be implanted into the first conductive type first doping region 21 and the first conductive type second doping region 23 ; and N-type doping ions may be implanted into the second conductive type doping region 22 and the second conductive type heavily doped region.

[0091] In some other embodiments of the present invention, the substrate 10 and the initial semiconductor epitaxial layer 20' are a whole SiC film structure formed in the same preparation process; ion implantation is then performed to form a first conductivity type first doping region 21, a second conductivity type doping region 22 and a first conductivity type second doping region 23 in the initial semiconductor epitaxial layer 20' to form a semiconductor epitaxial layer 20. That is, the substrate 10 and the semiconductor epitaxial layer 20 can be provided integrally.

[0092] Optionally, after the ion implantation, the method further includes: sputtering a carbon film on the surface of the semiconductor epitaxial layer 20, annealing in an annealing furnace, and then removing the carbon film on the surface of the semiconductor epitaxial layer 20. Since ion implantation may produce some lattice defects in the semiconductor, these defects may be eliminated by low temperature annealing or laser annealing after the ion implantation. Furthermore, after removing the carbon film on the surface of the semiconductor epitaxial layer 20, the method further includes: forming a sacrificial oxide layer on the surface of the semiconductor epitaxial layer 20 by a thermal oxidation process to repair the lattice on the surface of the semiconductor epitaxial layer 20; and then removing the sacrificial oxide layer.

[0093] On the basis of the above embodiments, on the basis of the above embodiments, Figure 4 is a schematic structural cross-sectional diagram corresponding to step S311 in a method for preparing a semiconductor power device provided by an embodiment of the present invention, Figure 5 is a schematic diagram of a structural cross-section corresponding to step S312 in a method for preparing a semiconductor power device provided in an embodiment of the present invention, with reference to Figure 4 and Figure 5 Step S130 of forming a gate structure layer 30 on a side of the semiconductor epitaxial layer 20 away from the substrate 10 and forming an opening 01 in the gate structure layer 30 to expose a portion of the first conductive type second doping region 23 may specifically include:

[0094] S131 , forming a gate insulating layer 31 and a polysilicon gate 32 in sequence on a side of the semiconductor epitaxial layer 20 away from the substrate 10 .

[0095] S132 , etching the polysilicon gate 32 and the gate insulating layer 31 above the first conductivity type second doping region 23 to form an opening 01 exposing a portion of the first conductivity type second doping region 23 .

[0096] The gate structure layer 30 includes a gate insulating layer 31 and a polysilicon gate 32; the gate material is polysilicon (POLY), forming the polysilicon gate 32; the gate insulating layer 31 may be made of SiO 2 The polysilicon gate 32 and the gate insulating layer 31 located above the first conductivity type second doping region 23 are etched to expose a portion of the surface of the first conductivity type second doping region 23 .

[0097] Based on the above embodiments, in one embodiment of the present invention, Figure 6 is a schematic diagram of a structural cross-section corresponding to step S411 in a method for preparing a semiconductor power device provided in an embodiment of the present invention, with reference to Figure 6 Step S140 forms a first supporting layer 40 on a side of the gate structure layer 30 away from the substrate 10, including:

[0098] S411 , forming a first supporting layer 40 on a surface of the gate structure layer 30 away from the substrate 10 and in the opening 01 by a deposition process.

[0099] Specifically, the first support layer 40 may be prepared by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0100] In another embodiment of the present invention, step S140 forms a first supporting layer 40 on a side of the gate structure layer 30 away from the substrate 10, comprising:

[0101] S421 , forming a first supporting layer 40 on a side of the gate structure layer 30 away from the substrate 10 through a bonding process.

[0102] Specifically, the method for preparing the first supporting layer 40 may form the first supporting layer 40 on a side of the gate structure layer 30 away from the substrate 10 by bonding.

[0103] Based on the above embodiments, the first support layer 40 may be a single-layer film structure or a multi-layer film structure. When the first support layer 40 is a multi-layer film structure, adjacent film layers may be bonded or stacked by deposition. The materials of different film layers may be the same or different.

[0104] Figure 7 is a schematic diagram of a structural cross-section corresponding to step S150 in a method for preparing a semiconductor power device provided in an embodiment of the present invention, with reference to Figure 7 Based on the support and protection of the semiconductor epitaxial layer 20 by the first support layer 40, the substrate 10 is thinned to form the substrate 101. Based on the above embodiments, in one embodiment of the present invention, in step S150, based on the support and protection of the semiconductor epitaxial layer 20 by the first support layer 40, the substrate 10 is thinned to form the substrate 101, which may specifically include:

[0105] S511 , based on the support and protection of the semiconductor epitaxial layer 20 by the first support layer 40 , the substrate 10 is thinned by dry etching combined with chemical mechanical polishing to form a substrate 101 .

[0106] Specifically, based on the supporting effect of the first supporting layer 40, the substrate 10 can be thinned by dry etching combined with chemical mechanical polishing to form a substrate 101, thereby preventing the problem of broken fragments during the thinning process of the substrate 10 and after the thinning process. Dry etching is a technology for thin film etching using plasma. When the gas exists in the form of plasma, it has two characteristics: on the one hand, the chemical activity of these gases in the plasma is much stronger than that in the normal state. According to the different materials to be etched, the appropriate gas can be selected to react with the material faster to achieve the purpose of etching and removal; on the other hand, the electric field can also be used to guide and accelerate the plasma so that it has a certain energy. When it bombards the surface of the etched object, it will knock out the atoms of the etched material, thereby achieving the purpose of etching by physical energy transfer. Therefore, dry etching is the result of a balance between physical and chemical processes on the surface of the wafer. Chemical mechanical polishing is also called chemical mechanical polishing. Its principle is a processing technology that combines chemical corrosion and mechanical removal. It is a technology that can achieve global surface flattening. In the embodiment of the present invention, the substrate 10 is thinned by dry etching combined with chemical mechanical polishing, which can improve the efficiency of thinning the substrate 10 and improve the flatness of the back side of the thinned substrate 10, thereby providing a flat surface for the preparation of the second electrode.

[0107] In another embodiment of the present invention, please continue to refer to Figure 7 In step S150, based on the support and protection of the semiconductor epitaxial layer 20 by the first support layer 40, the substrate 10 is thinned to form the substrate 101, which may specifically include:

[0108] S521 , based on the support and protection of the semiconductor epitaxial layer 20 by the first support layer 40 , the substrate 10 is thinned by laser stripping combined with chemical mechanical polishing to form a substrate 101 .

[0109] Specifically, based on the supporting function of the first supporting layer 40, the substrate 10 can be thinned by laser stripping combined with chemical mechanical polishing to prevent the problem of broken fragments during and after the thinning process of the substrate 10. The laser is shot into the substrate 10 and focused on a preset focal plane (or a focal region) in the substrate 10. The material of the substrate 10 at the focal plane (or in the focal region) is ablated / melted / decomposed / evaporated / quenched, etc., so that the substrate 10 on both sides of the focal plane (or the focal region) is separated, thereby achieving the thinning of the substrate 10. In the embodiment of the present invention, the substrate 10 is thinned by laser stripping combined with chemical mechanical polishing, which can improve the efficiency of the thinning of the substrate 10, improve the flatness of the back of the substrate 10 after thinning, and ensure that the peeled substrate material still has a certain thickness and can continue to be used, saving costs.

[0110] Based on the above embodiments, in another embodiment of the present invention, after the substrate 10 is thinned to form the substrate 101, the method further includes: annealing the substrate 101 and the semiconductor epitaxial layer 20, and planarizing the second surface of the substrate 101.

[0111] Specifically, the overall thickness of the material is very thin, and the SiC material layer is prone to bending or even breaking, so the substrate 10 is thinned and an annealing process is introduced to release the stress of the SiC material layer. Flattening the substrate 101 can be more conducive to subsequent operations.

[0112] Figure 8 is a schematic diagram of a structural cross-section corresponding to step S160 in a method for preparing a semiconductor power device provided in an embodiment of the present invention, with reference to Figure 8 , forming a second supporting layer 50 on the second surface of the substrate 101. Based on the above embodiments, in one embodiment of the present invention, the specific steps of forming the second supporting layer 50 on the second surface of the substrate 101 in step S160 may include:

[0113] S611 , forming an ohmic contact layer on the second surface of the substrate 101 .

[0114] S612 , forming an electrode metal layer on a side of the ohmic contact layer away from the substrate 101 .

[0115] Specifically, the metal material of the ohmic contact layer can be Ni or Ti, etc.; the electrode metal layer can be Al / Ti / Ni / Ag, Al / Ti / Ni / Au, Al / Si / Cu or other alloy materials with good conductive properties. The thickness of the electrode metal layer is greater than the thickness of the ohmic contact layer. The commonly used method for preparing the metal layer can be the PVD method. When the metal thickness requirement is large, electroplating, chemical plating or welding bonding methods can also be selected. Among them, the ohmic contact layer is a pure metal layer. The electrode metal layer is an alloy layer, which can improve the welding effect between the electrode metal layer and the external conductive structure.

[0116] In another embodiment of the present invention, the specific steps of forming the second supporting layer 50 on the second surface of the substrate 101 in step S160 include:

[0117] S621 , forming an ohmic contact layer on the second surface of the substrate 101 .

[0118] S622 , forming a barrier layer on a side of the ohmic contact layer away from the substrate 101 .

[0119] S613 , forming an electrode metal layer on a side of the ohmic contact layer away from the substrate 101 .

[0120] Specifically, in the embodiment of the present invention, a barrier layer is provided between the ohmic contact layer and the electrode metal layer, and the barrier layer blocks the metal material in the electrode metal layer, such as Al, from diffusing into the outer layer of the semiconductor, thereby preventing the Al material from reacting with the SiC material. The material of the barrier layer may be TiN, for example.

[0121] Based on the above embodiments, in one embodiment of the present invention, if a first support layer 40 is formed on the surface of the gate structure layer 30 away from the substrate 10 and in the opening 01 by a deposition process, then in step S170, thinning or removing the first support layer 40 includes:

[0122] The first support layer 40 is thinned or removed by at least one of wet etching, dry etching and chemical mechanical polishing.

[0123] Specifically, the first supporting layer 40 can be prepared by chemical vapor deposition (CVD) or physical vapor deposition (PVD); matching this preparation method, the first supporting layer 40 is thinned or removed by wet etching, dry etching or chemical mechanical polishing (CMP).

[0124] Based on the above embodiments, in another embodiment of the present invention, if the first support layer 40 is formed on the side of the gate structure layer 30 away from the substrate 10 by a bonding process, then in step S170, the first support layer 40 is thinned or removed, including:

[0125] The first supporting layer 40 is thinned or removed through a debonding process.

[0126] Specifically, the preparation method of the first support layer 40 can form the first support layer 40 on the side of the gate structure layer 30 away from the substrate 10 by bonding. That is, the first support layer 40 is combined with the device by bonding; matching this preparation method, the first support layer 40 is thinned or removed, which can be performed by debonding.

[0127] Based on the above embodiments, optionally, the material of the first supporting layer 40 includes a dielectric material or a conductive material. Fig. 9 is a schematic cross-sectional view of a structure after the first supporting layer is thinned in step S170 in a method for preparing a semiconductor power device provided by an embodiment of the present invention, Fig.101 is a schematic diagram of a structure cross-section after the first support layer is removed in step S170 in a method for preparing a semiconductor power device provided by an embodiment of the present invention. Fig. 9 When the material of the first support layer 40 is a dielectric material, the first support layer 40 is thinned, and the thinned first surface support layer 401 is used as an interlayer insulating layer ILD for isolating the polysilicon gate 32 and the first electrode 60, without the need to subsequently deposit dielectric materials to form the interlayer insulating layer ILD, thereby further simplifying the device preparation process. Fig.10 When the material of the first support layer 40 is a conductive material, the first support layer 40 is removed to prevent the first support layer 40 from causing a short circuit between the gate and the first electrode 60 .

[0128] Optionally, in order to enhance the insulation of the interlayer insulating layer ILD, a dielectric material may be deposited again on the surface of the thinned first surface supporting layer 401. Alternatively, when the material of the first supporting layer 40 is a dielectric material, the first supporting layer 40 may be removed, and a dielectric material may be deposited on a side of the gate structure layer 30 away from the substrate 10 to form the interlayer insulating layer ILD.

[0129] On the basis of the above embodiments, in one embodiment of the present invention, the first support layer 40 is thinned, and the step S180 of forming a contact hole exposing a portion of the first conductive type second doping region 23 includes:

[0130] S811, forming a contact hole 02 exposing a portion of the first conductive type second doping region 23 in the thinned first supporting layer 401; the thinned first supporting layer 401 is used as an interlayer insulating layer ILD isolating the first electrode 60 from the gate structure. (Refer to Fig.11 )

[0131] In the embodiment of the present invention, the first support layer 40 is a dielectric material, and the thinned first surface support layer 401 is reused as an interlayer insulating layer.

[0132] On the basis of the above embodiments, in another embodiment of the present invention, the first supporting layer 40 is removed, and in step S180, a contact hole exposing a portion of the first conductive type second doping region 23 is formed, including:

[0133] S821, forming an interlayer insulating layer ILD on the side of the gate structure layer 30 away from the substrate 10 and in the opening 01. (Refer to Fig.12 )

[0134] S822, forming a contact hole 03 in the interlayer insulating layer ILD to expose a portion of the first conductive type second doping region 23. (Refer to Fig.13 )

[0135] In the embodiment of the present invention, the first support layer 40 can be a conductive material or a dielectric material. The first support layer 40 and the interlayer insulating layer ILD are different film layer structures.

[0136] Fig.14 FIG. 1 is a schematic cross-sectional view of a structure of forming a first electrode in step S180 in a method for preparing a semiconductor power device provided by an embodiment of the present invention, with reference to FIG. Fig.14 Forming the first electrode 60 includes: depositing a metal material on a side of the interlayer insulating layer ILD away from the substrate 101 and in the contact hole to form the first electrode 60 .

[0137] Based on the above embodiments, in one embodiment of the present invention, after forming a contact hole exposing a portion of the first conductive type second doping region 23 in step S180 and forming a first electrode 60 in the contact hole, the method further includes:

[0138] A passivation layer is formed on the surface of the first electrode 60 away from the substrate 10, and the passivation layer is etched to expose the welding area where the first electrode 60 is welded to the external pad; and a dicing test is performed on the current wafer.

[0139] Among them, since the thickness of the SiC material layer in this application (the sum of the thickness of the semiconductor epitaxial layer 20 and the thickness of the substrate 101 after thinning treatment) is very thin, diamond cutting of the SiC material can be selected first during slicing, and the softer metal material on the back can be cut by wire cutting or high-pressure water jet cutting, which can further save costs.

[0140] The embodiment of the present invention further provides a semiconductor power device, which is formed by the method for preparing the semiconductor power device described in any of the above embodiments; Fig.14 , semiconductor power devices include:

[0141] The target substrate comprises a substrate 101 of a preset thickness and a second support layer 50 located on a second surface of the substrate 101; the resistivity of the second support layer 50 is lower than the resistivity of the substrate 10;

[0142] The semiconductor epitaxial layer 20 is located on the first surface of the substrate 101; wherein the semiconductor outer layer includes a first conductive type first doping region 21, a second conductive type doping region 22 and a first conductive type second doping region 23 which are sequentially away from the substrate 10; and the second conductive type doping region 22 covers the bottom and sidewalls of the first conductive type second doping region 23, and the first conductive type first doping region 21 covers the bottom and sidewalls of the second conductive type doping region 22;

[0143] The gate structure layer 30 is located on a side of the semiconductor epitaxial layer 20 away from the target substrate 10 , and the gate structure layer 30 includes an opening 01 exposing a portion of the first conductivity type second doping region 23 ;

[0144] An interlayer insulating layer ILD is located on a surface of the gate structure layer 30 away from the target substrate 10 and a sidewall of the gate structure layer 30; wherein the interlayer insulating layer ILD includes a contact hole exposing a portion of the first conductive type second doping region 23;

[0145] The first electrode 60 is located on a surface of the interlayer insulating layer ILD away from the target substrate 10 and in the contact hole.

[0146] The semiconductor power device provided in the embodiment of the present invention replaces the SiC substrate 10 in the prior art with a thinned substrate 101 and a second support layer 50 located on the second surface of the substrate 101. The second support layer 50 is used as a part of the substrate 10, and together with the thinned substrate 101, constitutes the target substrate 10. Based on the support and protection of the semiconductor epitaxial layer 20 by the second support layer 50, during the thinning or removal of the first support layer 40, and the completion of the subsequent preparation process, the wafer can be prevented from warping due to excessive thinness, or even breaking; the resistivity of the second support layer 50 is set to be lower than the resistivity of the substrate 10, and under the same substrate 10 thickness (the thickness of the SiC substrate 10 in the prior art is the same as the thickness of the target substrate 10 in the present application), the resistance of the substrate 10 can be reduced, thereby reducing the resistance ratio of the substrate 10 and the on-resistance of the semiconductor power device.

[0147] Optionally, the thickness of the substrate 101 is in the range of 2 um to 5 um; the thickness of the second supporting layer 50 is in the range of 80 um to 200 um.

[0148] Specifically, the back substrate 10 is thinned to 2um to 5um, and the high doping concentration of the thinned substrate 101 itself can be used as an electric field buffer layer during reverse withstand voltage, ensuring that the electric field does not extend to the metal below when the device withstands reverse voltage. At the same time, compared with the SiC substrate 10 in the prior art, the thickness is reduced by about 150um, and the on-resistance can be greatly reduced. The thickness of the second support layer 50 ranges from 80um to 200um, which can prevent the thickness of the second support layer 50 from being too low, affecting the support of the second support layer 50, and prevent the thickness of the second support layer 50 from being too large, resulting in excessive overall thickness and on-resistance of the semiconductor device.

[0149] Optionally, the material of the second supporting layer 50 includes metal, and the second supporting layer 50 is also reused as a second electrode; wherein the first electrode 60 is a source electrode S, and the second electrode is a drain electrode D; or, the first electrode 60 is a drain electrode D, and the second electrode is a source electrode S.

[0150] The second support layer 50 may further include an ohmic contact layer, a barrier layer (optional), and an electrode metal layer. The ohmic contact layer metal is commonly made of Ni, Ti, etc.; the barrier layer is commonly made of TiN, etc.; the electrode metal layer has the largest thickness and may be made of Al / Ti / Ni / Ag, Al / Ti / Ni / Au, Al / Si / Cu or other alloy materials with good electrical conductivity.

[0151] An embodiment of the present invention further provides a power module, comprising a substrate and at least one semiconductor power device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor power device. The same technical effects are achieved and will not be described in detail here.

[0152] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0153] The power conversion circuit comprises a circuit board and at least one semiconductor power device as described in any embodiment of the present invention, and the semiconductor power device is electrically connected to the circuit board. The same technical effects are achieved and will not be described in detail here.

[0154] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input the power into the load. The same technical effects are achieved, which will not be described in detail here.

[0155] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for preparing a semiconductor power device, characterized in that: include: Providing a substrate; the substrate comprising a first surface and a second surface opposite to each other; A semiconductor epitaxial layer is formed on the first surface of the substrate; wherein the semiconductor epitaxial layer comprises a first conductive type first doping region, a second conductive type doping region and a first conductive type second doping region which are sequentially away from the substrate; and the second conductive type doping region covers the bottom and sidewalls of the first conductive type second doping region, and the first conductive type first doping region covers the bottom and sidewalls of the second conductive type doping region; forming a gate structure layer on a side of the semiconductor epitaxial layer away from the substrate, and forming an opening in the gate structure layer that exposes a portion of the first conductive type second doped region; forming a first supporting layer on a side of the gate structure layer away from the substrate; Based on the support and protection of the semiconductor epitaxial layer by the first supporting layer, the substrate is thinned so that the substrate reaches a preset thickness; forming a second supporting layer on the second surface of the substrate; wherein the resistivity of the second supporting layer is lower than the resistivity of the substrate, and the substrate of the preset thickness and the second supporting layer are used to constitute a target substrate; Based on the support and protection of the semiconductor epitaxial layer by the second supporting layer, the first supporting layer is thinned or removed; forming a contact hole exposing a portion of the first conductive type second doped region, and forming a first electrode in the contact hole; Forming a first supporting layer on a side of the gate structure layer away from the substrate, comprising: forming the first supporting layer on a surface of the gate structure layer away from the substrate and in the opening by a deposition process; In the case of thinning the first supporting layer, forming a contact hole exposing a portion of the first conductive type second doping region, comprises: A contact hole exposing a portion of the second doped region of the first conductive type is formed in the thinned first supporting layer; the first supporting layer is used as an interlayer insulating layer isolating the first electrode from the gate structure; The semiconductor power device is a SiC power device; the substrate has the same doping type as the first conductive type first doping region, and the ion doping concentration of the substrate is greater than the ion doping concentration of the first conductive type first doping region, and the substrate is also used as a buffer layer.

2. The method for preparing a semiconductor power device according to claim 1, characterized in that: The preset thickness range is 2um~5um; the thickness range of the second supporting layer is 80um~200um.

3. The method for preparing a semiconductor power device according to claim 1, characterized in that: The material of the second supporting layer includes metal, and the second supporting layer is also reused as a second electrode; The first electrode is a source electrode, and the second electrode is a drain electrode; or the first electrode is a drain electrode, and the second electrode is a source electrode.

4. The method for preparing a semiconductor power device according to claim 1, characterized in that: The thinning or removing of the first supporting layer includes: The first supporting layer is thinned or removed by at least one of wet etching, dry etching and chemical mechanical polishing.

5. The method for preparing a semiconductor power device according to claim 1, characterized in that: A first supporting layer is formed on a side of the gate structure layer away from the substrate, comprising: Forming a first supporting layer on a side of the gate structure layer away from the substrate by a bonding process; The thinning or removing of the first supporting layer includes: The first supporting layer is thinned or removed through a debonding process.

6. The method for preparing a semiconductor power device according to claim 1, characterized in that: The material of the first supporting layer includes a dielectric material or a conductive material; In the case where the material of the first supporting layer is a conductive material, removing the first supporting layer; In the case that the material of the first supporting layer is a dielectric material, the first supporting layer is thinned.

7. The method for preparing a semiconductor power device according to claim 6, characterized in that: Based on removing the first supporting layer, a contact hole exposing a portion of the first conductive type second doping region is formed, including: forming an interlayer insulating layer on a side of the gate structure layer away from the substrate and in the opening; A contact hole exposing a portion of the first conductive type second doping region is formed in the interlayer insulating layer.

8. The method for preparing a semiconductor power device according to claim 1, characterized in that: The substrate is subjected to a thinning process, comprising: Thinning the substrate by dry etching combined with chemical mechanical polishing; Alternatively, the substrate is thinned by laser lift-off combined with chemical mechanical polishing.

9. The method for preparing a semiconductor power device according to claim 3, characterized in that: Forming a second supporting layer on the second surface of the substrate comprises: forming an ohmic contact layer on the second surface of the substrate; An electrode metal layer is formed on a side of the ohmic contact layer away from the substrate.

10. The method for preparing a semiconductor power device according to claim 1, characterized in that: After the substrate is thinned, the method further comprises: The substrate and the semiconductor epitaxial layer are annealed, and the second surface of the substrate is planarized.

11. A semiconductor power device, characterized in that: The semiconductor power device is formed by the method for preparing the semiconductor power device according to any one of claims 1 to 10; the semiconductor power device comprises: A target substrate; the target substrate comprises a substrate of a preset thickness and a second supporting layer located on a second surface of the substrate; the resistivity of the second supporting layer is lower than the resistivity of the substrate; A semiconductor epitaxial layer, located on the first surface of the substrate; wherein the semiconductor epitaxial layer comprises a first conductive type first doping region, a second conductive type doping region and a first conductive type second doping region, which are sequentially away from the substrate; and the second conductive type doping region covers the bottom and side walls of the first conductive type second doping region, and the first conductive type first doping region covers the bottom and side walls of the second conductive type doping region; a gate structure layer, located at a side of the semiconductor epitaxial layer away from the target substrate, the gate structure layer including an opening exposing a portion of the second doped region of the first conductivity type; an interlayer insulating layer, located on a surface of the gate structure layer away from the target substrate and a sidewall of the gate structure layer; wherein the interlayer insulating layer comprises a contact hole exposing a portion of the first conductive type second doping region; The first electrode is located on a surface of the interlayer insulating layer away from the target substrate and in the contact hole.

12. The semiconductor power device according to claim 11, characterized in that: The preset thickness ranges from 2um to 5um; the thickness range of the second supporting layer is from 80um to 200um.

13. The semiconductor power device according to claim 11, characterized in that: The material of the second supporting layer includes metal, and the second supporting layer is also reused as a second electrode; The first electrode is a source electrode, and the second electrode is a drain electrode; or the first electrode is a drain electrode, and the second electrode is a source electrode.

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