Methods for forming deep and shallow trenches in trench networks and their semiconductor devices

Abstract

This invention relates to a method for forming deep and shallow trenches in trench networks and related semiconductor devices. Specifically, it addresses the shortcomings of existing deep and shallow trench formation techniques. First, deep and shallow trenches are formed under the protection of a hard mask, with a protective transition region retained at the junction of the formed deep and shallow trenches. Then, etching continues to increase the width of the deep and shallow trenches until they interconnect within the chip. During this step, the transition region is etched to form a raised transition area. This invention reduces the difficulty of process control in photolithography and trench etching during manufacturing, and improves the uniformity and consistency of the trenches.

Description

Technical Field

[0001] This invention relates to a method for forming power semiconductor devices, and particularly to a method for forming deep trenches and shallow trenches in a trench network of a power semiconductor device. Background Technology

[0002] To further improve the performance of trench power devices, it is necessary to form a trench network structure consisting of deep trenches 101 and shallow trenches 102 in the trench device, as shown in Chinese patent applications CN2023116607210 and CN2023113557510.

[0003] Generally, the method for forming deep and shallow trenches in a trench network is as follows: A hard mask pattern is formed on the semiconductor. By adjusting the etching process and etching simultaneously, shallow trenches are etched at the narrower pattern opening, and deep trenches are etched at the wider pattern opening. Due to simultaneous etching, the depth difference between the deep and shallow trenches cannot be too large, and precise process control is required. Furthermore, since the trench depth is entirely controlled by the hard mask width, process offsets in the hard mask pattern opening width, surface material residue, and slight deviations in the etching angle can easily lead to defects in the trench structure after etching. For example, an over-etched region may appear at the junction of deep trench 101 and shallow trench 102. Figure 1 As shown in A; for example, in shallow trench 102, there are areas of insufficient etching, such as... Figure 1 As shown in B, this type of trench defect can affect subsequent trench filling processes and even cause device failure, thus reducing production yield. In addition, there is a significant transition region between the deep trench 101 and the shallow trench 102, which limits the further reduction of cell size along the shallow trench direction, thereby limiting further improvement in device performance.

[0004] Another method for forming deep and shallow trenches in a trench network is as follows: First, a hard mask is formed on the semiconductor. A first photolithography step is performed to form openings in the first hard mask pattern, and then etching is performed to create the first type of trenches. Next, a second photolithography step is performed to form openings in the second hard mask pattern. Finally, etching is performed, resulting in deep trenches formed from the first type of trenches and shallow trenches formed below the openings in the second hard mask pattern. In other words, different openings are formed sequentially on the hard mask, and then different openings are etched to form trenches of different depths. This method can increase the depth difference between deep and shallow trenches and improve / reduce the requirements for etching process control. However, it still struggles to solve the problem of excessively long transition regions between deep and shallow trenches. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides a method for forming deep trenches and shallow trenches in a trench network. In general, the method involves: first, under the protection of a hard mask, forming deep trenches and shallow trenches sequentially, with a protective transition region retained at the connection between the formed deep and shallow trenches; then, continuing etching to increase the width of the deep and shallow trenches until they are interconnected within the chip; in this step, the transition region is etched to form a raised transition area.

[0006] Specifically, one proposed method for forming this product includes the following steps: The first step is to form a hard mask layer on the upper surface of the semiconductor; The second step is to perform photolithography on the hard mask to form the first hard mask pattern opening; The third step is to perform vertical semiconductor etching to form the first type of trench; The fourth step is to perform a second photolithography on the hard mask to form a second hard mask pattern opening, wherein a transition area is retained at the connection between the first hard mask pattern opening and the second hard mask pattern opening to provide protection. The fifth step involves vertical semiconductor etching to form deep trenches and shallow trenches, with a protective transition region remaining at the junction of the deep and shallow trenches. The sixth step involves isotropic etching of the semiconductor to increase the width of the deep and shallow trenches, connecting them within the chip; or Thermal oxidation is performed to form a sacrificial oxide layer on the upper surface of the semiconductor and in all trenches, and to completely oxidize the transition region between deep trenches and shallow trenches. Then the sacrificial oxide layer is removed to connect the deep trenches and shallow trenches to each other. The transition area is characterized by a raised transition zone.

[0007] Furthermore, before the second photolithography step in the fourth step, the opening of the first hard mask pattern formed in the first photolithography is enlarged; or In step six, before isotropic etching of the semiconductor, the hard mask layer located on the upper surface of the semiconductor is removed; or Before thermal oxidation in step six, the trenches are pre-etched isotropically for a short period of time; or In the sixth step, during the removal of the sacrificial oxide layer, only the oxide material above the transition area is removed, so that the deep trenches and shallow trenches are connected to each other.

[0008] Furthermore, the manufacturing process of the shielded gate trench MOSFET device formed using this method is as follows: The first step involves forming a hard mask thin oxide layer, a hard mask thin nitride layer, and a hard mask thick oxide layer on the semiconductor layer, respectively. Then, photolithography is performed to form a first hard mask pattern opening. Next, the first hard mask pattern opening is etched to form a first type of trench. After etching, the first type of trench forms a deep trench. The second step involves photolithography to form a second hard mask pattern opening on the hard mask thin oxide layer, hard mask thin nitride layer, and hard mask thick oxide layer. Then, shallow trenches are etched under the opening of the second hard mask pattern, and a protective transition region exists between the shallow trenches and the deep trenches. The third step involves etching the hard mask thin oxide layer, hard mask thin nitride layer, and hard mask thick oxide layer to shrink the hard mask layer onto the semiconductor platform. At this point, the hard mask thin oxide layer and hard mask thin nitride layer located in the transition region between the deep trench and the shallow trench are completely removed. The fourth step involves thermal oxidation to form a trench oxide layer. At this point, the transition area is completely oxidized, and the resulting oxide connects the deep trenches and the shallow trenches. The fifth step is to form a shielding gate electrode in the deep trench; Step 6: Etch oxide to completely remove oxide from the transition area, making the deep trenches and shallow trenches interconnected, while retaining the raised transition area at the corresponding position of the transition area. Step 7: Fill with oxides; Step 8: Perform chemical mechanical polishing to remove the oxides on the upper surface and stop on the thick oxide layer of the hard mask; Step 8: Etch back the oxide; Step 9: Form the gate oxide layer and the gate electrode; The tenth step involves forming the ion implantation body region and source region, forming contact holes, metallizing, and finally forming a shielded gate trench MOSFET device.

[0009] Furthermore, in the fourth step, after the trench oxide layer is formed by thermal oxidation, additional oxides are deposited within the trenches to increase the thickness of the trench oxide layer, or additional nitride layers and oxides are deposited within the trenches; or, In the fifth step, the shielding gate electrode is made of polycrystalline silicon and is formed through deposition and etch-back. The depth of the shielding gate formed after etch-back is deeper than that of the shallow trench, and the polycrystalline silicon in the shallow trench is completely removed during the etch-back process; or After etching back the polysilicon, the thickness of the higher part of the trench oxide layer is reduced. At this time, the lower part of the trench oxide layer is protected by polysilicon to form a trench oxide layer that is thinner at the top and thicker at the bottom.

[0010] The manufacturing process of the shielded gate trench MOSFET device formed according to the above method is as follows: The first step is to form hard mask layers on the semiconductor layer, then to form the first hard mask pattern opening by photolithography, and then to etch the semiconductor on the first hard mask pattern opening to form the first type of trench. The second step involves performing a second photolithography on the hard mask to form the second hard mask pattern opening, and then performing semiconductor etching in the vertical direction. The first type of trench forms a deep trench, and the opening of the second hard mask pattern forms a shallow trench. At this time, the deep trench and the shallow trench are not connected to each other. The third step is to perform isotropic etching on the semiconductor to increase the width of the deep trenches and shallow trenches and to connect the deep trenches and shallow trenches inside the chip. The fourth step involves first forming a trench oxide layer in the trench, and then forming a shielding gate electrode in the deep trench. The shallow trench is completely filled with the trench oxide layer material. The fifth step involves first etching the trench oxide layer, and then forming the inter-electrode oxide layer and the gate oxide layer. The sixth step involves forming the ion implantation body region and source region, forming contact holes, metallizing, and finally forming a shielded gate trench MOSFET device.

[0011] Furthermore, in the fifth step, the method for etching the oxide layer of the trench is wet etching. The oxide layer remaining at the bottom of the shallow trench after etching is used to reduce the capacitance of the device and improve switching performance; or Before etching the trench oxide layer, ion implantation is performed on the polysilicon of the shielding gate electrode to increase the oxidation rate of the polysilicon and form a thick inter-electrode oxide layer.

[0012] The present invention discloses a semiconductor device prepared according to the above method. The semiconductor device includes a trench network composed of deep trenches and shallow trenches. The deep trenches and shallow trenches are formed by the above-described forming method. The edges of the shallow trenches and the deep trenches are provided with raised transition regions. The length of the raised transition regions is less than one-third of the length of the shallow trenches and is between 0.03-1 μm. The height of the raised transition regions is between 0.05-0.5 μm.

[0013] Furthermore, the raised transition area is a smooth arc surface that smoothly transitions from the sidewall to the inside by a shallow groove.

[0014] This invention solves the problem of excessively long transition regions between deep and shallow trenches. In addition, it reduces the difficulty of process control for photolithography and trench etching during the manufacturing of devices with trench network structures, and increases the uniformity and consistency of the depth and width of deep and shallow trenches in the trench network structure of trench power devices. Attached Figure Description

[0015] Figure 1 This is a defect in an existing method for forming trench network structures.

[0016] Figure 2-4 This is a cross-sectional schematic diagram of a key step in forming a trench network structure according to an embodiment of the present invention.

[0017] Figure 5-6 This is a cross-sectional schematic diagram of a key step in forming a trench network structure according to another embodiment of the present invention.

[0018] Figure 7-16 This is a cross-sectional schematic diagram of the key steps in the manufacturing process of a shielded gate trench MOSFET device according to an embodiment of the present invention.

[0019] Figure 17-22 This is a cross-sectional schematic diagram of a key step in the manufacturing process of a shielded gate trench MOSFET device according to another embodiment of the present invention. Detailed Implementation

[0020] The positional terms used in this document, such as "up," "down," "left," "right," "front," "back," "vertical," "horizontal," and "vertical," refer to the relative positions shown in the reference illustrations. No fixed orientation is restricted in actual implementation. It should be noted that the devices in the accompanying drawings are not necessarily drawn to scale. The straight lines representing the boundaries of doped regions and trenches in the drawings, as well as the sharp angles formed by these boundaries, are generally not straight lines or precise angles in practical applications.

[0021] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] The method of the first embodiment of the present invention is as follows: Figure 2-4 As shown: The first step is to form a hard mask layer 121 on the upper surface of the semiconductor.

[0023] The second step is to perform photolithography on the hard mask to form the first hard mask pattern opening 111.

[0024] The third step involves vertical semiconductor etching to form the first type of trench 201, such as... Figure 2 As shown.

[0025] The fourth step is to perform a second photolithography on the hard mask to form a second hard mask pattern opening 112, wherein the first hard mask pattern opening 111 and the second hard mask pattern opening 112 are not directly connected to each other.

[0026] The fifth step involves vertical semiconductor etching to form deep trenches 101 and shallow trenches 102. At this stage, the deep trenches 101 and shallow trenches 102 are not interconnected, and an etching protection zone 113 is maintained at the junction of the deep trenches 101 and shallow trenches 102. Figure 3 As shown.

[0027] The sixth step involves isotropic etching of the semiconductor to increase the width of the deep trench 101 and the shallow trench 102. The separated etch protection zones 113 are etched, connecting portions of the deep trench 101 and the shallow trench 102. Figure 4 As shown. In this step, due to the presence of the etch protection zone 113, the formed trench 102 is a connection transition region 114 with an upwardly convex structure. This transition region has a smooth arc surface, which helps to prevent breakdown weaknesses caused by process issues and avoids reliability problems caused by a drop in breakdown voltage. In addition, since the breakdown voltage of this upwardly convex connection transition region 114 is higher than the breakdown voltage at the location of the connected shallow trench 102, it can ensure that the path of avalanche current is far away from the trench transition region during device avalanche breakdown, preventing the thinner gate oxide layer in the transition region from being broken down, thus improving the overall avalanche breakdown resistance of the device.

[0028] In the first step described above, the hard mask layer 121 may be an oxide layer, a nitride layer, or a combination of oxide and nitride layers. In one embodiment, the hard mask layer 121 is a combination layer, consisting of, from bottom to top: a 100-1000 Å oxide layer, a 300-4000 Å nitride layer, and a 500-10000 Å oxide layer. The hard mask layer 121 may be formed by thermal oxidation and / or deposition.

[0029] In steps three and five above, the etching of the trench may be plasma etching; in step six, the trench etching step may include wet etching.

[0030] Before the second photolithography step in the fourth step, the opening 111 of the first hard mask pattern formed in the first photolithography step may be enlarged. This enlargement may be achieved by isotropic etching of all or part of the hard mask material. Due to alignment errors between the fourth and first photolithography steps, the distance between the first and second hard mask pattern openings 111 and 112 is easily affected by the photolithography process. This enlargement process increases the distance between the first and second hard mask pattern openings 111 and 112, reducing the process control requirements for the photolithography process.

[0031] In the sixth step of the above process, before isotropic etching of the semiconductor, the hard mask layer located on the upper surface of the semiconductor may be removed first. This can prevent device defects caused by the partial detachment of the hard mask layer material located between the first hard mask pattern opening 111 and the second hard mask pattern opening 112 during the semiconductor etching process, thereby improving the stability of the process.

[0032] As shown in the figure, the above embodiment can better control the uniformity of the morphology of the transition region between deep trenches and shallow trenches through the etching in the sixth step, so as to reduce the process problems that may occur in the subsequent device formation process.

[0033] Based on the above embodiments, a modified embodiment of the method is as follows: Figure 5-6 As shown, this embodiment is similar to Figure 2-3 The first five steps are the same as those in the embodiments described above, except that: The sixth step involves thermal oxidation to form a sacrificial oxide layer 123 on the upper surface of the semiconductor and within the trenches, and to completely oxidize the transition region 122 between the deep trench 101 and the shallow trench 102, as shown below. Figure 5 As shown.

[0034] Step 7: Remove the sacrificial oxide layer to connect the deep trench 101 and the shallow trench 102, as shown below. Figure 6 As shown.

[0035] In a modified embodiment, in step six above ( Figure 5 Before thermal oxidation, the hard mask layer on the upper surface of the semiconductor may be completely removed first. This step helps to increase the oxidation rate of the transition region 122 and prevents process problems caused by the hard mask falling off during the oxidation process and subsequent processes.

[0036] In one embodiment, in the sixth step described above ( Figure 5 Before thermal oxidation, the trench is first subjected to short-term isotropic etching. This method can further reduce the thickness of the transition region 122 to ensure that the region is completely oxidized in the subsequent thermal oxidation process.

[0037] In one embodiment, during the removal of the sacrificial oxide layer in the seventh step, the sacrificial oxide layer 123 may not be completely removed. Only a portion of the oxide material above the transition region 122 may be removed, so that the deep trench 101 and the shallow trench 102 are connected to each other. The remaining sacrificial oxide layer material 123 located in the trench may be retained and used as the trench oxide layer of the device.

[0038] Figure 5-6 The illustrated embodiments are compared to Figure 2-4 The embodiment shown utilizes thermal oxidation and oxide removal to ensure that the transition region between deep and shallow trenches is completely etched; moreover, the etching of this transition region is less susceptible to over-etching or under-etching caused by changes in the trench network morphology; and the method can make the morphology of the trench transition region more uniform.

[0039] The trench network formation methods described in the above embodiments can be applied to the manufacturing processes of various trench devices, forming new device manufacturing processes based on existing device formation steps.

[0040] The manufacturing process of a shielded gate trench MOSFET device according to an embodiment of the present invention is as follows: First, a hard mask thin oxide layer 133, a hard mask thin nitride layer 132, and a hard mask thick oxide layer 131 are formed on the semiconductor layer 100, respectively. Then, photolithography is performed to form a first hard mask pattern opening 111. Next, the semiconductor is etched on the first hard mask pattern opening to form a first type of trench 201. After etching, the first type of trench 201 forms a deep trench 101, such as... Figure 7 As shown.

[0041] The second step involves photolithography, forming a second hard mask pattern opening 112 on the hard mask thin oxide layer 133, hard mask thin nitride layer 132, and hard mask thick oxide layer 131. Then, the semiconductor is etched, forming a shallow trench 102 under the second hard mask pattern opening 112. The first type of trench 201 forms a deep trench 101 after etching. Figure 8 As shown.

[0042] Typically, the minimum spacing between the deep trench 101 and the shallow trench 102 after semiconductor etching is between 0.1 and 0.6 μm. In some embodiments, the sidewalls of the trenches formed after semiconductor etching may not be perfectly perpendicular, and may have an angle of 85 to 90 degrees with the upper plane of the semiconductor. In some embodiments, semiconductor etching may include a single isotropic etching step.

[0043] The third step involves etching the hard mask thin oxide layer 133, the hard mask thin nitride layer 132, and the hard mask thick oxide layer 131, causing the hard mask layers to shrink onto the semiconductor platform. At this point, the hard mask thin oxide layer 133 and the hard mask thin nitride layer 132 located in the transition region 122 between the deep trench 101 and the shallow trench 102 are completely removed. Figure 9 As shown.

[0044] In one embodiment, the above-described method for etching the hard mask layer may be: first, isotropically etching the thin nitride layer 132 of the hard mask, and then completely removing the thick oxide layer 131 of the hard mask.

[0045] In some embodiments, a portion of the hard mask thin oxide layer 133 and the hard mask thin nitride layer 132 may be retained on the transition region 122 after the hard mask layer is etched. The retained hard mask thin oxide layer 133 and hard mask thin nitride layer 132 may serve as a stop layer for the polishing process in subsequent processes.

[0046] The fourth step involves thermal oxidation to form a trench oxide layer 222. At this point, the transition region 122 is completely oxidized, and the resulting oxide connects the deep trench 101 and the shallow trench 102, as shown below. Figure 10 As shown.

[0047] In one embodiment, after the trench oxide layer 222 is formed by thermal oxidation, additional oxide may be deposited within the trench to increase the thickness of the trench oxide layer. In another embodiment, additional nitride layers and oxides may also be deposited within the trench. In some embodiments, the oxide layer formed by thermal oxidation may completely fill the shallow trench 102.

[0048] The fifth step is to form a shielding gate electrode 125 in the deep trench, such as... Figure 11 As shown.

[0049] The shielding gate electrode is typically made of polysilicon and is formed by deposition and etchback. Typically, the depth of the shielding gate formed after etchback is deeper than that of the shallow trench 102, and the polysilicon in the shallow trench 102 is completely removed during etchback.

[0050] In one embodiment, after etching back the polysilicon, an isotropic oxide etching step may be performed to thin the higher portion of the trench oxide layer 222. Meanwhile, the lower portion of the trench oxide layer 222 remains unetched due to the protection of the polysilicon, maintaining its original thickness. Then, polysilicon deposition is performed and etched back. This step creates a trench oxide layer 222 that is thinner at the top and thicker at the bottom, which is beneficial for device charge balance and improves device performance.

[0051] Step 6: Etch the oxide to completely remove the oxide on the transition region 122, making the deep trench 101 and the shallow trench 102 interconnected, as shown below. Figure 12 As shown.

[0052] The method for etching oxides is usually wet etching. After etching, a portion of the trench oxide layer 222 on the left and right sides of the shielding gate electrode 125 in the deep trench 101 may be etched to form oxide grooves. The shallower the groove, the better. If the depth-to-width ratio of the groove is too high, it may affect the subsequent oxide filling process. Therefore, in some variations, a method of first dry etching and then wet etching may be used to ensure the removal of the oxide layer on the transition region 122 while reducing the etching depth of the oxide grooves on the inner wall of the deep trench.

[0053] Step 7: Fill with oxides, such as Figure 13 As shown.

[0054] The oxide filling method may involve high-density ion deposition.

[0055] Step 8: Perform chemical mechanical polishing to remove the oxides on the upper surface, stopping at the thick oxide layer 131 on the hard mask, as shown. Figure 14 As shown.

[0056] Step 8: Etch back the oxide, such as... Figure 15 As shown.

[0057] Step nine involves forming the gate oxide layer and the gate electrode, such as... Figure 16 As shown.

[0058] The tenth step involves forming the ion implantation body region and source region, forming contact holes, metallizing, and finally forming a shielded gate trench MOSFET device.

[0059] The manufacturing process of another shielded gate trench MOSFET device according to another embodiment of the present invention is as follows: First, a hard mask layer 121 is formed on the semiconductor layer 100, followed by photolithography to form a first hard mask pattern opening 111. Then, the semiconductor is etched on the first hard mask pattern opening to form a first type of trench 201, such as... Figure 17 As shown.

[0060] The second step involves performing a second photolithography process on the hard mask to form a second hard mask pattern opening 112, followed by vertical semiconductor etching to form deep trenches 101 and shallow trenches 102. At this stage, the deep trenches 101 and shallow trenches 102 are not interconnected. Figure 18 As shown.

[0061] The third step involves isotropic etching of the semiconductor to increase the width of the deep trenches 101 and shallow trenches 102, and to interconnect the deep trenches 101 and shallow trenches 102 within the chip. Figure 19 As shown.

[0062] The hard mask layer 121 may be removed before isotropic etching of the semiconductor or after isotropic etching.

[0063] The fourth step involves first forming a trench oxide layer 222 within the trench, and then forming a shielding gate electrode 125 in the deep trench 101. The shallow trench 102 is completely filled with the trench oxide layer 222 material, such as... Figure 20 As shown.

[0064] The fifth step involves first etching the trench oxide layer 222, followed by forming the inter-electrode oxide layer 227 and the gate oxide layer, as follows: Figure 21 As shown.

[0065] The method for etching the oxide layer in the trench may be wet etching, and the etching depth is usually shallower than that of the shallow trench 102. Therefore, the oxide layer remaining at the bottom of the shallow trench is beneficial to reducing the capacitance of the device and improving the switching performance.

[0066] The inter-electrode oxide layer 227 and the gate oxide layer may be formed simultaneously through a thermal oxidation process. In one embodiment, ion implantation is performed on the shielded gate electrode polysilicon 125 before etching the trench oxide layer 222 to increase the oxidation rate of the polysilicon, which is beneficial for forming a thicker inter-electrode oxide layer 227 during thermal oxidation.

[0067] The sixth step involves forming the ion implantation body and source regions, creating contact holes, metallizing, and ultimately forming a shielded gate trench MOSFET device, such as... Figure 22 .

[0068] The device with a trench network structure is formed through the above process. Typically, the depth of the deep trench is between 1.5-12 μm, and the depth of the shallow trench is between 0.2-2 μm. A convex connecting transition region is formed between the deep trench 101 and the shallow trench 102, the length (lateral width d) of which is typically less than one-third of the length (lateral width D') of the shallow trench, and is between 0.03-1 μm. The height of the convexity of this connecting transition region is between 0.05-0.5 μm. Preferably, this transition region is a smooth arc surface that smoothly transitions from the sidewall of the shallow trench inward (towards the center of the shallow trench).

[0069] The device formed through the above process has a raised transition region (protruding transition area) between the deep trench 101 and the shallow trench 102, which helps prevent breakdown weaknesses caused by process issues and avoids reliability problems caused by breakdown voltage drop. Furthermore, since the breakdown voltage of this raised transition region is higher than that of the adjacent shallow trench 102, in the event of avalanche breakdown, the avalanche current path is kept away from this trench transition region, preventing the thinner gate oxide layer in the transition region from being broken down, thus improving the overall avalanche breakdown resistance of the device.

[0070] The above process flow illustrates the key manufacturing steps of the device structure of the present invention. In practice, these steps can be appropriately modified based on existing shielded trench field-effect transistor (SFET) processes. For example, the contact holes are formed using a self-aligned method. Those skilled in the art should understand that the above manufacturing steps only list the key steps and do not show the complete process for forming the device. Specific detailed manufacturing steps can be obtained based on common manufacturing processes and general knowledge, and can be appropriately added to, subtracted from, and modified.

[0071] Furthermore, those skilled in the art should understand that the structural features and process steps mentioned in the various embodiments of the present invention can be combined with each other to form more embodiment device structures and manufacturing processes.

Claims

1. A method for forming deep and shallow trenches in a trench network, characterized in that, The formation method is as follows: First, under the protection of a hard mask, deep trenches and shallow trenches are formed sequentially, with a protective transition area retained at the connection between the deep and shallow trenches; then, etching continues to increase the width of the deep and shallow trenches until the deep and shallow trenches inside the chip are interconnected. In this step, the location of the transition area is etched to form a raised transition area. The length of the raised transition area is less than one-third of the length of the shallow trench and is between 0.03-1µm, and the height of the raised transition area is between 0.05-0.5µm. The raised transition area is a smooth arc surface that smoothly transitions from the sidewall of the shallow trench inward.

2. The method for forming deep and shallow trenches in the trench network as described in claim 1, characterized in that, The formation method includes the following steps: The first step is to form a hard mask layer on the upper surface of the semiconductor; The second step is to perform photolithography on the hard mask to form the first hard mask pattern opening; The third step is to perform vertical semiconductor etching to form the first type of trench; The fourth step is to perform a second photolithography on the hard mask to form a second hard mask pattern opening, wherein a transition area is retained at the connection between the first hard mask pattern opening and the second hard mask pattern opening to provide protection. The fifth step involves vertical semiconductor etching to form deep trenches and shallow trenches, with a protective transition region remaining at the junction of the deep and shallow trenches. The sixth step involves isotropic etching of the semiconductor to increase the width of the deep and shallow trenches, connecting them within the chip; or Thermal oxidation is performed to form a sacrificial oxide layer on the upper surface of the semiconductor and in all trenches, and to completely oxidize the transition region between deep trenches and shallow trenches. Then the sacrificial oxide layer is removed to connect the deep trenches and shallow trenches to each other. The transition area is characterized by a raised transition zone.

3. The method for forming deep and shallow trenches in the trench network as described in claim 2, characterized in that, Before the second photolithography step in the fourth step, the opening of the first hard mask pattern formed in the first photolithography is enlarged; or In step six, before isotropic etching of the semiconductor, the hard mask layer located on the upper surface of the semiconductor is removed; or Before thermal oxidation in step six, the trench is pre-etched isotropically for a short period of time. or In the sixth step, during the removal of the sacrificial oxide layer, only the oxide material above the transition area is removed, so that the deep trenches and shallow trenches are connected to each other.

4. The method for forming deep and shallow trenches in the trench network as described in claim 1, characterized in that, The manufacturing process of the shielded gate trench MOSFET device formed using this method is as follows: The first step involves forming a hard mask thin oxide layer, a hard mask thin nitride layer, and a hard mask thick oxide layer on the semiconductor layer, respectively. Then, photolithography is performed to form a first hard mask pattern opening. Next, the first hard mask pattern opening is etched to form a first type of trench. After etching, the first type of trench forms a deep trench. The second step involves photolithography to form a second hard mask pattern opening on the hard mask thin oxide layer, hard mask thin nitride layer, and hard mask thick oxide layer. Then, shallow trenches are etched under the opening of the second hard mask pattern, and a protective transition region exists between the shallow trenches and the deep trenches. The third step involves etching the hard mask thin oxide layer, hard mask thin nitride layer, and hard mask thick oxide layer to shrink the hard mask layer onto the semiconductor platform. At this point, the hard mask thin oxide layer and hard mask thin nitride layer located in the transition region between the deep trench and the shallow trench are completely removed. The fourth step involves thermal oxidation to form a trench oxide layer. At this point, the transition area is completely oxidized, and the resulting oxide connects the deep trenches and the shallow trenches. The fifth step is to form a shielding gate electrode in the deep trench; Step 6: Etch oxide to completely remove oxide from the transition area, making the deep trenches and shallow trenches interconnected, while retaining the raised transition area at the corresponding position of the transition area. Step 7: Fill with oxides; Step 8: Perform chemical mechanical polishing to remove the oxides on the upper surface and stop on the thick oxide layer of the hard mask; Step 8: Etch back the oxide; Step 9: Form the gate oxide layer and the gate electrode; The tenth step involves forming the ion implantation body region and source region, forming contact holes, metallizing, and finally forming a shielded gate trench MOSFET device.

5. The method for forming deep and shallow trenches in the trench network as described in claim 4, characterized in that, In the fourth step, after the trench oxide layer is formed by thermal oxidation, additional oxides are deposited in the trench to increase the thickness of the trench oxide layer, or additional nitride layers and oxides are deposited in the trench. or, In the fifth step, the shielding gate electrode is polycrystalline silicon and is formed by deposition and etch-back. The depth of the shielding gate formed after etch-back is deeper than that of the shallow trench, and the polycrystalline silicon in the shallow trench is completely removed during etch-back. or After etching back the polysilicon, the thickness of the higher part of the trench oxide layer is reduced. At this time, the lower part of the trench oxide layer is protected by polysilicon to form a trench oxide layer that is thinner at the top and thicker at the bottom.

6. The method for forming deep and shallow trenches in the trench network as described in claim 1, characterized in that, The manufacturing process of the shielded gate trench MOSFET device formed using this method is as follows: The first step is to form hard mask layers on the semiconductor layer, then to form the first hard mask pattern opening by photolithography, and then to etch the semiconductor on the first hard mask pattern opening to form the first type of trench. The second step involves performing a second photolithography on the hard mask to form the second hard mask pattern opening, and then performing semiconductor etching in the vertical direction. The first type of trench forms a deep trench, and the opening of the second hard mask pattern forms a shallow trench. At this time, the deep trench and the shallow trench are not connected to each other. The third step is to perform isotropic etching on the semiconductor to increase the width of the deep trenches and shallow trenches and to connect the deep trenches and shallow trenches inside the chip. The fourth step involves first forming a trench oxide layer in the trench, and then forming a shielding gate electrode in the deep trench. The shallow trench is completely filled with the trench oxide layer material. The fifth step involves first etching the trench oxide layer, and then forming the inter-electrode oxide layer and the gate oxide layer. The sixth step involves forming the ion implantation body region and source region, forming contact holes, metallizing, and finally forming a shielded gate trench MOSFET device.

7. The method for forming deep and shallow trenches in the trench network as described in claim 6, characterized in that, In the fifth step, the method for etching the oxide layer of the trench is wet etching. The oxide layer remaining at the bottom of the shallow trench after etching is used to reduce the capacitance of the device and improve switching performance; or Before etching the trench oxide layer, ion implantation is performed on the polysilicon of the shielding gate electrode to increase the oxidation rate of the polysilicon and form a thick inter-electrode oxide layer.

8. A semiconductor device, said semiconductor device comprising a trench network composed of deep trenches and shallow trenches, characterized in that, The deep trench and shallow trench are formed by the forming method described in any one of claims 1-7. A raised transition area is provided at the junction of the edge of the shallow trench and the deep trench. The length of the raised transition area is less than one-third of the length of the shallow trench and is between 0.03-1 μm. The height of the raised transition area is between 0.05-0.5 μm.

9. The semiconductor device as claimed in claim 8, characterized in that, The raised transition zone is a smooth arc surface that smoothly transitions from the sidewall to the inside of the shallow groove.

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