Semiconductor device and method for manufacturing the same

Abstract

The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. The method comprises: providing a substrate; forming a metal gate layer on the substrate; forming a seed layer on the side of the metal gate layer away from the substrate; forming a dielectric layer on the side of the seed layer away from the metal gate layer using an atomic layer deposition process; forming the dielectric layer comprises cyclically performing at least the following steps: introducing a precursor metal source into the reaction chamber and performing a first purification operation; after the first purification operation is completed, introducing a first oxygen source into the reaction chamber and performing a second purification operation; after the second purification operation is completed, introducing a second oxygen source into the reaction chamber and performing a third purification operation; wherein the second oxygen source is different from the first oxygen source, the dielectric layer is a metal oxide, and the dielectric constant of the dielectric layer is greater than the dielectric constant of silicon oxide. The present application realizes the preparation of an ultra-thin high-κ dielectric layer with an equivalent oxide layer thickness of sub-0.5 nanometers.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] With the development of semiconductor technology, the industry continues to pursue higher performance and energy efficiency, and the research and development of high-κ dielectric material technology has become particularly important. High-κ dielectric materials can not only reduce the equivalent oxide thickness (Equivalent Oxide Thickness, EOT), thereby reducing the size of transistors, but also significantly increase the switching speed of transistors and reduce power consumption, which is crucial for the development of next-generation integrated circuits.

[0003] However, high-κ dielectric material technology faces considerable challenges. For example, in transistor gate structures, gate leakage of high-κ dielectric materials is a major obstacle, which directly affects the thermal management and energy efficiency of chips, especially at the 3nm and below technology nodes that pursue extreme size reduction.

[0004] One way to address the above technical challenges is to develop new high-κ dielectric materials or optimize the performance of existing materials through innovations in materials science and nanotechnology, such as perovskite (SrTiO 3 ), ionic crystals (CaF 2 ), molecular crystals such as (Sb 2 O 3 ) and two-dimensional materials such as (Bi 2 SeO 5 / Bi 2 SiO 5 ), but these methods are difficult to apply to standard manufacturing process lines due to technical compatibility issues such as high temperature processing, small scale limitations and specific channel requirements. Summary of the invention

[0005] The present application provides a semiconductor device and a method for preparing the same. By alternately using different oxygen sources to perform two-step oxidation on a precursor metal source, the growth process of the dielectric layer is optimized, the uniformity, interface quality and dielectric properties of the dielectric layer are further improved, and the preparation of an ultra-thin high-κ dielectric layer with an equivalent oxide layer thickness of sub-0.5 nanometers is achieved.

[0006] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor device, the method comprising:

[0007] providing a substrate;

[0008] forming a metal gate layer on the substrate;

[0009] forming a seed layer on a side of the metal gate layer away from the metal gate layer;

[0010] A dielectric layer is formed on a side of the seed layer away from the metal gate layer by an atomic layer deposition process; wherein forming the dielectric layer includes cyclically performing the following steps at least once:

[0011] Introducing a precursor metal source into the reaction chamber and performing a first purification operation;

[0012] After the first purification operation is completed, introducing a first oxygen source into the reaction chamber and performing a second purification operation;

[0013] After the second purification operation is completed, a second oxygen source is introduced into the reaction chamber, and a third purification operation is performed; wherein the second oxygen source is different from the first oxygen source, the dielectric layer is a metal oxide, and the dielectric constant of the dielectric layer is greater than the dielectric constant of silicon oxide.

[0014] In one embodiment, the thickness of the dielectric layer is greater than or equal to 1.2 nm.

[0015] In one embodiment, the thickness of the dielectric layer is positively correlated with the number of cycles.

[0016] In one embodiment, the number of cycles is 10, and the thickness of the dielectric layer is 1.3 nm;

[0017] The number of cycles is 20, and the thickness of the dielectric layer is 2.6 nm;

[0018] The number of cycles is 30, and the thickness of the dielectric layer is 3.9 nm.

[0019] In one embodiment, the precursor metal source includes a hafnium source, the first oxygen source includes ozone or water, the second oxygen source includes oxygen plasma, and the dielectric layer includes hafnium dioxide.

[0020] In one embodiment, the working power of the oxygen plasma is greater than or equal to 50W.

[0021] In one embodiment, the temperature of the precursor metal source is greater than or equal to 60° C., the flow rate of the precursor metal source is 0-5000 sccm, the pulse time of the precursor metal source is greater than 0 s, and the time of the first purification operation is greater than 0 s;

[0022] The flow rate of the first oxygen source is 0-5000 sccm, the pulse time of the first oxygen source is greater than 0 s, and the time of the second purification operation is greater than 0 s;

[0023] The flow rate of the second oxygen source is 0-5000 sccm, the pulse time of the second oxygen source is greater than 0 s, and the time of the third purification operation is greater than 0 s.

[0024] In one embodiment, the material of the seed layer includes a non-inert metal material.

[0025] In one embodiment, the thickness of the seed layer is greater than or equal to 0.1 nm.

[0026] In a second aspect, an embodiment of the present application provides a semiconductor device, comprising at least:

[0027] substrate;

[0028] A metal gate layer, located on the substrate;

[0029] A seed layer, located on a side of the metal gate layer away from the substrate;

[0030] The dielectric layer is located on a side of the seed layer away from the metal gate layer, and the dielectric layer is prepared by the above-mentioned method for preparing a semiconductor device.

[0031] The semiconductor device and its preparation method provide a substrate, form a metal gate layer on the substrate, form a seed layer on the side of the metal gate layer away from the substrate, and form a dielectric layer on the side of the seed layer away from the metal gate layer by using an atomic layer deposition process, wherein the metal gate layer provides a flat substrate with good electrical conductivity, which is conducive to the subsequent deposition of thin films and the performance of electrical properties, and the seed layer further enhances the uniformity and adhesion of the dielectric layer in the subsequent atomic layer deposition process, especially under low temperature conditions. The formation of the dielectric layer by using the atomic layer deposition process specifically includes cyclically performing the following process at least once, namely, firstly introducing a precursor metal source into a reaction chamber and performing a first purification operation, after the first purification operation is completed, then introducing a first oxygen source into the reaction chamber and performing a second purification operation, after the second purification operation is completed, then introducing a second oxygen source into the reaction chamber and performing a second purification operation, that is, one cycle includes two oxidation processes, and the first oxygen source and the second oxygen source are used alternately, so that the precursor metal source can be fully oxidized with different oxygen sources, and defects such as oxygen vacancies in the dielectric layer can be reduced, thereby improving the uniformity and compactness of the dielectric layer and improving the dielectric properties of the dielectric layer. The present application overcomes technical compatibility issues, including high-temperature processing, small-scale limitations, and specific channel requirements, by depositing a dielectric layer through two-step oxidation. It achieves the manufacture of an ultra-thin high-κ dielectric layer with an equivalent oxide layer thickness of sub-0.5 nanometers, which can solve the gate leakage problem caused by ultra-thin dimensions. In high-performance logic devices and memory devices, ultra-thin dielectric layers with high dielectric constants can effectively reduce gate capacitance and increase device switching speeds. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 A schematic diagram of a process for preparing a semiconductor device provided in an embodiment;

[0034] Figure 2 is a schematic structural diagram of a semiconductor device provided in an embodiment;

[0035] Figure 3 1 is a schematic flow chart of step S14 in a method for preparing a semiconductor device provided in an embodiment;

[0036] Figure 4 A schematic diagram of a process for preparing hafnium oxide by two-step oxidation provided in one embodiment;

[0037] Figure 5 A schematic diagram of oxygen vacancies in preparing hafnium oxide by one-step oxidation and preparing hafnium oxide by two-step oxidation provided in one embodiment;

[0038] Figure 6 A schematic flow chart of a method for preparing a semiconductor device provided in another embodiment;

[0039] Figure 7 1 is a schematic flow chart of step S24 in a method for preparing a semiconductor device provided in an embodiment;

[0040] Figure 8 An electron microscope image of 1.3 nm hafnium oxide provided in an embodiment;

[0041] Fig. 9 A schematic diagram of the relationship between the leakage current and the bias voltage of a semiconductor device including 1.3nm hafnium oxide provided by an embodiment;

[0042] Fig.10 A schematic structural diagram of an 8-inch wafer based on hafnium oxide provided in one embodiment. DETAILED DESCRIPTION

[0043] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0045] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0046] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0047] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0049] As mentioned in the background technology, the development of high-κ dielectric materials with sub-0.5 nanometer EOT and applicable to standard semiconductor manufacturing processes remains an important but elusive challenge. In this regard, the embodiments of the present application provide a semiconductor device and a preparation method thereof, which realizes the preparation of ultra-thin high-κ dielectric layers with sub-0.5 nanometer EOT, which can be widely used in semiconductor devices, aiming to solve the key technical challenges encountered by the semiconductor industry in the pursuit of higher performance and energy efficiency, especially the gate leakage problem encountered by high-κ dielectric materials at extreme size reduction, such as 3 nanometers and below technology nodes.

[0050] See also Figure 1 In one embodiment, the present application provides a method for preparing a semiconductor device, comprising the following steps S11 to S14.

[0051] S11: providing a substrate.

[0052] See also Figure 2 The material of the substrate 10 can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon oxide (SiO 2), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-sided polished silicon wafers (Double Side Polished Wafers, DSP), ceramic substrates such as aluminum oxide, sapphire, quartz or glass substrates, etc., which are not limited in this embodiment. The thickness of the substrate 10 can be any suitable size, for example, 100nm, 200nm, 300nm, which can be set according to the preparation requirements of the semiconductor device, and is not specifically limited here.

[0053] S12: forming a metal gate layer on the substrate.

[0054] Please continue reading Figure 2 The material of the metal gate layer 20 can be a metal conductive material, including but not limited to gold (Au), titanium (Ti), aluminum (Al), nickel (Ni), platinum (Pt), etc., and a suitable material can be selected according to the preparation requirements of the semiconductor device, which is not limited here. The thickness of the metal gate layer 20 can be any suitable size, for example, 5nm, 10nm, 20nm, etc., which is not specifically limited here.

[0055] The metal gate layer 20 can be formed on the substrate 10 by any suitable coating (deposition) technology, such as atomic layer deposition (ALD) process, physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, plasma enhanced chemical vapor deposition (PECVD) process, low pressure chemical vapor deposition (LPCVD) process or electron beam evaporation deposition (EBE), etc., which are not specifically limited here.

[0056] S13: forming a seed layer on a side of the metal gate layer away from the substrate.

[0057] Please continue reading Figure 2The material of the seed layer 30 may include a metal conductive material. The thickness of the seed layer 30 may be any size. The seed layer 30 may be formed on the side of the metal gate layer 20 away from the substrate 10 by any suitable coating technology, including but not limited to EBE, ALD, PVD, CVD, PECVD, LPCVD, which are not specifically limited here.

[0058] S14: forming a dielectric layer on a side of the seed layer away from the metal gate layer by using an atomic layer deposition process.

[0059] See also Figures 1 to 3 , an ALD process is used to form a dielectric layer 40 on a side of the seed layer 30 away from the metal gate layer 20. Wherein, step S14 includes cyclically performing the following steps S141 to S143 at least once.

[0060] S141: Introduce a precursor metal source into the reaction chamber and perform a first purification operation.

[0061] In application, the substrate prepared in the above steps S11 to S13 can be placed in a reaction chamber, and then a precursor metal source is introduced into the reaction chamber. After the precursor metal source is fully reacted, a first purification operation is performed. The substrate includes a substrate 10, a metal gate layer 20 and a seed layer 30 stacked in sequence. The precursor metal source includes metal elements. The first purification operation can specifically be to introduce a cleaning gas into the reaction chamber to remove reaction by-products and residual precursor metal sources. The cleaning gas can be an inert gas, such as argon (Ar), nitrogen (N 2 ), helium (He), neon, hydrogen (H 2 ) and their combinations are not limited here.

[0062] S142: After the first purification operation is completed, a first oxygen source is introduced into the reaction chamber, and a second purification operation is performed.

[0063] In the application, after the first purification operation is completed, that is, after the reaction byproducts and residual precursor metal source in the reaction chamber are removed, the first oxygen source is introduced into the reaction chamber, and after the first oxygen source is fully reacted, the second purification operation is performed. Among them, the first oxygen source includes oxygen element. The second purification operation can specifically be to introduce a clean gas into the reaction chamber to remove the reaction byproducts and the residual first oxygen source. Among them, the second purification operation is similar to the first purification operation process, which will not be repeated here.

[0064] S143: After the second purification operation is completed, a second oxygen source is introduced into the reaction chamber, and a third purification operation is performed.

[0065] Wherein, the second oxygen source is different from the first oxygen source, the dielectric layer 40 is a metal oxide, and the dielectric constant of the dielectric layer 40 is greater than the dielectric constant of silicon oxide. In the application, after the second purification operation is completed, that is, after removing the reaction byproducts and the residual first oxygen source in the reaction chamber, the second oxygen source is introduced into the reaction chamber, and after the second oxygen source is fully reacted, the third purification operation is performed. Wherein, the second oxygen source includes oxygen element, and the second oxygen source is different from the first oxygen source. The third purification operation can specifically be to introduce a clean gas into the reaction chamber to remove the reaction byproducts and the residual second oxygen source. Wherein, the third purification operation is similar to the first purification operation and the second purification operation process, which will not be repeated here.

[0066] It should be noted that the steps S141 to S143 may be cyclically performed according to the specific preparation requirements of the dielectric layer 40, so as to form the dielectric layer 40 on the side of the seed layer 30 away from the metal gate layer 20. The number of cyclic executions of the steps S141 to S143 may be once or multiple times, such as 10 times, 30 times, 50 times, etc., which are not specifically limited here. When the number of cycles is greater than one, after the third purification operation of one cycle is completed, the step S141 of the next cycle is executed.

[0067] The dielectric layer 40 formed based on the above steps is a metal oxide, such as hafnium oxide (HfO 2 ). The metal element in the dielectric layer 40 comes from the precursor metal source, and the oxygen element in the dielectric layer 40 comes from the precursor metal source, the first oxygen source, and the second oxygen source. The dielectric constant of the dielectric layer 40 is greater than that of silicon oxide (SiO 2 ) has a dielectric constant of , that is, the material of the dielectric layer 40 is a high-κ dielectric material.

[0068] The method for preparing the semiconductor device includes providing a substrate 10, forming a metal gate layer 20 on the substrate 10, forming a seed layer 30 on a side of the metal gate layer 20 away from the substrate 10, and forming a dielectric layer 40 on a side of the seed layer 30 away from the metal gate layer 20 by an atomic layer deposition process, wherein the metal gate layer 20 provides a flat substrate with good electrical conductivity, which is beneficial to the subsequent deposition of thin films and the performance of electrical properties, and the seed layer 30 further enhances the uniformity and adhesion of the dielectric layer 40 in the subsequent ALD process, especially under low temperature conditions; wherein the dielectric layer 40 is formed by the ALD process specifically The method comprises cyclically executing the following process at least once, namely, firstly introducing a precursor metal source into the reaction chamber and performing a first purification operation, and after the first purification operation is completed, introducing a first oxygen source into the reaction chamber and performing a second purification operation, and after the second purification operation is completed, introducing a second oxygen source into the reaction chamber and performing a second purification operation, that is, one cycle comprises two oxidation processes, and the first oxygen source and the second oxygen source are used alternately, so that the precursor metal source can be fully oxidized with different oxygen sources, and defects in the dielectric layer 40 such as oxygen vacancies can be reduced, thereby improving the uniformity and density of the dielectric layer 40, and thus improving the dielectric properties of the dielectric layer 40.

[0069] By providing the above-mentioned two-step oxidation atomic layer deposition (ALD) technology, the present application can achieve the deposition of a high-quality ultra-thin dielectric layer 40 at a relatively low temperature (such as 200°C) on a large-scale wafer scale (such as 8 inches), which is not only compatible with silicon-based complementary metal oxide semiconductor (CMOS) technology, but also compatible with two-dimensional semiconductor-based field effect transistors (Two-Dimensional Field-Effect Transistors, 2DFETs) and related flexible devices.

[0070] Through the above-mentioned preparation method, the present application overcomes the technical compatibility problems, including high temperature processing, small-scale limitations and specific channel requirements, and realizes the manufacture of ultra-thin high-κ dielectric materials, namely dielectric layers 40, with sub-0.5 nanometer equivalent oxide thickness (EOT), which will help to further reduce the size of transistors, improve switching speed, reduce power consumption, and provide key technical support for the development of next-generation high-performance, low-energy integrated circuits. For example, when applied to transistors such as CMOS and 2D FETs, ultra-thin high-κ dielectric materials, namely dielectric layers 40, with sub-0.5 nanometer equivalent oxide thickness can be realized to solve the gate leakage problem caused by ultra-thin size; in high-performance logic devices and memory devices, ultra-thin dielectric layers 40 with high dielectric constants can effectively reduce gate capacitance and improve the switching speed of devices.

[0071] In one embodiment, the thickness of the dielectric layer 40 is greater than or equal to 1.2 nm. For example, the thickness of the dielectric layer 40 may be 1.28 nm, 1.29 nm, 1.3 nm, 1.5 nm, 2 nm, 2.6 nm, 3 nm, 3.5 nm, 3.9 nm, 4 nm, 5 nm. The thickness of the dielectric layer 40 may also be other values ​​greater than or equal to 1.2 nm. In this way, the manufacture of ultra-thin high-κ dielectric materials with a sub-0.5 nm equivalent oxide layer thickness is achieved, which helps to further reduce the size of semiconductor devices such as transistors and improve the performance of semiconductor devices.

[0072] In one embodiment, the thickness of the dielectric layer 40 is positively correlated with the number of cycles of step S141 to step S143. That is, the more cycles there are, the thicker the dielectric layer 40 is. Exemplarily, the thickness of the dielectric layer 40 is proportional to the number of cycles. The proportional relationship between the thickness of the dielectric layer 40 and the number of cycles can be determined according to the conditions for depositing the dielectric layer 40 by ALD, which is not specifically limited here. In this way, the thickness of the dielectric layer 40 can be precisely controlled by adjusting the number of cycles of the ALD step.

[0073] In one embodiment, the number of steps S141 to S143 cycles is 10, and the thickness of the dielectric layer 40 is 1.3 nm. The number of steps S141 to S143 cycles is 20, and the thickness of the dielectric layer 40 is 2.6 nm. The number of steps S141 to S143 cycles is 30, and the thickness of the dielectric layer 40 is 3.9 nm. The present application realizes a dielectric layer 40 with a thickness of only 1.3 nm, such as HfO 2 , with an equivalent oxide thickness (EOT) of 2.7 angstroms. This breakthrough not only marks a major advance in the field of high-κ dielectric materials, but also has important significance for further reducing the size of semiconductor devices and improving integration. By reducing the EOT to such a low level, this application can effectively reduce the gate capacitance of the transistor, thereby increasing its switching speed, speeding up information processing, and realizing more efficient electronic devices.

[0074] In one embodiment, the precursor metal source includes a hafnium source, that is, the material of the precursor metal source can be a compound including the hafnium element. Exemplarily, the hafnium source includes tetrakis(ethylmethylamino)hafnium, tetrakis(dimethylamino)hafnium or hafnium tetrachloride. Among them, tetrakis(ethylmethylamino)hafnium is also called TEMAH, and the chemical formula of TEMAH is Hf[N(CH 3 )C 2 H 5 ] 4 The chemical formula of tetrakis(dimethylamino)hafnium is Hf(NMe 2 ) 4 The chemical formula of hafnium tetrachloride is HfCl 4The first oxygen source includes ozone (O 3 ) or water (H 2 O). The second oxygen source includes oxygen (O 2 ) plasma. The dielectric layer 40 includes hafnium dioxide (HfO 2 In practical applications, appropriate hafnium sources and first oxygen sources can be selected according to specific scenarios to deposit HfO 2 , and no further limitations are given here.

[0075] The hafnium source is TEMAH and the first oxygen source is O 3 , the second oxygen source is O 2 Plasma deposition of HfO 2 Take this as an example to illustrate. In an application, Figure 4 As shown, HfO is deposited 2 One cycle of the process includes firstly oxidizing the hafnium source TEMAH with ozone and then oxidizing it with O 2 The plasma performs a two-step oxidation of the hafnium source TEMAH. Figure 5 The test graph shown in the figure shows that the HfO obtained by one-step oxidation 2 The oxygen vacancy in the HfO is 25.7%, and the HfO obtained by two-step oxidation 2 It can be seen that the two-step oxidation ALD deposition operation can obtain a more uniform and denser dielectric layer 40 such as HfO 2 film, can effectively reduce the dielectric layer 40 such as HfO 2 Defects in the film, such as oxygen vacancies, etc., thus improving the dielectric layer 40 such as HfO 2 Dielectric properties of the films.

[0076] In one embodiment, oxygen (O 2 ) The working power of the plasma is greater than or equal to 50W, for example, it can be 50W, 100W, 500W, 1000W, 1500W, 3000W, or other values ​​greater than or equal to 50W. In practice, the dielectric layer 40 such as HfO can be deposited according to ALD. 2 Film Conditioning O 2 The working power of the plasma. 2 The power of the plasma enables fine control of the film growth rate and film properties. This fine control not only helps to obtain a more uniform and denser film, but also helps to reduce possible defects in the film layer, such as oxygen vacancies, thereby improving the dielectric properties.

[0077] In one embodiment, the temperature of the precursor metal source is greater than or equal to 60°C, for example, it can be 60°C, 75°C, 100°C, 125°C, 200°C, 250°C, or other values ​​greater than or equal to 60°C. The flow rate of the precursor metal source is 0-5000sccm, for example, it can be 10sccm, 100scm, 150sccm, 200sccm, 500sccm, 750sccm, 1000sccm, 2000sccm, 3000sccm, 4000sccm, 5000sccm, or other values ​​between 0-5000sccm. The pulse time of the precursor metal source is greater than 0s, for example, it can be 1ms, 10ms, 1s, 1.6s, 2s, 2.5s, 3s, 3.5s, 4s, 4.5s, 5s, or other values ​​greater than 0s. The time of the first purification operation is greater than 0s, for example, it can be 0.5s, 1s, 10s, 25s, 50s, 60s, 100s, 120s, or other values ​​greater than 0s. It should be noted that the first purification time is greater than the pulse time of the precursor metal source to fully remove the byproducts after the reaction of the precursor metal source.

[0078] The flow rate of the first oxygen source is 0 to 5000 sccm, for example, it can be 10 sccm, 100 scm, 150 sccm, 200 sccm, 500 sccm, 750 sccm, 1000 sccm, 2000 sccm, 3000 sccm, 4000 sccm, 5000 sccm, or other values ​​between 0 and 5000 sccm. The pulse time of the first oxygen source is greater than 0s, for example, it can be 0.5s, 1ms, 10ms, 1s, 1.6s, 2s, 2.5s, 3s, 3.5s, 4s, 4.5s, 5s, or other values ​​greater than 0s. The time of the second purification operation is greater than 0s, for example, it can be 0.5s, 1s, 10s, 25s, 50s, 60s, 100s, 120s, or other values ​​greater than 0s. It should be noted that the second purification time is greater than the pulse time of the precursor metal source so as to fully remove the byproducts after the first oxygen source reaction.

[0079] The flow rate of the second oxygen source is 0 to 5000 sccm, for example, it can be 10 sccm, 100 scm, 150 sccm, 200 sccm, 500 sccm, 750 sccm, 1000 sccm, 2000 sccm, 3000 sccm, 4000 sccm, 5000 sccm, or other values ​​between 0 and 5000 sccm. The pulse time of the second oxygen source is greater than 0s, for example, it can be 0.5s, 1ms, 10ms, 1s, 1.6s, 2s, 2.5s, 3s, 3.5s, 4s, 4.5s, 5s, or other values ​​greater than 0s. The time of the third purification operation is greater than 0s, for example, it can be 0.5s, 1s, 10s, 25s, 50s, 60s, 100s, 120s, or other values ​​greater than 0s. It should be noted that the third purification time is greater than the pulse time of the precursor metal source so as to fully remove the byproducts after the reaction of the second oxygen source.

[0080] In one embodiment, the material of the seed layer 30 is a non-inert metal material. Exemplarily, the material of the seed layer 30 may include titanium (Ti), aluminum (Al) or antimony (Sb). Using a non-inert metal material such as titanium as the seed layer 30 further enhances the uniformity and adhesion of the dielectric layer 40 in the subsequent ALD preparation process. This meticulous regulation helps to obtain a more uniform and denser dielectric layer 40.

[0081] In one embodiment, the thickness of the seed layer 30 is greater than or equal to 0.1 nm, for example, it can be 0.1 nm, 0.3 nm, 0.5 nm, 0.7 nm, 1 nm, 2 nm, 5 nm, or other values ​​greater than or equal to 0.1 nm. It can be specifically set according to factors such as the material of the seed layer 30 and the material of the dielectric layer 40.

[0082] In one embodiment, Figure 6 As shown, a method for preparing a semiconductor device is provided, the method comprising the following steps:

[0083] S21: Provide a 300 nm Si substrate.

[0084] S22: 10 nm of gold (Au) is deposited on the Si substrate as a metal gate layer by electron beam evaporation technology.

[0085] S23: Deposit 0.5 nm of titanium (Ti) as a seed layer on a side of the metal gate layer away from the substrate by electron beam evaporation technology.

[0086] S24: Using two-step oxidation atomic layer deposition technology, HfO is deposited on the side of the seed layer away from the metal gate layer. 2 Dielectric layer. Figure 7As shown, step S24 executes the following steps S241 to S243 at least once in a loop.

[0087] S241: TEMAH is introduced into the reaction chamber and nitrogen (N 2 ) as the cleaning gas to perform a first purification operation, wherein the temperature of the hafnium source is 125° C., the flow rate of the hafnium source is 150 sccm, the pulse time of the hafnium source is 1.6 s, and the time of the first purification operation is 25 s.

[0088] S242: Introducing ozone (O 3 ), and performing a second purification operation with nitrogen as the cleaning gas, wherein the ozone flow rate is 150 sccm, the ozone pulse time is 1.6 s, and the time of the second purification operation is 25 s.

[0089] S243: Introducing oxygen (O 2 ) plasma, and perform a third purification operation with nitrogen as the cleaning gas, wherein the flow rate of the oxygen plasma is 150 sccm, the pulse time of the oxygen plasma is 1.6 s, the working power of the oxygen plasma is 1500 W, and the time of the third purification operation is 25 s.

[0090] It is known from the test that after 10 cycles of the above steps S241 to S243, the hafnium oxide (HfO 2 ) The thickness of the film reached 1.3 nanometers; after 20 cycles, the thickness of the hafnium oxide film reached 2.6 nanometers; after 30 cycles, the thickness of the hafnium oxide film reached 3.9 nanometers. Figure 8 As shown, the resulting 1.3 nm HfO 2 Electron microscope image.

[0091] This application achieves HfO with a thickness of only 1.3 nanometers 2 The dielectric layer has an equivalent oxide thickness (EOT) of 2.7 angstroms, which is of great significance for further reducing the size of semiconductor devices and improving integration. By reducing the EOT to such a low level, the present application can effectively reduce the gate capacitance of the transistor, thereby increasing its switching speed, speeding up information processing, and realizing more efficient electronic devices.

[0092] 1.3nmHfO prepared by the above method 2 Thin films, such as metal / dielectric layer / metal structure, are tested as an example. Fig. 9 As shown, the HfO prepared in this application 2 The film exhibits extremely low leakage current, less than 10 at a bias voltage of 1 volt. -6 This performance shows that even at very thin thickness, HfO 2The film still maintains excellent insulating properties, significantly reducing power consumption, which is critical for designing and manufacturing low-power integrated circuits, especially in energy-sensitive applications such as mobile devices and wearable technology. Fig. 9 , the HfO 2 The film also exhibits a strong breakdown electric field of 10 -5 The bias voltage under leakage current of amperes per square centimeter is 4 volts, and the corresponding breakdown electric field of the equivalent oxide layer is about 32 megavolts per centimeter. This characteristic shows that although the film is extremely weak, it can withstand high electric field strength without breakdown, thereby ensuring the reliability and stability of the semiconductor device. This is an extremely important advantage for high-performance applications that operate under extreme working conditions. In the contemporary electronic device design that pursues energy efficiency, the dielectric layer with low leakage current and high breakdown electric field achieved in this application helps to significantly reduce energy consumption and can achieve green and environmentally friendly electronic product design.

[0093] The application scope and application scenarios of the present invention include field effect transistors, such as single-layer molybdenum disulfide (MoS 2 ) two-dimensional field effect transistors (2D FETs) with 1.3nm HfO 2 As an example, a 2.7 Å equivalent oxide thickness (EOT) HfO film was evaluated. 2 The practicality and effectiveness of dielectric materials in gating, these applications not only demonstrate the great potential of this material in improving device performance, but also highlight its broad application prospects in future semiconductor technology.

[0094] The 1.3nm HfO prepared in this application 2 The film is applied in 100 nanometer channel devices and can achieve an on-state current density of about 250 microamperes per micrometer and a current density of about 10 8 The impressive on / off ratio and ultra-low subthreshold slope (SS) of about 60 mV / dec at 0.5 V source-drain bias are shown in Figure 2. These performance indicators reflect the HfO 2 The dielectric layer plays a significant role in improving the performance of 2D FETs, especially in enhancing switching efficiency and reducing power consumption. Among them, 100 nanometers is the channel length of the channel device.

[0095] Furthermore, the present application also covers the fabrication of logic gates and memory devices with correct functions on an 8-inch wafer scale, such as Fig.10 As shown, such as inverters, logic gates (e.g., AND gates, NAND gates, and NOR gates), these application scenarios demonstrate the application potential of the present application in large-scale integrated circuit manufacturing, especially in building high-performance computing and various logic processing devices.

[0096] This application can also be applied to other scenarios, such as high-performance logic device manufacturing scenarios, using low EOT HfO 2 The dielectric layer can achieve smaller device size, higher switching speed and lower power consumption, which is particularly important for the next generation of high-performance computing and large-capacity storage devices; for example, in flexible electronics and wearable devices, the ALD technology provided by the present application is also suitable for manufacturing high-performance electronic devices on flexible substrates, which provides the possibility for the development of a new generation of wearable devices and flexible electronic products; for example, in terms of energy efficiency optimization, in the design of contemporary electronic equipment that pursues energy efficiency, the dielectric layer with low leakage current and high breakdown electric field achieved by the present application can help to significantly reduce energy consumption and realize green and environmentally friendly electronic product design.

[0097] It should be understood that, although the steps in each flowchart are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in each figure may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0098] Please continue reading Figure 2 Based on the same inventive concept, the present application also provides a semiconductor device, comprising: a substrate 10, a metal gate layer 20, a seed layer 30 and a dielectric layer 40. The metal gate layer 20 is located on the substrate 10. The seed layer 30 is located on the side of the metal gate layer 20 away from the substrate 10. The dielectric layer 40 is located on the side of the seed layer 30 away from the metal gate layer 20. The dielectric layer 40 can be formed by the method for preparing the semiconductor device provided by any of the aforementioned embodiments, and the details can be referred to the aforementioned related contents. Exemplarily, the dielectric layer 40 includes hafnium oxide (HfO 2 ).

[0099] The implementation solution provided by the above-mentioned semiconductor device to solve the problem is similar to the implementation solution recorded in the above-mentioned method. Therefore, the specific limitations in the semiconductor device provided in this application can refer to the limitations on the preparation method of the semiconductor device in the above text, and will not be repeated here.

[0100] Exemplarily, the semiconductor device can be a transistor such as CMOS, 2D FETs, an inverter, a logic gate such as an AND gate, a NAND gate, a NOR gate, etc., or it can be any other semiconductor device including a substrate 10, a metal gate layer 20, a seed layer 30 and a dielectric layer 40. The corresponding device can be prepared according to application requirements.

[0101] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0102] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method comprises: providing a substrate; forming a metal gate layer on the substrate; forming a seed layer on a side of the metal gate layer away from the substrate; A dielectric layer is formed on a side of the seed layer away from the metal gate layer by an atomic layer deposition process; wherein forming the dielectric layer includes cyclically performing the following steps at least once: Introducing a precursor metal source into the reaction chamber and performing a first purification operation; After the first purification operation is completed, introducing a first oxygen source into the reaction chamber and performing a second purification operation; After the second purge operation is completed, a second oxygen source is introduced into the reaction chamber, and a third purge operation is performed; wherein the second oxygen source is different from the first oxygen source, the dielectric layer is a metal oxide, and the dielectric constant of the dielectric layer is greater than the dielectric constant of silicon oxide, and the oxygen vacancies in the dielectric layer after the third purge operation are less than the oxygen vacancies in the same cycle after the second purge operation.

2. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the dielectric layer is greater than or equal to 1.2 nm.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The thickness of the dielectric layer is positively correlated with the number of cycles.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The number of cycles is 10, and the thickness of the dielectric layer is 1.3 nm; The number of cycles is 20, and the thickness of the dielectric layer is 2.6 nm; The number of cycles is 30, and the thickness of the dielectric layer is 3.9 nm.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: The precursor metal source includes a hafnium source, the first oxygen source includes ozone or water, the second oxygen source includes oxygen plasma, and the dielectric layer includes hafnium dioxide.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: The working power of the oxygen plasma is greater than or equal to 50W.

7. The method for preparing a semiconductor device according to claim 1, characterized in that: The temperature of the precursor metal source is greater than or equal to 60° C., the flow rate of the precursor metal source is 0 to 5000 sccm, the pulse time of the precursor metal source is greater than 0 s, and the time of the first purification operation is greater than 0 s; The flow rate of the first oxygen source is 0 to 5000 sccm, the pulse time of the first oxygen source is greater than 0 s, and the time of the second purification operation is greater than 0 s; The flow rate of the second oxygen source is 0-5000 sccm, the pulse time of the second oxygen source is greater than 0 s, and the time of the third purification operation is greater than 0 s.

8. The method for preparing a semiconductor device according to claim 1, wherein: The material of the seed layer includes a non-inert metal material.

9. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the seed layer is greater than or equal to 0.1 nm.

10. A semiconductor device, characterized in that: At least: substrate; A metal gate layer, located on the substrate; A seed layer, located on a side of the metal gate layer away from the substrate; A dielectric layer is located on a side of the seed layer away from the metal gate layer, and the dielectric layer is prepared by the method for preparing a semiconductor device according to any one of claims 1 to 9.

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