Resonant asymmetrical half-bridge flyback power converter and switching control circuit therefor

Abstract

A resonant asymmetrical half-bridge flyback power converter and a switching control circuit thereof. The resonant asymmetrical half-bridge flyback power converter comprises: first and second transistors for switching a transformer coupled with a resonant capacitor to generate an output power; a voltage divider coupled to an auxiliary winding of the transformer; a differential input sensing circuit comprising: first and second input terminals, wherein the first and second input terminals are coupled to the voltage divider and are configured to sense an auxiliary signal to generate a peak signal and a demagnetization time signal; and a pulse width modulation circuit configured to generate first and second pulse width modulation signals based on the peak signal and the demagnetization time signal, respectively, for controlling the first and second transistors of the resonant asymmetrical half-bridge flyback power converter; wherein an enabled state of the demagnetization time signal is associated with a level of the output power of the resonant asymmetrical half-bridge flyback power converter.

Description

Technical Field

[0001] This invention relates to a flyback power converter, and more particularly to a resonant asymmetrical half-bridge (AHB) flyback power converter with differential voltage sensing functionality. The invention also relates to a switching control circuit for controlling the resonant asymmetrical half-bridge flyback power converter. Background Technology

[0002] Figure 1 This is a schematic diagram showing a known resonant asymmetric half-bridge flyback power converter 1001. If the known resonant asymmetric half-bridge flyback power converter 1001 is to be applied to a wider voltage range (e.g., 5V–20V or 5V–48V), when the output voltage Vout is at a high level (e.g., 48V), the voltage ratio used to sense the auxiliary voltage VAUX must be limited by the maximum rated voltage on the DMG pin, resulting in a relatively low voltage ratio. However, Figure 1 The disadvantage of the prior art shown is that when the output voltage Vout is a low level (e.g., 5V), such a low voltage ratio will result in a low signal-to-noise ratio (SNR).

[0003] Compared to existing technologies, this invention proposes a resonant asymmetric half-bridge flyback power converter that has the function of sensing different differential voltages, thereby increasing the signal-to-noise ratio (SNR). Summary of the Invention

[0004] In one viewpoint, the present invention provides a switching control circuit for controlling a power stage circuit in a resonant asymmetrical half-bridge (AHB) flyback power converter, wherein the power stage circuit includes: a transformer, a resonant capacitor, a first transistor, and a second transistor coupled to each other, thereby switching an input power supply to generate an output power supply; the switching control circuit includes: a voltage divider coupled to an auxiliary winding of the transformer, wherein the voltage divider is used to divide an auxiliary signal generated via the auxiliary winding; a differential input sensing circuit including: a first input terminal and a second input terminal, wherein the first input terminal and the second input terminal are coupled to the voltage divider to sense the auxiliary signal, thereby generating a peak signal and a demagnetization-time signal; a feedback circuit for generating a feedback signal based on an electrical characteristic of the output power supply of the resonant asymmetrical half-bridge flyback power converter; and a pulse. A pulse width modulation circuit is used to generate a first pulse width modulation signal and a second pulse width modulation signal based on the feedback signal, the peak signal, and the demagnetization time signal. The first and second pulse width modulation signals are used to control the first and second transistors of the resonant asymmetric half-bridge flyback power converter, respectively. The first and second pulse width modulation signals control the first and second transistors to switch the transformer, thereby generating the output power of the resonant asymmetric half-bridge flyback power converter. An enable state of the demagnetization time signal is associated with a current level or a power level of the output power of the resonant asymmetric half-bridge flyback power converter. When the transformer has been demagnetized, the peak signal is associated with a quasi-resonance state of the transformer.

[0005] In one embodiment, the differential input sensing circuit generates the peak signal when the first pulse width modulation signal switches to an off state to turn off the first transistor and when the auxiliary signal is higher than a voltage threshold.

[0006] In one embodiment, the switching control circuit further includes: a first input circuit coupled to the first input terminal, wherein when the first pulse width modulation signal is switched to an on state to turn on the first transistor and when the transformer is magnetized, the first input circuit is used to generate an input voltage-related current signal; wherein the input voltage-related current signal is related to a bit level of an input voltage of the resonant asymmetric half-bridge flyback power converter.

[0007] In one embodiment, the differential input sensing circuit is used to generate an output voltage-dependent current signal based on a voltage across the first input terminal and the second input terminal; wherein the output voltage-dependent current signal is related to a bit level of an output voltage of the resonant asymmetric half-bridge flyback power converter.

[0008] In one embodiment, the output voltage-related current signal is used to generate a reflected output voltage signal, wherein the reflected output voltage signal is used to perform overvoltage protection and undervoltage protection for the output voltage of the resonant asymmetric half-bridge flyback power converter.

[0009] In one embodiment, the demagnetization time signal is generated based on the output voltage-related current signal, the input voltage-related current signal, and an on-time of the first pulse width modulation signal.

[0010] In one embodiment, the switching control circuit further includes: a timing simulation circuit; wherein when the first pulse width modulation signal switches to an off state to turn off the first transistor, the demagnetizing time signal switches to the enabled state; and wherein when a capacitor of the timing simulation circuit is discharged to a voltage below a first discharge threshold, the demagnetizing time signal switches to an disabled state; wherein the capacitor of the timing simulation circuit is charged by an input voltage-related current signal during an on-time of the first pulse width modulation signal, and the capacitor of the timing simulation circuit is discharged by an output voltage-related current signal when the first pulse width modulation signal switches to an off state.

[0011] In one embodiment, when a voltage of the capacitor is lower than a second discharge threshold, a boundary extension signal is generated, wherein the boundary extension signal is used to make the demagnetization time signal continue during the enabled state to generate a reverse circulating current, thereby enabling the first transistor to achieve zero-voltage switching.

[0012] In one embodiment, a non-conducting time of the first pulse width modulation signal is related to a bit level of the feedback signal; wherein the non-conducting time of the first pulse width modulation signal increases according to a reduction in an output load of the resonant asymmetric half-bridge flyback power converter.

[0013] In one embodiment, the conduction time of the second pulse width modulation signal is greater than the demagnetization time of the transformer, thereby enabling the resonant asymmetric half-bridge flyback power converter to achieve zero-voltage switching.

[0014] In one embodiment, an output voltage of the resonant asymmetric half-bridge flyback power converter is programmable, and the output voltage of the resonant asymmetric half-bridge flyback power converter includes a maximum value and a minimum value, wherein a ratio between the maximum value and the minimum value is equal to or greater than 4, or equal to or greater than 9.

[0015] In one embodiment, the resonant asymmetric half-bridge flyback power converter is a Universal Serial Bus Power Delivery (USB PD) type power converter, wherein the maximum value of the output voltage is 48 volts (V) and the minimum value of the output voltage is 5 volts (V).

[0016] In another viewpoint, the present invention provides a resonant asymmetric half-bridge flyback power converter, comprising: a power stage circuit including: a transformer, a resonant capacitor, a first transistor and a second transistor coupled to each other, thereby converting an input power supply to generate an output power supply; and any of the above-described switching control circuits, wherein the switching control circuit is used to control the power stage circuit in the resonant asymmetric half-bridge flyback power converter.

[0017] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features and effects achieved by the present invention. Attached Figure Description

[0018] Figure 1 This is a schematic diagram showing a known resonant asymmetric half-bridge flyback power converter.

[0019] Figure 2 This is a schematic diagram of a resonant asymmetric half-bridge flyback power converter according to an embodiment of the present invention.

[0020] Figure 3 This is a block diagram illustrating the primary-side controller of a resonant asymmetric half-bridge flyback power converter according to an embodiment of the present invention.

[0021] Figure 4 This is a waveform diagram showing the signal operation of a resonant asymmetric half-bridge flyback power converter according to an embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the differential input sensing circuit 201 of a resonant asymmetric half-bridge flyback power converter according to an embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of the first input circuit 202 of a resonant asymmetric half-bridge flyback power converter according to an embodiment of the present invention.

[0024] Figure 7 This is a schematic diagram of a timing simulation circuit 203 for a resonant asymmetric half-bridge flyback power converter according to an embodiment of the present invention.

[0025] Figure 8 This is a schematic diagram of the modulation circuit 204, logic control circuit 205, and timing circuit 206 of a resonant asymmetric half-bridge flyback power converter according to an embodiment of the present invention.

[0026] Explanation of symbols in the diagram

[0027] 1001: Known resonant asymmetric half-bridge flyback power converter

[0028] 1002: Resonant Asymmetric Half-Bridge Flyback Power Converter

[0029] 100: Secondary controller

[0030] 200: Primary Side Controller

[0031] 201: Differential Input Sensing Circuit

[0032] 202: First Input Circuit

[0033] 203: Timing Analog Circuit

[0034] 204: Modulation Circuit

[0035] 205: Logic Control Circuit

[0036] 206: Timing Circuit

[0037] 210: Operational amplifier

[0038] 215: Resistor

[0039] 225: Resistor

[0040] 220: Operational amplifier

[0041] 230: Comparator

[0042] 235: Pulse Generator

[0043] 240, 241, 242, 243, 250: Transistors

[0044] 330: Capacitor

[0045] 332: Comparator

[0046] 335: Pulse Generator

[0047] 340: Flip-Flipper

[0048] 345: With the door

[0049] 360: Pulse Generator

[0050] 361: OR Gate

[0051] 362: Buffer

[0052] 370: Flipper

[0053] 372: Buffer

[0054] 384: Comparator

[0055] 380: Transistor

[0056] 381, 382, ​​383: Resistors

[0057] 390: Voltage-to-current converter

[0058] 395: Timer

[0059] 501: Voltage divider

[0060] 10: Upper-bridge transistor

[0061] 20: Lower-bridge transistor

[0062] 25: Body diode

[0063] 30: Resonant capacitor

[0064] 40, 51, 52: Resistors

[0065] 50: Transformer

[0066] 60: Synchronous rectifier

[0067] 90: Optical Coupler

[0068] D: Data terminal

[0069] D+: First input terminal

[0070] D-: Second input terminal

[0071] EN: Enable signal

[0072] I240, I242: Current

[0073] I250: Current signal

[0074] IC: Input voltage-related current signal

[0075] ID: Output voltage-related current signal

[0076] IP: Primary Side Switching Current

[0077] LX: Switch Node

[0078] nVO: Reflected output voltage signal

[0079] Pzv: Zero-voltage switching pulse

[0080] RDY: Ready signal

[0081] RST: Reset signal

[0082] SB: Boundary Extension Signal

[0083] SDT: Demagnetization Time Signal

[0084] SG: Drive signal

[0085] SH: Drive signal (upper bridge control signal)

[0086] SL: Drive signal (lower bridge control signal)

[0087] SP: Peak signal

[0088] Str: Trigger signal

[0089] SW: Pulse Width Modulation Signal

[0090] TDS: Demagnetization time

[0091] Td1: Static Time

[0092] TX: Idle Time

[0093] WA: Auxiliary winding

[0094] WP: Primary winding

[0095] WS: Secondary winding

[0096] VA': First sub-signal

[0097] VAUX: Auxiliary signal

[0098] VAUX': Voltage divider auxiliary signal

[0099] Vauxi: Transpressure

[0100] VCC: Internal power supply

[0101] VCLAMP: Clamping voltage

[0102] VCS: Current sensing signal

[0103] VFB: Feedback signal

[0104] VFB': Feedback signal after level offset

[0105] VFB: Feedback signal of the voltage divider

[0106] VIN: Input voltage

[0107] Vout: Output voltage

[0108] VT3, VT4: Discharge threshold Detailed Implementation

[0109] The accompanying drawings in this invention are all schematic and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

[0110] Figure 2 This is a schematic diagram illustrating a resonant asymmetric half-bridge flyback power converter according to an embodiment of the present invention. The resonant asymmetric half-bridge flyback power converter 1002 of the present invention is used to convert an input power supply (e.g., input voltage VIN) to generate an output power supply (e.g., output voltage Vout). The resonant asymmetric half-bridge flyback power converter 1002 includes an upper-bridge transistor 10 and a lower-bridge transistor 20 constituting a half-bridge circuit. A transformer 50 and a resonant capacitor 30, connected in series, are coupled to the switching node LX of the half-bridge circuit. The transformer 50 includes a primary winding WP, a secondary winding WS, and an auxiliary winding WA. The primary winding WP and the secondary winding WS have a turns ratio Np / Ns, while the secondary winding WS and the auxiliary winding WA have a turns ratio Ns / Na. A primary-side controller 200 generates drive signals SH and SL, which are used to control the half-bridge circuit to switch the transformer 50, thereby generating an output voltage Vout (corresponding to the output power supply) on the secondary side of the transformer 50. A drive signal SH drives the upper-bridge transistor 10 to magnetize the transformer 50. A drive signal SL turns on the lower-bridge transistor 20 during the demagnetization time of the transformer 50 and the transition resonance period of the transformer 50. It is worth noting that the aforementioned transition resonance period is related to the resonance of the resonant capacitor 30 and the magnetizing inductance value of the transformer 50. In one embodiment, the drive signal SL is also used to turn on the lower-bridge transistor 20, thereby generating a circulating current through the transformer 50 and thereby enabling the upper-bridge transistor 10 to achieve zero-voltage switching. A resistor 40 is coupled to the primary-side winding WP, wherein the resistor 40 is used to generate a current sensing signal VCS based on the primary-side switching current of the transformer 50.

[0111] The drive signals SH and SL are generated based on a feedback signal VFB related to the output power supply (e.g., output voltage Vout or output current) of the resonant asymmetric half-bridge flyback power converter 1002. In one embodiment, the secondary-side controller 100 is coupled to the output voltage Vout, thereby generating the feedback signal VFB. The feedback signal VFB is also coupled to the primary-side controller 200 via an optocoupler 90. The secondary-side controller 100 may also generate a drive signal SG, which is used to drive the synchronous rectifier 60 during the demagnetization time TDS of the transformer 50. The auxiliary winding WA generates an auxiliary signal VAUX when the transformer 50 is switched. During the switching of the transformer 50, resistors 51 and 52 further reduce the auxiliary signal VAUX to generate a voltage divider auxiliary signal VAUX'. In one embodiment, the aforementioned "voltage divider auxiliary signal VAUX'" refers to the voltage across resistor 52, which is differentially sensed via the primary-side controller 200.

[0112] Figure 3 This is a block diagram illustrating the primary-side controller of a resonant asymmetric half-bridge flyback power converter according to a specific embodiment of the present invention. In one embodiment, the primary-side controller 200 includes: a differential input sensing circuit 201, a first input circuit 202, a timing simulation circuit 203, a modulation circuit 204, a timing circuit 206, and a logic control circuit 205.

[0113] The differential input sensing circuit 201 includes a first input terminal D+ and a second input terminal D-, wherein the first input terminal D+ and the second input terminal D- are coupled to a voltage divider 501 to differentially sense the voltage divider auxiliary signal VAUX', thereby generating a peak signal SP, an output voltage-related current signal ID, and a reflected output voltage signal nVO. Figure 2 As shown, in this embodiment, the first input terminal D+ is coupled to the node between resistors 51 and 52, while the second input terminal D- is coupled to ground. The primary-side controller 200 generates an upper-bridge control signal SH and a lower-bridge control signal SL based on the feedback signal VFB, the peak signal SP, and the demagnetization time signal SDT. The upper-bridge control signal SH and the lower-bridge control signal SL are used to control the upper-bridge transistor 10 and the lower-bridge transistor 20, respectively, to switch the transformer 50, thereby generating the output voltage Vout. The duration (i.e., time length) of the demagnetization time signal SDT is related to the level of the output voltage Vout. When the transformer 50 has been demagnetized, the peak signal SP is related to the quasi-resonance state of the transformer 50. It is worth noting that the aforementioned "quasi-resonance" refers to the resonance formed between the transformer 50, the parasitic capacitance value of the upper-bridge transistor 10, and the parasitic capacitance value of the lower-bridge transistor 20.

[0114] The first input circuit 202 generates an input voltage-dependent current signal IC based on the first sub-signal VA' of the voltage divider auxiliary signal VAUX' (which is received via the first input terminal D+). The timing simulation circuit 203 generates a boundary extension signal SB and a demagnetization time signal SDT based on the pulse width modulation (PWM) signal SW, the input voltage-dependent current signal IC, and the output voltage-dependent current signal ID. The modulation circuit 204 generates the pulse width modulation signal SW based on the trigger signal Str, the feedback signal VFB, and the current sensing signal VCS. The logic control circuit 205 generates an upper bridge control signal SH and a lower bridge control signal SL based on the pulse width modulation signal SW, the demagnetization time signal SDT, the peak signal SP, the ready signal RDY, the boundary extension signal SB, and the reset signal RST.

[0115] Figure 4 This is shown in an embodiment of the present invention. Figure 2 and Figure 3 The waveform diagram shown represents the signal operation of the resonant asymmetric half-bridge flyback power converter. Figure 4 The signal operation waveform diagram shown includes the waveforms of the following signals: upper bridge control signal SH, magnetizing current IM, lower bridge control signal SL, primary side switching current IP, auxiliary signal VAUX, peak signal SP, and ready signal RDY. When the upper bridge control signal SH turns on the upper bridge transistor 10 (e.g., turns on during t0 to t1), the input voltage VIN of the resonant asymmetric half-bridge flyback power converter 1002 is coupled, thereby magnetizing the transformer 50 via the resonant capacitor 30. In this case (e.g., during t0 to t1, when the upper bridge control signal SH turns on the upper bridge transistor 10), the magnetizing current IM and the primary side switching current IP increase in a ramp manner. On the other hand, when the upper bridge control signal SH controls the upper bridge transistor 10 to not turn on for a deadtime period Td1, the circulating current of the transformer 50 turns on the body diode 25 of the lower bridge transistor 20 during the deadtime period Td1.

[0116] After a standstill time Td1, the lower bridge control signal SL switches to zero voltage to turn on the lower bridge transistor 20. In this way, the transformer 50 is energized via the lower bridge transistor 20 and the resonant capacitor 30. Simultaneously, the energy stored in the transformer 50 and the resonant capacitor 30 is transferred to the secondary winding WS, thereby generating an output voltage Vout during the demagnetization time TDS of the transformer 50. During the demagnetization time TDS of the transformer 50, the resonant capacitor 30 is coupled to the output voltage Vout via the transformer 50. In this case, the voltage across the resonant capacitor 30 VC30 can be expressed by the following formula (1):

[0117] VC30 = [(Np / Ns) * Vo] ------------------ Formula (1)

[0118] It is worth noting that in formula (1), Np represents the number of windings in the primary winding WP, Ns represents the number of windings in the secondary winding WS, Na represents the number of windings in the auxiliary winding WA, and Vo represents the voltage level of the output voltage Vout. In this case, the voltage level of the auxiliary signal VAUX generated via the auxiliary winding WA is Vauxo, where the voltage level Vauxo is related to the output voltage Vout. The voltage level Vauxo of the auxiliary signal VAUX can be expressed by the following formula (2):

[0119] Vauxo = [(Na / Ns) * Vo] ------------------- Formula (2)

[0120] In one embodiment, the primary-side controller 200 can sense the output voltage Vout by sensing the voltage divider auxiliary signal VAUX'.

[0121] In one embodiment, the demagnetization time TDS of transformer 50 can be expressed by the following formula (3):

[0122] TDS=[(VIN–VC30)*Ton] / [(Np / Ns)*Vo]

[0123] TDS=[(VIN–VC30)*Ton] / VC30-----------------Formula (3)

[0124] Under heavy load conditions, after the demagnetization time TDS, the primary-side controller 200 extends the pulse width of the lower bridge control signal SL by combining it with the boundary extension signal SB, thereby generating a reverse circulating current. Thus, when the upper bridge transistor 10 is turned on, the reverse circulating current will cause the upper bridge transistor 10 to achieve zero-voltage switching. Figure 4As shown in the waveform, under light load conditions, after the demagnetization time TDS, the primary-side controller 200 immediately controls the lower bridge control signal SL to switch to the off state (to turn off the lower bridge transistor 20). Furthermore, after the ready signal RDY is enabled, the primary-side controller 200 initiates the next switching cycle. With both the ready signal RDY and the peak signal enabled, the primary-side controller 200 turns on the lower bridge control signal SL to generate a zero-voltage switching pulse Pzv, thereby generating a reverse circulating current, which in turn enables the upper bridge transistor 10 to achieve zero-voltage switching. Under light load conditions, the ready signal RDY is used to reduce the switching frequency of the upper bridge control signal SH and the lower bridge control signal SL, thereby saving power.

[0125] The period from the end of the demagnetization time TDS to the start of the ready signal RDY being enabled is defined as an idle period TX, which is determined by the voltage level of the feedback signal VFB. As the output load decreases, the voltage level of the feedback signal VFB decreases, thus increasing the idle period TX. The idle period TX is related to the aforementioned quasi-resonant period.

[0126] Figure 5 This is a schematic diagram of a differential input sensing circuit 201 for a resonant asymmetric half-bridge flyback power converter according to an embodiment of the present invention. The differential input sensing circuit 201 has a first input terminal D+ and a second input terminal D-, wherein the first input terminal D+ and the second input terminal D- are coupled to a voltage divider 501. The first input terminal D+ and the second input terminal D- are used to sense a voltage divider auxiliary signal VAUX' to generate a peak signal SP and a current signal ID related to the output voltage. It is noteworthy that during the demagnetization time TDS, the output voltage-related current signal ID is related to the level of the output voltage Vout. The output voltage-related current signal ID is also used to generate a demagnetization time signal SDT (details and characteristics of the demagnetization time signal SDT will be described later).

[0127] When both the upper bridge control signal SH and the lower bridge control signal SL are off, and when the voltage divider auxiliary signal VAUX' is higher than a voltage threshold approaching zero volts, the peak signal SP will generate a pulse. When the voltage at the first input terminal D+ is higher than the voltage at the second input terminal D- (approaching zero volts), the comparator 230 with hysteresis triggers the pulse generator 235 to generate a pulse of the peak signal SP.

[0128] After the upper bridge control signal SH turns off the upper bridge transistor 10, and after the transformer 50 is demagnetized, the operational amplifiers 210 and 220 and the resistor 215 will generate a current I240 in the transistor 240 through a feedback operation mechanism based on the voltage VauxD between the first input terminal D+ and the second input terminal D-. The current I240 can be expressed by the following formula (4):

[0129] I240 = VauxD / R215 ------------------ Formula (4)

[0130] In one embodiment, operational amplifiers 210 and 220 are implemented as unity-gain buffers. In this case, operational amplifiers 210 and 220 respectively become unity-gain buffers for the sub-signals of the voltage divider auxiliary signal VAUX' received from the first input terminal D+ and the second input terminal D-, respectively. It is worth noting that in one embodiment, operational amplifier 220 may be omitted, wherein, in this case, the second input terminal D- may be directly connected to resistor 215.

[0131] Current I240 is used to generate an output voltage-related current signal ID via a current mirror formed by transistors 241 and 243. Furthermore, current I240 is used to generate current I242 via another current mirror formed by transistors 241 and 242.

[0132] Current I242 flows through resistor 225 to generate a reflected output voltage signal nVO, wherein the reflected output voltage signal nVO is related to the voltage level of the output voltage Vout. In one embodiment, the reflected output voltage signal nVO is used to perform overvoltage protection and undervoltage protection for the output voltage Vout of the resonant asymmetric half-bridge flyback power converter 1002.

[0133] Figure 6This is a schematic diagram showing the first input circuit 202 of a resonant asymmetric half-bridge flyback power converter according to an embodiment of the present invention. The first input circuit 202 is coupled to a first input terminal D+, wherein when the upper bridge control signal SH turns on and when the transformer 50 is magnetized, the first input circuit 202 generates an input voltage-dependent current signal IC. The input voltage-dependent current signal IC is related to the level of the input voltage VIN of the resonant asymmetric half-bridge flyback power converter 1002. Since the clamping voltage VCLAMP approaches zero volts, when the transformer 50 is magnetized, when the first input terminal D+ is pulled to a negative voltage via resistor 51 of voltage divider 501 (through the voltage divider auxiliary signal VAUX', which is also pulled to a negative voltage), the voltage at the first input terminal D+ is clamped to a level approaching zero volts. In this case, the voltage across resistor 51 is Vauxi, where the voltage across resistor 51 Vauxi is related to the input voltage VIN, where the related voltage Vaux is related to the current signal I250 generated by transistor 250. In this case, the current signal I250 can be expressed by the following formula (5):

[0134] I250 = Vauxi / R51

[0135] I250=[(VIN–VC30)x(Na / Np)] / R51------------Formula (5)

[0136] The current signal I250 is used to generate the input voltage-related current signal IC by a current mirror formed by transistors 252 and 253.

[0137] Figure 7 This is a schematic diagram of a timing simulation circuit 203 for a resonant asymmetric half-bridge flyback power converter according to an embodiment of the present invention. The timing simulation circuit 203 generates a demagnetizing time signal SDT and a boundary extension signal SB. The demagnetizing time signal SDT is generated based on the on-time of the output voltage-related current signal ID, the input voltage-related current signal IC, and the upper bridge control signal SH (i.e., via the pulse width modulation signal SW). When the upper bridge control signal SH (i.e., the pulse width modulation signal SW) turns to an off state to trigger the flip-flop 340, the demagnetizing time signal SDT is enabled via AND gate 345. Notably, the internal power supply VCC coupled to the data input terminal of the flip-flop 340 can be the supply voltage of the timing simulation circuit 203. When the voltage of capacitor 330 is discharged below the discharge threshold VT3, the demagnetizing time signal SDT is disabled.

[0138] Specifically, during the on-time of the upper bridge control signal SH (i.e., the pulse width modulation signal SW), capacitor 330 is charged by the input voltage-related current signal IC. Conversely, after the upper bridge control signal SH turns off, capacitor 330 is discharged by the output voltage-related current signal ID. In other words, when the demagnetizing time signal SDT is enabled, it simulates the on-time of the upper bridge transistor 10; and when the demagnetizing time signal SDT is disabled, it simulates the on-time of the lower bridge transistor 20.

[0139] Furthermore, when the voltage of capacitor 330 is lower than another discharge threshold VT4 (wherein the voltage of capacitor 330 and discharge threshold VT4 are compared with each other via comparator 332), a boundary extension signal SB is generated by pulse generator 335. The boundary extension signal SB is used to generate a reverse circulating current during the continuous enabled state of the demagnetization time signal SDT, thereby enabling zero-voltage switching of the upper bridge transistor 10. From one perspective, during periods of heavy load, after the enabled state of the demagnetization time signal SDT, the boundary extension signal SB is used to extend the pulse width of the lower bridge control signal SL. In one embodiment, the discharge threshold VT4 is higher than the discharge threshold VT3.

[0140] Figure 8 This is a schematic diagram of a modulation circuit 204, a logic control circuit 205, and a timing circuit 206 of a resonant asymmetric half-bridge flyback power converter according to an embodiment of the present invention. The modulation circuit 204 generates a pulse width modulation signal SW; the logic control circuit 205 generates an upper bridge control signal SH and a lower bridge control signal SL; and the timing circuit 206 generates a ready signal RDY. From one perspective, the modulation circuit 204, the logic control circuit 205, and the timing circuit 206 are considered as a single PWM control circuit.

[0141] In one embodiment, the modulation circuit 204 includes a comparator 384, a flip-flop 370, and a level shifting and divider circuit, wherein the level shifting and divider circuit includes a transistor 380, a resistor 381, a resistor 382, ​​and a resistor 383.

[0142] The flip-flop 370 is triggered by the trigger signal Str to enable the conduction of the pulse width modulation signal SW (i.e., to put the pulse width modulation signal SW in the on state). It is worth noting that when a protection mechanism for the output voltage Vout (e.g., the aforementioned overvoltage and undervoltage protection) occurs, the enable signal EN coupled to the data terminal D of the flip-flop 370 is disabled, causing the pulse width modulation signal SW to stop switching. The pulse width of the pulse width modulation signal SW is determined based on the level of the feedback signal VFB. In one embodiment, the feedback signal VFB is related to the amplified value of the difference between the reference signal and the output power supply (e.g., the output voltage Vout), wherein the aforementioned amplification off operation is implemented by the secondary-side controller 100. Comparator 384 compares the current sensing signal VCS with the divided feedback signal VFB” to determine the off-time of the pulse width modulation signal SW, thereby performing the pulse width modulation function in peak-current mode operation. The current sensing signal VCS is related to the transformer current of transformer 50. The level shift and voltage divider circuit is used to level shift the feedback signal VFB to generate a level-shifted feedback signal VFB’. Resistors 382 and 383 further divide the level-shifted feedback signal VFB’ to generate the divided feedback signal VFB”.

[0143] Please continue reading. Figure 8 The timing circuit 206 includes a voltage-to-current converter 390 and a timer 395. In one embodiment, since the resonant asymmetric half-bridge flyback power converter 1002 is in peak current mode, the level of the feedback signal VFB increases with the increase of the output load (output load refers to, for example, the current or power consumed by the load). In one embodiment, the off-time of the pulse width modulation signal SW (also the off-time of the upper bridge control signal SH) is related to the level of the feedback signal VFB. The off-time of the upper bridge control signal SH increases with the decrease of the output load, and the off-time of the upper bridge control signal SH is controlled by a ready signal RDY. The ready signal RDY is generated via the timer 395. The period of the timer 395 is determined by the feedback signal VFB via the voltage-to-current converter 390.

[0144] Please continue reading. Figure 8 The logic control circuit 205 generates the upper bridge control signal SH, the lower bridge control signal SL, and the trigger signal Str based on the pulse width modulation signal SW, the peak signal SP, the ready signal RDY, the boundary extension signal SB, the demagnetization time signal SDT, and the reset signal RST.

[0145] OR gate 361 and buffer 362 are used to generate the lower bridge control signal SL. The pulse width of the lower bridge control signal SL (corresponding to the enable state) is determined based on the demagnetization time signal SDT and / or the output of pulse generator 360. Pulse generator 360 is used to generate a zero-voltage switching pulse Pzv, which generates a reverse circulating current, thereby enabling the lower bridge transistor 20 to achieve zero-voltage switching. Once the ready signal RDY is enabled, the peak signal SP or the boundary extension signal SB will trigger pulse generator 360. If the ready signal RDY is enabled before the end of the demagnetization time TDS of transformer 50, the boundary extension signal SB will increase the duration of the lower bridge control signal SL. The pulse width modulation signal SW generates the upper bridge control signal SH via buffer 372. In one embodiment, the reset signal RST is a power-on reset signal used to reset the state of the primary side controller 200 after the primary side controller 200 is powered on.

[0146] It is worth noting that the differential ground inductive voltage divider auxiliary signal VAUX' will enable the primary-side controller 200, enabling the primary-side controller 200 to accurately generate the output voltage-related current signal ID and the peak signal SP with precise timing. In this way, when the resonant asymmetric half-bridge flyback power converter 1002 of the present invention is intended to be applied to a wider voltage range, under light load conditions, the present invention can have precise non-conduction period and precise discontinuous conduction mode (DCM) timing control, thereby increasing power conversion efficiency.

[0147] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the scope of the invention. The described embodiments are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components of one embodiment can be used to replace corresponding components in another embodiment. Furthermore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the phrase "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many ways to combine them, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A switching control circuit for controlling a power stage circuit in a resonant asymmetric half-bridge flyback power converter, wherein, The power stage circuit includes: a transformer, a resonant capacitor, a first transistor, and a second transistor coupled to each other, thereby converting an input power supply to generate an output power supply; the switching control circuit includes: A voltage divider coupled to an auxiliary winding of the transformer, wherein the voltage divider is used to divide an auxiliary signal generated via the auxiliary winding; A differential input sensing circuit includes: a first input terminal and a second input terminal, wherein the first input terminal and the second input terminal are coupled to the voltage divider to sense the auxiliary signal, thereby generating a peak signal and a demagnetization time signal; A feedback circuit is used to generate a feedback signal based on an electrical characteristic of the output power supply of the resonant asymmetric half-bridge flyback power converter; and A pulse width modulation circuit is used to generate a first pulse width modulation signal and a second pulse width modulation signal according to the feedback signal, the peak signal and the demagnetization time signal, wherein the first pulse width modulation signal and the second pulse width modulation signal are respectively used to control the first transistor and the second transistor of the resonant asymmetric half-bridge flyback power converter. The first pulse width modulation signal and the second pulse width modulation signal are used to control the first transistor and the second transistor to switch the transformer, thereby generating the output power of the resonant asymmetric half-bridge flyback power converter. During an enable state of the demagnetization time signal, a current level or a power level of the output power supply of the resonant asymmetric half-bridge flyback power converter is associated with it. In the case where the transformer has been demagnetized, the peak signal is related to a quasi-resonant state of the transformer.

2. The switching control circuit as described in claim 1, wherein, When the first pulse width modulation signal turns to a shutdown state to turn off the first transistor and when the auxiliary signal is higher than a voltage threshold, the differential input sensing circuit generates the peak signal.

3. The switching control circuit as described in claim 1, wherein, Also includes: A first input circuit coupled to the first input terminal, wherein the first input circuit is used to generate an input voltage-related current signal when the first pulse width modulation signal is switched to an on state to turn on the first transistor and when the transformer is energized. The input voltage-related current signal is related to a bit level of an input voltage of the resonant asymmetric half-bridge flyback power converter.

4. The switching control circuit as described in claim 3, wherein, The differential input sensing circuit is used to generate an output voltage-dependent current signal based on a voltage difference between the first input terminal and the second input terminal. The current signal associated with the output voltage is related to a bit level of an output voltage of the resonant asymmetric half-bridge flyback power converter.

5. The switching control circuit as described in claim 4, wherein, The current signal associated with the output voltage is used to generate a reflected output voltage signal, which is used to perform overvoltage protection and undervoltage protection for the output voltage of the resonant asymmetric half-bridge flyback power converter.

6. The switching control circuit as described in claim 4, wherein, The demagnetizing time signal is generated based on the output voltage-related current signal, the input voltage-related current signal, and an on-time of the first pulse width modulation signal.

7. The switching control circuit as described in claim 1, wherein, Also includes: A timing analog circuit; Wherein, when the first pulse width modulation signal switches to an off state to turn off the first transistor, the demagnetizing time signal switches to the enable state; and When a capacitor in the timing simulation circuit is discharged to a voltage below a first discharge threshold, the demagnetizing time signal is switched to an inhibited state. The capacitor of the timing simulation circuit is charged by an input voltage-related current signal during a conduction period of the first pulse width modulation signal, and the capacitor of the timing simulation circuit is discharged by an output voltage-related current signal when the first pulse width modulation signal turns to a turn-off state.

8. The switching control circuit as described in claim 7, wherein, When the voltage of the capacitor is lower than a second discharge threshold, a boundary extension signal is generated, wherein the boundary extension signal is used to make the demagnetization time signal continue during the enable state to generate a reverse circulating current, thereby enabling the first transistor to achieve zero-voltage switching.

9. The switching control circuit as described in claim 1, wherein, A non-conducting time of the first pulse width modulation signal is related to a bit level of the feedback signal; wherein the non-conducting time of the first pulse width modulation signal increases according to a decrease in an output load of the resonant asymmetric half-bridge flyback power converter.

10. The switching control circuit as described in claim 1, wherein, The conduction time of the second pulse width modulation signal is greater than the demagnetization time of the transformer, thereby enabling the resonant asymmetric half-bridge flyback power converter to achieve zero-voltage switching.

11. The switching control circuit as described in claim 1, wherein, The output voltage of the resonant asymmetric half-bridge flyback power converter is programmable, and the output voltage of the resonant asymmetric half-bridge flyback power converter includes a maximum value and a minimum value, wherein a ratio between the maximum value and the minimum value is equal to or greater than 4, or equal to or greater than 9.

12. The switching control circuit as described in claim 1, wherein, This resonant asymmetric half-bridge flyback power converter is a universal serial bus power transmission type power converter, in which the maximum output voltage is 48 volts and the minimum output voltage is 5 volts.

13. A resonant asymmetric half-bridge flyback power converter, comprising: A power stage circuit, comprising: A transformer, a resonant capacitor, a first transistor, and a second transistor are coupled to each other, thereby converting an input power supply to generate an output power supply. as well as The switching control circuit as described in any one of claims 1 to 12, wherein the switching control circuit is used to control the power stage circuit in the resonant asymmetric half-bridge flyback power converter.

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