Solar cell and photovoltaic module

Abstract

The present invention provides a solar cell and a photovoltaic module, and relates to the field of photovoltaic technology. The solar cell includes: a silicon substrate; the silicon substrate includes a first surface and a second surface relative to each other; an N-type doped layer, located on at least a portion of the first surface of the silicon substrate; the square resistance of the N-type doped layer is 14 ohms / square to 40 ohms / square; a plurality of N-type collector grid lines that are spaced and distributed in parallel, located on the side of the N-type doped layer away from the silicon substrate; the spacing between adjacent N-type collector grid lines is less than 1.391 mm. In the present application, the square resistance of the N-type doped layer is 14 ohms / square to 40 ohms / square, and the spacing between adjacent N-type collector grid lines is less than 1.391 mm, so that factors such as parasitic absorption, composite current of the metal area and lateral resistance can achieve a better balance, so that the performance of the solar cell is better and the photoelectric conversion efficiency is higher.

Description

Technical Field

[0001] The invention relates to the field of photovoltaic technology, in particular to a solar cell and a photovoltaic module. Background Art

[0002] Solar cells can convert solar energy into electrical energy. They utilize clean energy and therefore have broad application prospects.

[0003] The various factors in a solar cell need to cooperate with each other to achieve the function of converting solar energy into electrical energy. However, in existing solar cells, the cooperation between the various factors is not appropriate, resulting in poor performance of the solar cell. Summary of the invention

[0004] The present invention provides a solar cell and a photovoltaic module, aiming to solve the problem that the performance of the solar cell is poor due to inappropriate coordination between different factors in the existing solar cell.

[0005] A first aspect of the present invention provides a solar cell, comprising:

[0006] A silicon substrate; the silicon substrate comprises a first surface and a second surface opposite to each other;

[0007] An N-type doped layer is located on at least a portion of the first surface of the silicon substrate; the sheet resistance of the N-type doped layer is 14 ohms / square to 40 ohms / square;

[0008] A plurality of N-type collector gate lines that are spaced apart and distributed in parallel are located on a side of the N-type doped layer away from the silicon substrate; and a spacing between adjacent N-type collector gate lines is less than 1.391 mm.

[0009] In an embodiment of the present invention, the square resistance of the N-type doped layer is 14 ohms / square to 40 ohms / square, the spacing between adjacent N-type collector grid lines is less than 1.391 mm, and the square resistance of the N-type doped layer and the spacing between adjacent N-type collector grid lines are respectively within the above ranges, so that factors such as parasitic absorption, composite current of the metal area and lateral resistance can achieve a better balance, so that the performance of the solar cell is better and the photoelectric conversion efficiency is higher.

[0010] Optionally, the sheet resistance of the N-type doped layer is 14 ohms / square to 20 ohms / square, and the spacing between adjacent N-type collector grid lines is 1.019 mm to 1.296 mm; or,

[0011] The square resistance of the N-type doped layer is greater than 20 ohms / square and less than or equal to 40 ohms / square, and the spacing between adjacent N-type collector grid lines is 0.839 mm to 0.977 mm.

[0012] Optionally, the thickness of the N-type doping layer is 100 nm to 140 nm.

[0013] Optionally, the doping concentration of the N-type doping layer is 3E20 cm -3 to 7E20 cm -3 .

[0014] Optionally, the solar cell further comprises: a P-type doping layer, wherein the sheet resistance of the P-type doping layer is 20 ohms / square to 166 ohms / square;

[0015] A plurality of P-type collector gate lines which are spaced apart and distributed in parallel are located on a side of the P-type doped layer away from the silicon substrate.

[0016] Optionally, the N-type doped layer includes: an N-type doped polysilicon layer and / or an N-type doped microcrystalline silicon layer;

[0017] The solar cell further comprises: a first tunneling oxide layer, located between the N-type doped layer and the silicon substrate;

[0018] The spacing between adjacent P-type collector gate lines is less than or equal to the spacing between adjacent N-type collector gate lines.

[0019] Optionally, the first surface includes: a first conductive area and a second conductive area that are spaced apart;

[0020] The N-type doped layer is located on the first conductive region;

[0021] The P-type doped layer is located on the second conductive region;

[0022] The solar cell further includes: a second tunneling oxide layer located between the P-type doping layer and the silicon substrate.

[0023] Optionally, the N-type doped layer is located on the first surface of the silicon substrate, and the P-type doped layer is located on the second surface of the silicon substrate.

[0024] Optionally, the P-type doped layer is a P-type polysilicon doped layer and / or a P-type doped microcrystalline silicon layer.

[0025] A second aspect of the present invention provides a photovoltaic assembly, comprising: a plurality of any of the aforementioned solar cells.

[0026] The above-mentioned solar cells and photovoltaic modules have the same or similar beneficial effects, which will not be described again here to avoid repetition. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0028] Figure 1 A partial structural schematic diagram of a solar cell in an embodiment of the present invention is shown;

[0029] Figure 2 A curve diagram showing the influence of the square resistance of an N-type doped layer and the spacing between adjacent N-type collector grid lines on the efficiency of a solar cell in an embodiment of the present invention is shown;

[0030] Figure 3 A fitting curve diagram of the square resistance of an N-type doped layer and the spacing between adjacent N-type collector grid lines in an embodiment of the present invention is shown;

[0031] Figure 4 A curve diagram showing the influence of the thickness of an N-type doping layer and the spacing between adjacent N-type collector grid lines on the efficiency of a solar cell in an embodiment of the present invention is shown;

[0032] Figure 5 A curve diagram showing the influence of the square resistance of a P-type doped layer and the spacing between adjacent P-type collector grid lines on the efficiency of a solar cell in an embodiment of the present invention is shown.

[0033] Description of the accompanying drawings:

[0034] 1-N type doped layer, 2-N type collector grid line. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] The present invention provides a solar cell, which may include: a silicon substrate, the doping type and crystal type of the silicon substrate are not specifically limited, for example, the silicon substrate may be N-type doped single crystal silicon, etc. The silicon substrate includes a first surface and a second surface opposite to each other, wherein one of the first surface and the second surface is a light-facing surface and the other is a backlight surface, and during normal operation of the solar cell, the surface that mainly receives light is the light-facing surface, and the backlight surface is opposite to the light-facing surface.

[0037] The solar cell may also include: an N-type doped layer, which may form a high-low junction or a PN junction with the aforementioned silicon substrate, which is not specifically limited. The N-type doped layer is located on at least a portion of the first surface of the silicon substrate, which may be located on the entire first surface, or only on a portion of the first surface, which is not specifically limited. The square resistance of the N-type doped layer is 14 ohms / square (Ω / □) to 40 ohms / square. The square resistance of the N-type doped layer refers to: for a portion of the N-type doped layer with a length of l, a width of w, and a height of d (that is, the thickness of the N-type doped layer), at this time, L=l, S=w×d of this portion, so R sh =ρ×l / (w×d)=(ρ / d)×(l / w). Let l=w, so R sh =(ρ / d), where ρ is the resistivity of the N-type doped layer. sh is the square resistance of the N-type doped layer. The square here refers to a region in the N-type doped layer with equal length and width and variable thickness. When the length and width of the square are equal, the length and width have little effect on the square resistance. For example, when the length and width of the square are equal, the length and width can both be 1 cm or 1 m, and the corresponding square resistances are equal, but the square resistance decreases as the thickness of the square increases.

[0038] The solar cell may further include: a plurality of N-type collector grid lines that are spaced apart and distributed in parallel, and are located on a side of the N-type doped layer away from the silicon substrate, and the N-type collector grid lines are used to collect carriers. Figure 1 In the figure, 1 is a schematic diagram of an N-type doped layer, 2 is a schematic diagram of an N-type collector grid line, and the number of N-type collector grid lines 2 in the solar cell is not specifically limited. Figure 1 In the embodiment of the present invention, the square resistance of the N-type doped layer is 14 ohms / square to 40 ohms / square, the spacing between adjacent N-type collector grid lines is less than 1.391 mm, and the square resistance of the N-type doped layer and the spacing between adjacent N-type collector grid lines are respectively within the above ranges, so that factors such as parasitic absorption, composite current of the metal region and lateral resistance can achieve a better balance, so that the performance of the solar cell is better and the photoelectric conversion efficiency is higher.

[0039] For example, the square resistance of the N-type doped layer can be 14 ohms / square, 14.7 ohms / square, 15 ohms / square, 16.8 ohms / square, 17.6 ohms / square, 18.5 ohms / square, 19.3 ohms / square, 20.4 ohms / square, 22 ohms / square, 25 ohms / square, 23.1 ohms / square, 29.5 ohms / square, 27 ohms / square, 30 ohms / square, 32.5 ohms / square, 38 ohms / square, 39.1 ohms / square, 40 ohms / square, the spacing between adjacent N-type collector grid lines can be 1.296mm, 1.213mm, 1.141mm, 1.076mm, 1.019mm, 1mm, 0.977mm, 0.967mm, 0.92mm, 0.878mm, 0.839mm, 0.8mm.

[0040] More specifically, Figure 2 The figure is a graph showing the effect of the square resistance of the N-type doped layer and the spacing between adjacent N-type collector grid lines on the efficiency of the solar cell. Figure 2 , Figure 2 The horizontal axis in the middle is the square resistance of the N-type doped layer such as the N-type doped polysilicon layer or the phosphorus-doped polysilicon layer. Figure 2 The vertical axis is the efficiency of the solar cell. Figure 2 The order of the curves from bottom to top corresponds to the spacing between adjacent N-type collector grid lines: 1.964mm, 1.78mm, 1.628mm, 1.5mm, 1.391mm, 1.296mm, 1.213mm, 1.141mm, 1.076mm, 1.019mm, 0.977mm, 0.967mm, 0.92mm, 0.878mm, and 0.839mm, a total of 15 spacings. Figure 2 In the example, a solar cell with an efficiency greater than or equal to 26%, such as 26.0% to 26.5%, is selected as a solar cell with a higher efficiency, that is, Figure 2 The efficiency of the solar cells in the dotted box and the part below the dotted box is less than 26%. Figure 2It can be concluded that among the above-mentioned 15 adjacent N-type collector grid lines, the spacing between adjacent N-type collector grid lines greater than or equal to 1.391mm, namely the 5 spacings of 1.964mm, 1.78mm, 1.628mm, 1.5mm, and 1.391mm, and / or the square resistance of the N-type doped layer is less than 14 ohms / square, or greater than 40 ohms / square, and the efficiency of the corresponding solar cell is less than 26%, indicating that the spacing between adjacent N-type collector grid lines is greater than or equal to 1.391mm, and / or the square resistance of the N-type doped layer is less than 14 ohms / square, or greater than 40 ohms / square, and the solar cell cannot obtain a better efficiency. Therefore, in the present application, the spacing between adjacent N-type collector grid lines is selected to be less than 1.391mm, and the square resistance of the N-type doped layer is 14 ohms / square to 40 ohms / square, which is conducive to improving the efficiency of the solar cell, such as Figure 2 In the present application, the spacing between adjacent N-type collector grid lines is selected to be less than 1.391 mm, and the square resistance of the N-type doped layer is 14 ohms / square to 40 ohms / square, then the efficiency of the solar cell is greater than or equal to 26%, and even reaches 26.5% or more.

[0041] Optionally, the square resistance of the N-type doped layer is 14 ohms / square to 20 ohms / square, and the spacing between adjacent N-type collector grid lines is 1.019 mm to 1.296 mm; or, the square resistance of the N-type doped layer is greater than 20 ohms / square and less than or equal to 40 ohms / square, and the spacing between adjacent N-type collector grid lines is 0.839 mm to 0.977 mm. For details, refer to Figure 2, the square resistance of the N-type doped layer is 20 ohms / square, which is roughly the square resistance of the N-type doped layer corresponding to the inflection point of the efficiency in the part with an efficiency greater than or equal to 26%. More specifically, when the square resistance of the N-type doped layer is 14 ohms / square to 20 ohms / square, the spacing between adjacent N-type collector grid lines is 1.019mm to 1.296mm, the efficiency of the solar cell is greater than or equal to 26.0%, and the efficiency increases fastest. When the square resistance of the N-type doped layer is greater than 20 ohms / square to less than or equal to 40 ohms / square, the spacing between adjacent N-type collector grid lines is 0.839mm to 0.977m m, the efficiency of the solar cell is greater than or equal to 26.0%, and the rate of efficiency decline is the slowest. Therefore, in the present application, the square resistance of the N-type doped layer is 14 ohms / square to 20 ohms / square, and the spacing between adjacent N-type collector grid lines is 1.019mm to 1.296mm; or, the square resistance of the N-type doped layer is greater than 20 ohms / square and less than or equal to 40 ohms / square, and the spacing between adjacent N-type collector grid lines is 0.839mm to 0.977mm. The efficiency of the solar cell is further improved by further combining and optimizing the square resistance of the N-type doped layer and the spacing between adjacent N-type collector grid lines. It should be noted that there is no specific limitation on the material of the N-type collector grid line. For example, the N-type collector grid line can be a silver collector grid line.

[0042] For example, the square resistance of the N-type doped layer can be 14 ohms / square, 14.7 ohms / square, 15 ohms / square, 15.3 ohms / square, 16 ohms / square, 16.5 ohms / square, 17 ohms / square, 17.7 ohms / square, 18 ohms / square, 18.5 ohms / square, 19 ohms / square, 19.5 ohms / square, 20 ohms / square, and the spacing between adjacent N-type collector grid lines can be 1.019 mm, 1.05 mm, 1.076 mm, 1.112 mm, 1.141 mm, 1.173 mm, 1.213 mm, 1.25 mm, 1.296 mm. Or, the square resistance of the N-type doped layer can be 20.3 ohms / square, 20.7 ohms / square, 21 ohms / square, 21.3 ohms / square, 22 ohms / square, 22.5 ohms / square, 23 ohms / square, 23.5 ohms / square, 24 ohms / square, 24.5 ohms / square, 25 ohms / square, 25.6 ohms / square, 27 ohms / square, 28 ohms / square, 29. 9.6 ohms / square, 30 ohms / square, 31.6 ohms / square, 36.2 ohms / square, 38.56 ohms / square, 40 ohms / square, the spacing between adjacent N-type collector grid lines can be 0.977mm, 0.971mm, 0.967mm, 0.9mm, 0.92mm, 0.913mm, 0.878mm, 0.8mm, 0.839mm.

[0043] More specifically, combined with the above Figure 2 In the embodiment, the relevant data of the case where the efficiency of the solar cell is greater than or equal to 26.0%, such as 26.0% to 26.5%, are fitted to obtain the fitting curve between the spacing y between adjacent N-type collector grid lines and the square resistance x of the N-type doped layer in the back contact solar cell (BC) as shown in FIG. Figure 3 As shown, y = 0.004x 4 -0.542x 3 +24.53x 2 -492.4x+4687.3. The correlation of the fitting curve is R 2 =0.998, in the fitting curve or fitting formula, the unit of y is micrometer (μm), and the unit of x is ohm / square. Figure 3 In the figure, each point includes data on the left and data on the right. The data on the left of each point are the square resistance of the N-type doped layer, and the data on the right are the spacing between adjacent N-type collector grid lines corresponding to the square resistance. The combination of the spacing between adjacent N-type collector grid lines obtained by the fitting curve and the square resistance of the N-type doped layer enables factors such as parasitic absorption, composite current in the metal area, and lateral resistance to achieve a better balance, resulting in better performance of the solar cell and higher photoelectric conversion efficiency.

[0044] Optionally, the thickness of the N-type doping layer is 100nm (nanometer) to 140nm. The thickness of the N-type doping layer is relatively suitable, which is beneficial to the square resistance, parasitic absorption, passivation region recombination current, metal region recombination current and other factors of the N-type doping layer, so that the performance of the solar cell is better and the photoelectric conversion efficiency is higher. For more details, refer to Figure 1 , the side wall of the N-type collector grid line 2 contacts the N-type doped layer 1. The larger the height h and the bottom side length a of the N-type collector grid line 2 are, the larger the side wall area of ​​the N-type collector grid line 2 is, and the larger the recombination current of the metal area is. Assuming that the recombination rate of the side wall of the N-type collector grid line 2 is 10 7 cm / s, and the composite current of the metal area and the composite current of the passivation area are estimated by weighted average according to the area ratio to obtain the composite current of the macroscopic metal area. When the height h of the N-type collector grid line 2 is fixed, the thickness of the N-type doped layer 1 is changed to t, and the composite current of the metal area is estimated. Figure 4 The figure is a curve diagram showing the influence of the thickness of the N-type doping layer and the spacing between adjacent N-type collector grid lines on the efficiency of the solar cell. Figure 4In the figure, the order of the curves from bottom to top corresponds to the spacing between adjacent N-type collector grid lines: 1.964mm, 1.78mm, 1.628mm, 1.5mm, 1.391mm, 1.296mm, 1.213mm, 1.141mm, 1.076mm, 1.019mm, 0.977mm, 0.967mm, 0.92mm, 0.878mm, and 0.839mm, a total of 15 spacings. Figure 4 In the figure, a point includes data on the left and data on the right. The data on the left of the point is the thickness of the N-type doping layer, and the data on the right is the efficiency of the solar cell corresponding to the thickness. Figure 4 , it can be concluded that when the thickness of the N-type doping layer is 100nm to 140nm, especially when it is about 120nm, for the spacing between the above 15 adjacent N-type collector grid lines, the efficiency of the solar cell basically reaches the maximum. At the same time, when the thickness of the N-type doping layer is less than 100nm, the efficiency of the solar cell increases with the increase of the thickness of the N-type doping layer, and when the thickness of the N-type doping layer is greater than 140nm, the efficiency of the solar cell remains stable or tends to decrease with the increase of the thickness of the N-type doping layer. Moreover, when the thickness of the N-type doping layer is 100nm to 140nm, the composite current of the metal area estimated by the above method is also small. Therefore, in the present application, the thickness of the N-type doping layer is 100nm to 140nm, which is more favorable to the square resistance, parasitic absorption, composite current of the passivation zone, composite current of the metal zone and other factors of the N-type doping layer, so that the performance of the solar cell is better and the photoelectric conversion efficiency is higher. For example, if the thickness of the N-type doping layer is selected to be 120nm, the formula is used Roughly estimate the square resistance R of the N-type doped layer sh , the square resistance R of the N-type doped layer is calculated sh It is about 29.5 ohms / square, which is within the range of 14 ohms / square to 40 ohms / square mentioned above. In the above formula, q is the basic charge or elementary charge, q = 1.6021766208×10 -19 Coulomb, μ is the migration rate (the drift rate of carriers under unit electric field strength) is about 35.27 cm 2 / V·s, n is the doping concentration of the N-type doping layer, which is about 5×10 20 cm -3 , t is the thickness of the N-type doped layer, i.e. 120nm.

[0045] For example, the thickness of the N-type doping layer may be 100 nm, 103.2 nm, 105 nm, 109 nm, 110 nm, 115 nm, 118.3 nm, 120 nm, 125 nm, 128 nm, 130 nm, 132.3 nm, 135 nm, 137.9 nm, or 140 nm.

[0046] Optionally, the doping concentration of the N-type doping layer is 3E20 cm -3 to 7E20 cm -3 Specifically, the doping concentration of the N-type doping layer is an important factor affecting the square resistance of the N-type doping layer. In the present application, the doping concentration of the N-type doping layer is limited to a relatively suitable range so that the square resistance of the N-type doping layer can be within the aforementioned required range.

[0047] For example, the doping concentration of the N-type doped layer can be 3E20 cm -3 、3.2E20 cm -3 、3.5E20 cm -3 、4E20cm -3 , 4.3E20 cm -3 、4.7E20 cm -3 , 4.21E20 cm -3 、5E20 cm -3 , 5.2E20 cm -3 、5.5E20 cm -3 、6E20cm -3 、6.3E20 cm -3 、7E20 cm -3 .

[0048] Optionally, the solar cell further includes: a P-type doped layer, the P-type doped layer forms a PN junction or a high-low junction with the silicon substrate, the square resistance of the P-type doped layer is 20 ohms / square to 166 ohms / square, and the square resistance of the P-type doped layer refers to: for a portion of the P-type doped layer with a length of l, a width of w, and a height of d (i.e., the thickness of the P-type doped layer), at this time, L=l, S=w×d of the portion, so R sh =ρ×l / (w×d)=(ρ / d)×(l / w). Let l=w, so R sh =(ρ / d), where ρ is the resistivity of the P-type doped layer. sh is the square resistance of the P-type doped layer. The square resistance of the P-type doped layer within this range is conducive to improving the efficiency of the solar cell, such as making the efficiency of the solar cell greater than or equal to 25.99%. The solar cell also includes: a plurality of P-type collector grid lines that are spaced and distributed in parallel, located on the side of the P-type doped layer away from the silicon substrate, and the P-type collector grid lines are used to collect carriers.

[0049] For more specific reference Figure 5 , Figure 5 The figure is a curve diagram showing the influence of the square resistance of a P-type doped layer, such as a boron-doped polysilicon layer, and the spacing between adjacent P-type collector grid lines on the efficiency of a solar cell. Figure 5 The horizontal axis is the square resistance of a P-type doped layer such as a P-type doped polysilicon layer or a boron doped polysilicon layer. Figure 5 The vertical axis is the efficiency of the solar cell. Figure 5 In the figure, the order of the curves from bottom to top corresponds to the spacing between adjacent P-type collector grid lines: 1.964mm, 1.78mm, 1.628mm, 1.5mm, 1.391mm, 1.296mm, 1.213mm, 1.141mm, 1.076mm, 1.019mm, 0.977mm, 0.967mm, 0.92mm, 0.878mm, and 0.839mm, a total of 15 spacings. Figure 5 In the example, the efficiency of the solar cell corresponding to the framed portion is greater than or equal to 25.99%, and the efficiency of the solar cell corresponding to the portion outside the frame is less than 25.99%. Figure 5 It can be concluded that when the square resistance of the P-type doped layer is 20 ohms / square to 166 ohms / square, the performance of the solar cell is relatively good, and the efficiency of the solar cell is relatively high, reaching 25.99% or more. Figure 5 In the figure, the data of the two points include the data on the left and the data on the right. The data on the left are the square resistance of the P-type doped layer, and the data on the right are the efficiency of the solar cell corresponding to the square resistance. In the present application, by limiting the combination of factors such as the square resistance of the N-type doped layer and the square resistance of the P-type doped layer, the solar cell can appropriately select a relatively large grid line spacing, thereby reducing the grid line unit consumption.

[0050] For example, the square resistance of the P-type doped layer can be 20 ohms / square, 20.5 ohms / square, 36 ohms / square, 40 ohms / square, 50 ohms / square, 60 ohms / square, 70 ohms / square, 80 ohms / square, 90 ohms / square, 93 ohms / square, 100 ohms / square, 120 ohms / square, 130 ohms / square, 140 ohms / square, 150 ohms / square, 160 ohms / square, and 166 ohms / square.

[0051] Optionally, the N-type doped layer includes: an N-type doped polysilicon layer and / or an N-type doped microcrystalline silicon layer, and the solar cell further includes: a first tunneling oxide layer, located between the N-type doped layer and the silicon substrate, and the first tunneling oxide layer and the aforementioned N-type doped layer can form a passivation contact structure, further improving the efficiency of the solar cell. The spacing between adjacent P-type collector grid lines is less than or equal to the spacing between adjacent N-type collector grid lines. Specifically, because it is not easy for the P-type doped layer to obtain a higher doping concentration, the spacing between adjacent P-type collector grid lines can be smaller, which can further improve the efficiency of the solar cell. In the case where the spacing between adjacent P-type collector grid lines is less than the spacing between adjacent N-type collector grid lines, the difference between the two is not specifically limited. It should be noted that there is no specific limitation on the material of the P-type collector grid line, and whether the material of the P-type collector grid line is the same as that of the N-type collector grid line is not specifically limited. For example, the P-type collector grid line can be a silver collector grid line, etc.

[0052] Optionally, the first surface of the aforementioned silicon substrate includes: a first conductive region and a second conductive region that are spaced apart, the space between the first conductive region and the second conductive region is used to avoid leakage, and the relative size of the first conductive region and the second conductive region is not limited. The N-type doped layer is located on the first conductive region, and the P-type doped layer is located on the second conductive region. The solar cell may also include: a second tunneling oxide layer, located between the P-type doped layer and the silicon substrate, and the second tunneling oxide layer and the first tunneling oxide layer may be formed in the same process, or the second tunneling oxide layer and the first tunneling oxide layer may be formed in different processes, which is not specifically limited. In the case where the second tunneling oxide layer and the first tunneling oxide layer are formed in different processes, whether the first tunneling oxide layer is made first or the second tunneling oxide layer is made first is not specifically limited. For example, the first tunneling oxide layer may be made first, and then the second tunneling oxide layer may be made later. The first surface here may be the backlight surface of the silicon substrate, and the solar cell is a back contact solar cell, in which the light-facing surface of the silicon substrate in the solar cell is not blocked by an electrode, and has higher efficiency.

[0053] Optionally, the aforementioned N-type doped layer may be located on the first surface of the silicon substrate, or in other words, the N-type doped layer covers the entire first surface of the silicon substrate, and the P-type doped layer is located on the second surface of the silicon substrate, or in other words, the P-type doped layer covers the entire second surface of the silicon substrate. The solar cell is a bifacial cell, and the types of solar cells are flexible and diverse. Of the first surface and the second surface here, one is the light-facing surface and the other is the backlight surface. For example, the silicon substrate may be N-type doped monocrystalline silicon, the N-type doped layer is an N-type doped polycrystalline silicon layer, the N-type doped polycrystalline silicon layer may be located on the backlight surface of the silicon substrate, the P-type doped layer is a P-type doped polycrystalline silicon layer, the P-type doped polycrystalline silicon layer is located on the light-facing surface of the silicon substrate, and a first tunneling oxide layer is also provided between the N-type doped layer and the silicon substrate. The solar cell may also include anti-reflection layers and other film layers, and other film layers included therein are not specifically limited.

[0054] Optionally, the P-type doped layer is a P-type polysilicon doped layer and / or a P-type doped microcrystalline silicon layer, and the P-type doped layer is flexible and diverse.

[0055] The present application is further explained below in conjunction with specific embodiments.

[0056] The solar cell is a back-contact solar cell. The silicon substrate is N-type doped monocrystalline silicon, the first surface of the silicon substrate is a backlight surface, the first surface includes a first conductive region and a second conductive region that are spaced apart, and the space between the first conductive region and the second conductive region is used to avoid leakage. The N-type doped layer is an N-type doped polysilicon layer, the P-type doped layer is a P-type doped polysilicon layer, the N-type doped polysilicon layer is located on the first conductive region, and the P-type doped polysilicon layer is located on the second conductive region. The doping elements in the N-type doped polysilicon layer include phosphorus, and the doping elements in the P-type doped layer include boron. A second tunneling oxide layer is also arranged between the P-type doped polysilicon layer and the silicon substrate, and a first tunneling oxide layer is also arranged between the N-type doped polysilicon layer and the silicon substrate. The square resistance of the N-type doped polysilicon layer is 24 ohms / square, and the square resistance of the P-type doped polysilicon layer is 59 ohms / square. The spacing between adjacent N-type collector grid lines is 0.9 mm, and the spacing between adjacent P-type collector grid lines is also 0.9 mm. Various cell performance parameters of the back-contact solar cell are measured, and the measurement results and the above-mentioned parameters of the back contact are shown in the table below.

[0057] Table of parameters of back contact solar cells

[0058]

[0059] In the above table, Eta is the efficiency of the back-contact solar cell, Voc is the open-circuit voltage of the back-contact solar cell, Jsc is the short-circuit current density of the back-contact solar cell, and FF is the fill factor of the back-contact solar cell. The efficiency of the back-contact solar cell has reached 26.5%. The main reason is that in the back-contact solar cell, through the coordination of the square resistance of the N-type doped polysilicon layer, the square resistance of the P-type doped polysilicon layer, the spacing between adjacent N-type collector grid lines, and the spacing between adjacent P-type collector grid lines, the parasitic absorption, the recombination current of the metal area and the lateral resistance in the back-contact solar cell are better balanced, so that the performance of the solar cell is better and the photoelectric conversion efficiency is higher.

[0060] The present invention also provides a photovoltaic module, comprising a plurality of any of the aforementioned solar cells. The photovoltaic module may also include other structures. For example, the photovoltaic module may also include a packaging film located on opposite sides of the solar cell, etc. There is no specific limitation on the other structures of the photovoltaic module. The photovoltaic module has the same or similar beneficial effects as any of the aforementioned solar cells, and will not be described again here to avoid repetition.

[0061] It should be noted that, for the method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the described order of actions, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0062] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0063] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0064] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A solar cell, characterized in that: include: A silicon substrate; the silicon substrate comprises a first surface and a second surface opposite to each other; the first surface is a backlight surface of the silicon substrate; An N-type doped layer is located on at least a portion of the first surface of the silicon substrate; the sheet resistance of the N-type doped layer is 14 ohms / square to 40 ohms / square; A plurality of N-type collector gate lines that are spaced apart and distributed in parallel are located on a side of the N-type doped layer away from the silicon substrate; and a spacing between adjacent N-type collector gate lines is less than 1.391 mm.

2. The solar cell according to claim 1, characterized in that The sheet resistance of the N-type doped layer is 14 ohms / square to 20 ohms / square, and the spacing between adjacent N-type collector grid lines is 1.019 mm to 1.296 mm; or, The square resistance of the N-type doped layer is greater than 20 ohms / square and less than or equal to 40 ohms / square, and the spacing between adjacent N-type collector grid lines is 0.839 mm to 0.977 mm.

3. The solar cell according to claim 1, characterized in that The thickness of the N-type doping layer is 100 nm to 140 nm.

4. The solar cell according to claim 1, characterized in that The doping concentration of the N-type doping layer is 3E20cm -3 to 7E20 cm -3 .

5. The solar cell according to any one of claims 1 to 4, characterized in that: Also includes: A P-type doped layer, wherein the sheet resistance of the P-type doped layer is 20 ohms / square to 166 ohms / square; A plurality of P-type collector gate lines which are spaced apart and distributed in parallel are located on a side of the P-type doped layer away from the silicon substrate.

6. The solar cell according to claim 5, characterized in that The N-type doped layer includes: an N-type doped polysilicon layer and / or an N-type doped microcrystalline silicon layer; The solar cell further comprises: a first tunneling oxide layer, located between the N-type doped layer and the silicon substrate; The spacing between adjacent P-type collector gate lines is less than or equal to the spacing between adjacent N-type collector gate lines.

7. The solar cell according to claim 6, characterized in that: The first surface includes: first conductive areas and second conductive areas that are spaced apart from each other; The N-type doped layer is located on the first conductive region; The P-type doped layer is located on the second conductive region; The solar cell further includes: a second tunneling oxide layer located between the P-type doping layer and the silicon substrate.

8. The solar cell according to claim 6, characterized in that: The N-type doping layer is located on the first surface of the silicon substrate, and the P-type doping layer is located on the second surface of the silicon substrate.

9. The solar cell according to claim 5, characterized in that: The P-type doped layer is a P-type polysilicon doped layer and / or a P-type doped microcrystalline silicon layer.

10. A photovoltaic module, characterized in that: include: A solar cell as claimed in any one of claims 1 to 9.

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