Method for preparing stacked transistor, stacked transistor and semiconductor device

Abstract

The present application provides a method for preparing a stacked transistor, a stacked transistor and a semiconductor device. The method includes: forming a first sacrificial layer and an active structure located on the first sacrificial layer on a semiconductor substrate; the active structure includes: a first active structure and a second active structure; depositing an oxide material on the semiconductor substrate to form a shallow trench isolation structure; the shallow trench isolation structure wraps the second active structure and the first sacrificial layer, and the first active structure is exposed outside the shallow trench isolation structure; based on the first active structure, forming a first transistor; flipping and removing the semiconductor substrate to expose the shallow trench isolation structure and the first sacrificial layer; removing the first sacrificial layer and forming a hard mask structure at the position of the removed first sacrificial layer; using the hard mask structure as a hard mask, thinning the shallow trench isolation structure so that the second active structure is exposed outside the shallow trench isolation structure; after removing the hard mask structure, forming a second transistor based on the second active structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip manufacturing, and in particular to a method for preparing a stacked transistor, a stacked transistor and a semiconductor device. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In some schemes for preparing stacked transistors, active regions of upper and lower layers of transistors of the same source are formed by etching, and stacked transistors are made on the front and back sides of the wafer by flipping the wafer. This can also be called a "self-aligned flip transistor" scheme. However, in the "self-aligned flip transistor" scheme, after flipping the wafer, it is necessary to etch a shallow trench isolation structure to expose the upper active region. During the etching process, the upper active region is often damaged, resulting in differences in device performance, so it is necessary to optimize the process scheme to ensure device performance. Summary of the invention

[0004] The present application provides a method for preparing a stacked transistor, a stacked transistor and a semiconductor device to optimize the process of exposing an upper active region of the stacked transistor and improve the performance of the upper transistor.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, comprising: forming a first sacrificial layer and an active structure located above the first sacrificial layer on a semiconductor substrate; wherein the active structure comprises: a first active structure and a second active structure; the first active structure and the second active structure are stacked along a first direction, and the first active structure is farther away from the first sacrificial layer than the second active structure; an oxide material is deposited on the semiconductor substrate to form a shallow trench isolation structure; the shallow trench isolation structure wraps the second active structure and the first sacrificial layer, and the first active structure is exposed outside the shallow trench isolation structure; based on the first active structure, a first transistor is formed; flipping and removing the semiconductor substrate to expose the shallow trench isolation structure and the first sacrificial layer; removing the first sacrificial layer and forming a hard mask structure at the position of the removed first sacrificial layer; using the hard mask structure as a hard mask, thinning the shallow trench isolation structure to expose the second active structure outside the shallow trench isolation structure; after removing the hard mask structure, a second transistor is formed based on the second active structure.

[0006] In some possible embodiments, the first sacrificial layer is removed and a hard mask structure is formed at the location of the removed first sacrificial layer, including: removing the first sacrificial layer to form a groove; the bottom of the groove is formed by a second active structure; and depositing a hard mask material in the groove to form a hard mask structure.

[0007] In some possible embodiments, a hard mask material is deposited in the groove to form a hard mask structure, including: depositing a hard mask material on the surface of the shallow trench isolation structure and the bottom of the groove to form a first hard mask; thinning the first hard mask through a chemical mechanized planarization process until the shallow trench isolation structure is exposed to form a hard mask structure.

[0008] In some possible embodiments, a hard mask material is deposited in the groove to form a hard mask structure, including: depositing a hard mask material on the surface of the shallow trench isolation structure and the bottom of the groove to form a second hard mask; thinning the second hard mask through a chemical mechanized planarization process until the top surface of the second hard mask is at the same height to form a third hard mask; and etching the third hard mask using a dry etching process until the shallow trench isolation structure is exposed to form a hard mask structure.

[0009] In some possible embodiments, a first sacrificial layer and an active structure located above the first sacrificial layer are formed on a semiconductor substrate, including: forming a first material layer and a second material layer on the semiconductor substrate; the first material layer is away from the semiconductor substrate relative to the second material layer; using the same etching process to etch the first material layer to form an initial active structure and to etch the second material layer to form an initial first sacrificial layer; using a fin cutting process to remove the initial active structure located in the two side areas of the stacked transistor to form an active structure, and using a fin cutting process to remove the initial first sacrificial layer located in the two side areas of the stacked transistor to form a first sacrificial layer.

[0010] In some possible embodiments, the first material layer is a single-layer structure formed by depositing the first material; or, the first material layer is a stacked structure formed by stacking at least two material layers; the stacking direction of the stacked structure is a first direction; and the second material layer is a single-layer structure formed by depositing the second material.

[0011] In some possible implementations, the first material and the second material are different; or, the first material and the second material are the same.

[0012] In some possible embodiments, at least two material layers include: a first semiconductor layer, an oxide layer, and a second semiconductor layer; the oxide layer is located between the first semiconductor layer and the second semiconductor layer; the first semiconductor layer is away from the second material layer relative to the second semiconductor layer; the material forming the oxide layer is different from the material forming the first semiconductor layer or the second semiconductor layer; etching the first material layer to form an initial active structure includes: etching the first semiconductor layer, the oxide layer, and the second semiconductor layer to form an initial first active structure, an initial insulating structure, and an initial second active structure, respectively; using a fin cutting process to remove the initial active structure located in the two side areas of the stacked transistor to form an active structure, including: using a fin cutting process to remove the initial first active structure, the initial insulating structure, and the initial second active structure located in the two side areas of the stacked transistor to form a first active structure, an insulating structure, and a second active structure, respectively; the insulating structure is used to electrically isolate the first active structure from the second active structure.

[0013] In some possible implementations, at least two material layers include: a first semiconductor layer, a second sacrificial layer, and a second semiconductor layer; the second sacrificial layer is located between the first semiconductor layer and the second semiconductor layer; the first semiconductor layer is far away from the second material layer relative to the second semiconductor layer; the material forming the second sacrificial layer is different from the material forming the first semiconductor layer or the second semiconductor layer; etching the first material layer to form an initial active structure includes: etching the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer to form an initial first active structure, an initial third sacrificial layer, and an initial second active structure, respectively; using a fin cutting process to remove the initial active structure located in the two side regions of the stacked transistor to form an active structure, including: using a fin cutting process to remove the initial first active structure, the initial third sacrificial layer, and the initial second active structure located in the two side regions of the stacked transistor to form a first active structure, a third sacrificial layer, and a second active structure, respectively; based on the first active structure, forming a first transistor, including: depositing a dummy gate material in the gate region of the stacked transistor to form a first dummy gate structure; removing the third sacrificial layer, and depositing a dielectric material at the position of the removed third sacrificial layer to form a dielectric structure; the dielectric structure is used to electrically isolate the first active structure and the second active structure.

[0014] In some possible embodiments, the first semiconductor layer and the second semiconductor layer are a single-layer structure or a multi-layer structure; the material forming the first semiconductor layer is the same as the material forming the second semiconductor layer; or, the material forming the first semiconductor layer is different from the material forming the second semiconductor layer.

[0015] In some possible embodiments, the second material is a first silicon germanium material; the second semiconductor layer is a multi-layer structure, the multi-layer structure including: a bottom material layer; the bottom material layer is adjacent to the second material layer, and the bottom material layer is formed by depositing the second silicon germanium material; the germanium content in the first silicon germanium material is different from the germanium content in the second silicon germanium material.

[0016] In a second aspect, an embodiment of the present application provides a stacked transistor, comprising: a first transistor; a second transistor stacked along a first direction with the first transistor; a first active structure of the first transistor and a second active structure of the second transistor forming an active structure; a first gate structure of the first transistor and a second gate structure of the second transistor being arranged back to back.

[0017] In some possible implementations, the first transistor and the second transistor are any of the following: a planar transistor, a fin field effect transistor, a gate-all-around nanosheet transistor, and a stacked forkplate transistor.

[0018] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a stacked transistor as described in the above embodiment.

[0019] In the embodiment of the present application, by etching to form a first sacrificial layer and an active structure with a certain depth, the active areas of the upper and lower layers of transistors can be self-aligned. Subsequently, a first transistor can be prepared based on the first active structure in the active structure, and the substrate structure can be etched to expose the first sacrificial layer after flipping, so that it is convenient to remove the first sacrificial layer and fill the hard mask material to form a hard mask structure; then, in the process of thinning the shallow trench isolation structure, the hard mask structure is used to protect the lower half of the active area to obtain an undamaged second active structure. Finally, a second transistor is prepared based on the undamaged second active structure to improve the performance of the second transistor.

[0020] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0022] Figure 1 is a top view of a stacked transistor according to an embodiment of the present application;

[0023] Figures 2 to 3 is a schematic diagram of a preparation process of a first stacked transistor according to an embodiment of the present application;

[0024] Figure 4A schematic diagram of an implementation process of a method for preparing a stacked transistor according to an embodiment of the present application;

[0025] Figures 5 to 18 is a schematic diagram of a preparation process of a second stacked transistor according to an embodiment of the present application;

[0026] Figures 19 to 28 is a schematic diagram of a preparation process of a third type of stacked transistor according to an embodiment of the present application;

[0027] Figure 29 to Figure 30 is a schematic diagram of a fourth method for preparing a stacked transistor according to an embodiment of the present application;

[0028] Fig.31 It is a schematic diagram of a stacked transistor according to an embodiment of the present application.

[0029] Fig.32 It is a schematic diagram of another stacked transistor according to an embodiment of the present application.

[0030] Figures 10, stacked transistor; 11, first transistor; 12, second transistor; 111, first pseudo gate sidewall; 112, first source-drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source-drain metal; 116, first metal interconnect layer; 121, second pseudo gate sidewall; 122, second source-drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source-drain metal; 126, second Metal interconnect layer; 20, semiconductor substrate; 21, first sacrificial layer; 22, active structure; 221, first active structure; 222, second active structure; 23, first material layer; 24, second material layer; 25, initial shallow trench isolation structure; 26, shallow trench isolation structure; 27, hard mask structure; 28, insulating layer; 29, carrier wafer; 30, groove; 31, first hard mask; 32, third hard mask; 33, buried oxide layer; 34, intermediate dielectric isolation layer. DETAILED DESCRIPTION

[0031] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0032] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0033] In one embodiment, there are two schemes for manufacturing processes of stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.

[0034] The sequential solution is based on wafer bonding and is processed layer by layer. However, thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. The main challenges faced by the sequential stacking transistor process include: (1) preparation of high-quality upper transistor active layer; (2) thinning and defect control of the upper bonded wafer; (3) alignment errors between the upper and lower transistors, which requires extremely high lithography accuracy.

[0035] In the monolithic stacked transistor technology, wafer bonding technology is not used. Instead, N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) are made on the same substrate, which also determines that the transistors on the same layer must be of the same type, that is, NFET or PFET. In addition, the upper and lower layers of transistors are strictly in the same plane space, and there is no alignment deviation. Obviously, the advantage of monolithic stacked transistors is higher integration density. However, its disadvantages are also obvious: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and it must rely on two layers of transistors to form a basic CMOS circuit, which has poor design flexibility.

[0036] In order to solve the technical problems of the above two solutions, a "self-aligned flip transistor" solution is proposed. This "self-aligned flip transistor" solution forms the active area of ​​the upper and lower layers of the same source transistors by etching, and realizes the production of stacked transistors on the front and back of the wafer by flipping the wafer to overcome the shortcomings of the above two solutions. However, the preparation process of the self-aligned flip transistor still has room for optimization to further improve the performance of the stacked transistor.

[0037] Figure 1 FIG. 1 is a top view of a stacked transistor according to an embodiment of the present application, see Figure 1As shown, the top view only shows the fin structure, gate structure and source-drain structure of the stacked transistor 10. It is understandable that, based on the different types of stacked transistors, the fin structure can also be a columnar structure or a block structure, which is not specifically limited in the embodiments of the present application.

[0038] Figures 2 to 3 FIG. 1 is a schematic diagram of a manufacturing process of a first stacked transistor according to an embodiment of the present application. For ease of understanding, Figures 2 to 3 (a) shows the Figure 1 The cross-sectional view along the dashed line AA'. Figures 2 to 3 (b) shows the Figure 1 The cross-sectional view along the dotted line BB', Figures 2 to 3 (c) shows the Figure 1 Cross-sectional view along the dotted line CC'. Figures 2 to 3 As shown, after the self-aligned flip-chip transistor is flipped, the substrate structure can be removed to expose the second active structure 222 and the shallow trench isolation structure 26. Among them, the height of the second active structure 222 is h1. Subsequently, it is necessary to etch the shallow trench isolation structure to complete the exposure of the second active structure 222. During the etching process, the second active structure 222 is often damaged by the etching, so that the height of the second active structure 222 changes to h2. Here, h2 is less than h1. It can be seen that the current process will damage the second active structure 222, resulting in a difference between the actual performance of the device and the designed performance of the device, so it is necessary to optimize the process scheme to ensure the device performance.

[0039] It can be seen that there are areas that need to be improved in the preparation process of self-aligned flip-chip transistors. In order to solve the above technical problems, the embodiment of the present application provides a method for preparing a stacked transistor to optimize the process of exposing the upper active region of the stacked transistor and improve the performance of the upper transistor.

[0040] Figure 4 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a stacked transistor according to an embodiment of the present application, see Figure 4 As shown, the method for preparing a stacked transistor may include:

[0041] S401: forming a first sacrificial layer and an active structure located on the first sacrificial layer on a semiconductor substrate; wherein the active structure comprises: a first active structure and a second active structure; the first active structure and the second active structure are stacked along a first direction, and the first active structure is farther away from the first sacrificial layer than the second active structure;

[0042] S402: depositing an oxide material on the semiconductor substrate to form a shallow trench isolation structure; the shallow trench isolation structure encapsulates the second active structure and the first sacrificial layer, and the first active structure is exposed outside the shallow trench isolation structure;

[0043] S403: forming a first transistor based on the first active structure;

[0044] S404: flipping the wafer and removing the semiconductor substrate to expose the shallow trench isolation structure and the first sacrificial layer;

[0045] S405: removing the first sacrificial layer, and forming a hard mask structure at the position of the removed first sacrificial layer;

[0046] S406: using the hard mask structure as a hard mask, thinning the shallow trench isolation structure so that the second active structure is exposed outside the shallow trench isolation structure;

[0047] S407: After removing the hard mask structure, a second transistor is formed based on the second active structure.

[0048] It should be noted that Figure 4 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 4 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0049] It is understandable that by forming a hard mask structure on top of the second active structure after flipping the wafer, the second active structure can be protected. In this way, when the process of thinning the shallow trench isolation structure is started, the second active structure will not be damaged, thereby ensuring the performance of the second transistor.

[0050] Figures 5 to 18 FIG. 1 is a schematic diagram of a preparation process of a second stacked transistor according to an embodiment of the present application. For ease of understanding, Figures 5 to 18 (a) shows the Figure 1 The cross-sectional view along the dashed line AA'. Figures 5 to 18 (b) shows the Figure 1 The cross-sectional view along the dotted line BB', Figures 5 to 18 (c) shows the Figure 1 The cross-sectional view along the dotted line CC' Figures 1 to 18 The method for preparing the stacked transistor provided in the embodiment of the present application and the prepared stacked transistor are exemplarily described.

[0051] In step S401 : a first sacrificial layer 21 and an active structure 22 located on the first sacrificial layer 21 are formed on a semiconductor substrate 20 .

[0052] It is understandable that material layer deposition, epitaxial growth, photolithography and other processes may be performed on the semiconductor substrate 20 to form a first sacrificial layer 21 and an active structure 22 located on the first sacrificial layer 21 on the semiconductor substrate 20 .

[0053] The active structure 22 includes a first active structure 221 and a second active structure 222. The first active structure 221 and the second active structure 222 are stacked along a first direction (a direction perpendicular to the semiconductor substrate 20), and the first active structure 221 is farther away from the first sacrificial layer 21 than the second active structure 222.

[0054] It can be understood that the first active structure 221 is used to form the active area of ​​the first transistor 11 (located in the lower layer) of the stacked transistor 10; the second active structure 222 stacked along the first direction with the first active structure 221 is used to form the active area of ​​the second transistor 12 (located in the upper layer) of the stacked transistor 10.

[0055] It should be noted that the first sacrificial layer 21 is located at the bottom of the active structure 22 . After flipping, the first sacrificial layer 21 may be located at the top of the active structure 22 .

[0056] In one embodiment, the step S401 forms a first sacrificial layer 21 and an active structure 22 located on the first sacrificial layer 21 on the semiconductor substrate 20, including: forming a first material layer 23 and a second material layer 24 on the semiconductor substrate 20; the first material layer 23 is away from the semiconductor substrate 20 relative to the second material layer 24. Subsequently, the first material layer 23 is etched to form an initial active structure and the second material layer 24 is etched to form an initial first sacrificial layer using the same etching process. Subsequently, the initial active structure located in the two side regions of the stacked transistor 10 is removed using a fin cutting process to form an active structure 22, and the initial first sacrificial layer located in the two side regions of the stacked transistor 10 is removed using a fin cutting process to form a first sacrificial layer 21.

[0057] The two side regions of the stacked transistor 10 refer to regions located on two sides of the stacked transistor along the second direction (the extension direction or the length direction of the fin structure).

[0058] It can be understood that by forming the material layer required for the active structure 22 and the first sacrificial layer 21 on the semiconductor substrate 20, and etching the material layer using the standard semiconductor manufacturing process, an initial active structure (which can be a fin structure, a columnar structure or a block structure) and an initial first sacrificial layer can be formed. Subsequently, a fin cutting process is performed to cut off the active structure located adjacent to the two transistors to isolate the active areas of the adjacent transistor units. In addition, the active structure 22 and the first sacrificial layer 21 required for the subsequent manufacturing process are obtained.

[0059] It is understandable that when the active structure 22 (including the first active structure 221 and the second active structure 222) and the first sacrificial layer 21 are formed by photolithography, a larger etching depth can be used. For example, the height of the active structure 22 obtained by etching can be greater than 100 nm. It should be noted that the height of the active structure 22 can be set according to actual conditions, and the embodiment of the present application does not specifically limit this.

[0060] It should be noted that the steps of the photolithography process may include: depositing a photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, etching to remove a material layer corresponding to the portion of the photoresist material, etc.

[0061] Here, when the type of the stacked transistor 10 is different, the shape of the active structure 22 may be different.

[0062] In some possible implementations, the first material layer 23 away from the semiconductor substrate 20 is used to form an active structure 22. Based on the structural composition of different types of active structures 22, it can be known that the first material layer 23 is a single-layer structure formed by depositing the first material; or, the first material layer 23 is a stacked structure formed by stacking at least two material layers.

[0063] Wherein, the stacking direction of the stacking structure is a first direction.

[0064] It can be understood that when the types of stacked transistors 10 are different, the structural composition of the active structure 22 in the transistor is different, so that the structure of the first material layer 23 forming the active structure 22 may also be different.

[0065] In one embodiment, when the stacked transistor 10 is a fin field effect transistor, the active structure 22 may constitute a fin structure. When the stacked transistor 10 is a planar transistor, the active structure 22 may constitute a block structure. Here, the fin structure and the block structure may be a single-layer structure formed by depositing the same first material, or a stacked structure formed by stacking at least two material layers.

[0066] In one embodiment, when the stacked transistor 10 is a gate-all-around nanosheet (GAA Nanosheet), the active structure 22 may constitute a columnar structure. Here, the columnar structure may be a stacked structure formed by stacking at least two material layers. For example, the first active structure 221 and the second active structure 222 may be formed by alternately deposited silicon layers and silicon germanium layers.

[0067] It should be noted that the structure of the first material layer 23 is designed according to the structures of the first active structure 221 and the second active structure 222. The structures of the first active structure 221 and the second active structure 222 can be set according to the actual needs of the stacked transistor 10, and the embodiment of the present application does not make specific limitations on this.

[0068] In some embodiments, the first transistor 11 and the second transistor 12 may be transistors of the same type. For example, the first transistor 11 and the second transistor 12 may both be fin field effect transistors.

[0069] In some embodiments, the first transistor 11 and the second transistor 12 may be transistors of different types. For example, one transistor is a fin field effect transistor and the other is a gate-all-around transistor; or, one transistor is a fin field effect transistor and the other is a planar transistor; or, one transistor is a gate-all-around transistor and the other is a planar transistor.

[0070] In some embodiments, when the first material layer 23 is a single-layer structure formed by depositing the first material, the first active structure 221 and the second active structure 222 are formed of the same material. For example, the first active structure 221 and the second active structure 222 are formed of silicon. At this time, in order to prevent a conductive current path from being formed between the active regions of the first transistor 11 and the second transistor 12 that are subsequently formed, the first active structure 221 and the second active structure 222 need to be electrically isolated.

[0071] Here, the process of isolating the first active structure 221 and the second active structure 222 can be set according to actual needs, and is not specifically limited in comparison with the embodiment of the present application.

[0072] Exemplarily, ion implantation may be performed at the junction of the first active structure 221 and the second active structure 222 to electrically isolate the first active structure 221 and the second active structure 222. The ions implanted include P-type ions, N-type ions, or oxygen ions. The P-type ions include one or more of boron ions, gallium ions, and indium ions; and the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.

[0073] In some possible implementations, the second material layer 24 close to the semiconductor substrate 20 is used to form the first sacrificial layer 21. The second material layer 24 may be a single-layer structure formed by depositing the second material.

[0074] It is understandable that the first sacrificial layer 21 may be a single-layer structure formed by depositing the second material. Then, only the etching process of one material (ie, the second material) needs to be considered to remove the first sacrificial layer 21, thereby reducing the process difficulty.

[0075] Exemplarily, the second material layer 24 may be a single-layer structure formed of a silicon material; or, the second material layer 24 may be a single-layer structure formed of a silicon germanium material.

[0076] In some possible implementations, when both the first material layer 23 and the second material layer 24 are single-layer structures, the first material layer 23 is formed by depositing the first material, and the second material layer 24 is formed by depositing the second material. The first material may be different from the second material, for example, the first material may be silicon, and the second material may be silicon germanium, thereby utilizing the different etching selectivity between silicon and silicon germanium to remove the first sacrificial layer 21 formed of silicon germanium in a subsequent process. Alternatively, the first material may be the same as the second material, for example, the first material may be silicon, and the second material may also be silicon, thereby controlling the etching time to achieve the removal of the first sacrificial layer 21 formed of silicon in a subsequent process.

[0077] It is understood that when the first material and the second material are different, the second material layer 24 can be formed by depositing or epitaxially growing the second material on the semiconductor substrate 20; then, the first material layer 23 is formed by depositing or epitaxially growing the first material on the second material layer 24. Then, the second material layer 24 is etched to form the first sacrificial layer 21, and the first material layer 23 is etched to form the active structure 22 located on the first sacrificial layer 21.

[0078] It is understood that when the first material and the second material are the same, the first material layer 23 and the second material layer 24 can be formed simultaneously by depositing or epitaxially growing the first material on the semiconductor substrate 20. The first material layer 23 and the second material layer 24 are then etched to form the first sacrificial layer 21 and the active structure 22 located on the first sacrificial layer 21.

[0079] It should be noted that, in the embodiment of the present application, a deeper etching depth can also be directly used to etch the silicon wafer to form the first sacrificial layer 21 and the active structure 22 at one time. In this case, the first sacrificial layer 21 and the active structure 22 are both formed of silicon.

[0080] For example, Figures 5 and 6 As shown, etching the silicon wafer can obtain the first sacrificial layer 21 and the active structure 22. At the same time, Figure 6 Also shown is a hard mask structure 27 disposed on top of the active structure 22. The hard mask structure 27 is used to protect the first active structure 221 from damage during the subsequent exposure of the first active structure 221.

[0081] In some possible implementations, the first material layer 23 may be formed by stacking at least two material layers. The at least two material layers include: a first semiconductor layer, an oxide layer, and a second semiconductor layer. The oxide layer is located between the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer is away from the second material layer relative to the second semiconductor layer. That is, the second semiconductor layer is located on the second material layer, the oxide layer is located on the second semiconductor layer, and the first semiconductor layer is located on the oxide layer.

[0082] Then, the first material layer 23 is etched to form an initial active structure, including: etching the first semiconductor layer, the oxide layer and the second semiconductor layer to respectively form an initial first active structure, an initial insulating structure and an initial second active structure; subsequently, a fin cutting process is used to remove the initial first active structure, the initial insulating structure and the initial second active structure located in the two side areas of the stacked transistor 10 to respectively form a first active structure 221, an insulating structure and a second active structure 222.

[0083] It is understood that the first semiconductor layer away from the second material layer 24 can be used to form the first active structure 221, and the second semiconductor layer close to the second sacrificial layer can be used to form the second active structure 222. The oxide layer between the first semiconductor layer and the second semiconductor layer can be used to form an insulating structure. The insulating structure can electrically isolate the first active structure 221 and the second active structure 222.

[0084] That is, the first active structure 221, the insulating structure and the second active structure 222 can be formed by etching, so that no other process steps are required to form the isolation structure between the first active structure 221 and the second active structure 222, which greatly reduces the complexity of the preparation process.

[0085] The material for forming the oxide layer can be selected according to actual needs, and the application embodiment does not specifically limit this. Exemplarily, the material for forming the oxide layer can be an oxide material.

[0086] It should be noted that, in the embodiment of the present application, a silicon-on-insulator (SOI) substrate may also be directly obtained, and then the SOI substrate may be etched at a deeper etching depth to form the first active structure 221, the insulating structure, and the second active structure 222. At this time, the buried oxide layer in the SOI substrate is equivalent to the oxide layer, which is used to form the insulating structure; the material layer above the buried oxide layer is equivalent to the first semiconductor layer, which is used to form the first active structure 221; the material layer below the buried oxide layer is equivalent to the second semiconductor layer and the second material layer, which are used to form the second active structure 222 and the first sacrificial layer 21.

[0087] In some possible implementations, a second sacrificial layer may be used to replace the oxide layer in the above embodiment. That is, at least two material layers include: a first semiconductor layer, a second sacrificial layer, and a second semiconductor layer. The second sacrificial layer is located between the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer is away from the second material layer relative to the second semiconductor layer. That is, the second semiconductor layer is located on the second material layer, the second sacrificial layer is located on the second semiconductor layer, and the first semiconductor layer is located on the second sacrificial layer.

[0088] Then, the first material layer 23 is etched to form an initial active structure, including: etching the first semiconductor layer, the second sacrificial layer and the second semiconductor layer to respectively form an initial first active structure, an initial third sacrificial layer and an initial second active structure; subsequently, a fin cutting process is used to remove the initial first active structure, the initial third sacrificial layer and the initial second active structure located in the two side areas of the stacked transistor 10 to respectively form a first active structure 221, a third sacrificial layer and a second active structure 222.

[0089] It can be understood that the first semiconductor layer away from the second material layer 24 can be used to form the first active structure 221, and the second semiconductor layer close to the second sacrificial layer can be used to form the second active structure 222. The second sacrificial layer located between the first semiconductor layer and the second semiconductor layer can be used to form a third sacrificial layer. The third sacrificial layer is used to form a dielectric structure in a subsequent step. The dielectric structure can electrically isolate the first active structure 221 and the second active structure 222.

[0090] That is, the first active structure 221, the third sacrificial layer and the second active structure 222 can be formed by etching, thereby providing a new solution for forming an isolation structure between the first active structure 221 and the second active structure 222 to meet the preparation requirements under different process conditions.

[0091] The material forming the third sacrificial layer can be selected according to actual needs, and the application embodiment does not specifically limit this. Exemplarily, the material forming the third sacrificial layer can be different from the material forming the active structure 22, so as to facilitate the removal of the third sacrificial layer in subsequent processes.

[0092] In some embodiments, the first semiconductor layer and the second semiconductor layer are a single-layer structure or a multi-layer structure according to the structures of the first active structure 221 and the second active structure 222 .

[0093] For example, if the first active structure is a fin-shaped structure, the first semiconductor layer may be a single-layer structure; if the second active structure is a columnar structure, the second semiconductor layer may be a multi-layer structure.

[0094] Here, the multilayer structure refers to a structure formed by stacking at least two material layers, for example, a multilayer structure formed by alternately stacking silicon and silicon germanium.

[0095] In some embodiments, the material forming the first semiconductor layer is the same as the material forming the second semiconductor layer; or, the material forming the first semiconductor layer is different from the material forming the second semiconductor layer.

[0096] It is understandable that, based on the performance setting of the stacked transistor 10 , the materials of the first semiconductor layer and the second semiconductor layer can be set according to actual needs, and the embodiments of the present application do not specifically limit this.

[0097] In some embodiments, the second material forming the second material layer may be a first silicon germanium material. The second semiconductor layer is a multilayer structure. The multilayer structure at least includes: a bottom material layer adjacent to the second material layer. The bottom material layer may be formed by depositing the second silicon germanium material.

[0098] Here, the germanium content in the first silicon germanium material is different from the germanium content in the second silicon germanium material.

[0099] It is understandable that when the second transistor 12 in the stacked transistor 10 is a full-surround gate transistor, the second active structure 222 of the second transistor 12 can be formed by alternating stacking of silicon and silicon germanium. When the bottom material layer of the second active structure 22, that is, a material layer adjacent to the second semiconductor layer and the second material layer, is a second silicon germanium material, the second material should be a first silicon germanium material. The germanium content in the first silicon germanium material is different from the germanium content in the second silicon germanium material, so that the first sacrificial layer 21 and the second semiconductor layer can be distinguished.

[0100] In step S402 : an oxide material is deposited on the semiconductor substrate 20 with the active structure 22 formed thereon to form a shallow trench isolation structure 26 .

[0101] Here, the shallow trench isolation structure 26 wraps the second active structure 222 and the first sacrificial layer 21 , and the first active structure 221 is exposed outside the shallow trench isolation structure 26 .

[0102] It is understood that an initial shallow trench isolation (STI) structure 25 may be formed on the semiconductor substrate 20 by depositing an oxide material. The height of the initial shallow trench isolation structure 25 may be equal to the height of the active structure 22. Figure 7 It can also be greater than the height of the active structure 22, such as Figure 8 Subsequently, the initial shallow trench isolation structure 25 is etched to expose the first active structure 221, and a shallow trench isolation structure 26 is formed to wrap the second active structure 222 and the first sacrificial layer 21, so as to obtain Fig. 9 The structure shown.

[0103] The oxide used to form the shallow trench isolation structure 26 may be a silicon-based oxide (SiOx, where x is the number of oxygen atoms), such as silicon dioxide (SiO2).

[0104] It should be noted that the height in the embodiment of the present application refers to: the distance between the highest point and the lowest point of the stacked transistor 10 in the first direction.

[0105] The etching process mentioned in the embodiments of the present application may include any one of the following: dry etching, wet etching, reactive ion etching and chemical oxide removal process, which is not limited in the embodiments of the present application.

[0106] In step S403 , a first transistor 11 is formed based on the first active structure 221 .

[0107] It is understandable that the first transistor 11 in the stacked transistor 10 can be formed by using a semiconductor manufacturing process based on the exposed first active structure 221. The first transistor 11 includes: a first dummy gate spacer 111, a first source-drain structure 112, a first interlayer dielectric layer 113, a first gate structure 114, and a first source-drain metal 115.

[0108] In some embodiments, see Fig.10 As shown, based on the first active structure 221, a first transistor 11 is formed, including: forming a plurality of first dummy gate structures spaced apart along the second direction on the first active structure 221; forming a first dummy gate sidewall 111 covering the sidewalls of the plurality of second dummy gate structures based on the plurality of first dummy gate structures. Using the first dummy gate sidewall 111 as a hard mask, the first active structure 221 in the source and drain region of the stacked transistor 10 is etched to form a first source and drain groove; and a first source and drain structure 112 is epitaxially grown in the first source and drain groove. After forming the first source and drain structure 112, an insulating material may be deposited on the first source and drain structure 112 to form a first interlayer dielectric layer 113. Subsequently, the first dummy gate structure may be removed to form a first gate structure 114, and a first source and drain metal 115 may be formed on the first source and drain structure 112.

[0109] It can be understood that the source and drain regions of the stacked transistor 10 may be regions for forming source and drain structures, and the gate region may be a region for forming a gate structure.

[0110] In one embodiment, the material forming the first dummy gate structure may be polysilicon, amorphous silicon, etc.; the material forming the first dummy gate spacer 111 may be silicon oxide, silicon nitride, etc. In one example, the first dummy gate spacer 111 may have a single-layer structure, and the entire structure may be made of the same material (e.g., porous silicon carbon oxyhydride (SiCOH)).

[0111] In one embodiment, when a third sacrificial layer is formed between the active structure 22 and the semiconductor substrate 20 , after forming the first dummy gate structure, the third sacrificial layer may be removed, and a dielectric material may be deposited at the location of the removed third sacrificial layer to form a dielectric structure.

[0112] Here, the dielectric material can be selected according to actual needs, and the embodiments of the present application do not make any specific limitations on this.

[0113] In one embodiment, a fin recess may be formed on the first active structure 221 by using a fin recess etching process.

[0114] In one embodiment, strained materials such as silicon germanium or silicon carbide may be formed in the first source / drain grooves by selective epitaxial growth to fill the first source / drain grooves, and then the first source / drain structure 112 may be formed on the strained material by a heavy doping process.

[0115] In one embodiment, after removing the plurality of first dummy gate structures, a metal material may be deposited at the locations of the removed first dummy gate structures, and the deposited metal material is used to form the first gate structure 114 .

[0116] The first gate structure 114 at least includes: a first gate dielectric layer and a first gate electrode layer. The materials of the gate dielectric layer and the gate electrode layer can be set according to actual needs, and the embodiment of the present application does not specifically limit this.

[0117] Exemplarily, the first gate dielectric layer may be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the first transistor 11. The first gate electrode layer may be composed of multiple layers of electrode materials, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0118] In one example, the first gate dielectric layer may include: a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0119] In one embodiment, the first interlayer dielectric layer 113 may be etched to expose the first source-drain structure 112 , and a metal material may be deposited on the first source-drain structure 112 to form a first source-drain metal 115 .

[0120] In one embodiment, after forming the first gate structure 114 and the first source-drain metal 115, a first metal interconnect layer 116 may be formed on the first source-drain metal 115 and the first gate structure 114 by using a standard back-end process of semiconductor manufacturing (such as deposition of dielectric between interconnect lines, formation of metal lines, formation of lead pads, etc.). Fig.10 shown.

[0121] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, etc. are similar to the first source-drain groove, where "source-drain" is an abbreviation for "source electrode and / or drain electrode".

[0122] It should be noted that the above one or more embodiments only illustrate the preparation process of a transistor type of a fin field effect transistor. Those skilled in the art should know that when the transistor types of the first transistor 11 and the second transistor 12 are other types, the embodiments of the present application also include standard preparation processes corresponding to other types of transistors. For the sake of brevity of the specification, it will not be repeated here.

[0123] In step S404 , the semiconductor substrate 20 is flipped and removed to expose the shallow trench isolation structure 26 and the first sacrificial layer 21 .

[0124] It is understood that an insulating material (such as silicon oxide) may be deposited on the first transistor 11 to form an insulating layer 28, and the insulating layer 28 may be bonded to the carrier wafer 29. Subsequently, the first transistor 11 may be flipped so that the first transistor 11 is located at the bottom, and the semiconductor substrate 20 and the first sacrificial layer 21 connected to the semiconductor substrate 20 are located at the top, so that the first sacrificial layer 21 is used to form a hard mask structure 27, such as Fig.11 shown.

[0125] It should be noted that the carrier wafer 29 bonded to the first transistor 11 can provide physical support for the flipped first transistor 11 after flipping, effectively preventing the first transistor 11 from being broken by external force during the preparation of the second transistor 12.

[0126] See also Fig.12 As shown, after flipping, the semiconductor substrate 20 may be removed by polishing or chemical mechanical planarization to expose the shallow trench isolation structure 26 and the first sacrificial layer 21 .

[0127] In step S405, Fig.15 As shown, the first sacrificial layer 21 is removed, and a hard mask structure 27 is formed at the location of the removed first sacrificial layer 21 .

[0128] It is understandable that an etching process can be used to remove part or all of the first sacrificial layer 21, and a hard mask structure 27 can be formed at the location of the removed first sacrificial layer 21, so that a hard mask structure 27 can be provided above the second active structure 222, and the hard mask structure 27 protects the second active structure 222 from damage.

[0129] In one embodiment, the first sacrificial layer 21 is removed in step S405, and a hard mask structure 27 is formed at the position of the removed first sacrificial layer 21, including: removing the first sacrificial layer 21 to form a groove 30. The bottom of the groove 30 is formed by the second active structure 222, and the groove wall of the groove 30 is formed by the shallow trench isolation structure 26; then, a hard mask material is deposited in the groove 30 to form the hard mask structure 27.

[0130] It is understandable that the first sacrificial layer 21 may be removed by an etching process to expose the second active structure 222, and the second active structure 222 and the shallow trench isolation structure 26 may be surrounded to form a groove 30, such as: Fig.13 Subsequently, a hard mask material may be deposited in the recess 30 to form a hard mask structure 27 .

[0131] In some embodiments, a hard mask material is deposited in the groove 30 to form a hard mask structure 27, including: depositing a hard mask material on the surface of the shallow trench isolation structure 26 and the bottom of the groove 30 to form a first hard mask 31, such as Fig.14 Subsequently, the first hard mask 31 is thinned by a chemical mechanical planarization process until the shallow trench isolation structure 26 is exposed to form a hard mask structure 27, such as Fig.15 shown.

[0132] It is understandable that the method of depositing the hard mask material on the surface of the shallow trench isolation structure 26 and the bottom of the groove 30 is easier to implement and reduces the difficulty of preparation. At the same time, the hard mask structure 27 can be obtained by thinning the first hard mask 31 through a chemical mechanical flattening process, which effectively reduces the complexity of the process.

[0133] In some embodiments, a hard mask material is deposited in the groove 30 to form a hard mask structure 27, including: depositing a hard mask material on the surface of the shallow trench isolation structure and the bottom of the groove to form a second hard mask (not shown, refer to Fig.14 Subsequently, the second hard mask is thinned by a chemical mechanical planarization process until the top surface of the second hard mask is at the same height to form a third hard mask 32, such as Fig.16 Using a dry etching process to etch the third hard mask 32 until the shallow trench isolation structure 26 is exposed to form a hard mask structure 27, such as to obtain Fig.15The structure shown.

[0134] It can be understood that by first controlling the surface of the hard mask to be at the same height and then using a dry etching process to etch to form the hard mask structure 27, the consistency of the etching depth can be improved, thereby controlling the consistency of multiple hard mask structures, which is beneficial to the preparation of the stacked transistor 10.

[0135] In step S406, if Fig.17 As shown, the hard mask structure 27 is used as a hard mask to thin the shallow trench isolation structure 26 so that the second active structure 222 is exposed outside the shallow trench isolation structure 26 .

[0136] It can be understood that when the shallow trench isolation structure 26 is thinned, the hard mask structure 27 can protect the second active structure 222 and effectively prevent the second active structure 222 from being damaged.

[0137] In step S407 , after removing the hard mask structure 27 , a second transistor 12 may be formed based on the second active structure 22 in step S203 .

[0138] It is understood that after removing the hard mask structure 27, the top of the second active structure 222 can be exposed; then, based on the exposed second active structure 222, a semiconductor manufacturing process can be used to form the second transistor 12 in the stacked transistor 10, such as Fig.18 The second transistor 12 includes: a second dummy gate spacer 121 , a second source-drain structure 122 , a second interlayer dielectric layer 123 , a second gate structure 124 , and a second source-drain metal 125 . The second transistor 12 also includes: a second metal interconnect layer 126 .

[0139] It is understandable that the preparation process of forming the second transistor 12 in step S407 can refer to the preparation process of forming the first transistor 11 in step S403, and for the sake of brevity of the specification, it will not be repeated here.

[0140] At this point, the preparation of the stacked transistor 10 is completed.

[0141] It should be noted that one or more of the above embodiments take the first sacrificial layer and the active structure as an example of the same material to illustrate a method for preparing the stacked transistor 10. In this method, when etching to form the active structure, the etching depth is slightly deeper than the etching depth of etching only the active structure, and the excess portion forms the first sacrificial layer. This method does not require deposition or epitaxy of other material layers, and the preparation process is simpler.

[0142] In the embodiment of the present application, by etching to form a first sacrificial layer and an active structure with a certain depth, the active areas of the upper and lower layers of transistors can be self-aligned. Subsequently, a first transistor can be prepared based on the first active structure in the active structure, and the substrate structure can be etched to expose the first sacrificial layer after flipping, so that it is convenient to remove the first sacrificial layer and fill the hard mask material to form a hard mask structure; then, in the process of thinning the shallow trench isolation structure, the hard mask structure is used to protect the lower half of the active area to obtain an undamaged second active structure. Finally, a second transistor is prepared based on the undamaged second active structure to improve the performance of the second transistor.

[0143] Figures 19 to 28 FIG. 1 is a schematic diagram of a preparation process of a third stacked transistor according to an embodiment of the present application. For ease of understanding, Figures 19 to 28 (a) shows the Figure 1 The cross-sectional view along the dashed line AA'. Figures 19 to 28 (b) shows the Figure 1 The cross-sectional view along the dotted line BB', Figures 19 to 28 (c) shows the Figure 1 The cross-sectional view along the dotted line CC' Figures 1 to 28 The method for preparing the stacked transistor provided in the embodiment of the present application and the prepared stacked transistor are exemplarily described.

[0144] Different from the preparation process of the second stacked transistor, the preparation process of the third stacked transistor can use different materials to form the active structure and the first sacrificial layer.

[0145] In one embodiment, step S401 further includes: epitaxially growing a second material layer on the semiconductor substrate 20, and then epitaxially growing a first material layer on the second material layer. Subsequently, etching the first material layer and the second material layer to form a first sacrificial layer 21 and an active structure 22 on the semiconductor substrate 20.

[0146] It is understood that the material forming the first sacrificial layer 21 and the material forming the active structure 22 may be different. For example, the material forming the first sacrificial layer 21 may be silicon germanium, and the material forming the active structure 22 may be silicon. Fig.19 As shown. Then, the first material layer and the second material layer are etched to obtain Fig. 20 The structure shown.

[0147] In one embodiment, after forming the first sacrificial layer 21 and the active structure 22, step S402 may be performed. An oxide material may be deposited on the semiconductor substrate 20 to obtain an initial shallow trench isolation structure 25, such as Fig.21 As shown or Fig. 22Subsequently, the initial shallow trench isolation structure 25 is etched back to expose the first active structure 221 to obtain a shallow trench isolation structure 26, as shown Fig.23 shown.

[0148] In one embodiment, after the first active structure 221 is exposed, step S403 may be performed. Based on the first active structure 221, the first transistor 11 is formed to obtain Fig.24 Then, step S404 can be performed to flip the first transistor 11 to obtain Fig.25 Subsequently, the semiconductor substrate 20 can be removed to expose the shallow trench isolation structure 26 and the first sacrificial layer 21, and the structure shown in FIG. Fig.26 The structure shown.

[0149] For the specific process, please refer to Figures 5 to 18 For the sake of brevity of the specification, the description of one or more corresponding embodiments will not be repeated here.

[0150] In one embodiment, the first sacrificial layer 21 formed of silicon germanium is removed to obtain Fig. 27 Compared with the second manufacturing process, the third manufacturing process can selectively etch silicon germanium, thereby achieving better process control and causing less damage to the second active structure 222 .

[0151] In one embodiment, Fig. 27 Based on the structure shown in FIG. 1 , continuing to perform steps S405 to S407, the following can be obtained: Fig.28 The structure shown.

[0152] In the embodiment of the present application, the material forming the first sacrificial layer is different from the material forming the active structure, so the first sacrificial layer can be removed by a selective etching process, which not only improves the control performance of the process but also reduces damage to the second active structure.

[0153] Figure 29 to Figure 30 FIG. 1 is a schematic diagram of a fourth method for preparing a stacked transistor according to an embodiment of the present application. For ease of understanding, Figure 29 to Figure 30 (a) shows the Figure 1 The cross-sectional view along the dashed line AA'. Figure 29 to Figure 30 (b) shows the Figure 1 The cross-sectional view along the dotted line BB', Figure 29 to Figure 30 (c) shows the Figure 1 The cross-sectional view along the dotted line CC' Figures 1 to 30 The method for preparing the stacked transistor provided in the embodiment of the present application and the prepared stacked transistor are exemplarily described.

[0154] See also Figure 29 to Figure 30As shown, the solution of forming the first sacrificial layer 21 and removing the first sacrificial layer 21 after flipping to form a hard mask structure is applicable to a full-surround gate transistor. By using the hard mask structure as a hard mask and thinning the shallow trench isolation structure, the second active area can be protected from damage during the exposure process, effectively improving the performance of the transistor.

[0155] It should be noted that the solution in the embodiment of the present application is also applicable to the flip-chip stacking solution of planar transistors.

[0156] In an embodiment of the present disclosure, a stacked transistor 10 is provided. The stacked transistor 10 can be used Figures 3 to 30 The method of one or more corresponding embodiments is prepared. Fig.18 , Fig.28 and Fig.30 As shown, the stacked transistor 10 includes: a first transistor 11 and a second transistor 12 stacked with the first transistor 11 along a first direction.

[0157] The first active structure 221 of the first transistor 11 and the second active structure 222 of the second transistor 12 form an active structure 22 ; the first gate structure 114 of the first transistor 11 and the second gate structure 124 of the second transistor 12 are arranged opposite to each other.

[0158] It can be understood that the first transistor 11 and the second transistor 12 form a self-aligned flip-chip transistor.

[0159] Fig.31 It is a schematic diagram of a stacked transistor according to an embodiment of the present application. Fig.32 FIG. 1 is a schematic diagram of another stacked transistor according to an embodiment of the present application. Figure 31 to Figure 32 As shown, it can be seen that the preparation method in the embodiment of the present application is also applicable to flip-chip stacked transistors formed based on SOI substrates and flip-chip stacked transistors with intermediate dielectric isolation.

[0160] Understandably, Fig.31 The buried oxide layer 33 shown in FIG. 1 corresponds to the oxide layer in the first material layer; Fig.32 The intermediate dielectric isolation layer 34 shown in FIG. 1 corresponds to a dielectric structure formed by the second sacrificial layer in the first material layer.

[0161] In some embodiments, the type of the first transistor 11 or the second transistor 12 is any one of the following: a planar transistor, a fin field effect transistor, or a gate-all-around transistor.

[0162] It is understandable that the stacked transistor in the embodiment of the present application can be used Figures 3 to 32The embodiment of the present application forms a hard mask structure to protect the second active structure before thinning the shallow trench isolation structure of the second transistor, thereby protecting the second active structure from damage, which is beneficial to improving the performance of the stacked transistor.

[0163] It should be noted that the solution of realizing upper and lower transistors by flipping the wafer in the embodiment of the present application is an organic fusion of the current sequential and monolithic stacked transistor solutions, taking into account the consistency, defect density, alignment and thermal budget of the active areas of the upper and lower transistors. This solution solves the long-standing problems existing in the mainstream technical solutions for stacked transistors, such as complex process, fixed polarity (monolithic solution) and difficult alignment, and high defect density of upper semiconductor materials (sequential solution), thereby promoting the industrialization of transistor stacking technology.

[0164] In addition, the mature technology of the flip-chip stacked transistor solution has high reuse, which can avoid a lot of expensive process development to save costs and has high feasibility. At the same time, the flip-chip transistor adopts a self-aligned "back-to-back" active area design. The front and back transistors have independent signal and power supply networks and are connected through local interconnection, which greatly releases metal wiring resources (compared to the current solution, it is increased by more than 60%), and there is huge room for collaborative optimization of process design.

[0165] Finally, the flip-chip transistor solution is compatible with existing mainstream device architectures, and can realize the front and back stacking of planar transistors, FinFETs, GAA Nanosheets, and even vertical transistors (VTFETs), without the need for special process development for specific device architectures. It is highly flexible and has strong extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, is highly practical, and has broad prospects for expansion.

[0166] The present application embodiment provides a semiconductor device, including: a stacked transistor as described in the above embodiment. The specific definition of the stacked transistor can be at least referred to in the above Fig.18 , Fig.28 , Figure 30 to Figure 32 The stacked transistors shown are not described in detail here.

[0167] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above stacked transistor. The specific definition of the stacked transistor can be at least referred to in the above Fig.18 , Fig.28 , Figure 30 to Figure 32 The structure shown will not be described in detail here.

[0168] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0169] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: The method comprises: A first sacrificial layer and an active structure located on the first sacrificial layer are formed on a semiconductor substrate; wherein the active structure comprises: a first active structure and a second active structure; the first active structure and the second active structure are stacked along a first direction, and the first active structure is farther away from the first sacrificial layer than the second active structure; Depositing an oxide material on the semiconductor substrate to form a shallow trench isolation structure; the shallow trench isolation structure encapsulates the second active structure and the first sacrificial layer, and the first active structure is exposed outside the shallow trench isolation structure; Based on the first active structure, forming a first transistor; Flipping and removing the semiconductor substrate to expose the shallow trench isolation structure and the first sacrificial layer; removing the first sacrificial layer and forming a hard mask structure at the location of the removed first sacrificial layer; Using the hard mask structure as a hard mask, thinning the shallow trench isolation structure so that the second active structure is exposed outside the shallow trench isolation structure; After removing the hard mask structure, forming a second transistor based on the second active structure; Wherein, removing the first sacrificial layer and forming a hard mask structure at the position of the removed first sacrificial layer includes: removing the first sacrificial layer to form a groove; the bottom of the groove is formed by the second active structure; and depositing a hard mask material in the groove to form the hard mask structure.

2. The preparation method according to claim 1, characterized in that: The step of depositing a hard mask material in the groove to form the hard mask structure comprises: Depositing a hard mask material on the surface of the shallow trench isolation structure and on the bottom of the groove to form a first hard mask; The first hard mask is thinned by a chemical mechanical planarization process until the shallow trench isolation structure is exposed to form the hard mask structure.

3. The preparation method according to claim 1, characterized in that: The step of depositing a hard mask material in the groove to form the hard mask structure comprises: Depositing a hard mask material on the surface of the shallow trench isolation structure and on the bottom of the groove to form a second hard mask; thinning the second hard mask by a chemical mechanical planarization process until top surfaces of the second hard masks are at the same height to form a third hard mask; The third hard mask is etched by a dry etching process until the shallow trench isolation structure is exposed to form the hard mask structure.

4. The preparation method according to claim 1, characterized in that: The step of forming a first sacrificial layer and an active structure located on the first sacrificial layer on a semiconductor substrate comprises: Forming a first material layer and a second material layer on a semiconductor substrate; the first material layer is farther away from the semiconductor substrate than the second material layer; Using the same etching process, etching the first material layer to form an initial active structure and etching the second material layer to form an initial first sacrificial layer; The initial active structure located in the two side regions of the stacked transistor is removed by a fin cutting process to form the active structure, and the initial first sacrificial layer located in the two side regions of the stacked transistor is removed by a fin cutting process to form the first sacrificial layer.

5. The preparation method according to claim 4, characterized in that: The first material layer is a single-layer structure formed by depositing the first material; or, the first material layer is a stacked structure formed by stacking at least two material layers; the stacking direction of the stacked structure is the first direction; The second material layer is a single-layer structure formed by depositing the second material.

6. The preparation method according to claim 5, characterized in that: The first material and the second material are different; or, the first material and the second material are the same.

7. The preparation method according to claim 5, characterized in that: The at least two material layers include: a first semiconductor layer, an oxide layer, and a second semiconductor layer; the oxide layer is located between the first semiconductor layer and the second semiconductor layer; the first semiconductor layer is farther away from the second material layer than the second semiconductor layer; the material forming the oxide layer is different from the material forming the first semiconductor layer or the second semiconductor layer; The etching of the first material layer to form an initial active structure comprises: Etching the first semiconductor layer, the oxide layer and the second semiconductor layer to form an initial first active structure, an initial insulating structure and an initial second active structure respectively; The step of removing the initial active structure located in the two side regions of the stacked transistor by a fin cutting process to form the active structure comprises: The initial first active structure, the initial insulating structure and the initial second active structure located in the two side regions of the stacked transistor are removed by a fin cutting process to form a first active structure, an insulating structure and a second active structure respectively; the insulating structure is used to electrically isolate the first active structure from the second active structure.

8. The preparation method according to claim 5, characterized in that: The at least two material layers include: a first semiconductor layer, a second sacrificial layer, and a second semiconductor layer; the second sacrificial layer is located between the first semiconductor layer and the second semiconductor layer; the first semiconductor layer is away from the second material layer relative to the second semiconductor layer; the material forming the second sacrificial layer is different from the material forming the first semiconductor layer or the second semiconductor layer; The etching of the first material layer to form an initial active structure comprises: Etching the first semiconductor layer, the second sacrificial layer and the second semiconductor layer to form an initial first active structure, an initial third sacrificial layer and an initial second active structure, respectively; The step of removing the initial active structure located in the two side regions of the stacked transistor by a fin cutting process to form the active structure comprises: Using a fin cutting process to remove the initial first active structure, the initial third sacrificial layer and the initial second active structure located in the two side regions of the stacked transistor to form a first active structure, a third sacrificial layer and a second active structure respectively; The forming of a first transistor based on the first active structure comprises: A dummy gate material is deposited in the gate region of the stacked transistor to form a first dummy gate structure; the third sacrificial layer is removed, and a dielectric material is deposited at the position of the removed third sacrificial layer to form a dielectric structure; the dielectric structure is used to electrically isolate the first active structure and the second active structure.

9. The preparation method according to claim 7 or 8, characterized in that: The first semiconductor layer and the second semiconductor layer are a single-layer structure or a multi-layer structure; The material forming the first semiconductor layer is the same as the material forming the second semiconductor layer; or, the material forming the first semiconductor layer is different from the material forming the second semiconductor layer.

10. The preparation method according to claim 7 or 8, characterized in that: The second material is a first silicon germanium material; The second semiconductor layer is a multi-layer structure, and the multi-layer structure includes: a bottom material layer; the bottom material layer is adjacent to the second material layer, and the bottom material layer is formed by depositing a second silicon germanium material; The germanium content in the first silicon germanium material is different from the germanium content in the second silicon germanium material.

11. A stacked transistor, prepared by the preparation method according to any one of claims 1 to 10, characterized in that: include: a first transistor; a second transistor stacked with the first transistor along a first direction; The first active structure of the first transistor and the second active structure of the second transistor constitute the active structure; the first gate structure of the first transistor and the second gate structure of the second transistor are arranged opposite to each other.

12. The stacked transistor according to claim 11, characterized in that The first transistor and the second transistor are any of the following: Planar transistors, FinFETs, gate-all-around nanosheet transistors, and stacked forkplate transistors.

13. A semiconductor device, characterized in that: include: A stacked transistor as claimed in any one of claims 11 to 12.

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