Miniature LED Chip and Its Fabrication Method

Abstract

A miniature light-emitting diode (LED) chip and its fabrication method are disclosed. The miniature LED chip includes: a first epitaxial layer containing a first doped ion, the first epitaxial layer having a first side and a second side opposite to each other; a multi-quantum well layer located on the first side, in contact with the first epitaxial layer; a second epitaxial layer located on the first side, containing a second doped ion, the second doped ion having a different electrical type from the first doped ion; the multi-quantum well layer located between the first and second epitaxial layers; and multiple reflective rings arranged sequentially around the first side, wherein the innermost reflective ring surrounds the multi-quantum well layer. By adding multiple reflective rings around the multi-quantum well layer, the light emitted from the multi-quantum well layer can be subjected to multiple reflections, effectively reducing the sidewall effect caused by the small device size, thereby effectively improving the luminous efficiency and operational stability of the miniature LED chip.

Description

Technical Field

[0001] This invention relates to the field of microdisplay technology, and more particularly to a micro light-emitting diode chip and a method for forming the same. Background Technology

[0002] Inorganic micro-pixel light-emitting diodes, also known as micro LEDs or μ-LEDs, are a high-pixel-density LED planar display technology that uses micrometer-scale LEDs as pixels, assembled on a CMOS backplane at micrometer-scale intervals. The display principle involves thinning, miniaturizing, and arraying the LED structure, reducing its size to only a few to tens of micrometers. These micro-LED chips are then mass-produced and transferred onto a TFT or CMOS backplane. Micro LED displays possess excellent characteristics such as high luminous efficiency, high brightness, short response time, and high reliability, and are hailed by the industry as the next-generation display technology and the ultimate form of display.

[0003] However, existing miniature light-emitting diode chips still have many problems. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a micro light-emitting diode chip and a method for forming the same, thereby improving the luminous efficiency of the micro light-emitting diode chip.

[0005] To address the aforementioned problems, the present invention provides a micro light-emitting diode chip, comprising: a first epitaxial layer having a first doped ion, the first epitaxial layer having a first side and a second side opposite to each other; a multi-quantum well layer located on the first side, the multi-quantum well layer being in contact with the first epitaxial layer; a second epitaxial layer located on the first side, the second epitaxial layer having a second doped ion, the second doped ion having a different electrical type than the first doped ion, the multi-quantum well layer being located between the first epitaxial layer and the second epitaxial layer; and multiple reflective rings arranged sequentially around the first side, wherein the innermost reflective ring surrounds the multi-quantum well layer.

[0006] Optionally, the multilayer reflective ring includes: a first reflective ring surrounding the multi-quantum-well layer; and a second reflective ring surrounding the first reflective ring, the second reflective ring being in contact with the first epitaxial layer.

[0007] Optionally, it further includes: a first through-hole and a second through-hole located within the first epitaxial layer; a conductive layer located on the first side, the conductive layer being electrically connected to the second epitaxial layer and the first reflective ring respectively; a first lead located in the first through-hole, the first lead being electrically connected to the first reflective ring; and a second lead located in the second through-hole, the second lead being electrically connected to the second reflective ring.

[0008] Optionally, it also includes: a bottom reflective layer located on the second side, wherein the first through-hole and the second through-hole penetrate the bottom reflective layer.

[0009] Optionally, it further includes: an insulating layer located on the second side, the insulating layer being located between the first epitaxial layer and the bottom reflective layer, the first through-hole and the second through-hole penetrating the insulating layer.

[0010] Optionally, it further includes: a protective layer located on the second side, the protective layer covering the bottom reflective layer, and the bottom reflective layer being located between the first epitaxial layer and the protective layer, wherein the first through-hole and the second through-hole penetrate the protective layer.

[0011] Optionally, the sidewalls of the multi-quantum well layer are inclined surfaces, and the projection region of the surface of the multi-quantum well layer away from the first epitaxial layer toward the first epitaxial layer is located within the projection region of the surface of the multi-quantum well layer close to the first epitaxial layer toward the first epitaxial layer.

[0012] Optionally, the tilt angle of the sidewalls of the multi-quantum well layer is in the range of 70° to 80°.

[0013] Optionally, the sidewall of the first reflective ring is an inclined surface, and the projection area of ​​the surface of the first reflective ring away from the first epitaxial layer toward the first epitaxial layer is located within the projection area of ​​the surface of the first reflective ring close to the first epitaxial layer toward the first epitaxial layer.

[0014] Optionally, the tilt angle of the sidewall of the first reflective ring is in the range of 73° to 85°.

[0015] Optionally, the sidewall of the second reflective ring is an inclined surface, and the projection area of ​​the surface of the second reflective ring away from the first epitaxial layer toward the first epitaxial layer is located within the projection area of ​​the surface of the second reflective ring close to the first epitaxial layer toward the first epitaxial layer.

[0016] Optionally, the tilt angle of the sidewall of the second reflective ring is in the range of 73° to 85°.

[0017] Optionally, the surface of the first reflective ring away from the first epitaxial layer has a first spacing dimension with respect to the first epitaxial layer, and the surface of the multiple quantum well layer away from the first epitaxial layer has a second spacing dimension with respect to the first epitaxial layer, wherein the first spacing dimension is larger than the second spacing dimension.

[0018] Optionally, the surface of the second reflective ring away from the first epitaxial layer has a third spacing dimension with respect to the first epitaxial layer, the third spacing dimension being greater than or equal to the first spacing dimension.

[0019] Optionally, it further includes: a first passivation layer located on the first side, the sidewall of the first via, and the sidewall of the second via; the first passivation layer located on the first side covers a portion of the surface of the first epitaxial layer located on the first side, and the second reflective ring is electrically connected to the first epitaxial layer exposed by the first passivation layer; the first passivation layer located on the first side also covers the sidewall of the multiple quantum well layer and the second epitaxial layer, as well as a portion of the surface of the second epitaxial layer away from the first epitaxial layer, and the conductive layer is electrically connected to the second epitaxial layer exposed by the first passivation layer.

[0020] Optionally, it further includes: a second passivation layer located on the first side, the second passivation layer covering the multiple quantum well layer, the second epitaxial layer, the first reflection ring, the second reflection ring, the second passivation layer, and the conductive layer.

[0021] Optionally, it further includes: a microlens located on the first side, wherein the projection region of the multi-quantum well layer toward the first epitaxial layer is located within the projection region of the microlens toward the first epitaxial layer.

[0022] Optionally, it further includes: a first pad located on the second side, the first pad being electrically connected to the first lead; and a second pad located on the second side, the second pad being electrically connected to the second lead.

[0023] Optionally, it further includes: an electron blocking layer located on the first side, the electron blocking layer being located between the multiple quantum well layer and the second epitaxial layer.

[0024] Optionally, the materials of the first epitaxial layer and the second epitaxial layer include gallium nitride.

[0025] Accordingly, the present invention also provides a method for forming a micro light-emitting diode chip, comprising: forming a first epitaxial layer having a first doped ion, the first epitaxial layer having a first side and a second side opposite to each other; stacking a multi-quantum well layer and a second epitaxial layer on the first side, the multi-quantum well layer being in contact with the first epitaxial layer and located between the first epitaxial layer and the second epitaxial layer, the second epitaxial layer having a second doped ion, the second doped ion having a different electrical type than the first doped ion; forming multiple layers of sequentially arranged reflective rings on the first side, wherein the innermost reflective ring surrounds the multi-quantum well layer.

[0026] Optionally, the multilayer reflective ring includes: a first reflective ring surrounding the multi-quantum-well layer; and a second reflective ring surrounding the first reflective ring, the second reflective ring being in contact with the first epitaxial layer.

[0027] Optionally, before forming the first epitaxial layer, the method further includes: providing a first temporary substrate; the first epitaxial layer is formed on the first temporary substrate, the first temporary substrate being located on the second side.

[0028] Optionally, before forming the multilayer reflective ring, the method further includes: etching the first epitaxial layer from the first side to the second side, forming a first through-hole and a second through-hole in the first epitaxial layer; forming a conductive layer on the first side, the conductive layer being electrically connected to the second epitaxial layer and the first reflective ring respectively; after forming the multilayer reflective ring, the method further includes: forming a first lead in the first through-hole, the first lead being electrically connected to the first reflective ring; forming a second lead in the second through-hole, the second lead being electrically connected to the second reflective ring.

[0029] Optionally, after forming the first lead and the second lead, the method further includes: forming a microlens on the first side, wherein the projection region of the multi-quantum well layer toward the first epitaxial layer is located within the projection region of the microlens toward the first epitaxial layer; providing a second temporary substrate; bonding the second temporary substrate to the microlens from the first side; and removing the first temporary substrate after bonding.

[0030] Optionally, after removing the first temporary substrate, the method further includes: forming a first pad and a second pad on the second side, wherein the first pad is electrically connected to the first lead and the second pad is electrically connected to the second lead; and removing the second temporary substrate after forming the first pad and the second pad.

[0031] Optionally, before forming the first epitaxial layer, the method further includes: forming a buffer layer on the first temporary substrate; the buffer layer is located on the second side and is located between the first epitaxial layer and the first temporary substrate.

[0032] Optionally, after etching the first epitaxial layer, the method further includes etching the buffer layer from the first side to the second side, wherein the first via and the second via are also located within the buffer layer.

[0033] Optionally, after removing the first temporary substrate, the process further includes removing the buffer layer.

[0034] Optionally, before forming the first pad and the second pad, the method further includes forming a bottom reflective layer on the second side, wherein the first via and the second via penetrate the bottom reflective layer.

[0035] Optionally, before forming the bottom reflective layer, the method further includes: forming an insulating layer on the second side; the insulating layer is located between the first epitaxial layer and the bottom reflective layer, and the first via and the second via penetrate the insulating layer.

[0036] Optionally, after forming the bottom reflective layer, the method further includes: forming a protective layer on the second side; the protective layer covers the bottom reflective layer, and the bottom reflective layer is located between the first epitaxial layer and the protective layer, wherein the first via and the second via penetrate the protective layer.

[0037] Optionally, the sidewalls of the multi-quantum well layer are inclined surfaces, and the projection region of the surface of the multi-quantum well layer away from the first epitaxial layer toward the first epitaxial layer is located within the projection region of the surface of the multi-quantum well layer close to the first epitaxial layer toward the first epitaxial layer.

[0038] Optionally, the tilt angle of the sidewalls of the multi-quantum well layer is in the range of 70° to 80°.

[0039] Optionally, the sidewall of the first reflective ring is an inclined surface, and the projection area of ​​the surface of the first reflective ring away from the first epitaxial layer toward the first epitaxial layer is located within the projection area of ​​the surface of the first reflective ring close to the first epitaxial layer toward the first epitaxial layer.

[0040] Optionally, the tilt angle of the sidewall of the first reflective ring is in the range of 73° to 85°.

[0041] Optionally, the sidewall of the second reflective ring is an inclined surface, and the projection area of ​​the surface of the second reflective ring away from the first epitaxial layer toward the first epitaxial layer is located within the projection area of ​​the surface of the second reflective ring close to the first epitaxial layer toward the first epitaxial layer.

[0042] Optionally, the tilt angle of the sidewall of the second reflective ring is in the range of 73° to 85°.

[0043] Optionally, the surface of the first reflective ring away from the first epitaxial layer has a first spacing dimension with respect to the first epitaxial layer, and the surface of the multiple quantum well layer away from the first epitaxial layer has a second spacing dimension with respect to the first epitaxial layer, wherein the first spacing dimension is larger than the second spacing dimension.

[0044] Optionally, the surface of the second reflective ring away from the first epitaxial layer has a third spacing dimension with respect to the first epitaxial layer, the third spacing dimension being greater than or equal to the first spacing dimension.

[0045] Optionally, before forming the conductive layer, the method further includes: forming a first passivation layer on the first side, the sidewall of the first via, and the sidewall of the second via; the first passivation layer on the first side covers a portion of the surface of the first epitaxial layer on the first side, and the second reflective ring is electrically connected to the first epitaxial layer exposed by the first passivation layer; the first passivation layer on the first side also covers the sidewalls of the multiple quantum well layer and the second epitaxial layer, as well as a portion of the surface of the second epitaxial layer away from the first epitaxial layer, and the conductive layer is electrically connected to the second epitaxial layer exposed by the first passivation layer.

[0046] Optionally, the process of forming the microlens further includes: forming a second passivation layer on the first side, the second passivation layer covering the multiple quantum well layer, the second epitaxial layer, the first reflection ring, the second reflection ring, the second passivation layer, and the conductive layer.

[0047] Optionally, the microlens and the second passivation layer are made of the same material.

[0048] Optionally, the method for forming the microlens and the second passivation layer includes: forming a passivation material layer on the first side, the passivation material layer covering the multiple quantum well layer, the second epitaxial layer, the first reflection ring, the second reflection ring, the second passivation layer, and the conductive layer; and performing patterned etching on the passivation material layer to form the microlens and the second passivation layer.

[0049] Optionally, the microlens and the second passivation layer are made of different materials.

[0050] Optionally, the method for forming the microlens and the second passivation layer includes: forming a passivation material layer on the first side, the passivation material layer covering the multiple quantum well layer, the second epitaxial layer, the first reflection ring, the second reflection ring, the second passivation layer, and the conductive layer; forming a microlens material layer on the passivation material layer; and performing patterned etching on the passivation material layer and the microlens material layer to form the microlens and the second passivation layer.

[0051] Optionally, after forming the multiple quantum well layer and before forming the second epitaxial layer, the method further includes: forming an electron blocking layer on the first side, the electron blocking layer being located between the multiple quantum well layer and the second epitaxial layer.

[0052] Optionally, the materials of the first epitaxial layer and the second epitaxial layer include gallium nitride.

[0053] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0054] In the micro light-emitting diode chip of the present invention, by adding multiple reflection rings around the multi-quantum well layer, the light emitted by the multi-quantum well layer can be subjected to multiple reflection processing, which can effectively reduce the sidewall effect caused by the small device size, thereby effectively improving the luminous efficiency and stability of the micro light-emitting diode chip.

[0055] Furthermore, it also includes: a first through-hole and a second through-hole located within the first epitaxial layer; a conductive layer located on the first side, the conductive layer being electrically connected to the second epitaxial layer and the first reflective ring respectively; a first lead located in the first through-hole, the first lead being electrically connected to the first reflective ring; and a second lead located in the second through-hole, the second lead being electrically connected to the second reflective ring. By electrically connecting the first reflective ring to the first epitaxial layer as a transition component for the lead-out of the first epitaxial layer interconnect, and the second reflective ring being electrically connected to the second epitaxial layer as a transition component for the lead-out of the second epitaxial layer interconnect, the need for additional fabrication of the transition component for the lead-out of the first and second epitaxial layers is eliminated, thereby simplifying the device structure and reducing fabrication steps and manufacturing costs.

[0056] Furthermore, it also includes a bottom reflective layer located on the second side, with a first through-hole and a second through-hole penetrating through the bottom reflective layer. The bottom reflective layer can reflect light emitted from the multi-quantum-well layer towards the second side, further improving the luminous efficiency of the micro LED chip.

[0057] Furthermore, it also includes a protective layer located on the second side, which covers the bottom reflective layer and is situated between the first epitaxial layer and the protective layer. A first through-hole and a second through-hole penetrate the protective layer. Covering the bottom reflective layer with a protective layer enhances the stability of the bottom reflective layer.

[0058] Furthermore, the sidewalls of the multi-quantum-well layer are inclined surfaces, and the projection region of the surface of the multi-quantum-well layer away from the first epitaxial layer toward the first epitaxial layer is located within the projection region of the surface of the multi-quantum-well layer closer to the first epitaxial layer toward the first epitaxial layer. By making the sidewalls of the multi-quantum-well layer inclined surfaces, the light emission angle and light emission area of ​​the multi-quantum-well layer can be effectively increased. Moreover, the inclined sidewalls also facilitate the formation of a V-shaped angle between the sidewalls opposite to the first and second reflection rings, which is beneficial for the reflection of light by the first and second reflection rings.

[0059] Furthermore, the sidewalls of the first reflective ring are inclined surfaces, and the projection area of ​​the surface of the first reflective ring away from the first epitaxial layer toward the first epitaxial layer is located within the projection area of ​​the surface of the first reflective ring close to the first epitaxial layer toward the first epitaxial layer. This allows a V-shaped angle to be formed between the inclined sidewalls of the first reflective ring and the inclined sidewalls of the multi-quantum-well layer, which is beneficial for the reflection of light by the first reflective ring.

[0060] Furthermore, the sidewalls of the second reflective ring are inclined surfaces, and the projection area of ​​the surface of the second reflective ring away from the first epitaxial layer toward the first epitaxial layer is located within the projection area of ​​the surface of the second reflective ring close to the first epitaxial layer toward the first epitaxial layer. This allows a V-shaped angle to be formed between the inclined sidewalls of the second reflective ring and the inclined sidewalls of the multi-quantum-well layer, which is beneficial for the reflection of light by the second reflective ring.

[0061] Furthermore, the surface of the first reflective ring furthest from the first epitaxial layer has a first spacing dimension with respect to the first epitaxial layer, and the surface of the multi-quantum well layer furthest from the first epitaxial layer has a second spacing dimension with respect to the first epitaxial layer, wherein the first spacing dimension is larger than the second spacing dimension. The purpose of setting the height of the first reflective ring higher than the height of the multi-quantum well layer is to ensure that the first reflective ring can reflect as much of the optical emitted by the multi-quantum well layer as possible, thereby improving the luminous efficiency of the micro-LED chip.

[0062] Furthermore, the surface of the second reflective ring furthest from the first epitaxial layer has a third spacing dimension between it and the first epitaxial layer, and the third spacing dimension is greater than or equal to the first spacing dimension. When the third spacing dimension is greater than the first spacing dimension, the second reflective ring can reflect the light that was not reflected by the first reflective ring again, further improving the luminous efficiency of the micro LED chip.

[0063] In the method for forming a micro light-emitting diode chip according to the technical solution of the present invention, by forming a multi-layer reflection ring around the multi-quantum well layer, the light emitted by the multi-quantum well layer can be subjected to multiple reflection processing, which can effectively reduce the sidewall effect caused by the small device size, thereby effectively improving the luminous efficiency and stability of the micro light-emitting diode chip.

[0064] Furthermore, before forming the multilayer reflective ring, the method further includes: etching a first epitaxial layer from a first side to a second side, forming a first via and a second via within the first epitaxial layer; forming a conductive layer on the first side, the conductive layer being electrically connected to the second epitaxial layer and the first reflective ring respectively; after forming the multilayer reflective ring, the method further includes: forming a first lead within the first via, the first lead being electrically connected to the first reflective ring; forming a second lead within the second via, the second lead being electrically connected to the second reflective ring. By electrically connecting the first reflective ring to the first epitaxial layer as a transition component for the connection of the first epitaxial layer, and electrically connecting the second reflective ring to the second epitaxial layer as a transition component for the connection of the second epitaxial layer, the method eliminates the need to additionally fabricate a transition component for the connection of the first and second epitaxial layers, thereby simplifying the device structure and reducing fabrication steps and manufacturing costs.

[0065] Furthermore, before forming the first and second pads, a bottom reflective layer is formed on the second side, with the first and second vias penetrating through the bottom reflective layer. The bottom reflective layer reflects light emitted from the multi-quantum-well layer toward the second side, further improving the luminous efficiency of the micro LED chip.

[0066] Furthermore, after forming the bottom reflective layer, the method further includes: forming a protective layer on the second side; the protective layer covers the bottom reflective layer, and the bottom reflective layer is located between the first epitaxial layer and the protective layer, with the first through-hole and the second through-hole penetrating the protective layer. By covering the bottom reflective layer with a protective layer, the stability of the bottom reflective layer can be improved.

[0067] Furthermore, the sidewalls of the multi-quantum-well layer are inclined surfaces, and the projection region of the surface of the multi-quantum-well layer away from the first epitaxial layer toward the first epitaxial layer is located within the projection region of the surface of the multi-quantum-well layer closer to the first epitaxial layer toward the first epitaxial layer. By making the sidewalls of the multi-quantum-well layer inclined surfaces, the light emission angle and light emission area of ​​the multi-quantum-well layer can be effectively increased. Moreover, the inclined sidewalls also facilitate the formation of a V-shaped angle between the sidewalls opposite to the first and second reflection rings, which is beneficial for the reflection of light by the first and second reflection rings.

[0068] Furthermore, the sidewalls of the first reflective ring are inclined surfaces, and the projection area of ​​the surface of the first reflective ring away from the first epitaxial layer toward the first epitaxial layer is located within the projection area of ​​the surface of the first reflective ring close to the first epitaxial layer toward the first epitaxial layer. This allows a V-shaped angle to be formed between the inclined sidewalls of the first reflective ring and the inclined sidewalls of the multi-quantum-well layer, which is beneficial for the reflection of light by the first reflective ring.

[0069] Furthermore, the sidewalls of the second reflective ring are inclined surfaces, and the projection area of ​​the surface of the second reflective ring away from the first epitaxial layer toward the first epitaxial layer is located within the projection area of ​​the surface of the second reflective ring close to the first epitaxial layer toward the first epitaxial layer. This allows a V-shaped angle to be formed between the inclined sidewalls of the second reflective ring and the inclined sidewalls of the multi-quantum-well layer, which is beneficial for the reflection of light by the second reflective ring.

[0070] Furthermore, the surface of the first reflective ring furthest from the first epitaxial layer has a first spacing dimension with respect to the first epitaxial layer, and the surface of the multi-quantum well layer furthest from the first epitaxial layer has a second spacing dimension with respect to the first epitaxial layer, wherein the first spacing dimension is larger than the second spacing dimension. The purpose of setting the height of the first reflective ring higher than the height of the multi-quantum well layer is to ensure that the first reflective ring can reflect as much of the optical emitted by the multi-quantum well layer as possible, thereby improving the luminous efficiency of the micro-LED chip.

[0071] Furthermore, the surface of the second reflective ring furthest from the first epitaxial layer has a third spacing dimension between it and the first epitaxial layer, and the third spacing dimension is greater than or equal to the first spacing dimension. When the third spacing dimension is greater than the first spacing dimension, the second reflective ring can reflect the light that was not reflected by the first reflective ring again, further improving the luminous efficiency of the micro LED chip. Attached Figure Description

[0072] Figures 1 to 15 This is a schematic diagram of the structure of each step in the method for forming a micro light-emitting diode chip according to an embodiment of the present invention. Detailed Implementation

[0073] As described in the background section, existing miniature light-emitting diode (LED) chips still have many problems. These will be explained in detail below.

[0074] While miniature LED chips currently offer numerous advantages, they also present technological challenges. The EQE (Emission Efficiency and Emission Efficiency) of miniature LED chips is significantly low. Solving the luminous efficiency problem of miniature LED chips is fundamental to achieving large-scale mass production.

[0075] Based on this, the present invention provides a micro light-emitting diode chip and a method for forming the same. By adding multiple reflection rings around the multi-quantum well layer, the light emitted from the multi-quantum well layer can be subjected to multiple reflection processes, which can effectively reduce the sidewall effect caused by the small device size, thereby effectively improving the luminous efficiency and stability of the micro light-emitting diode chip.

[0076] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0077] In the description of this invention, it should be understood that the terms "upper," "lower," "top surface," "bottom surface," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the indicated position or element must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations of the invention. Furthermore, the terms "first" and "second" are used only to distinguish an entity or operation from another entity or operation, and do not require or imply any actual relationship, order, or relative importance between these entities or operations.

[0078] Figures 1 to 15 This is a schematic diagram of the structure of each step in the method for forming a micro light-emitting diode chip according to an embodiment of the present invention.

[0079] Please refer to Figure 1 Provide a first temporary substrate 100.

[0080] In this embodiment, the first temporary substrate 100 is an epitaxial substrate layer. The first temporary substrate 100 is used as a temporary support structure in the flip-chip fabrication process of the micro light-emitting diode chip. After the actual device structure of the micro light-emitting diode chip is fabricated, the first temporary substrate 100 needs to be removed.

[0081] Please continue to refer to this. Figure 1 In this embodiment, after providing the first temporary substrate 100, a buffer layer 101 is also formed on the first temporary substrate 100. Since a bottom reflective layer needs to be formed on the back side of the micro LED chip in subsequent fabrication processes to further improve the luminous efficiency of the micro LED chip, the buffer layer 101 needs to be formed first to reserve space for the subsequently formed bottom reflective layer.

[0082] In this embodiment, the buffer layer 101 is an epitaxial buffer layer of aluminum nitride (ALN).

[0083] Please refer to Figure 2 A first epitaxial layer 102 is formed on a first temporary substrate 100. The first epitaxial layer 102 contains first doped ions. The first epitaxial layer 102 has a first side 102a and a second side 102b opposite to each other. The first temporary substrate 100 is located on the second side 102b.

[0084] In this embodiment, the buffer layer 101 is located on the second side 102b, and the buffer layer 101 is located between the first epitaxial layer 102 and the first temporary substrate 100.

[0085] In this embodiment, the electrical type of the first doped ion is N-type.

[0086] It should be noted that in this embodiment, the first side 102a is the front side of the micro LED chip, and the second side 102b is the back side of the micro LED chip.

[0087] In this embodiment, the material of the first epitaxial layer is gallium nitride.

[0088] Please refer to Figure 3 On the first side 102a, a multi-quantum well layer 103 and a second epitaxial layer 105 are stacked sequentially. The multi-quantum well layer 103 is in contact with the first epitaxial layer 102. The second epitaxial layer 105 contains second doped ions, and the second doped ions have different electrical types from the first doped ions.

[0089] In this embodiment, after forming the multi-quantum well layer 103 and before forming the second epitaxial layer 105, the method further includes forming an electron blocking layer 104 on the first side 102a, wherein the electron blocking layer 104 is located between the multi-quantum well layer 103 and the second epitaxial layer 105.

[0090] In this embodiment, the method for forming the multiple quantum well layer 103, the electron blocking layer 104, and the second epitaxial layer 105 includes: sequentially stacking a multiple quantum well material layer, an electron blocking material layer, and a second gallium nitride material layer (not shown) on a first side 102a; and sequentially etching the second gallium nitride material layer, the electron blocking material layer, and the multiple quantum well material layer to form the multiple quantum well layer 103, the electron blocking layer 104, and the second epitaxial layer 105.

[0091] It should be noted that, in this embodiment, after etching the multi-quantum well material layer, a certain amount of etching is also performed on the first epitaxial layer 102, so that the first epitaxial layer 102 has protrusions (not shown) to support the multi-quantum well layer 103, the electron blocking layer 104 and the second epitaxial layer 105.

[0092] In this embodiment, the electrical type of the second doped ion is P-type. The first epitaxial layer 102 and the second epitaxial layer 105 serve as the positive and negative electrodes of the micro-LED chip, respectively.

[0093] In this embodiment, the material of the second epitaxial layer is gallium nitride.

[0094] In this embodiment, the sidewalls of the multi-quantum well layer 103 are inclined surfaces, and the projection region of the surface of the multi-quantum well layer 103 away from the first epitaxial layer 102 toward the first epitaxial layer 102 is located within the projection region of the surface of the multi-quantum well layer 103 close to the first epitaxial layer 102 toward the first epitaxial layer 102. By making the sidewalls of the multi-quantum well layer 103 inclined surfaces, the light emission angle and light emission area of ​​the multi-quantum well layer 103 can be effectively increased. Moreover, the inclined sidewalls also facilitate the formation of a V-shaped angle between the sidewalls opposite to the subsequently formed first and second reflection rings, which is beneficial for the reflection of light by the first and second reflection rings.

[0095] In this embodiment, by adjusting the chamfer of the photoresist morphology, and then using the photoresist as a mask to etch the multi-quantum well material layer, the sidewalls of the multi-quantum well layer 103 can be made to have an inclined morphology.

[0096] In this embodiment, the tilt angle of the sidewalls of the multi-quantum well layer 103 ranges from 70° to 80°.

[0097] Please refer to Figure 4 The first epitaxial layer 102 is etched from the first side 102a to the second side 102b, forming a first through hole 117 and a second through hole 118 in the first epitaxial layer 102.

[0098] It should be noted that in this embodiment, deep via photolithography is used to create the vias at the horizontal position of the first epitaxial layer 102. It is important to note that because the vias are small, the photolithographic offset must be less than 0.2 micrometers. Ion etching is used to form the deep vias, and the etching depth must reach the first temporary substrate 100 to facilitate subsequent back-side epitaxial thinning after removing the first temporary substrate 100. Due to the characteristics of the photoresist, the etching morphology of the first via 117 and the second via 118 generally exhibits an inverted trapezoidal structure, larger at the top and smaller at the bottom.

[0099] In this embodiment, since the first via 117 and the second via 118 need to extend to the first temporary substrate 100, after etching the first epitaxial layer 102, the method further includes etching a buffer layer 101 from the first side 102a to the second side 102b, and the first via 117 and the second via 118 are also located within the buffer layer 101.

[0100] Please refer to Figure 5 A first passivation layer 106 is formed on the first side 102a, the sidewall of the first through hole 117, and the sidewall of the second through hole 118.

[0101] In this embodiment, the first passivation layer 106 located on the first side 102a covers a portion of the surface of the first epitaxial layer 102 located on the first side 102a; the first passivation layer 106 located on the first side 102a also covers the sidewalls of the multiple quantum well layer 103, the electron blocking layer 104, and the second epitaxial layer 105, as well as a portion of the surface of the second epitaxial layer 105 away from the first epitaxial layer 102.

[0102] In this embodiment, the method for forming the first passivation layer 106 includes: forming a first passivation material layer (not shown) on the first side 102a, the sidewall of the first via 117, and the sidewall of the second via 118; the first passivation material layer on the first side 102a covers the surface of the first epitaxial layer 102 on the first side 102a, the multiple quantum well layer 103, the electron blocking layer 104, the sidewall of the second epitaxial layer 105, and the surface of the second epitaxial layer 105 away from the first epitaxial layer 102; etching the first passivation material layer to expose a portion of the surface of the first epitaxial layer 102 and a portion of the surface of the second epitaxial layer 105, thereby forming the first passivation layer 106.

[0103] In this embodiment, the first passivation layer 106 mainly serves as an electrical isolation layer, and the first passivation material layer can be an alumina (AL2O3) film layer formed by an atomic layer deposition process with good step coverage.

[0104] Please refer to Figure 6 A conductive layer 107 is formed on the first side 102a, and the conductive layer 107 is electrically connected to the second epitaxial layer 105.

[0105] In this embodiment, the first passivation layer 106 is used for electrical isolation between the conductive layer 107, the first epitaxial layer 102, the multiple quantum well layer 103, and the electron blocking layer 104.

[0106] In this embodiment, the conductive layer 107 is made of indium tin oxide, which ensures good ohmic contact with the second epitaxial layer 105 and also ensures the transmittance of light from the front and side of the multi-quantum well layer 103.

[0107] In this embodiment, the conductive layer 107 is electrically connected to the second epitaxial layer 105 exposed by the first passivation layer 106.

[0108] In this embodiment, after the conductive layer 107 is formed, a multi-layered reflective ring is formed on the first side 102a, wherein the innermost reflective ring surrounds the multi-quantum well layer 103.

[0109] In this embodiment, the number of reflection ring layers is taken as two: a first reflection ring surrounding the multi-quantum well layer 103; and a second reflection ring surrounding the first reflection ring and in contact with the first epitaxial layer 102. For details, please refer to [reference needed]. Figure 7 and Figure 8 .

[0110] Please refer to Figure 7 A first reflective ring 108 is formed on the first side 102a, the first reflective ring 108 surrounds the multi-quantum well layer 103, and the first reflective ring 108 is electrically connected to the conductive layer 107.

[0111] In this embodiment, the first reflective ring 108 is formed by one or a combination of magnetron sputtering coating process and vapor deposition process, and the material of the first reflective ring 108 can be chromium, aluminum, titanium, nickel, platinum or gold.

[0112] It should be noted that in this embodiment, during the formation of the first reflective ring 108, a first lead 109 is also formed in the first through hole 117. The first lead 109 is electrically connected to the first reflective ring 108, that is, the first reflective ring 108 and the first lead 109 are formed simultaneously.

[0113] In this embodiment, the sidewall of the first reflective ring 108 is an inclined surface, and the projection area of ​​the surface of the first reflective ring 108 away from the first epitaxial layer 102 toward the first epitaxial layer 102 is located within the projection area of ​​the surface of the first reflective ring 108 close to the first epitaxial layer 102 toward the first epitaxial layer 102. This allows a V-shaped angle to be formed between the inclined sidewall of the first reflective ring 108 and the inclined sidewall of the multi-quantum well layer 103, which is beneficial for the reflection of light by the first reflective ring 108.

[0114] In this embodiment, the tilt angle of the sidewall of the first reflective ring 108 is in the range of 73° to 85°.

[0115] In this embodiment, the surface of the first reflective ring 108 away from the first epitaxial layer 102 has a first spacing dimension d1 with respect to the first epitaxial layer 102, and the surface of the multi-quantum well layer 103 away from the first epitaxial layer 102 has a second spacing dimension d2 with respect to the first epitaxial layer 102. The first spacing dimension d1 is greater than the second spacing dimension d2. The purpose of setting the height of the first reflective ring 108 to be higher than the height of the multi-quantum well layer 103 is to ensure that the first reflective ring 108 can reflect as much of the optical emitted by the multi-quantum well layer 103 as possible, thereby improving the luminous efficiency of the micro LED chip.

[0116] Please refer to Figure 8 and Figure 9 , Figure 8 This is a top view showing the positional relationships of some structures. Figure 9 yes Figure 8 A cross-sectional view along line AA shows a second reflective ring 110 formed on the first side 102a. The second reflective ring 110 surrounds the first reflective ring 108 and is electrically connected to the first epitaxial layer 102.

[0117] In this embodiment, the second reflective ring 110 is formed by one or a combination of magnetron sputtering coating process and vapor deposition process, and the material of the second reflective ring 110 can be chromium, aluminum, titanium, nickel, platinum or gold.

[0118] It should be noted that in this embodiment, during the process of forming the second reflective ring 110, a second lead 111 is also formed in the second through hole 118. The second lead 111 is electrically connected to the second reflective ring 110, that is, the second reflective ring 110 and the second lead 111 are formed simultaneously.

[0119] In other embodiments, the first lead and the second lead may also be formed using separate fabrication steps.

[0120] In this embodiment, the sidewall of the second reflective ring 110 is an inclined surface, and the projection area of ​​the surface of the second reflective ring 110 away from the first epitaxial layer 102 toward the first epitaxial layer 102 is located within the projection area of ​​the surface of the second reflective ring 110 close to the first epitaxial layer 102 toward the first epitaxial layer 102. This allows a V-shaped angle to be formed between the inclined sidewall of the second reflective ring 110 and the inclined sidewall of the multi-quantum well layer 103, which is beneficial for the reflection of light by the first reflective ring 108.

[0121] In this embodiment, the tilt angle of the sidewall of the second reflective ring 110 is in the range of 73° to 85°.

[0122] In this embodiment, the surface of the second reflective ring 110 away from the first epitaxial layer 102 has a third spacing dimension d3 with respect to the first epitaxial layer 102, and the third spacing dimension d3 is greater than the first spacing dimension d1. When the third spacing dimension d3 is greater than the first spacing dimension d1, the second reflective ring 110 can reflect the light that was not reflected by the first reflective ring 108 again, thereby further improving the luminous efficiency of the micro light-emitting diode chip.

[0123] It should be noted that, in this embodiment, since the height of the first reflective ring 108 and the height of the second reflective ring 110 are different, the first reflective ring 108 and the second reflective ring 110 need to be manufactured separately.

[0124] In other embodiments, the third spacing dimension can also be equal to the first spacing dimension. When the third spacing dimension is equal to the first spacing dimension, that is, the height of the first reflective ring and the height of the second reflective ring are the same, so the first reflective ring and the second reflective ring can be manufactured simultaneously.

[0125] In this embodiment, the second reflective ring 110 is electrically connected to the first epitaxial layer 102 exposed by the first passivation layer 106.

[0126] Please refer to Figure 10After the second reflective ring 110 is formed, a microlens 113 is formed on the first side 102a. The microlens 113 is in contact with the conductive layer 107, and the projection area of ​​the multi-quantum well layer 103 toward the first epitaxial layer 102 is located within the projection area of ​​the microlens 113 toward the first epitaxial layer 102.

[0127] In this embodiment, during the formation of the microlens 113, a second passivation layer 112 is formed on the first side 102a. The second passivation layer 112 covers the multiple quantum well layer 103, the electron blocking layer 104, the second epitaxial layer 105, the first reflection ring 108, the second reflection ring 110, the second passivation layer 112, and the conductive layer 107.

[0128] In this embodiment, the microlens 113 and the second passivation layer 112 are made of the same material, and the materials of the second passivation layer 112 and the microlens 113 are silicon dioxide (SiO2).

[0129] In this embodiment, the method for forming the microlens 113 and the second passivation layer 112 includes: forming a passivation material layer (not shown) on the first side 102a, the passivation material layer covering the multi-quantum well layer 103, the electron blocking layer 104, the second epitaxial layer 105, the first reflection ring 108, the second reflection ring 110, the second passivation layer 112, and the conductive layer 107; and performing patterned etching on the passivation material layer to form the microlens 113 and the second passivation layer 112.

[0130] In other embodiments, the materials of the microlens and the second passivation layer may also be different; the material of the second passivation layer may be silicon oxide, and the material of the second passivation layer may be silicon nitride.

[0131] Correspondingly, the method for forming the microlens and the second passivation layer includes: forming a passivation material layer on a first side, the passivation material layer covering a multi-quantum well layer, an electron blocking layer, a second epitaxial layer, a first reflection ring, a second reflection ring, a second passivation layer, and a conductive layer; forming a microlens material layer on the passivation material layer; and performing patterned etching on the passivation material layer and the microlens material layer to form the microlens and the second passivation layer.

[0132] In this embodiment, the microlens 113 has a hemispherical shape, and the hemispherical structure can further improve the light extraction efficiency of the micro light-emitting diode chip.

[0133] Please refer to Figure 11 Provide a second temporary substrate 200.

[0134] In this embodiment, the second temporary substrate 200 is a silicon wafer. The second temporary substrate 200 is also used as a temporary support structure in the flip-chip fabrication process of the micro light-emitting diode chip. After the actual device structure of the micro light-emitting diode chip is fabricated, the second temporary substrate 200 needs to be removed.

[0135] Please refer to Figure 12 The second temporary substrate 200 is bonded to the microlens 113 from the first side 102a.

[0136] In this embodiment, the second temporary substrate 200 is temporarily bonded to the surface of the microlens 113 by a temporary bonding adhesive layer 201.

[0137] In this embodiment, the temporary bonding adhesive layer 201 needs to have high temperature resistance (200°C to 220°C) to cope with the heat treatment in subsequent process steps.

[0138] Please refer to Figure 13 After bonding, the first temporary substrate 100 is removed.

[0139] In this embodiment, the process of removing the first temporary substrate 100 is a laser lift-off process.

[0140] Please continue to refer to this. Figure 13 In this embodiment, after removing the first temporary substrate 100, the buffer layer 101 is also removed. The process for removing the buffer layer 101 is an ion etching process.

[0141] It should be noted that in this embodiment, during the removal of the buffer layer 101, an additional sacrificial layer is formed to protect the first lead 109 and the second lead 111, so that after the buffer layer 101 is removed by dry etching, the first lead 109 and the second lead 111 still protrude from the surface of the first epitaxial layer 102.

[0142] In other embodiments, the first and second leads may not be protected during the removal of the buffer layer, so that after the buffer layer is removed by dry etching, the first and second leads are flush with the surface of the first epitaxial layer.

[0143] Please refer to Figure 14 A bottom reflective layer 114 is formed on the second side 102b, and a first through hole 117 and a second through hole 118 penetrate the bottom reflective layer 114.

[0144] The bottom reflective layer 114 can reflect the light emitted from the multi-quantum well layer 103 toward the second side 102b, further improving the luminous efficiency of the micro LED chip.

[0145] In this embodiment, the material of the bottom reflective layer 114 can be aluminum or silver.

[0146] Please continue to refer to this. Figure 14 In this embodiment, before forming the bottom reflective layer 114, an insulating layer 115 is formed on the second side 102b; the insulating layer 115 is located between the first epitaxial layer 102 and the bottom reflective layer 114, and the first through hole 117 and the second through hole 118 penetrate the insulating layer 115.

[0147] In this embodiment, the insulating layer 115 is used to provide electrical isolation between the bottom reflective layer 114 and the first epitaxial layer 102. The material of the insulating layer 115 can be silicon dioxide or aluminum oxide.

[0148] Please continue to refer to this. Figure 14 In this embodiment, after forming the bottom reflective layer 114, a protective layer 116 is formed on the second side 102b. The protective layer 116 covers the bottom reflective layer 114, and the bottom reflective layer 114 is located between the first epitaxial layer 102 and the protective layer 116. The first through-hole 117 and the second through-hole 118 penetrate the protective layer 116. By covering the bottom reflective layer 114 with the protective layer 116, the stability of the bottom reflective layer 114 can be improved.

[0149] In this embodiment, the material of the protective layer 116 can be silicon dioxide or silicon nitride (SiN).

[0150] In other embodiments, if the first lead and the second lead are flush with the surface of the first epitaxial layer, after the insulating layer, the bottom reflective layer and the protective layer are formed, the insulating layer, the bottom reflective layer and the protective layer covering the first lead and the second lead need to be removed, and a first connection hole and a second connection hole are formed in the insulating layer, the bottom reflective layer and the protective layer. The first connection hole exposes the first lead and the second connection hole protects the second lead.

[0151] Please refer to Figure 15 On the second side 102b, a first pad 119 and a second pad 120 are formed. The first pad 119 is electrically connected to the first lead 109, and the second pad 120 is electrically connected to the second lead 111.

[0152] By adding a first reflection ring 108 and a second reflection ring 110 around the multi-quantum well layer 103, the light emitted from the multi-quantum well layer 103 can be subjected to multiple reflection processes, which can effectively reduce the sidewall effect caused by the small device size, thereby effectively improving the luminous efficiency and stability of the micro LED chip.

[0153] In addition, the first reflective ring 108 is electrically connected to the first epitaxial layer 102 as a transition component for the lead-out of the first epitaxial layer 102, and the second reflective ring 110 is electrically connected to the second epitaxial layer 105 as a transition component for the lead-out of the second epitaxial layer 105. This eliminates the need to fabricate an additional transition component for the lead-out of the first epitaxial layer 102 and the second epitaxial layer 105, thereby simplifying the device structure and reducing fabrication processes and manufacturing costs.

[0154] In this embodiment, the materials of the first pad 119 and the second pad 120 can be one or more combinations of chromium, aluminum, titanium, nickel, platinum, gold and tin.

[0155] In other embodiments, if a first connection hole and a second connection hole are formed in an insulating layer, a bottom reflective layer, and a protective layer, metal is also filled into the first connection hole and the second connection hole during the formation of the first pad and the second pad, so that the first lead and the first pad are electrically connected, and the second lead and the second pad are electrically connected.

[0156] Please continue to refer to this. Figure 15 In this embodiment, after the first pad 119 and the second pad 120 are formed, the second temporary substrate 200 is removed.

[0157] Accordingly, this invention also provides a miniature light-emitting diode chip, please refer to the following embodiments. Figure 15 The system includes: a first epitaxial layer 102, which contains a first doped ion and has a first side 102a and a second side 102b opposite to each other; a multi-quantum well layer 103 located on the first side 102a, which is in contact with the first epitaxial layer 102; a second epitaxial layer 105 located on the first side 102a, which contains a second doped ion and has a different electrical type than the first doped ion; and the multi-quantum well layer 103 located between the first epitaxial layer 102 and the second epitaxial layer 105; and a multilayered reflective ring arranged sequentially around the first side 102a, wherein the innermost reflective ring surrounds the multi-quantum well layer 103.

[0158] By adding a first reflection ring 108 and a second reflection ring 110 around the multi-quantum well layer 103, the light emitted from the multi-quantum well layer 103 can be subjected to multiple reflection processes, which can effectively reduce the sidewall effect caused by the small device size, thereby effectively improving the luminous efficiency and stability of the micro LED chip.

[0159] In this embodiment, the multilayer reflective ring includes: a first reflective ring 108, which surrounds the multi-quantum well layer 103; and a second reflective ring 110, which surrounds the first reflective ring 108 and is in contact with the first epitaxial layer 102.

[0160] In this embodiment, the micro light-emitting diode chip further includes: a first through-hole 117 and a second through-hole 118 located in the first epitaxial layer 102; a conductive layer 107 located on the first side 102a, the conductive layer 107 being electrically connected to the second epitaxial layer 105 and the first reflective ring 108 respectively; a first lead 109 located in the first through-hole 117, the first lead 109 being electrically connected to the first reflective ring 108; and a second lead 111 located in the second through-hole 118, the second lead 111 being electrically connected to the second reflective ring 110.

[0161] The first reflective ring 108 is electrically connected to the first epitaxial layer 102 to serve as a transition component for the lead-out of the first epitaxial layer 102, and the second reflective ring 110 is electrically connected to the second epitaxial layer 105 to serve as a transition component for the lead-out of the second epitaxial layer 105. This eliminates the need to additionally fabricate a transition component for the lead-out of the first epitaxial layer 102 and the second epitaxial layer 105, thereby simplifying the device structure and reducing fabrication processes and manufacturing costs.

[0162] In this embodiment, the micro LED chip further includes a bottom reflective layer 114 located on the second side 102b, with a first via 117 and a second via 118 penetrating through the bottom reflective layer 114. The bottom reflective layer 114 can reflect light emitted from the multi-quantum-well layer 103 toward the second side 102b, further improving the luminous efficiency of the micro LED chip.

[0163] In this embodiment, the micro light-emitting diode chip further includes an insulating layer 115 located on the second side 102b, the insulating layer 115 being located between the first epitaxial layer 102 and the bottom reflective layer 114, and the first through-hole 117 and the second through-hole 118 penetrating the insulating layer 115.

[0164] In this embodiment, the micro LED chip further includes a protective layer 116 located on the second side 102b, which covers the bottom reflective layer 114. The bottom reflective layer 114 is located between the first epitaxial layer 102 and the protective layer 116, and a first via 117 and a second via 118 penetrate the protective layer 116. By covering the bottom reflective layer 114 with the protective layer 116, the stability of the bottom reflective layer 114 can be improved.

[0165] In this embodiment, the sidewalls of the multi-quantum well layer 103 are inclined surfaces, and the projection region of the surface of the multi-quantum well layer 103 away from the first epitaxial layer 102 toward the first epitaxial layer 102 is located within the projection region of the surface of the multi-quantum well layer 103 close to the first epitaxial layer 102 toward the first epitaxial layer 102. By making the sidewalls of the multi-quantum well layer 103 inclined surfaces, the light emission angle and light emission area of ​​the multi-quantum well layer 103 can be effectively increased. Moreover, the inclined sidewalls also facilitate the formation of a V-shaped angle between the sidewalls opposite to the first reflection ring 108 and the second reflection ring 110, which is beneficial for the reflection of light by the first reflection ring 108 and the second reflection ring 110.

[0166] In this embodiment, the tilt angle of the sidewalls of the multi-quantum well layer 103 ranges from 70° to 80°.

[0167] In this embodiment, the sidewall of the first reflective ring 108 is an inclined surface, and the projection area of ​​the surface of the first reflective ring 108 away from the first epitaxial layer 102 toward the first epitaxial layer 102 is located within the projection area of ​​the surface of the first reflective ring 108 close to the first epitaxial layer 102 toward the first epitaxial layer 102. This allows a V-shaped angle to be formed between the inclined sidewall of the first reflective ring 108 and the inclined sidewall of the multi-quantum well layer 103, which is beneficial for the reflection of light by the first reflective ring 108.

[0168] In this embodiment, the tilt angle of the sidewall of the first reflective ring 108 is in the range of 73° to 85°.

[0169] In this embodiment, the sidewall of the second reflective ring 110 is an inclined surface, and the projection area of ​​the surface of the second reflective ring 110 away from the first epitaxial layer 102 toward the first epitaxial layer 102 is located within the projection area of ​​the surface of the second reflective ring 110 close to the first epitaxial layer 102 toward the first epitaxial layer 102. This allows a V-shaped angle to be formed between the inclined sidewall of the second reflective ring 110 and the inclined sidewall of the multiple quantum well layer 103, which is beneficial for the reflection of light by the second reflective ring 110.

[0170] In this embodiment, the tilt angle of the sidewall of the second reflective ring 110 is in the range of 73° to 85°.

[0171] In this embodiment, the surface of the first reflective ring 108 away from the first epitaxial layer 102 has a first spacing dimension d1 with respect to the first epitaxial layer 102, and the surface of the multi-quantum well layer 103 away from the first epitaxial layer 102 has a second spacing dimension d2 with respect to the first epitaxial layer 102. The first spacing dimension d1 is greater than the second spacing dimension d2. The purpose of setting the height of the first reflective ring 108 to be higher than the height of the multi-quantum well layer 103 is to ensure that the first reflective ring 108 can reflect as much of the optical emitted by the multi-quantum well layer 103 as possible, thereby improving the luminous efficiency of the micro LED chip.

[0172] In this embodiment, the surface of the second reflective ring 110 away from the first epitaxial layer 102 has a third spacing dimension d3 with respect to the first epitaxial layer 102, and the third spacing dimension d3 is greater than the first spacing dimension d1. When the third spacing dimension d3 is greater than the first spacing dimension d1, the second reflective ring 110 can reflect the light that was not reflected by the first reflective ring 108 again, thereby further improving the luminous efficiency of the micro light-emitting diode chip.

[0173] In other embodiments, the third spacing dimension may also be equal to the first spacing dimension.

[0174] In this embodiment, the micro LED chip further includes: a first passivation layer 106 located on the sidewalls of the first side 102a, the first via 117, and the second via 118; the first passivation layer 106 located on the first side 102a covers a portion of the surface of the first epitaxial layer 102 located on the first side 102a, and the second reflective ring 110 is electrically connected to the first epitaxial layer 102 exposed by the first passivation layer 106; the first passivation layer 106 located on the first side 102a also covers the sidewalls of the multiple quantum well layer 103, the electron blocking layer 104, and the second epitaxial layer 105, as well as a portion of the surface of the second epitaxial layer 105 away from the first epitaxial layer 102, and the conductive layer 107 is electrically connected to the second epitaxial layer 105 exposed by the first passivation layer 106.

[0175] In this embodiment, the micro light-emitting diode chip further includes a second passivation layer 112 located on the first side 102a, the second passivation layer 112 covering a multi-quantum well layer 103, an electron blocking layer 104, a second epitaxial layer 105, a first reflective ring 108, a second reflective ring 110, the second passivation layer 112, and a conductive layer 107.

[0176] In this embodiment, the micro light-emitting diode chip further includes a microlens 113 located on the first side 102a, wherein the projection area of ​​the multi-quantum well layer 103 toward the first epitaxial layer 102 is located within the projection area of ​​the microlens 113 toward the first epitaxial layer 102.

[0177] In this embodiment, the micro light-emitting diode chip further includes: a first pad 119 located on the second side 102b, the first pad 119 being electrically connected to the first lead 109; and a second pad 120 located on the second side 102b, the second pad 120 being electrically connected to the second lead 111.

[0178] In this embodiment, the micro light-emitting diode chip further includes an electron blocking layer 104 located on the first side 102a, the electron blocking layer 104 being located between the multiple quantum well layer 103 and the second epitaxial layer 105.

[0179] In this embodiment, the first epitaxial layer 102 and the second epitaxial layer 105 are made of gallium nitride.

[0180] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A micro light emitting diode chip, characterized by, Comprising: a first epitaxial layer having first doping ions therein, the first epitaxial layer having opposite first and second sides; a multi-quantum well layer on the first side, the multi-quantum well layer being in contact with the first epitaxial layer; a second epitaxial layer on the first side, the second epitaxial layer having second doping ions therein, the second doping ions and the first doping ions being different in electrical type, the multi-quantum well layer being between the first epitaxial layer and the second epitaxial layer; a plurality of reflector rings arranged in a nested manner on the first side, wherein an innermost one of the reflector rings surrounds the multi-quantum well layer; and the plurality of reflector rings comprises a first reflector ring surrounding the multi-quantum well layer. A sidewall of the multi-quantum well layer is an inclined surface, and a projection area of a surface of the multi-quantum well layer away from the first epitaxial layer towards the first epitaxial layer is within a projection area of a surface of the multi-quantum well layer close to the first epitaxial layer towards the first epitaxial layer. A sidewall of the first reflector ring is an inclined surface, and a projection area of a surface of the first reflector ring away from the first epitaxial layer towards the first epitaxial layer is within a projection area of a surface of the first reflector ring close to the first epitaxial layer towards the first epitaxial layer. A V-shaped angle is formed between the inclined sidewall of the first reflector ring and the inclined sidewall of the multi-quantum well layer.

2. The micro light emitting diode chip of claim 1, wherein, The plurality of reflector rings further comprises a second reflector ring surrounding the first reflector ring, the second reflector ring being in contact with the first epitaxial layer.

3. The micro light emitting diode chip of claim 2, wherein, Further comprising: a first via and a second via in the first epitaxial layer; a conductive layer on the first side, the conductive layer being electrically connected to the second epitaxial layer and the first reflector ring respectively; a first lead wire in the first via, the first lead wire being electrically connected to the first reflector ring; and a second lead wire in the second via, the second lead wire being electrically connected to the second reflector ring.

4. The micro light emitting diode chip of claim 3, wherein, Further comprising: a bottom reflector layer on the second side, the first via and the second via penetrating the bottom reflector layer.

5. The micro light emitting diode chip of claim 4, wherein, Further comprising: an insulating layer on the second side, the insulating layer being between the first epitaxial layer and the bottom reflector layer, the first via and the second via penetrating the insulating layer.

6. The micro light emitting diode chip of claim 4, wherein, Further comprising: a protective layer on the second side, the protective layer covering the bottom reflector layer, and the bottom reflector layer being between the first epitaxial layer and the protective layer, the first via and the second via penetrating the protective layer.

7. The micro light emitting diode chip of claim 1, wherein, An inclination angle of the sidewall of the multi-quantum well layer ranges from 70° to 80°.

8. The micro light emitting diode chip of claim 1, wherein, An inclination angle of the sidewall of the first reflector ring ranges from 73° to 85°.

9. The micro light emitting diode chip of claim 2, wherein, A sidewall of the second reflector ring is an inclined surface, and a projection area of a surface of the second reflector ring away from the first epitaxial layer towards the first epitaxial layer is within a projection area of a surface of the second reflector ring close to the first epitaxial layer towards the first epitaxial layer.

10. The micro light emitting diode chip of claim 9, wherein, An inclination angle of the sidewall of the second reflector ring ranges from 73° to 85°.

11. The micro light emitting diode chip of claim 2, wherein, The first reflective ring has a first spacing dimension between a surface of the first epitaxial layer and the first epitaxial layer, and the multi-quantum well layer has a second spacing dimension between a surface of the first epitaxial layer and the first epitaxial layer, the first spacing dimension being greater than the second spacing dimension.

12. The micro light emitting diode chip of claim 11, wherein, The second reflective ring has a third spacing dimension between a surface of the first epitaxial layer and the first epitaxial layer, the third spacing dimension being greater than or equal to the first spacing dimension.

13. The micro light emitting diode chip of claim 3, wherein, Further comprising: a first passivation layer on the first side, the first via sidewall and the second via sidewall; the first passivation layer on the first side covering a portion of a surface of the first epitaxial layer on the first side, the second reflective ring being electrically connected to the first epitaxial layer exposed by the first passivation layer; the first passivation layer on the first side further covering a sidewall of the multi-quantum well layer and the second epitaxial layer, and a portion of a surface of the second epitaxial layer away from the first epitaxial layer, the conductive layer being electrically connected to the second epitaxial layer exposed by the first passivation layer.

14. The micro light emitting diode chip of claim 13, wherein, Further comprising: A second passivation layer on the first side, the second passivation layer covering the multi-quantum well layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer and the conductive layer.

15. The micro light emitting diode chip of claim 1, wherein, Further comprising: A microlens on the first side, a projection area of the multi-quantum well layer towards the first epitaxial layer being within a projection area range of the microlens towards the first epitaxial layer.

16. The micro light emitting diode chip of claim 3, wherein, Further comprising: a first pad on the second side, the first pad being electrically connected to the first lead; a second pad on the second side, the second pad being electrically connected to the second lead.

17. The micro light emitting diode chip of claim 1, wherein, Further comprising: An electron blocking layer on the first side, the electron blocking layer being between the multi-quantum well layer and the second epitaxial layer.

18. The micro light emitting diode chip of claim 1, wherein, Materials of the first epitaxial layer and the second epitaxial layer include gallium nitride.

19. A method of forming a micro light emitting diode chip, characterized by, Comprising: forming a first epitaxial layer having first doping ions therein, the first epitaxial layer having opposite first and second sides; stacking a multi-quantum well layer and a second epitaxial layer on the first side, the multi-quantum well layer being in contact with the first epitaxial layer, and the multi-quantum well layer being between the first epitaxial layer and the second epitaxial layer, the second epitaxial layer having second doping ions therein, the second doping ions and the first doping ions being of different electrical types; forming a plurality of reflective rings on the first side in a stacked arrangement, wherein an innermost one of the reflective rings surrounds the multi-quantum well layer; wherein, the plurality of reflective rings include a first reflective ring surrounding the multi-quantum well layer; a sidewall of the multi-quantum well layer is an inclined surface, and a projection area of a surface of the multi-quantum well layer away from the first epitaxial layer towards the first epitaxial layer is within a projection area range of a surface of the multi-quantum well layer close to the first epitaxial layer towards the first epitaxial layer; The side wall of the first reflective ring is an inclined surface, and a projection area of the first reflective ring away from the surface of the first epitaxial layer is within a projection area of the first reflective ring close to the surface of the first epitaxial layer. An inclined side wall of the first reflective ring and an inclined side wall of the multi-quantum well layer form a V-shaped angle.

20. The method of claim 19, wherein the micro-LED chip is formed by a process comprising: The multi-layer reflective ring further comprises a second reflective ring surrounding the first reflective ring, and the second reflective ring is in contact with the first epitaxial layer.

21. The method of claim 20, wherein the micro-LED chip is formed by: Before forming the first epitaxial layer, a first temporary substrate is provided, and the first epitaxial layer is formed on the first temporary substrate, and the first temporary substrate is located on the second side.

22. The method of claim 21, wherein the micro-LED chip is formed by: Before forming the multi-layer reflective ring, the first epitaxial layer is etched from the first side to the second side to form a first through hole and a second through hole in the first epitaxial layer; a conductive layer is formed on the first side, and the conductive layer is electrically connected to the second epitaxial layer and the first reflective ring respectively; after forming the multi-layer reflective ring, a first lead is formed in the first through hole, and the first lead is electrically connected to the first reflective ring; and a second lead is formed in the second through hole, and the second lead is electrically connected to the second reflective ring.

23. The method of claim 22, wherein the micro-LED chip is formed by: After forming the first lead and the second lead, a microlens is formed on the first side, a projection area of the multi-quantum well layer toward the first epitaxial layer is within a projection area of the microlens toward the first epitaxial layer; a second temporary substrate is provided; the second temporary substrate is bonded to the microlens from the first side; and the first temporary substrate is removed after bonding.

24. The method of claim 23, wherein the micro-LED chip is formed by a process comprising: forming a plurality of micro-LEDs on a substrate; forming a plurality of micro-LEDs on a substrate; and transferring the plurality of micro-LEDs from the substrate to the target substrate. After removing the first temporary substrate, a first pad and a second pad are formed on the second side, the first pad is electrically connected to the first lead, and the second pad is electrically connected to the second lead; and the second temporary substrate is removed after forming the first pad and the second pad.

25. The method of claim 24, wherein the micro-LED chip is formed by: Before forming the first epitaxial layer, a buffer layer is formed on the first temporary substrate; the buffer layer is located on the second side, and the buffer layer is located between the first epitaxial layer and the first temporary substrate.

26. The method of claim 25, wherein the micro-LED chip is formed by: After etching the first epitaxial layer, the buffer layer is etched from the first side to the second side, and the first through hole and the second through hole are also located in the buffer layer.

27. The method of claim 26, wherein the micro-LED chip is formed by: After removing the first temporary substrate, the buffer layer is removed.

28. The method of claim 27, wherein the micro-LED chip is formed by: Before forming the first pad and the second pad, a bottom reflective layer is formed on the second side, and the first through hole and the second through hole pass through the bottom reflective layer.

29. The method of claim 28, wherein the micro-LED chip is formed by a process comprising: forming a plurality of micro-LEDs on a substrate; forming a plurality of micro-LEDs on a substrate; and transferring the plurality of micro-LEDs from the substrate to the carrier substrate. Before forming the bottom reflective layer, an insulating layer is formed on the second side; the insulating layer is located between the first epitaxial layer and the bottom reflective layer, and the first through hole and the second through hole pass through the insulating layer.

30. The method of claim 28, wherein the micro-LED chip is formed by a process comprising: forming a plurality of micro-LEDs on a substrate; forming a plurality of micro-LEDs on a substrate; and transferring the plurality of micro-LEDs from the substrate to the target substrate. Further comprising, after forming the bottom reflective layer: forming a protective layer on the second side; the protective layer covering the bottom reflective layer, and the bottom reflective layer being between the first epitaxial layer and the protective layer, the first via and the second via penetrating the protective layer.

31. The method of claim 19, wherein the micro-LED chip is formed by a process comprising: forming a plurality of micro-LEDs on a substrate; forming a plurality of micro-LEDs on a substrate; and transferring the plurality of micro-LEDs from the substrate to the target substrate. The inclined angle of the sidewall of the multi-quantum well layer ranges from 70° to 80°.

32. The method of claim 19, wherein the micro-LED chip is formed by a process comprising: forming a plurality of micro-LEDs on a substrate; forming a plurality of micro-LEDs on a substrate; and transferring the plurality of micro-LEDs from the substrate to the target substrate. The inclined angle of the sidewall of the first reflective ring ranges from 73° to 85°.

33. The method of claim 20, wherein the micro-LED chip is formed by a process comprising: forming a plurality of micro-LEDs on a substrate; forming a plurality of micro-LEDs on a substrate; and transferring the plurality of micro-LEDs from the substrate to the target substrate. The sidewall of the second reflective ring is an inclined surface, and the projection area of the surface of the second reflective ring away from the first epitaxial layer towards the first epitaxial layer is within the projection area of the surface of the second reflective ring close to the first epitaxial layer towards the first epitaxial layer.

34. The method of claim 33, wherein the micro-LED chip is formed by: The inclined angle of the sidewall of the second reflective ring ranges from 73° to 85°.

35. The method of claim 20, wherein the micro-LED chip is formed by a process comprising: The first reflective ring has a first spacing dimension between the surface of the first reflective ring away from the first epitaxial layer and the first epitaxial layer, and the multi-quantum well layer has a second spacing dimension between the surface of the multi-quantum well layer away from the first epitaxial layer and the first epitaxial layer, the first spacing dimension being greater than the second spacing dimension. ​ 36. The method of claim 35, wherein the micro-LED chip is formed by: The second reflective ring has a third spacing dimension between the surface of the second reflective ring away from the first epitaxial layer and the first epitaxial layer, the third spacing dimension being greater than or equal to the first spacing dimension.

37. The method of claim 23, wherein the micro-LED chip is formed by a process comprising: forming a plurality of micro-LEDs on a substrate; forming a plurality of micro-LEDs on a substrate; and transferring the plurality of micro-LEDs from the substrate to a target substrate. Further comprising, before forming the conductive layer: forming a first passivation layer on the first side, the first via sidewall and the second via sidewall; the first passivation layer on the first side covering the part of the surface of the first epitaxial layer on the first side, and the first epitaxial layer exposed by the first passivation layer being electrically connected with the second reflective ring; the first passivation layer on the first side also covering the sidewall of the multi-quantum well layer and the second epitaxial layer, and the part of the surface of the second epitaxial layer away from the first epitaxial layer, the second epitaxial layer exposed by the first passivation layer being electrically connected with the conductive layer.

38. The method of claim 37, wherein the micro-LED chip is formed by: Further comprising, in the process of forming the microlens: forming a second passivation layer on the first side, the second passivation layer covering the multi-quantum well layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer and the conductive layer.

39. The method of claim 38, wherein the micro-LED chip is formed by: The microlens and the second passivation layer are made of the same material.

40. The method of claim 39, wherein the micro-LED chip is formed by: The forming method of the microlens and the second passivation layer comprises: forming a passivation material layer on the first side, the passivation material layer covering the multi-quantum well layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer and the conductive layer; and performing a patterned etching treatment on the passivation material layer to form the microlens and the second passivation layer.

41. The method of claim 38, wherein the micro-LED chip is formed by: The microlens and the second passivation layer are made of different materials.

42. The method of claim 41, wherein the micro-LED chip is formed by: The method for forming the microlens and the second passivation layer comprises: forming a passivation material layer on the first side, the passivation material layer covering the multi-quantum well layer, the second epitaxial layer, the first reflective ring, the second reflective ring, the second passivation layer, and the conductive layer; forming a microlens material layer on the passivation material layer; and performing a patterned etching treatment on the passivation material layer and the microlens material layer to form the microlens and the second passivation layer.

43. The method for forming a micro light-emitting diode chip according to claim 19, characterized in that, After the multi-quantum well layer is formed, and before the second epitaxial layer is formed, the method further comprises: forming an electron blocking layer on the first side, the electron blocking layer being located between the multi-quantum well layer and the second epitaxial layer.

44. The method for forming a micro light-emitting diode chip according to claim 19, characterized in that, The material of the first epitaxial layer and the second epitaxial layer comprises gallium nitride.

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