Shift register, gate drive circuit, array substrate and wearable device

Abstract

A shift register, a gate drive circuit, an array substrate and a wearable device are provided, and belong to the technical field of wearable devices. The shift register comprises an input sub-circuit (1), a reset sub-circuit (2), a pull-down control sub-circuit (4), a pull-down sub-circuit (5), an output sub-circuit (3), a first noise reduction sub-circuit (61), a second noise reduction sub-circuit (62) and an auxiliary noise reduction sub-circuit (8). The auxiliary noise reduction sub-circuit (8) is configured to reduce the output of the signal output end (OUTPUT) by the first power supply voltage (VGL) in response to the second clock signal (CLKB).

Description

Technical Field

[0001] This disclosure belongs to the field of wearable device technology, specifically relating to a shift register, a gate drive circuit, an array substrate, and a wearable device. Background Technology

[0002] People are increasingly valuing their health and advocating for improving their physical fitness through exercise. Consequently, smart wearable products are becoming increasingly popular. These products not only offer traditional timekeeping functions but also integrate alarm clocks, camera functions, heart rate monitoring, and exercise data statistics and status tracking. Currently, smartwatches and fitness trackers are extremely popular, and consumers are not only demanding integrated functions but also paying increasing attention to their appearance, requiring high screen-to-body ratios and narrow bezels. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a shift register, a gate driving circuit, an array substrate, and a wearable device.

[0004] In a first aspect, embodiments of this disclosure provide a shift register, which includes an input sub-circuit, a reset sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, an output sub-circuit, a first noise reduction sub-circuit, a second noise reduction sub-circuit, and an auxiliary noise reduction sub-circuit; wherein...

[0005] The input sub-circuit is configured to respond to an input voltage and pre-charge the pull-up node with the input voltage; the pull-up node is the connection node between the input sub-circuit, the reset sub-circuit, the first noise reduction sub-circuit, and the output sub-circuit.

[0006] The output sub-circuit is configured to output a first clock signal through a signal output terminal in response to the potential of the pull-up node.

[0007] The reset sub-circuit is configured to reset the pull-up node via a first power supply voltage in response to the reset signal;

[0008] The pull-down control sub-circuit is configured to respond to a second clock signal and control the potential of the pull-down node through the second clock signal; the pull-down node is the connection node between the pull-down control sub-circuit, the pull-down sub-circuit, the first noise reduction sub-circuit, and the second noise reduction sub-circuit.

[0009] The pull-down sub-circuit is configured to pull down the pull-down node via the first power supply voltage in response to the potential of the pull-up node;

[0010] The first noise reduction sub-circuit is configured to reduce the noise of the output of the pull-up node in response to the potential of the pull-down node using the first power supply voltage;

[0011] The second noise reduction sub-circuit is configured to reduce the noise of the signal output terminal in response to the potential of the pull-down node using the first power supply voltage;

[0012] The auxiliary noise reduction sub-circuit is configured to reduce the noise of the signal output terminal in response to the second clock signal by using the first power supply voltage.

[0013] The shift register further includes a global reset sub-circuit, configured to reset the pull-up node via the first power supply voltage in response to the frame strobe signal.

[0014] The global reset sub-circuit includes a fourth transistor;

[0015] The second electrode is connected to the first power supply voltage terminal, and the control electrode is connected to the frame selection signal terminal.

[0016] The auxiliary noise reduction sub-circuit includes a seventh transistor;

[0017] The first terminal of the seventh transistor is connected to the signal output terminal, the second terminal is connected to the first power supply voltage terminal, and the control terminal is connected to the second clock signal terminal.

[0018] The input sub-circuit includes a first transistor;

[0019] The first terminal of the first transistor is connected to the control terminal and the signal input terminal, and the second terminal is connected to the pull-up node.

[0020] The reset sub-circuit includes a second transistor;

[0021] The first terminal of the second transistor is connected to the pull-up node, the second terminal is connected to the first power supply voltage terminal, and the control terminal is connected to the reset signal terminal.

[0022] The output sub-circuit includes a third transistor and a storage capacitor;

[0023] The first terminal of the third transistor is connected to the first clock signal terminal, the second terminal is connected to the signal output terminal and the second terminal of the storage capacitor, and the control terminal is connected to the first terminal of the storage capacitor and the pull-up node.

[0024] The pull-down control sub-circuit includes a fifth transistor;

[0025] The first terminal of the fifth transistor is connected to the control terminal and the second clock signal terminal, and the second terminal is connected to the pull-down node.

[0026] The pull-down sub-circuit includes a sixth transistor;

[0027] The first terminal of the sixth transistor is connected to the pull-down node, the second terminal is connected to the first power supply voltage terminal, and the control terminal is connected to the pull-up node.

[0028] The first noise reduction sub-circuit includes a tenth transistor;

[0029] The first terminal of the tenth transistor is connected to the pull-up node, the second terminal is connected to the first power supply voltage terminal, and the control terminal is connected to the pull-down node.

[0030] The second noise reduction sub-circuit includes an eleventh transistor;

[0031] The first terminal of the eleventh transistor is connected to the signal output terminal, the second terminal is connected to the first power supply voltage terminal, and the control terminal is connected to the pull-down node.

[0032] Secondly, embodiments of this disclosure provide a gate driving circuit comprising a plurality of cascaded shift registers, wherein the shift registers are the shift registers described in any of the preceding claims; wherein,

[0033] The signal input terminal of the shift register located in the first stage is connected to the first frame control signal input terminal, and the signal input terminals of the shift registers in other stages besides the first stage are connected to the signal output terminals of the corresponding shift registers in the previous stage.

[0034] The reset signal terminal of the last stage shift register is connected to the second frame control signal input terminal, and the reset signal terminals of the other stages of the shift register are connected to the signal output terminals of the corresponding next stage shift register.

[0035] Thirdly, embodiments of this disclosure provide an array substrate, which includes: a first substrate, the first substrate including: a pixel setting area and a peripheral area surrounding the pixel setting area, and a gate driving circuit as described in claim 11 is disposed on the first substrate and located in the peripheral area.

[0036] The peripheral area includes a first area and a second area arranged opposite to each other along a first direction; the gate driving circuit is provided in both the first area and the second area; the pixel setting area is provided with multiple rows of gate lines arranged side by side along a second direction;

[0037] The signal output terminals of each shift register in the gate drive circuit located in the first region are connected one-to-one with the gates located in the odd-numbered rows;

[0038] The signal output terminals of each shift register in the gate drive circuit located in the second region are connected one-to-one with the gates located in the even-numbered rows.

[0039] Each of the gate driving circuits further includes a first clock signal line, a second clock signal line, a first frame control signal line, and a first power supply signal line disposed on the first substrate.

[0040] For one of the gate driving circuits, the signal input terminal of the first shift register is connected to the first frame control signal line; the first clock signal terminal of each shift register is connected to the first clock signal line, the second clock signal terminal of each shift register is connected to the second clock signal line, and the first power supply voltage terminal of each shift register is connected to the first power supply signal line; the first clock signal line, the second clock signal line, the first frame control signal line, and the first power supply signal line are disposed on the side of each shift register away from the pixel setting area.

[0041] The input sub-circuit includes a first transistor, the reset sub-circuit includes a second transistor, the output sub-circuit includes a third transistor and a storage capacitor, the pull-down control sub-circuit includes a fifth transistor, the pull-down sub-circuit includes a sixth sub-circuit, the auxiliary noise reduction sub-circuit includes a seventh transistor, the first noise reduction sub-circuit includes a tenth transistor, and the second noise reduction sub-circuit includes an eleventh transistor.

[0042] For each shift register, the sixth transistor, the tenth transistor, the eleventh transistor, the first transistor, and the second transistor are sequentially arranged along the edge of the array substrate pointing towards the pixel setting area; the storage capacitor is adapted to the eleventh transistor, and the third transistor is located between the storage capacitor and the first transistor;

[0043] The fifth and seventh transistors of the shift register in this stage are located on the side of the sixth and tenth transistors away from the shift register in the next stage, and the seventh transistor is closer to the storage capacitor than the fifth transistor.

[0044] The input sub-circuit includes a first transistor, the reset sub-circuit includes a second transistor, the output sub-circuit includes a third transistor and a storage capacitor, the pull-down control sub-circuit includes a fifth transistor, the pull-down sub-circuit includes a sixth sub-circuit, the auxiliary noise reduction sub-circuit includes a seventh transistor, the first noise reduction sub-circuit includes a tenth transistor, and the second noise reduction sub-circuit includes an eleventh transistor.

[0045] For each of the shift registers, the sixth transistor, the tenth transistor, the eleventh transistor, the first transistor, and the second transistor are sequentially arranged along the direction from the edge of the array substrate toward the pixel setting area;

[0046] The fifth and seventh transistors of the shift register in this stage are located on the side of the sixth and tenth transistors away from the shift register of the next stage, and the third transistor is located on the side of the fifth and seventh transistors away from the sixth and tenth transistors; the storage capacitor is located between the third transistor and the first transistor; and the seventh transistor is closer to the storage capacitor than the fifth transistor.

[0047] The input sub-circuit includes a first transistor, the reset sub-circuit includes a second transistor, the output sub-circuit includes a third transistor and a storage capacitor, the pull-down control sub-circuit includes a fifth transistor, the pull-down sub-circuit includes a sixth sub-circuit, the auxiliary noise reduction sub-circuit includes a seventh transistor, the first noise reduction sub-circuit includes a tenth transistor, and the second noise reduction sub-circuit includes an eleventh transistor.

[0048] For each of the shift registers, the sixth transistor, the tenth transistor, the eleventh transistor, the seventh transistor, the first transistor, and the second transistor are arranged sequentially along the direction from the edge of the array substrate toward the pixel setting area;

[0049] The fifth transistor of the shift register in this stage is located on the side away from the sixth and tenth transistors of the shift register in the next stage, and the third transistor is located on the side away from the sixth and tenth transistors of the fifth transistor; the storage capacitor is located between the third transistor and the first transistor.

[0050] The array substrate further includes a plurality of pixel units disposed on the first substrate and located in the pixel setting area, each pixel unit including a first electrode and a second electrode disposed sequentially along the direction away from the first substrate.

[0051] The array substrate includes a first metal layer, a first interlayer insulating layer, a semiconductor active layer, a first transparent conductive layer, a second metal layer, a second interlayer insulating layer, and a second transparent conductive layer, which are sequentially disposed along a side away from the first substrate.

[0052] The first metal layer includes a first clock signal line, a second clock signal line, a first frame control signal line, a first power signal line, a control electrode of the first transistor, a control electrode of the second transistor, a control electrode of the third transistor, a control electrode of the fifth transistor, a control electrode of the sixth transistor, a control electrode of the seventh transistor, a control electrode of the tenth transistor, and a control electrode of the eleventh transistor;

[0053] The semiconductor active layer includes the active layer of the first transistor, the active layer of the second transistor, the active layer of the third transistor, the active layer of the fifth transistor, the active layer of the sixth transistor, the active layer of the seventh transistor, the active layer of the tenth transistor, and the active layer of the eleventh transistor.

[0054] The first transparent conductive layer includes a first electrode in each of the pixel units;

[0055] The second metal layer includes the first and second terminals of the first transistor, the first and second terminals of the second transistor, the first and second terminals of the third transistor, the first and second terminals of the fifth transistor, the first and second terminals of the sixth transistor, the first and second terminals of the seventh transistor, the first and second terminals of the tenth transistor, and the first and second terminals of the eleventh transistor.

[0056] The second transparent conductive layer includes a second electrode in each of the pixel units.

[0057] The second transparent conductive layer further includes a first connection electrode, which connects the first clock signal line to the second electrode of the third transistor through a first via and a second via; the first via penetrates the first interlayer insulating layer and the second interlayer insulating layer; the second via penetrates the second interlayer insulating layer.

[0058] The second transparent conductive layer further includes a second connection electrode, which is connected to the first power signal line through a third via; the second electrode of the second transistor, the second electrode of the sixth transistor, the second electrode of the seventh transistor, the second electrode of the tenth transistor, and the second electrode of the eleventh transistor are respectively electrically connected to the second connection electrode through their respective fourth vias; the third via penetrates the first interlayer insulating layer and the second interlayer insulating layer; the fourth via penetrates the second interlayer insulating layer.

[0059] The second transparent conductive layer further includes a third connection electrode, which is connected to the signal output of the previous stage shift register through a fifth via, and is connected to the drain of the first transistor through a sixth via, and to the gate of the first transistor through a seventh via; the fifth via and the seventh via both penetrate the first interlayer insulating layer and the second interlayer insulating layer; the sixth via penetrates the second interlayer insulating layer.

[0060] The storage capacitor includes a first electrode, a second electrode, and a third electrode stacked together; the first electrode is located in the first metal layer, the second electrode is located in the second metal layer, and the third electrode is located in the second transparent conductive layer.

[0061] Fourthly, embodiments of this disclosure also provide a wearable device comprising any of the array substrates described above. Attached Figure Description

[0062] Figure 1 This is a circuit diagram of an exemplary shift register.

[0063] Figure 2 This is a circuit of a shift register according to an embodiment of the present disclosure.

[0064] Figure 3 for Figure 2 The timing diagram of the shift register shown is shown.

[0065] Figure 4 The circuit of the shift register is a second example of the embodiments of this invention.

[0066] Figure 5 The circuit of the shift register is a third example of the embodiments of this invention.

[0067] Figure 6 This is a schematic diagram of the array substrate in an embodiment of the present invention.

[0068] Figure 7 This is a schematic diagram of the gate driving circuit on the array substrate according to an embodiment of the present disclosure.

[0069] Figure 8 This is a cross-sectional view of a pixel unit in an array substrate according to an embodiment of the present disclosure.

[0070] Figure 9 This is a schematic diagram of the film layers of the array substrate according to an embodiment of the present disclosure.

[0071] Figure 10 This is a layout diagram of a gate driving circuit on an array substrate according to an embodiment of the present disclosure.

[0072] Figure 11This is a schematic diagram of a jumper connection method in an embodiment of this disclosure.

[0073] Figure 12 This is a schematic diagram of another jumper connection method according to an embodiment of the present disclosure.

[0074] Figure 13 This is a cross-sectional view of the storage capacitor according to an embodiment of the present disclosure.

[0075] Figure 14 This is a layout diagram of another gate driving circuit on an array substrate according to an embodiment of the present disclosure.

[0076] Figure 15 This is a layout diagram of another gate driving circuit on an array substrate according to an embodiment of the present disclosure. Detailed Implementation

[0077] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0078] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0079] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics. In this embodiment, the coupling method of the drain and source of each transistor can be interchanged; therefore, the drain and source of each transistor in this disclosure embodiment are actually indistinguishable. Here, one of the two terminals of the transistor other than the control terminal (i.e., the gate) is called the drain, and the other is called the source. The transistors used in the embodiments of this disclosure can be N-type transistors or P-type transistors. In the embodiments of this disclosure, when an N-type transistor is used, its first terminal can be the source, and its second terminal can be the drain. In the following embodiments, the description uses an N-type transistor as an example, that is, the transistor is turned on when the control terminal signal is high. It can be imagined that when a P-type transistor is used, the timing of the drive signal needs to be adjusted accordingly. Specific details are not elaborated here, but should be within the protection scope of this disclosure.

[0080] Furthermore, in this embodiment, "effective level" refers to the level that controls the corresponding transistor to turn on, and "ineffective level" refers to the level that controls the corresponding transistor to turn off. For N-type transistors, a high level is an effective level, and a low level is an ineffective level; for P-type transistors, a low level is an effective level, and a high level is an ineffective level. In this embodiment, the specific voltage magnitudes of "effective level" and "ineffective level" are not limited. The first power supply signal terminal is a low-level signal terminal.

[0081] In addition, in the embodiments of this disclosure, the A film layer being located above the B film layer means that the A film layer is prepared before the B film layer. That is, if the A film layer is prepared first and the B film layer is prepared later in the process, then the A film layer is considered to be located above the B film layer.

[0082] Figure 1 Here is a circuit diagram of an exemplary shift register, such as... Figure 1 As shown, the shift register includes an input sub-circuit 1, a reset sub-circuit 2, an output sub-circuit 3, a pull-down control sub-circuit 4, a first pull-down sub-circuit 51 and a second pull-down sub-circuit 52, a first noise reduction sub-circuit 61, a second noise reduction sub-circuit 62, a global reset sub-circuit 72, and an auxiliary reset sub-circuit 2. Specifically, the input sub-circuit 1 includes a first transistor M1, the reset sub-circuit 2 includes a second transistor M2, the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1, the pull-down control sub-circuit 4 includes a fifth transistor M4 and a ninth transistor M9, the first pull-down sub-circuit 51 includes a sixth transistor M6, the second pull-down sub-circuit 52 includes an eighth transistor M8, the first noise reduction sub-circuit 61 includes a tenth transistor M10, the eleventh noise reduction sub-circuit includes an eleventh transistor M11, the global reset sub-circuit 72 includes a fourth transistor M4, and the auxiliary noise reduction sub-circuit 8 includes a seventh transistor M7.

[0083] Specifically, the source of the first transistor M1 is connected to the first operating power supply signal terminal VDS, the drain of the first transistor M1 is connected to the signal input terminal INPUT, and the drain of the first transistor M1 is connected to the pull-up node PU. The source of the second transistor M2 is connected to the pull-up node PU, the drain of the second transistor M2 is connected to the second operating power supply signal terminal VSD, and the gate of the second transistor M2 is connected to the reset signal terminal RESET. The source of the third transistor M3 is connected to the first clock signal terminal CLK, the drain of the third transistor M3 is connected to the second terminal of the storage capacitor C1 and the signal output terminal OUTPUT, and the gate of the third transistor M3 is connected to the first terminal of the storage capacitor C1 and the pull-up node PU. The source of the fourth transistor M4 is connected to the pull-up node PU and the first terminal of the storage capacitor C1, the drain of the fourth transistor M4 is connected to the low-level signal terminal VGL, and the gate of the fourth transistor M4 is connected to the frame strobe signal terminal STV0. The source of the fifth transistor M4 is connected to the gate of the ninth transistor M9 and the third operating power supply signal terminal, the drain of the fifth transistor M4 is connected to the pull-down node PD, and the gate of the fifth transistor M4 is connected to the pull-down control node PDCN. The drain of the ninth transistor M9 is connected to the pull-down control node PDCN. The source of the sixth transistor M6 is connected to the pull-down node PD, the drain of the sixth transistor M6 is connected to the low-level signal terminal VGL, and the gate of the sixth transistor M6 is connected to the pull-up node PU. The source of the seventh transistor M7 is connected to the signal output terminal OUTPUT, the drain of the seventh transistor M7 is connected to the low-level signal terminal VGL, and the gate of the seventh transistor M7 is connected to the auxiliary noise reduction signal terminal GCL. The source of the eighth transistor M8 is connected to the pull-down control node PDCN, the drain of the eighth transistor M8 is connected to the low-level signal terminal VGL, and the gate of the eighth transistor M8 is connected to the pull-up node PU. The source of the tenth transistor M10 is connected to the pull-up node PU, the drain of the tenth transistor M10 is connected to the low-level signal terminal VGL, and the gate of the tenth transistor M10 is connected to the pull-down node PD. The source of the eleventh transistor M11 is connected to the signal output terminal OUTPUT, the drain of the eleventh transistor M11 is connected to the low-level signal terminal VGL, and the gate of the eleventh transistor M11 is connected to the pull-down node PD.

[0084] The operation of the aforementioned shift register consists of four stages: input stage, output stage, reset stage, and noise reduction stage.

[0085] Specifically, during the input phase: an effective level is written to the signal input terminal INPUT, the first transistor M1 is turned on, and the pull-up node PU is pre-charged by the input voltage written to the first working power supply terminal.

[0086] Output stage: A high-level signal is written to the first clock signal terminal CLK, the third transistor M3 is turned on, the storage capacitor C1 bootstraps, further pulling up the potential of the pull-up node PU, and the signal output terminal OUTPUT outputs a high-level signal.

[0087] Reset phase: The reset signal written to the RESET terminal is at an active level, the second transistor M2 is turned on, and a low-level signal is written to the second working power supply terminal to reset the pull-up node PU.

[0088] Noise Reduction Stage: The third working power supply terminal is written with the third working power supply voltage, the fifth transistor M4 and the ninth transistor M9 are turned on, the voltages of the pull-down control node PDCN and the pull-down node PD are set high, and the tenth transistor M10 and the eleventh transistor are turned on via the IT transistor to reduce noise at the output of the pull-up node PU and the signal output terminal OUTPUT, respectively.

[0089] It should be noted that between two display frames, a valid level is written to the global reset signal terminal RESET to turn on the fourth transistor M4, and a low-level signal written to the low-level signal terminal VGL resets the pull-up node PU. At the same time, a valid level is written to the auxiliary noise reduction signal terminal to turn on the seventh transistor M7, and a low-level signal written to the low-level signal terminal VGL reduces the noise of the output terminal OUTPUT.

[0090] The inventors discovered that the aforementioned shift register structure is complex, making its fabrication difficult in wearable devices with narrow bezel designs. Therefore, the following technical solution is provided in the embodiments of this disclosure.

[0091] Firstly, Figure 2 This is a circuit of a shift register according to an embodiment of the present disclosure; such as Figure 2 As shown, this embodiment of the present disclosure provides a shift register, which includes an input sub-circuit 1, a reset sub-circuit 2, a pull-down control sub-circuit 4, a pull-down sub-circuit 5, an output sub-circuit 3, a first noise reduction sub-circuit 61, a second noise reduction sub-circuit 62, and an auxiliary noise reduction sub-circuit 8; wherein, the connection node between the input sub-circuit 1, the reset sub-circuit 2, the first noise reduction sub-circuit 61, and the output sub-circuit 3 is a pull-up node PU; the connection node between the pull-down control sub-circuit 4, the pull-down circuit 5, the first noise reduction sub-circuit 61, and the second noise reduction sub-circuit 62 is a pull-down node PD.

[0092] Specifically, input sub-circuit 1 is configured to respond to the input voltage and pre-charge the pull-up node PU using the input voltage. Output sub-circuit 3 is configured to respond to the potential of the pull-up node PU and output a first clock signal through the signal output terminal OUTPUT. Reset sub-circuit 2 is configured to respond to a reset signal and reset the pull-up node PU using the first power supply voltage. Pull-down control sub-circuit 4 is configured to respond to a second clock signal and control the potential of the pull-down node PD using the second clock signal. Pull-down sub-circuit 5 is configured to respond to the potential of the pull-up node PU and pull down the pull-down node PD using the first power supply voltage. First noise reduction sub-circuit 61 is configured to respond to the potential of the pull-down node PD and perform noise reduction on the output of the pull-up node PU using the first power supply voltage. Second noise reduction sub-circuit 62 is configured to respond to the potential of the pull-down node PD and perform noise reduction on the output of the signal output terminal OUTPUT using the first power supply voltage. Auxiliary noise reduction sub-circuit 8 is configured to respond to the second clock signal and perform noise reduction on the output of the signal output terminal OUTPUT using the first power supply voltage.

[0093] Compared to existing shift register structures, the shift register structure of this disclosure is simple, facilitating the implementation of narrow bezel designs in display devices and making it applicable to wearable devices. Furthermore, the auxiliary noise reduction sub-circuit 8 in the shift register of this disclosure, under the control of the second clock signal, can further reduce noise at the signal output terminal OUTPUT, effectively avoiding the risk that the second noise reduction sub-circuit 62 cannot adequately reduce noise at the signal output terminal OUTPUT.

[0094] In some examples, Figure 5 The circuit of the shift register is a third example of the embodiments of this invention; see reference. Figure 5 The shift register in this embodiment includes not only the structure described above, but also a global reset sub-circuit 72. The global reset sub-circuit 72 is configured to reset the pull-up node PU by a low-level signal in response to a frame strobe signal.

[0095] Further, continue to refer to Figure 5The global reset sub-circuit 72 includes a fourth transistor M4. The source of the fourth transistor M4 is connected to the pull-up node PU, the drain of the fourth transistor M4 is connected to the low-level signal terminal VGL, and the gate of the fourth transistor M4 is connected to the frame strobe signal terminal STV0. This configuration is because the gate drive circuit includes multiple cascaded shift registers. The signal output terminal OUTPUT of the current shift register is connected to the reset signal terminal RESET of the previous shift register. At this time, there will be no signal input to the reset signal terminal RESET of the last shift register, and the pull-up node PU in the shift register cannot be reset. By setting the global reset sub-circuit 72, a valid level can be written to the frame strobe signal terminal STV0 between two display frames, so that the fourth transistor M4 is turned on, and the pull-up node PU is reset by the low-level signal written to the low-level signal terminal VGL.

[0096] In some examples, refer to Figure 2 The auxiliary noise reduction sub-circuit 8 includes a seventh transistor M7; wherein the source of the seventh transistor M7 is connected to the signal output terminal OUTPUT, the drain of the seventh transistor M7 is connected to the low-level signal terminal VGL, and the gate of the seventh transistor M7 is connected to the second clock signal terminal CLKB.

[0097] Specifically, during the noise reduction stage, the seventh transistor M7 can be selected, and the low-level signal written by the low-level signal terminal VGL can be used to further reduce the noise at the signal output terminal OUTPUT, thereby reducing the risk that the second noise reduction sub-circuit 62 cannot fully reduce the noise at the output terminal OUTPUT.

[0098] In some examples, refer to Figure 2 The input sub-circuit 1 includes a first transistor M1. The source of the first transistor M1 is connected to its gate and the signal input terminal INPUT, and its drain is connected to the pull-up node PU. When multiple shift registers are cascaded to form a gate drive circuit, the signal input terminal INPUT of the first-stage shift register is connected to the first frame control signal line. In addition to the first-stage shift register, the signal input terminal INPUT of this stage shift register is connected to the signal output terminal OUTPUT of the next-stage shift register. That is, the output signal of the previous-stage shift register serves as the input voltage of this stage shift register, and the input stage of this stage shift register is the output stage of the previous stage shift register. In this case, wiring can be reduced while ensuring continuous and compact operation of the shift registers.

[0099] Specifically, during the input phase, the input voltage applied to the signal input terminal INPUT is a high-level signal, and the first transistor M1 switches. At this time, the pull-up node PU is pre-charged through the input voltage.

[0100] In some examples, refer to Figure 2 The reset sub-circuit 2 includes a second transistor M2. The source of the second transistor M2 is connected to the pull-up node PU, the drain of the second transistor M2 is connected to the low-level signal terminal VGL, and the gate of the second transistor M2 is connected to the reset signal terminal RESET. When multiple shift registers are cascaded to form a gate drive circuit, except for the last stage shift register, the reset signal terminal RESET of the current stage shift register is connected to the signal output terminal OUTPUT of the next stage shift register. That is, when the next stage shift register is in the output stage, the current stage shift register is in the reset stage. In this case, wiring can be reduced while ensuring continuous and compact operation of the shift registers.

[0101] Specifically, during the reset phase, the reset signal received by the RESET terminal is at an active level (e.g., a high-level signal output from the next-stage shift register). The second transistor M2 is turned on, and the pull-up node PU is reset by the low-level signal of the low-level signal terminal VGL, that is, the pull-up node PU is set to a low level.

[0102] In some examples, refer to Figure 2 The output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1. The source of the third transistor M3 is connected to the first clock signal terminal CLK, the drain of the third transistor M3 is connected to the signal output terminal OUTPUT and the second terminal of the storage capacitor C1, and the gate of the third transistor M3 is connected to the first terminal of the storage capacitor C1 and the pull-up node PU.

[0103] Specifically, during the output phase, the first clock signal terminal CLK is written with an effective level, i.e., a high-level signal, which charges the storage capacitor C1. The storage capacitor C1 bootstraps and pulls the pull-up node PU higher. At this time, the third transistor M3 is fully turned on, and the signal output terminal OUTPUT outputs a high-level signal.

[0104] In some examples, refer to Figure 2 The pull-down control sub-circuit 4 includes a fifth transistor M4. The source of the fifth transistor M4 is connected to its gate and the second clock signal terminal CLKB, and the drain of the fifth transistor M4 is connected to the pull-down node PD.

[0105] Specifically, during the noise reduction stage, the second clock signal terminal CLKB is written with an effective level, i.e., a high-level signal, and the fifth transistor M4 is turned on, pulling the potential of the pull-down node PD to a high level.

[0106] In some examples, refer to Figure 2 The pull-down sub-circuit 5 includes a sixth transistor M6; the source of the sixth transistor M6 is connected to the pull-down node PD, the drain of the sixth transistor M6 is connected to the low-level signal terminal VGL, and the gate of the sixth transistor M6 is connected to the pull-up node PU.

[0107] Specifically, during the input and output phases, the potential of the pull-up node PU is high, and the sixth transistor M6 is turned on. At this time, the pull-down node PD is pulled down by the low-level signal of the low-level signal terminal VGL, so that the pull-down node PD is at a low level. This effectively prevents the first noise reduction sub-circuit 61 and the second noise reduction sub-circuit 62 from working, and pulls down the potential of the pull-up node PU and the signal output terminal OUTPUT, thereby effectively avoiding erroneous output.

[0108] In some examples, refer to Figure 2 The first noise reduction sub-circuit 61 includes a tenth transistor M10. The source of the tenth transistor M10 is connected to the pull-up node PU, the drain of the tenth transistor M10 is connected to the low-level signal terminal VGL, and the gate of the tenth transistor M10 is connected to the pull-down node PD.

[0109] Specifically, during the noise reduction stage, the pull-down control sub-circuit 4 sets the voltage of the pull-down node PD high and turns on the tenth transistor M10. At this time, the low-level signal of the low-level signal terminal VGL is used to reduce the noise of the output of the pull-up node PU.

[0110] In some examples, refer to Figure 2 The second noise reduction sub-circuit 62 includes an eleventh transistor M11. The source of the eleventh transistor M11 is connected to the signal output terminal OUTPUT, the drain of the eleventh transistor M11 is connected to the low-level signal terminal VGL, and the gate of the eleventh transistor M11 is connected to the pull-down node PD.

[0111] Specifically, during the noise reduction stage, the pull-down control sub-circuit 4 sets the voltage of the pull-down node PD high, and the eleventh transistor M11 is turned on. At this time, the low-level signal of the low-level signal terminal VGL is used to reduce the noise of the output of the signal output terminal OUTPUT.

[0112] To better understand the specific structure and operation of the shift register in the embodiments of this disclosure, the following description is provided in conjunction with specific examples.

[0113] First example: (Refer to) Figure 2The shift register includes an input sub-circuit 1, a reset sub-circuit 2, an output sub-circuit 3, a pull-down control sub-circuit 4, a pull-down sub-circuit 5, a first noise reduction sub-circuit 61, a second noise reduction sub-circuit 62, and an auxiliary noise reduction sub-circuit 8. Specifically, the input sub-circuit 1 includes a first transistor M1; the reset sub-circuit 2 includes a second transistor M2; the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1; the pull-down control sub-circuit 4 includes a fifth transistor M4; the pull-down sub-circuit 5 includes a sixth transistor M6; the first noise reduction sub-circuit 61 includes a tenth transistor M10; the second noise reduction sub-circuit 62 includes an eleventh transistor M11; and the auxiliary noise reduction sub-circuit 8 includes a seventh transistor M7. The source of the seventh transistor M7 is connected to the signal output terminal OUTPUT, the drain of the seventh transistor M7 is connected to the low-level signal terminal VGL, and the gate of the seventh transistor M7 is connected to the second clock signal terminal CLKB.

[0114] Specifically, the source of the first transistor M1 is connected to its gate and the signal input terminal INPUT, and its drain is connected to the pull-up node PU. The source of the second transistor M2 is connected to the pull-up node PU, its drain is connected to the low-level signal terminal VGL, and its gate is connected to the reset signal terminal RESET. The source of the third transistor M3 is connected to the first clock signal terminal CLK, its drain is connected to the signal output terminal OUTPUT and the second terminal of the storage capacitor C1, and its gate is connected to the first terminal of the storage capacitor C1 and the pull-up node PU. The source of the fifth transistor M4 is connected to its gate and the second clock signal terminal CLKB, and its drain is connected to the pull-down node PD. The source of the sixth transistor M6 is connected to the pull-down node PD, its drain is connected to the low-level signal terminal VGL, and its gate is connected to the pull-up node PU. The source of the seventh transistor M7 is connected to the signal output terminal OUTPUT, its drain is connected to the low-level signal terminal VGL, and its gate is connected to the second clock signal terminal CLKB. The source of the tenth transistor M10 is connected to the pull-up node PU, the drain of the tenth transistor M10 is connected to the low-level signal terminal VGL, and the gate of the tenth transistor M10 is connected to the pull-down node PD. The source of the eleventh transistor M11 is connected to the signal output terminal OUTPUT, the drain of the eleventh transistor M11 is connected to the low-level signal terminal VGL, and the gate of the eleventh transistor M11 is connected to the pull-down node PD.

[0115] It should be noted that when multiple shift registers are cascaded to form a gate drive circuit, the signal input terminal INPUT of the first-stage shift register is connected to the first frame control signal line. Except for the first-stage shift register, the signal input terminal INPUT of this stage shift register is connected to the signal output terminal OUTPUT of the next-stage shift register. That is, the output signal of the previous-stage shift register serves as the input voltage of this stage shift register, and the input stage of this stage shift register is the output stage of the previous stage shift register. Except for the last stage shift register, the reset signal terminal RESET of this stage shift register is connected to the signal output terminal OUTPUT of the next-stage shift register. In other words, when the next-stage shift register is in the output stage, this stage shift register is in the reset stage. This saves wiring space, and the timing of the gate drive circuit is more continuous and compact.

[0116] Next, Figure 3 for Figure 2 The timing diagram of the shift register shown is included; combined with... Figure 2 and 3 The working process of the shift register described above includes four stages: input stage T1, output stage T2, reset stage T3, and noise reduction stage T4.

[0117] Input phase T1: The input voltage written to the signal input terminal INPUT is an effective level, that is, a high level signal. The first transistor M1 is turned on, and the pull-up node PU is pre-charged through the high level signal input to the signal input terminal INPUT.

[0118] Output phase T2: The first clock signal input at the first clock signal terminal CLK is a high-level signal, charging the storage capacitor C1. The bootstrap function of the storage capacitor C1 further pulls the potential of the pull-up node PU high, and the third transistor M3 is fully turned on. Since the first clock signal is a high-level signal during this phase, the signal output terminal OUTPUT outputs a high-level signal. At the same time, since the pull-up node PU is high, the sixth transistor M6 is turned on, and the low-level signal at the low-level signal terminal VGL pulls the potential of the pull-down node PD low.

[0119] Reset Phase T3: The reset signal written to the RESET terminal is at a valid level, i.e., a high-level signal. The second transistor M2 is turned on. At this time, the low-level signal at the VGL terminal pulls the potential of the pull-up node PU low, thereby completing the reset of the pull-up node PU. Simultaneously, the third transistor M3 is turned off, and the OUTPUT terminal outputs a low-level signal.

[0120] Noise Reduction Stage T4: Since the potential of the pull-up node PU was pulled low in the previous stage, the potential of the pull-down node PD was set to high level. The second clock signal of the second clock signal terminal CLKB alternates between active and inactive levels, that is, alternating high and low levels. When the second clock signal is a high level signal, the pull-down node PD is pulled high, and the tenth transistor M10, the eleventh transistor M11 and the seventh transistor M7 are turned on. At this time, the low level signal of the low level signal terminal VGL performs noise reduction on the output of the pull-up node PU through the tenth transistor M10, and the low level signal of the low level signal terminal VGL performs noise reduction on the output of the signal output terminal OUTPUT through the eleventh transistor M11 and the seventh transistor M7.

[0121] In this example, during the noise reduction stage, the seventh transistor M7 can be selected to further reduce noise at the signal output terminal OUTPUT by using the low-level signal written at the low-level signal terminal VGL. This reduces the risk that the eleventh transistor M11 cannot adequately reduce noise at the output terminal OUTPUT.

[0122] Second example: Figure 4 This is a circuit diagram of a shift register according to a second example of an embodiment of this disclosure; as shown below. Figure 4 As shown, the structure of this shift register is largely the same as that of the shift register in the first example, the only difference being that the auxiliary noise reduction sub-circuit 8, i.e., the seventh transistor M7, is not included in this example. In this case, setting the aspect ratio of the channel of the eleventh transistor M11 in the second noise reduction sub-circuit 62 can also achieve sufficient noise reduction at the signal output terminal OUTPUT. Since the other structures in this shift register are the same as in the first example, they will not be described again here.

[0123] The third example: such as Figure 5As shown, the structure of this shift register is largely the same as that of the shift register in the third example, except that a global reset sub-circuit 72 is added, which is equivalent to adding a fourth transistor M4. The source of the fourth transistor M4 is connected to the pull-up node PU, the drain of the fourth transistor M4 is connected to the low-level signal terminal VGL, and the gate of the fourth transistor M4 is connected to the frame strobe signal terminal STV0. This configuration is because the gate drive circuit includes multiple cascaded shift registers. The signal output terminal OUTPUT of the current shift register is connected to the reset signal terminal RESET of the previous shift register. At this time, there will be no signal input to the reset signal terminal RESET of the last shift register, and the pull-up node PU in the shift register cannot be reset. By setting the global reset sub-circuit 72, a valid level can be written to the frame strobe signal terminal STV0 between two display frames, so that the fourth transistor M4 is turned on, and the pull-up node PU is reset by the low-level signal written to the low-level signal terminal VGL. The other structures in this shift register are the same as in the first example, so they will not be described again here.

[0124] Secondly, embodiments of this disclosure provide a gate driving circuit comprising multiple cascaded shift registers, wherein the shift registers are any of the shift registers described above. Specifically, the signal input terminal INPUT of the first-stage shift register is connected to the first frame control signal input terminal INPUT, and the signal input terminals INPUT of the other shift registers (excluding the first-stage shift register) are connected to the signal output terminal OUTPUT of the corresponding previous-stage shift register; the reset signal terminal RESET of the last-stage shift register is connected to the second frame control signal input terminal INPUT, and the reset signal terminals RESET of the other shift registers (excluding the last-stage shift register) are connected to the signal output terminal OUTPUT of the corresponding next-stage shift register.

[0125] Thirdly, Figure 6 This is a schematic diagram of the array substrate structure according to an embodiment of the present invention; as shown below. Figure 6 As shown, this embodiment of the present disclosure provides an array substrate, which includes a first substrate 10. The first substrate 10 includes a pixel setting region Q1 and a peripheral region Q2 surrounding the pixel setting region Q1, and the aforementioned gate driving circuit is disposed on the first substrate 10 and located within the peripheral region Q2.

[0126] In some examples, Figure 7 This is a schematic diagram of the gate driving circuit on the array substrate according to an embodiment of the present disclosure; as shown Figure 7As shown, the peripheral area Q2 includes a first area and a second area arranged opposite to each other along a first direction; gate driving circuits are provided in both the first and second areas; the pixel setting area Q1 has multiple rows of gate lines arranged side by side along a second direction; the signal output terminal OUTPUT of each shift register in the gate driving circuit of the first area is connected to the gates located in the odd-numbered rows; the signal output terminal OUTPUT of each shift register in the gate driving circuit of the second area is connected to the gates located in the even-numbered rows. That is, the array substrate adopts bilateral driving, thereby effectively reducing the bezel width.

[0127] In some examples, each of the gate drive circuits further includes a first clock signal line, a second clock signal line, a first frame control signal line, and a low power signal line disposed on the first substrate 10.

[0128] Furthermore, for a gate driving circuit, the signal input terminal INPUT of the first shift register is connected to the first frame control signal line; the first clock signal terminal CLK of each shift register is connected to the first clock signal line, the second clock signal terminal CLKB of each shift register is connected to the second clock signal line, and the low voltage signal terminal of each shift register is connected to the low power supply signal line; the first clock signal line, the second clock signal line, the first frame control signal line, and the first power supply signal line are disposed on the side of each shift register away from the pixel setting area Q1. Specifically, the first frame control signal line, the low power supply signal line, the second clock signal line, and the first clock signal line are sequentially disposed from the edge of the first substrate 10 toward the middle region.

[0129] In some examples, the pixel setting area Q1 has multiple gate lines extending along a first direction and arranged side by side along a second direction, and multiple data lines extending along the second direction Y and arranged side by side along the first direction X. The gate lines and data lines are intersected to define multiple pixel units. Figure 8 This is a cross-sectional view of a pixel unit in an array substrate according to an embodiment of this disclosure; as shown Figure 8 As shown, each pixel unit includes a pixel switching transistor, a first electrode, and a second electrode. One of the first electrode and the second electrode is the pixel electrode, and the other is a common electrode. In this embodiment, the first electrode is used as the pixel electrode, and the second electrode as the common electrode. Since the common electrode is located on the side of the pixel electrode opposite to the first substrate 10, the common electrode is a slit electrode. The pixel switching transistor can be a bottom-gate thin-film transistor or a top-gate transistor; in this embodiment, the pixel switching transistor is a bottom-gate thin-film transistor.

[0130] In some examples, the transistors in the shift register can be of the same type as the pixel switch transistors. That is, they can all be bottom-gate thin-film transistors, in which case the transistors in the shift register can be fabricated together with the pixel switch transistors.

[0131] Specifically, in the embodiments of this disclosure, a shift register is used. Figure 2 The shift register shown, i.e., input sub-circuit 1 includes a first transistor M1, reset sub-circuit 2 includes a second transistor M2, output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1, pull-down control sub-circuit 4 includes a fifth transistor M4, pull-down sub-circuit 5 includes a sixth sub-circuit, auxiliary noise reduction sub-circuit 8 includes a seventh transistor M7, first noise reduction sub-circuit 61 includes a tenth transistor M10, and second noise reduction sub-circuit 62 includes an eleventh transistor M11.

[0132] Furthermore, Figure 9 This is a schematic diagram of the film layers of the array substrate according to an embodiment of the present disclosure; as shown Figure 9 As shown, the array substrate includes a first metal layer Gate, a first interlayer insulating layer GI, a semiconductor active layer Active, a first transparent conductive layer 1st ITO, a second metal layer SD, a second interlayer insulating layer PVX, and a second transparent conductive layer 2nd ITO, which are sequentially disposed along a side away from the first substrate 10.

[0133] The first metal layer Gate includes a first clock signal line, a second clock signal line, a first frame control signal line, a first power signal line, the gate of the first transistor M1, the gate of the second transistor M2, the gate of the third transistor M3, the gate of the fifth transistor M4, the gate of the sixth transistor M6, the gate of the seventh transistor M7, the gate of the tenth transistor M10, the gate of the eleventh transistor M11, and the gate of the pixel switch transistor.

[0134] The active semiconductor layer includes the active layer of the first transistor M1, the active layer of the second transistor M2, the active layer of the third transistor M3, the active layer of the fifth transistor M4, the active layer of the sixth transistor M6, the active layer of the seventh transistor M7, the active layer of the tenth transistor M10, the active layer of the eleventh transistor M11, and the active layer of the pixel switch transistor.

[0135] The first transparent conductive layer 1st ITO includes the first electrode in each pixel unit.

[0136] The second metal layer SD includes the source and drain of the first transistor M1, the source and drain of the second transistor M2, the source and drain of the third transistor M3, the source and drain of the fifth transistor M4, the source and drain of the sixth transistor M6, the source and drain of the seventh transistor M7, the source and drain of the tenth transistor M10, the source and drain of the eleventh transistor M11, and the source and drain of the pixel switching transistor.

[0137] The second transparent conductive layer 2nd ITO includes the second electrode in each pixel unit.

[0138] In some examples, Figure 10 This is a layout diagram of a gate driving circuit on an array substrate according to an embodiment of the present disclosure; as follows: Figure 10 As shown, for each shift register, along the direction from the edge of the array substrate towards the pixel setting area Q1, the sixth transistor M6, the tenth transistor M10, the eleventh transistor M11, the first transistor M1, and the second transistor M2 are sequentially arranged; the storage capacitor C1 is adapted to the eleventh transistor M11, and the third transistor M3 is located between the storage capacitor C1 and the first transistor M1; the fifth transistor M4 and the seventh transistor M7 of this stage shift register are located on the side of the sixth transistor M6 and the tenth transistor M10 away from the next stage shift register, and the seventh transistor M7 is closer to the storage capacitor C1 than the fifth transistor M4. That is, the first transistor M1 and the second transistor M2 are located on the innermost side, the third transistor M3 and the storage capacitor C1 are connected to the first transistor M1, the seventh transistor M7, the tenth transistor M10, and the eleventh transistor M11 are located in the middle position, and the fifth transistor M4 and the sixth transistor M6 are located on the outermost side.

[0139] In this case, the seventh transistor M7 is arranged horizontally and is a 1-shaped transistor, while the other transistors can be U-shaped transistors.

[0140] Continue to refer to Figure 10 The size of the first transistor M1 in the shift register is equal to or approximately equal to the size of the second transistor M2. The size of the sixth transistor M6 is equal to or approximately equal to the size of the eleventh transistor M11, and both are slightly smaller than the size of the first transistor M1. The size of the seventh transistor M7 is approximately equal to the size of the tenth transistor M10, and both are larger than the size of the fifth transistor M5. The size of the third transistor M3 is larger than the sizes of the other transistors in the shift register.

[0141] Figure 11 This is a schematic diagram of a jumper connection method in an embodiment of this disclosure; as shown Figure 11As shown, the first clock signal line needs to be connected to the source of the third transistor M3 via a jumper. Specifically, a first connection electrode is provided in the second transparent conductive layer 2nd ITO. The first connection electrode is connected to the first clock signal line through a first via, and simultaneously connected to the drain of the third transistor M3 through a second via. The first via penetrates the first interlayer insulating layer GI and the second interlayer insulating layer PVX; the second via penetrates the second interlayer insulating layer PVX.

[0142] A second connection electrode can also be provided in the second transparent layer. The second connection electrode is connected to the low power signal line through a third via. Simultaneously, the second connection electrode is connected to the drains of the second transistor M2, the sixth transistor M6, the seventh transistor M7, the tenth transistor M10, and the eleventh transistor M11 through multiple fourth vias, respectively. The multiple fourth vias are respectively configured to correspond one-to-one with the drains of the second transistor M2, the sixth transistor M6, the seventh transistor M7, the tenth transistor M10, and the eleventh transistor M11. The third via penetrates the first interlayer insulating layer GI and the second interlayer insulating layer PVX; the fourth vias penetrate the second interlayer insulating layer PVX.

[0143] Since the signal input terminal INPUT of this stage shift register is connected to the signal output of the previous stage shift register, a third connection electrode can also be provided in the second transparent layer. The third connection electrode is connected to the signal output of the previous stage shift register through a fifth via, and is also connected to the drain of the first transistor M1 through a sixth via, and to the gate of the first transistor M1 through a seventh via. The fifth and seventh vias both penetrate the first interlayer insulating layer GI and the second interlayer insulating layer PVX; the sixth via penetrates the second interlayer insulating layer PVX.

[0144] Figure 12 This is a schematic diagram of another jumper connection method according to an embodiment of this disclosure; as shown Figure 12 As shown, since the RESET signal terminal of this stage shift register is connected to the signal output of the next stage shift register, a fourth connection electrode can also be set in the second transparent layer. The fourth connection electrode is connected to the signal output of the next stage shift register through the eighth via, and simultaneously connected to the gate of the second transistor M2 through the ninth via. Both the eighth and ninth vias penetrate the first interlayer insulating layer GI and the second interlayer insulating layer PVX.

[0145] Of course, the gate of the tenth transistor M10 and the drain of the sixth transistor M6 also need to be connected by a via. The same method as above can be used, that is, the connection electrode is prepared by using the second transparent conductive layer 2nd ITO and connected by drilling. These will not be listed one by one here.

[0146] In the embodiments disclosed herein, such as Figure 11 As shown, the single-hole process of the first metal layer Gate and the second metal layer SD can reduce the bezel size by 0.1mm. Because the holes in the first metal layer Gate, which are deep holes in the first interlayer insulating layer GI and the second interlayer insulating layer PVX, have small diameters, the conductive patterns of the first metal layer Gate (e.g., the gate connection positions) can be made small. Conversely, the holes penetrating the second interlayer insulating layer PVX in the second metal layer SD are shallow holes with larger diameters, therefore the conductive patterns of the second metal layer SD (e.g., the source and drain connection positions) can be made larger. Figure 12 As shown, the design of a single-interface hole with first metal layer Gate - second metal layer SD - first metal layer Gate at the OUTPUT position can further reduce the risk of ESD.

[0147] In some examples, Figure 13 This is a cross-sectional view of the storage capacitor C1 according to an embodiment of this disclosure; as shown Figure 13 As shown, the storage capacitor C1 in each shift register includes a stacked first plate, a second plate, and a third plate; the first plate is located on the first metal layer Gate, the second plate is located on the second metal layer SD, and the third plate is located on the second transparent conductive layer 2ndITO. This double-layer capacitor structure effectively reduces the bezel width, which can be reduced by approximately 0.05mm.

[0148] In some examples, Figure 14 This is a layout diagram of another gate driving circuit on the array substrate according to an embodiment of the present disclosure; as follows: Figure 14 As shown, for each shift register, along the direction from the edge of the array substrate towards the pixel setting area Q1, the sixth transistor M6, the tenth transistor M10, the eleventh transistor M11, the first transistor M1, and the second transistor M2 are arranged sequentially; the fifth transistor M4 and the seventh transistor M7 of this stage shift register are located on the side of the sixth transistor M6 and the tenth transistor M10 away from the next stage shift register, and the third transistor M3 is located on the side of the fifth transistor M4 and the seventh transistor M7 away from the sixth transistor M6 and the tenth transistor M10; the storage capacitor C1 is located between the third transistor M3 and the first transistor M1; and the seventh transistor M7 is closer to the storage capacitor C1 than the fifth transistor M4.

[0149] Continue to refer to Figure 14In the shift register, the size of the first transistor M1 is equal to or approximately equal to the size of the second transistor M2. The size of the fifth transistor M5 is equal to or approximately equal to the size of the seventh transistor M7, and both are slightly smaller than the size of the first transistor M1. The size of the sixth transistor M6 is between the size of the first transistor M1 and the fifth transistor M5. The size of the eleventh transistor M11 is larger than the size of the first transistor M1. The size of the tenth transistor M10 is smaller than the size of the eleventh transistor M11. The size of the third transistor M3 is larger than the sizes of the other transistors in the shift register.

[0150] In some examples, Figure 15 This is a layout diagram of another gate driving circuit on the array substrate according to an embodiment of the present disclosure; as follows: Figure 15 As shown, for each shift register, along the direction from the edge of the array substrate towards the pixel setting area Q1, the sixth transistor M6, the tenth transistor M10, the eleventh transistor M11, the seventh transistor M7, the first transistor M1, and the second transistor M2 are arranged sequentially; the fifth transistor M4 of this stage shift register is located on the side of the sixth transistor M6 and the tenth transistor M10 away from the next stage shift register, and the third transistor M3 is located on the side of the fifth transistor M4 away from the sixth transistor M6 and the tenth transistor M10; the storage capacitor C1 is located between the third transistor M3 and the first transistor M1.

[0151] Continue to refer to Figure 15 In the shift register, the size of the first transistor M1 is equal to or approximately equal to the size of the second transistor M2. The size of the fifth transistor M5 is smaller than the size of the first transistor M1. The sizes of the sixth transistor M6 and the seventh transistor are both between the sizes of the first transistor M1 and the fifth transistor M5. The eleventh transistor M11 is larger than the size of the first transistor M1. The tenth transistor M10 is smaller than the size of the eleventh transistor M11. The size of the third transistor M3 is larger than the sizes of the other transistors in the shift register.

[0152] Fourthly, embodiments of this disclosure provide a wearable device comprising any of the array substrates described above.

[0153] The wearable device in this embodiment of the disclosure has traditional time display functions, and also integrates functions such as alarm clock, photo taking, heart rate detection, and exercise data statistics and exercise status detection. This wearable device can be a smartwatch, bracelet, etc.

[0154] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register, comprising an input sub-circuit, a reset sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, an output sub-circuit, a first noise reduction sub-circuit, a second noise reduction sub-circuit, and an auxiliary noise reduction sub-circuit; wherein, The input sub-circuit is configured to respond to an input voltage and pre-charge the pull-up node with the input voltage; the pull-up node is the connection node between the input sub-circuit, the reset sub-circuit, the first noise reduction sub-circuit, and the output sub-circuit. The output sub-circuit is configured to output a first clock signal through a signal output terminal in response to the potential of the pull-up node. The reset sub-circuit is configured to reset the pull-up node via a first power supply voltage in response to a reset signal; The pull-down control sub-circuit is configured to respond to a second clock signal and control the potential of the pull-down node via the second clock signal; The pull-down node is the connection node between the pull-down control sub-circuit, the pull-down sub-circuit, the first noise reduction sub-circuit, and the second noise reduction sub-circuit. The pull-down sub-circuit is configured to pull down the pull-down node via the first power supply voltage in response to the potential of the pull-up node; The first noise reduction sub-circuit is configured to reduce the noise of the output of the pull-up node in response to the potential of the pull-down node using the first power supply voltage; The second noise reduction sub-circuit is configured to reduce the noise of the signal output terminal in response to the potential of the pull-down node using the first power supply voltage; The auxiliary noise reduction sub-circuit is configured to reduce the noise of the signal output terminal by means of the first power supply voltage in response to the second clock signal. A global reset sub-circuit is configured to reset the pull-up node via the first power supply voltage in response to a frame strobe signal, wherein the frame strobe signal is an effective level signal written between two display frames via the frame strobe signal terminal STV0. The global reset sub-circuit includes a fourth transistor; The first terminal of the fourth transistor is connected to the pull-up node, the second terminal is connected to the first power supply voltage terminal, and the control terminal is connected to the frame strobe signal terminal.

2. The shift register according to claim 1, wherein, The auxiliary noise reduction sub-circuit includes a seventh transistor; The first terminal of the seventh transistor is connected to the signal output terminal, the second terminal is connected to the first power supply voltage terminal, and the control terminal is connected to the second clock signal terminal.

3. The shift register according to claim 1, wherein, The input sub-circuit includes a first transistor; The first terminal of the first transistor is connected to the control terminal and the signal input terminal, and the second terminal is connected to the pull-up node.

4. The shift register according to claim 1, wherein, The reset sub-circuit includes a second transistor; The first terminal of the second transistor is connected to the pull-up node, the second terminal is connected to the first power supply voltage terminal, and the control terminal is connected to the reset signal terminal.

5. The shift register according to claim 1, wherein, The output sub-circuit includes a third transistor and a storage capacitor; The first terminal of the third transistor is connected to the first clock signal terminal, the second terminal is connected to the signal output terminal and the second terminal of the storage capacitor, and the control terminal is connected to the first terminal of the storage capacitor and the pull-up node.

6. The shift register according to claim 1, wherein, The pull-down control sub-circuit includes a fifth transistor; The first terminal of the fifth transistor is connected to the control terminal and the second clock signal terminal, and the second terminal is connected to the pull-down node.

7. The shift register according to claim 1, wherein, The pull-down sub-circuit includes a sixth transistor; The first terminal of the sixth transistor is connected to the pull-down node, the second terminal is connected to the first power supply voltage terminal, and the control terminal is connected to the pull-up node.

8. The shift register according to claim 1, wherein, The first noise reduction sub-circuit includes a tenth transistor; The first terminal of the tenth transistor is connected to the pull-up node, the second terminal is connected to the first power supply voltage terminal, and the control terminal is connected to the pull-down node.

9. The shift register according to claim 1, wherein, The second noise reduction sub-circuit includes an eleventh transistor; The first terminal of the eleventh transistor is connected to the signal output terminal, the second terminal is connected to the first power supply voltage terminal, and the control terminal is connected to the pull-down node.

10. A gate driving circuit comprising a plurality of cascaded shift registers, wherein the shift registers are any one of the shift registers described in claims 1 to 9; wherein, The signal input terminal of the shift register located in the first stage is connected to the first frame control signal input terminal, and the signal input terminals of the shift registers in other stages besides the first stage are connected to the signal output terminals of the corresponding shift registers in the previous stage. The reset signal terminal of the last stage shift register is connected to the second frame control signal input terminal, and the reset signal terminals of the other stages of the shift register are connected to the signal output terminals of the corresponding next stage shift register.

11. An array substrate comprising: A first substrate, comprising: a pixel setting area and a peripheral area surrounding the pixel setting area, wherein a gate driving circuit as described in claim 10 is disposed on the first substrate and located within the peripheral area.

12. The array substrate according to claim 11, wherein, The peripheral area includes a first area and a second area arranged opposite to each other along a first direction; the gate driving circuit is provided in both the first area and the second area; the pixel setting area is provided with multiple rows of gate lines arranged side by side along a second direction; The signal output terminals of each shift register in the gate drive circuit located in the first region are connected one-to-one with the gates located in the odd-numbered rows; The signal output terminals of each shift register in the gate drive circuit located in the second region are connected one-to-one with the gates located in the even-numbered rows.

13. The array substrate according to claim 11, wherein, Each of the gate drive circuits further includes a first clock signal line, a second clock signal line, a first frame control signal line, and a first power supply signal line disposed on the first substrate. For one of the gate drive circuits, the signal input terminal of the first shift register is connected to the first frame control signal line; the first clock signal terminal of each shift register is connected to the first clock signal line, the second clock signal terminal of each shift register is connected to the second clock signal line, and the first power supply voltage terminal of each shift register is connected to the first power supply signal line. The first clock signal line, the second clock signal line, the first frame control signal line, and the first power signal line are located on the side of each shift register away from the pixel setting area.

14. The array substrate according to claim 13, wherein, The input sub-circuit includes a first transistor, the reset sub-circuit includes a second transistor, the output sub-circuit includes a third transistor and a storage capacitor, the pull-down control sub-circuit includes a fifth transistor, the pull-down sub-circuit includes a sixth transistor, the auxiliary noise reduction sub-circuit includes a seventh transistor, the first noise reduction sub-circuit includes a tenth transistor, and the second noise reduction sub-circuit includes an eleventh transistor. For each shift register, the sixth transistor, the tenth transistor, the eleventh transistor, the first transistor, and the second transistor are sequentially arranged along the edge of the array substrate pointing towards the pixel setting area; the storage capacitor is adapted to the eleventh transistor, and the third transistor is located between the storage capacitor and the first transistor; The fifth and seventh transistors of the shift register in this stage are located on the side of the sixth and tenth transistors away from the shift register in the next stage, and the seventh transistor is closer to the storage capacitor than the fifth transistor.

15. The array substrate according to claim 13, wherein, The input sub-circuit includes a first transistor, the reset sub-circuit includes a second transistor, the output sub-circuit includes a third transistor and a storage capacitor, the pull-down control sub-circuit includes a fifth transistor, the pull-down sub-circuit includes a sixth transistor, the auxiliary noise reduction sub-circuit includes a seventh transistor, the first noise reduction sub-circuit includes a tenth transistor, and the second noise reduction sub-circuit includes an eleventh transistor. For each of the shift registers, the sixth transistor, the tenth transistor, the eleventh transistor, the first transistor, and the second transistor are sequentially arranged along the direction from the edge of the array substrate toward the pixel setting area; The fifth and seventh transistors of the shift register in this stage are located on the side of the sixth and tenth transistors away from the shift register of the next stage, and the third transistor is located on the side of the fifth and seventh transistors away from the sixth and tenth transistors; the storage capacitor is located between the third transistor and the first transistor; and the seventh transistor is closer to the storage capacitor than the fifth transistor.

16. The array substrate according to claim 13, wherein, The input sub-circuit includes a first transistor, the reset sub-circuit includes a second transistor, the output sub-circuit includes a third transistor and a storage capacitor, the pull-down control sub-circuit includes a fifth transistor, the pull-down sub-circuit includes a sixth transistor, the auxiliary noise reduction sub-circuit includes a seventh transistor, the first noise reduction sub-circuit includes a tenth transistor, and the second noise reduction sub-circuit includes an eleventh transistor. For each of the shift registers, the sixth transistor, the tenth transistor, the eleventh transistor, the seventh transistor, the first transistor, and the second transistor are arranged sequentially along the direction from the edge of the array substrate toward the pixel setting area; The fifth transistor of the shift register in this stage is located on the side away from the sixth and tenth transistors of the shift register in the next stage, and the third transistor is located on the side away from the sixth and tenth transistors of the fifth transistor; the storage capacitor is located between the third transistor and the first transistor.

17. The array substrate according to any one of claims 14-16, wherein, It also includes a plurality of pixel units disposed on the first substrate and located in the pixel setting area, each pixel unit including a first electrode and a second electrode disposed sequentially along a direction away from the first substrate; The array substrate includes a first metal layer, a first interlayer insulating layer, a semiconductor active layer, a first transparent conductive layer, a second metal layer, a second interlayer insulating layer, and a second transparent conductive layer, which are sequentially disposed along a side away from the first substrate. The first metal layer includes a first clock signal line, a second clock signal line, a first frame control signal line, a first power signal line, a control electrode of the first transistor, a control electrode of the second transistor, a control electrode of the third transistor, a control electrode of the fifth transistor, a control electrode of the sixth transistor, a control electrode of the seventh transistor, a control electrode of the tenth transistor, and a control electrode of the eleventh transistor; The semiconductor active layer includes the active layer of the first transistor, the active layer of the second transistor, the active layer of the third transistor, the active layer of the fifth transistor, the active layer of the sixth transistor, the active layer of the seventh transistor, the active layer of the tenth transistor, and the active layer of the eleventh transistor. The first transparent conductive layer includes a first electrode in each of the pixel units; The second metal layer includes the first and second terminals of the first transistor, the first and second terminals of the second transistor, the first and second terminals of the third transistor, the first and second terminals of the fifth transistor, the first and second terminals of the sixth transistor, the first and second terminals of the seventh transistor, the first and second terminals of the tenth transistor, and the first and second terminals of the eleventh transistor. The second transparent conductive layer includes a second electrode in each of the pixel units.

18. The array substrate according to claim 17, wherein, The second transparent conductive layer further includes a first connection electrode, which connects the first clock signal line to the second terminal of the third transistor through a first via and a second via; the first via penetrates the first interlayer insulating layer and the second interlayer insulating layer. The second via penetrates the second interlayer insulation layer.

19. The array substrate according to claim 17, wherein, The second transparent conductive layer further includes a second connection electrode, which is connected to the first power signal line through a third via; the second electrode of the second transistor, the second electrode of the sixth transistor, the second electrode of the seventh transistor, the second electrode of the tenth transistor, and the second electrode of the eleventh transistor are respectively electrically connected to the second connection electrode through their respective fourth vias; The third via penetrates the first interlayer insulation layer and the second interlayer insulation layer; the fourth via penetrates the second interlayer insulation layer.

20. The array substrate according to claim 17, wherein, The second transparent conductive layer further includes a third connection electrode, which is connected to the signal output of the previous stage shift register through a fifth via, and is connected to the drain of the first transistor through a sixth via, and to the gate of the first transistor through a seventh via; both the fifth via and the seventh via penetrate the first interlayer insulating layer and the second interlayer insulating layer. The sixth via penetrates the second interlayer insulation layer.

21. The array substrate according to claim 17, wherein, The storage capacitor includes a first electrode, a second electrode, and a third electrode stacked together; the first electrode is located in the first metal layer, the second electrode is located in the second metal layer, and the third electrode is located in the second transparent conductive layer.

22. A wearable device comprising an array substrate according to any one of claims 11-21.

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