A method for precisely positioning growth of stacked silicon germanium island chain nanowires

Abstract

The application discloses a method for precisely positioning growth of stacked silicon germanium island chain nanowires, which comprises the following steps: obtaining a guide groove for moving a metal catalytic droplet; depositing at least one group of a-Ge precursor and SiO2 or SiN x stack; etching the stack in the guide groove to form a bevel surface stack structure; preparing a strip-shaped catalytic metal at one end of the guide groove; treating the catalytic metal layer by a reducing gas plasma to convert it into separated metal nanoparticles; covering the whole sample surface with a layer of a-Si precursor matched with the required growth of Si nanowires; and performing an annealing treatment in a vacuum or a gas atmosphere, so that the catalytic metal nanoparticles absorb the a-Si precursor and move along the bevel surface of the a-Si-a-Ge stack to the guide groove, and form a three-dimensional structure of crystalline Si nanowire-crystalline SiGe island-crystalline Si nanowire at the back end of the catalytic metal particles.

Description

Technical Field

[0001] This invention relates to a method for precisely positioning and growing three-dimensional stacked silicon-germanium island chain nanowires, and more particularly to a method for preparing positionable silicon-germanium island chain nanowires using a beveled section of a stacked amorphous precursor. Specifically, the method involves etching a stack of amorphous germanium and silicon nitride or silicon oxide to form a beveled structure, with the amorphous germanium at the beveled section and the subsequently deposited amorphous silicon stack serving as precursors. This enables the precise positioning and growth of spontaneously phase-separated silicon-germanium island chain nanowires, and belongs to the field of silicon-based nanowire preparation technology. Background Technology

[0002] Traditional silicon-based materials have long been a focus of research in both scientific and industrial fields. However, silicon alone has limitations in certain applications, failing to meet the demands for diversity and high performance. To overcome these limitations, silicon-germanium materials have attracted widespread attention as an emerging material, considered a promising candidate for addressing the needs of multiple application areas. Silicon-germanium alloys combine the advantages of both silicon and germanium and are fully compatible with traditional silicon processes. They can, to some extent, compensate for the limitations of single materials, enabling the manipulation of band structure and mobility, as well as improvement of the piezoresistive effect, thus facilitating their application in high-performance TFTs, photoelectric detection, smart skin, thermoelectric functional devices, and more.

[0003] Nanomaterials offer significant advantages over bulk materials in device performance. Industry typically employs a top-down approach to fabricate nanodevices, progressively shrinking material dimensions from a macroscopic scale using mature microfabrication techniques such as photolithography, electron beam lithography, and ion etching. This approach offers advantages like high controllability, high integration, and mature equipment; however, the processes are overly complex, the manufacturing threshold is high, and device costs are high, with limitations on size and shape control. Research, on the other hand, often utilizes a bottom-up approach, which offers significant advantages in morphology and composition control. This approach allows for the fabrication of diverse nanostructures and functional materials, such as controllably prepared quantum dots, nanowires, thin films, and three-dimensional materials, which can then be further functionalized to obtain micro / nano structures and functionalized devices with specific functions.

[0004] The most widely used and representative method for nanowire fabrication and growth is the VLS (gas-liquid-solid) growth mode. VLS nanowires are typically grown in a gaseous precursor environment. Axial heterojunction nanowires can be grown by switching the gas precursor, but obtaining abrupt heterojunction interfaces requires ensuring complete gas switching and a complex catalyst alloying process, and the precise positioning of the heterojunction is difficult. The grown nanowires are vertical arrays or bundles perpendicular to the substrate surface, greatly limiting their application range. The incompatibility between the vertical growth mode and 2D planar device architecture requires additional repositioning or manipulation steps to integrate vertically oriented nanowires into a two-dimensional layout. Typically, micro / nano manipulation methods such as "pick-and-place" are used to collect, transfer, and position nanowires onto planar substrates. However, these micro / nano manipulations are costly and have low compatibility with standard silicon processes, especially the large-scale controllable positioning and integration technology of nanowires, which has been difficult to achieve.

[0005] To better integrate with planar processes and achieve precise positioning, the applicant initially proposed a planar solid-liquid-solid (IP-SLS) growth mode for fabricating heterogeneous or alloy semiconductor nanowires using a multilayer amorphous precursor layer. This mode employs an amorphous silicon (a-Si) / amorphous germanium (a-Ge) multilayer film as the precursor layer, and through the absorption of metal droplets and the planar nanowire growth process, spontaneously phase-separated silicon-germanium island chain nanowire structures are fabricated. However, in implementing the above-mentioned technical solution, the inventors discovered that this method cannot precisely position the growth of SiGe islands; it can only rely on trenches for guidance in one dimension. Furthermore, the periodicity of the SiGe islands is unstable, leading to mispositioning, which significantly limits the application of precise positioning and integration of individual or specific SiGe islands. Summary of the Invention

[0006] This application provides a method for precisely positioning and growing three-dimensional stacked silicon-germanium island nanowires, which solves the problem that existing technologies cannot precisely position and grow SiGe islands and control the size of germanium islands. It realizes a method for precisely positioning and growing three-dimensional stacked SiGe island close-packed array structures with controllable size.

[0007] This application provides a method for precisely positioning and growing stacked silicon-germanium island nanowires, characterized by comprising the following steps: The first step is to perform photolithography or electron beam exposure on the substrate and use ICP or RIE etching processes to obtain guide trenches for the movement of metal catalytic droplets. The second step involves depositing at least one set of a-Ge precursor and SiO2 or SiN using PECVD, CVD, or PVD deposition techniques. x The stacked structure; The third step is to use ICP or RIE etching technology to etch the stacked structure in a direction perpendicular to the guide trench to form a beveled stacked structure that exposes the substrate. Step 4: Using photolithography and evaporation or sputtering metal deposition processes, a strip of catalytic metal is prepared at one end of the guide trench as the growth starting point for Si nanowires; Step 5: At a temperature higher than the melting point of the catalytic metal, the catalytic metal layer is treated with reducing gas plasma to transform it into separated metal nanoparticles. Step 6: Using PECVD or PVD coating technology, cover the entire sample surface with an a-Si precursor layer of thickness matching the required diameter of the Si nanowires to be grown; Step 7: Annealing is performed in a vacuum or gas atmosphere, which allows the catalytic metal nanoparticles to spontaneously absorb the a-Si precursor to grow Si nanowires and move along the guide groove towards the oblique section of the a-Si-a-Ge stack. At the oblique section, the catalytic metal particles spontaneously absorb the a-Si-a-Ge stack, forming spontaneously phase-separated crystalline SiGe islands at their rear ends. The catalytic metal particles continue to absorb the a-Si precursor along the guide groove to grow Si nanowires, ultimately forming at least one three-dimensional loop structure of crystalline Si nanowires-spontaneously phase-separated crystalline SiGe islands-crystalline Si nanowires.

[0008] Preferably, in the first step, the substrate is crystalline silicon, glass, polymer, or a metal thin film substrate covered by a dielectric layer.

[0009] Preferably, in the second step, at least one stacked structure of a-Ge precursor of 2nm-500nm and SiO2 or SiN of 5nm-500nm with the required thickness is deposited using PECVD or PVD coating technology, wherein the total height of the stacked structure is 1-1000 nm lower than the height of the guide trench.

[0010] Preferably, during the etching process in the third step, A mixture of C4F8 and O2 gases is used. The C4F8 gas is used to vertically etch the stacked layers, while the O2 gas is used to horizontally shrink the mask layer until it reaches the substrate, forming a beveled surface with a certain slope. Alternatively, a mixture of CF4 and O2 gases can be used. CF4 gas is used to vertically etch the stacked layers, while O2 gas is used to horizontally etch the mask layer until it reaches the substrate, forming a beveled surface with a certain slope. Alternatively, SF6 gas can be used for isotropic etching until the substrate is etched, forming a beveled surface with a certain slope.

[0011] The thickness of the a-Ge precursor and the slope of the bevel jointly determine the slope length of the exposed a-Ge precursor. The thicker the precursor and the greater the etching slope, the longer the slope length of the exposed precursor.

[0012] Preferably, in the fourth step, the catalytic metal is indium, tin, gallium, aluminum, copper, manganese, silver, iron, platinum, nickel, gold, or zinc and their metal alloys.

[0013] Preferably, in the sixth step, the thickness of the a-Si precursor ranges from 5 to 100 nm, and its thickness determines the diameter of the Si nanowires.

[0014] Preferably, in the fifth step, the temperature is 200℃~500℃, the hydrogen plasma power is 10W~40W, the gas pressure is 100Pa~150Pa, the sample processing time is 2~20min, and the diameter of the catalytic metal droplets is controlled to be 5-800nm.

[0015] The technical solution provided in this application has at least the following technical effects or advantages: 1) This invention solves the key problems of unstable SiGe island periods and inaccurate positioning in SiGe island-chain heterostructure nanowires grown spontaneously using the IP-SLS method. The precisely positioned SiGe islands grown in this invention can be simultaneously arrayed in a planar array and stacked in a three-dimensional close packing array.

[0016] 2) This invention employs isotropic etching or O2 shrinkage etching techniques to form a beveled surface of the dielectric layer / a-Ge stack, upon which an a-Si layer is then deposited. This results in the formation of a-Si / dielectric layer stacks and a-Si / a-Ge stacks at the beveled surface, achieving a-Ge-a-Si stacks with slope lengths ranging from 1 nm to 500 nm. Without the need for additional high-precision photolithography, spontaneously phase-separated SiGe islands can be generated at the intersection of the guide channel and the beveled surface. Therefore, this invention's method can precisely locate and grow SiGe islands at specific positions without requiring high-precision photolithography.

[0017] 3) This invention increases the number of dielectric / a-Ge stack layers and uses etching processes to control the slope of the beveled surface to achieve multiple beveled a-Ge / a-Si stack points, thereby precisely positioning and growing a three-dimensional stacked SiGe island dense array structure. This provides a key technology for the application of next-generation three-dimensional integrated micro-nano optoelectronic devices, and also provides a new technical means for the fields of novel optoelectronic and nanoelectronic devices.

[0018] 4) The preparation method of this invention does not require high-precision photolithography technology (such as electron beam exposure and ultra-deep ultraviolet exposure), and has broad and important application prospects in fields such as photoelectric detection, thermoelectric conversion, single-electron devices, and low-dimensional photonic crystals. Attached Figure Description

[0019] Figure 1 This is a schematic diagram illustrating the specific implementation method of preparing positionable silicon-germanium island chain nanowires using the oblique section of a stacked amorphous precursor in Embodiment 1 of the present invention. Figure 2 This is a schematic diagram of the process for growing SiGe island chain nanowires in a double-layer a-Ge / dielectric layer stack in Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the process for growing SiGe island chain nanowires in multilayer a-Ge / dielectric layer stacking in Embodiment 3 of the present invention. Detailed Implementation

[0020] This invention utilizes a beveled structure of a multilayer amorphous precursor to prepare positionable silicon-germanium island nanowires. In the region where the a-Ge and a-Si layers are isolated by SiO2 or SiNx layers, only uniformly sized Si nanowires grow. SiGe islands are grown at the beveled section of the a-Ge / a-Si stack, achieving SiGe island structures at specific locations without the need for high-precision photolithography. The slope of the dielectric layer / a-Ge bevel obtained by this method is determined by the longitudinal etching degree of C4F8, CF4, or SF6 and the lateral shrinkage degree of O2, thus overcoming the limitations of planar photolithography spatial resolution. The slope length of the exposed a-Ge precursor at the bevel also determines the length (1nm-500nm) of the a-Ge-a-Si stack spontaneously absorbed by the metal catalytic droplet, allowing for the control of the absorption amount of the a-Ge precursor by the catalytic droplet, thereby regulating the size and composition of the generated silicon-germanium islands.

[0021] Based on the above method, this invention increases the number of dielectric / a-Ge stack layers to achieve multiple obliquely shaped a-Ge / a-Si stack sites, thereby precisely positioning and growing a three-dimensional stacked SiGe island close-packed array structure. This special structure achieves dual constraint and control over carrier transport, including size constraints and band structure (such as the Type-II band junction of the silicon-germanium heterojunction). This allows for more effective control over the transmission and detection of electrons, photons, and phonons, providing a key technological foundation for the development of high-performance field-effect transistors, heterojunction bipolar transistors, optoelectronics, thermoelectrics, single-electronic devices, and flexible electronics.

[0022] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods. Example

[0023] This embodiment provides a method for precisely positioning and growing stacked silicon-germanium island nanowires, such as... Figure 1 As shown: Includes the following steps: Step 1: Perform photolithography or electron beam exposure on a thin metal film substrate covered with a dielectric layer, such as crystalline silicon, glass, polymer, or metal, and form steps with a height of approximately 150 nm by ICP or RIE etching. These steps serve as trenches to guide the movement of the metal catalytic droplets. Figure 1 a.

[0024] Step 2: Deposit an a-Ge precursor of approximately 5-10 nm and a SiO2 stack of approximately 10-20 nm using PECVD or PVD deposition techniques, such as... Figure 1 b.

[0025] Step 3: Using ICP or RIE etching technology, etch the stacked layers in a direction perpendicular to the guide trench to form a beveled structure. During the etching process, a mixed gas of C4F8 and O2 is used. C4F8 gas vertically etches the stacked layers, while O2 gas horizontally etches the mask layer until the substrate is reached, forming a beveled surface with a certain slope. Figure 1 c, Figure 1 d is the side view.

[0026] Step 4: Using photolithography and metal deposition processes such as evaporation or sputtering, a 30nm thick indium strip-shaped catalyst layer is prepared at any end of the guiding step as the starting point for Si nanowire growth. Figure 1 e.

[0027] Step 5: Place the sample in a PECVD chamber at a temperature higher than the melting point of indium (400℃), a hydrogen pressure of 130 Pa, and a power of 35 W. Treat the indium catalyst metal layer with hydrogen plasma for 15 min to transform it into separated 100-150 nm indium nanoparticles. Figure 1 f.

[0028] Step 6: Using PECVD or PVD coating technology, coat the entire sample surface with a 10-30nm layer of a-Si precursor, such as... Figure 1 g.

[0029] Step 7: Perform vacuum or gas atmosphere annealing (chamber temperature 560℃) to allow the catalytic metal nanoparticles to spontaneously absorb the a-Si precursor and grow Si nanowires (approximately 50 nm in diameter). The nanoparticles then move along the guide groove towards the oblique section of the a-Si-a-Ge stack. At the oblique section, the catalytic metal particles spontaneously absorb the a-Si-a-Ge stack, forming spontaneously phase-separated crystalline SiGe islands (approximately 150 nm in diameter, with a Ge content as high as approximately 95%) at their rear ends. The catalytic metal particles continue to absorb the a-Si precursor along the guide groove to grow Si nanowires, ultimately forming a three-dimensional structure of crystalline Si nanowires – spontaneously phase-separated crystalline SiGe islands – crystalline Si nanowires, as shown below. Figure 1h. The growth direction of the silicon-germanium island chain nanowires is determined by the guide channel. Spontaneously phase-separated SiGe islands are generated at the intersection of the guide channel and the oblique section of the a-Ge-a-Si stack, which can be precisely located.

[0030] In this embodiment, a beveled layered structure with different slopes is formed by isotropic etching or O2 shrinkage etching. The SiO2 layer is used to isolate the contact between a-Si and a-Ge precursors, allowing only the metal catalytic droplet to absorb the a-Ge precursor at the beveled surface. The a-Ge exposed at the beveled surface contacts the subsequently covered a-Si layer, forming an a-Ge-a-Si layered precursor. When the metal catalytic droplet absorbs the layered amorphous precursor, it stimulates corresponding spontaneous growth regulation, thereby spontaneously growing heterogeneous nanowire island structures with "phase separation". By adjusting the thickness of the a-Ge-a-Si layer, the diameter of this island chain structure (the diameter of SiGe islands is 2-50 times larger than that of Si nanowires) and the degree of phase separation (the Ge content in SiGe islands can reach over 98%) can be effectively controlled. Example

[0031] This embodiment provides a method for precisely positioning and growing SiGe island-chain nanowires, such as... Figure 2 As shown: The specific steps include: Step 1: Perform photolithography or electron beam exposure on a thin metal film substrate covered with a dielectric layer, such as crystalline silicon, glass, polymer, or dielectric layer. Then, use ICP or RIE etching to form steps approximately 150 nm high, which serve as trenches to guide the movement of the metal catalytic droplets. Figure 2 a.

[0032] Step 2: Deposit two cycles of a-Ge precursor and SiO2 stack using PECVD or PVD deposition techniques, such as... Figure 2 b.

[0033] Step 3: Using ICP or RIE etching technology, the stacked layers are etched in a direction perpendicular to the guide trench to form a beveled structure. A mixed gas of CF4 and O2 is used during the etching process. CF4 gas etches the stacked layers longitudinally, while O2 gas laterally etches the mask layer until the substrate is reached, forming a beveled surface with a certain slope. Figure 2 c, Figure 2 d is the side view.

[0034] Step 4: Using photolithography and metal deposition processes such as evaporation or sputtering, a 30nm thick indium strip-shaped catalyst layer is prepared at any end of the guiding step as the starting point for Si nanowire growth. Figure 2 e.

[0035] Step 5: Place the sample in a PECVD chamber at a temperature higher than the melting point of indium (400℃), a hydrogen pressure of 130 Pa, and a power of 35 W. Treat the indium catalyst metal layer with hydrogen plasma for 15 min to transform it into separated 100-150 nm indium nanoparticles. Figure 2 f.

[0036] Step 6: Using PECVD or PVD coating technology, coat the entire sample surface with a 10-30 nm layer of a-Si precursor, such as... Figure 2 g.

[0037] Step 7: Perform vacuum or gas atmosphere annealing (chamber temperature 560℃) to allow the catalytic metal nanoparticles to spontaneously absorb a-Si precursors and grow Si nanowires (approximately 50 nm in diameter). The nanoparticles then move along the guide grooves towards the oblique section of the a-Si-a-Ge stack. At the oblique section, the catalytic metal particles spontaneously absorb the a-Si-a-Ge stack, forming spontaneously phase-separated crystalline SiGe islands (approximately 150 nm in diameter, with a Ge content as high as approximately 95%) at their rear ends. The catalytic metal particles continue to absorb a-Si precursors along the guide grooves to grow Si nanowires, ultimately forming a three-dimensional cyclic structure of two crystalline Si nanowires – spontaneously phase-separated crystalline SiGe islands – crystalline Si nanowires, as shown below. Figure 2 h. Two spontaneously phase-separated SiGe islands are generated at the two intersection points of the guiding channel and the oblique section of the a-Ge-a-Si stack, allowing for precise positioning. In this embodiment, the thickness of the SiO2 layer also determines the spacing between adjacent SiGe islands, i.e., the length of the silicon nanowires between adjacent SiGe islands. Example

[0038] This embodiment provides a method for precisely positioning and growing SiGe island-chain nanowires, such as... Figure 3 As shown: The specific steps include: Step 1: Perform photolithography or electron beam exposure on a thin metal film substrate covered with a dielectric layer, such as crystalline silicon, glass, polymer, or metal, and form steps with a height of approximately 150 nm by ICP or RIE etching. These steps serve as trenches to guide the movement of the metal catalytic droplets. Figure 3 a.

[0039] Step 2: Deposit multiple cycles of a-Ge precursor and SiO2 stack using PECVD or PVD coating technology, such as Figure 3 b.

[0040] Step 3: Using ICP or RIE etching technology, etch the stacked layers in a direction perpendicular to the guide trench to form a beveled structure. During the etching process, SF6 gas isotropically etched until the substrate is reached, forming a beveled surface with a certain slope, such as... Figure 3 c, Figure 3 d is the side view.

[0041] Step 4: Using photolithography and metal deposition processes such as evaporation or sputtering, a 30nm thick indium strip-shaped catalyst layer is prepared at any end of the guiding step as the starting point for Si nanowire growth. Figure 3 e.

[0042] Step 5: Place the sample in a PECVD chamber at a temperature higher than the melting point of indium (400℃), a hydrogen pressure of 130 Pa, and a power of 35 W. Treat the indium catalyst metal layer with hydrogen plasma for 15 min to transform it into separated 100-150 nm indium nanoparticles. Figure 3 f.

[0043] Step 6: Using PECVD or PVD coating technology, coat the entire sample surface with a 10-30 nm layer of a-Si precursor, such as... Figure 3 g.

[0044] Step 7: Perform vacuum or gas atmosphere annealing (chamber temperature 560℃) to allow the catalytic metal nanoparticles to spontaneously absorb a-Si precursors and grow Si nanowires (approximately 50 nm in diameter). The nanoparticles then move along the guide grooves towards the oblique section of the a-Si-a-Ge stack. At the oblique section, the catalytic metal particles spontaneously absorb the a-Si-a-Ge stack, forming spontaneously phase-separated crystalline SiGe islands (approximately 150 nm in diameter, with a Ge content as high as approximately 95%) at their rear ends. The catalytic metal particles continue to absorb a-Si precursors along the guide grooves to grow Si nanowires, ultimately forming a three-dimensional cyclic structure of multiple crystalline Si nanowires – spontaneously phase-separated crystalline SiGe islands – crystalline Si nanowires, as shown below. Figure 3 h. Multiple spontaneously phase-separated SiGe islands are generated at multiple intersection points between the guide channel and the oblique section of the a-Ge-a-Si stack, and can be precisely located.

[0045] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements can be made without departing from the principle of the present invention, and these improvements should also be considered within the scope of protection of the present invention.

Claims

1. A method for precisely positioning and growing stacked silicon-germanium island nanowires, characterized in that, It includes the following steps: The first step is to perform photolithography or electron beam exposure on the substrate and use ICP or RIE etching processes to obtain guide trenches for the movement of metal catalytic droplets. The second step involves depositing at least one set of a-Ge precursor and SiO2 or SiN using PECVD or PVD deposition technology. x The stacked structure; The third step is to use ICP or RIE etching technology to etch the stacked structure in a direction perpendicular to the guide trench to form a beveled stacked structure that exposes the substrate. Step 4: Using photolithography and evaporation or sputtering metal deposition processes, a strip of catalytic metal is prepared at one end of the guide trench as the growth starting point for Si nanowires; Step 5: At a temperature higher than the melting point of the catalytic metal, the catalytic metal layer is treated with reducing gas plasma to transform it into separated metal nanoparticles. Step 6: Using CVD or PVD coating technology, cover the entire sample surface with an a-Si precursor layer of thickness matching the required diameter of the Si nanowires to be grown; Step 7: Annealing is performed in a vacuum or gas atmosphere, which allows the catalytic metal nanoparticles to spontaneously absorb the a-Si precursor to grow Si nanowires and move along the guide groove towards the oblique section of the a-Si-a-Ge stack. At the oblique section, the catalytic metal particles spontaneously absorb the a-Si-a-Ge stack, forming spontaneously phase-separated crystalline SiGe islands at their rear ends. The catalytic metal particles continue to absorb the a-Si precursor along the guide groove to grow Si nanowires, ultimately forming at least one three-dimensional loop structure of crystalline Si nanowires-spontaneously phase-separated crystalline SiGe islands-crystalline Si nanowires.

2. The method for precisely positioning and growing stacked silicon-germanium island nanowires according to claim 1, characterized in that, In the first step, the substrate is crystalline silicon, glass, polymer, or a metal thin film substrate covered by a dielectric layer.

3. The method for precisely positioning and growing stacked silicon-germanium island nanowires according to claim 1, characterized in that, In the second step, at least one stacked structure of a-Ge precursor and SiO2 or SiNx of the required thickness is deposited using PECVD or PVD coating technology, wherein the total height of the stacked structure is 1 to 1000 nanometers lower than the height of the guide trench.

4. The method for precisely positioning and growing stacked silicon-germanium island nanowires according to claim 1, characterized in that, During the etching process in the third step, A mixture of C4F8 and O2 gases is used. The C4F8 gas is used to vertically etch the stacked layers, while the O2 gas is used to laterally shrink the mask layer until it is etched to the substrate, forming a beveled surface with a set slope. Alternatively, a mixture of CF4 and O2 gases can be used. CF4 gas is used to vertically etch the stacked layers, while O2 gas is used to laterally etch the mask layer until it reaches the substrate, forming a beveled surface with a set slope. Alternatively, SF6 gas can be used for isotropic etching until the substrate is etched, forming a beveled surface with a set slope.

5. The method for precisely positioning and growing stacked silicon-germanium island nanowires according to claim 1, characterized in that, During the etching process in the third step, The slope of the oblique section is adjusted to control the slope length of the exposed a-Ge precursor, thereby controlling the length of the spontaneous absorption of the a-Ge-a-Si stack by the catalytic metal droplet and the amount of a-Ge precursor absorbed, ultimately controlling the size and composition of the silicon-germanium islands generated, wherein the length is 1~500nm.

6. The method for precisely positioning and growing stacked silicon-germanium island nanowires according to claim 1, characterized in that, In the fourth step, the catalytic metal is indium, tin, gallium, aluminum, copper, manganese, silver, iron, platinum, nickel, gold or zinc and their metal alloys, and the thickness of the catalytic metal ranges from 2nm to 200nm.

7. The method for precisely positioning and growing stacked silicon-germanium island nanowires according to claim 1, characterized in that, In the sixth step, the thickness of the a-Si precursor ranges from 5 to 100 nm, and its thickness determines the diameter of the Si nanowires.

8. The method for precisely positioning and growing stacked silicon-germanium island nanowires according to claim 1, characterized in that, In the fifth step, the temperature is 200℃~500℃, the hydrogen plasma power is 10W~40W, the gas pressure is 100Pa~150Pa, the sample processing time is 2~20min, and the diameter of the catalytic metal droplets is controlled between 5nm and 800nm.

Images