Spread spectrum video transmission source driver integrated with the display panel

Abstract

The video display unit includes a display panel with gate drivers and source drivers. Each source driver receives an encoded analog signal representing a video stream on a transmission medium and decodes the signal to produce samples for output to the display. Gate driver control signals synchronize the gate driver with the source drivers. The source drivers are partially or entirely integrated with the display panel glass. The amplifier and level shifter for each source driver are implemented on the panel glass, while the collector and decoder are not. Alternatively, the amplifier, shifter, and collector are implemented on the panel glass, while the decoder is not. Or, the amplifier, shifter, collector, and decoder for each source driver are all implemented on the panel glass. The source drivers can drive the displays of mobile devices. Thin-film transistors are used to implement the source drivers on the glass.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 317,336, filed March 7, 2022, entitled “SPREAD-SPECTRUM VIDEO TRANSPORT SOURCE DRIVER INTEGRATION WITH DISPLAY GLASS”; U.S. Provisional Patent Application No. 63 / 346,064, filed May 26, 2022, entitled “SPREAD-SPECTRUM VIDEO TRANSPORT SOURCE DRIVER INTEGRATION WITH DISPLAY GLASS”; and U.S. Patent Application No. 18 / 117,288, filed March 3, 2023, entitled “SPREAD-SPECTRUM VIDEO TRANSPORT SOURCE DRIVER INTEGRATION WITH DISPLAY PANEL”, which are incorporated herein by reference.

[0003] This application incorporates, by reference, U.S. Application No. 15 / 925,123 (filed March 19, 2018, File No.: HYFYP001), U.S. Application No. 16 / 494,901 (filed September 17, 2019, File No.: HYFYP002), U.S. Application No. 17 / 879,499 (filed August 2, 2022, File No.: HYFYP003), U.S. Application No. 17 / 686,790 (filed March 4, 2022, File No.: HYFYP004AX1), U.S. Application No. 17 / 887,849 (filed August 15, 2022, File No.: HYFYP006), and U.S. Application No. 1 (filed June 28, 2022, File No.: HYFYP006). U.S. Application No. 7 / 851,821 (Case No.: HYFYP007), U.S. Application No. 63 / 421,062 (Case No.: HYFYP008P2) filed on October 31, 2022, U.S. Application No. 17 / 900,570 (Case No.: HYFYP009) filed on August 31, 2022, U.S. Application No. 17 / 946,479 (Case No.: HYFYP010) filed on September 16, 2022, U.S. Application No. 18 / 095,801 (Case No.: HYFYP011) filed on January 11, 2023, and U.S. Application No. 18 / 098,612 (Case No.: HYFYP013) filed on January 18, 2023. Technical Field

[0004] This invention generally relates to displaying video on a display panel of a display unit. More particularly, this invention relates to a source driver integrated with the display panel. Background Technology

[0005] Image sensors, display panels, and video processors are constantly racing to achieve larger formats, deeper colors, higher frame rates, and higher resolutions. Local site video transmission suffers from performance scalability bottlenecks that limit throughput and reduce performance, while consuming more cost and power. Eliminating these bottlenecks can bring benefits.

[0006] For example, as display resolution increases, the data rate at which video information is transmitted from the video source to the display screen grows exponentially: from 3Gbps for Full HD a decade ago to 160Gbps for new 8K screens. Typically, a 4K display requires approximately 18Gbps of bandwidth at 60Hz and 40Gbps at 120Hz. Furthermore, an 8K display requires 80Gbps at 60Hz and 160Gbps at 120Hz.

[0007] To date, data has been transmitted digitally using a variant of Low Voltage Differential Signaling (LVDS) data transmission, with each signal pair using a bit rate of 16 Gbps, and these signal pairs are parallelized to achieve the desired total bit rate. With a wiring delay of 5 ns / m, the wavelength per bit on the digital connection is 12 mm, which is close to the limit of this type of connection and requires extensive data synchronization to obtain usable data. This digital information then needs to be converted into analog pixel information using an ultra-fast digital-to-analog (D-to-A) converter on the display's source driver.

[0008] Currently, D-to-A converters use 8 bits; soon, D-to-A conversion may require 10 or even 12 bits, and then accurate conversion at a sufficiently fast data rate will become very difficult. Therefore, displays must complete the D-to-A conversion in a very short time, and the available time for conversion also becomes shorter, leading to issues with the stability of D-to-A conversion.

[0009] Furthermore, today's large-scale display architectures consist of large-area active matrix display pixels. In the past, display drivers (source and gate) were mounted on the edge of the glass, rather than on the glass itself, providing the source and gate drive circuitry. Further integration of drive electronics onto the glass has stalled due to the complexity of high-speed digital circuitry and the large area required for D-to-A conversion. For example, digital transmission to the source drive circuitry operates at around 3 GHz, a frequency too high for integration onto the glass.

[0010] To drive a full-resolution LCD or OLED screen, numerous display drivers must be connected to the edge of the display. A typical driver has approximately 1,000 outputs, so a typical 4K display requires 4,000 x RGB = 12,000 connections, which translates to 12 source drivers. Increasing the panel resolution to 8K would increase this number to 24 source drivers. Data rates, synchronization difficulties, and bonding logic have made further development in this direction challenging.

[0011] Therefore, new devices and technologies are needed to integrate the source driver of the display with the display panel itself. Summary of the Invention

[0012] To achieve the above, and in accordance with the purpose of this invention, a source driver for a display panel in a display unit is disclosed, which is integrated with the glass of the display panel.

[0013] Video signals are lists of luminance values. It has been recognized that precisely maintaining fixed-bit-width (i.e., digital) luminance values ​​is inefficient for video transmission because voltage provides a greater dynamic range and bit-accurate reproduction is not required. Therefore, this disclosure will transmit the display panel video signal as an encoded analog signal rather than as a digital signal.

[0014] Advantages include reduced power consumption. In existing technologies, power consumption significantly limits system performance. Furthermore, the embodiments offer noise immunity and EM stealth, with EMI / RFI emissions from the display panel well below specified limits. Additionally, the encoded analog signals can be transmitted over much greater distances than conventional Ethernet or HDBaseT signals. Moreover, while conventional transmissions use expensive mixed-signal processing for high-speed digital circuits, the embodiments of this invention use fully devalued analog processing for greater flexibility and lower production costs.

[0015] Due to the complexity of high-speed digital circuits and the large area required for D-to-A conversion, existing source drivers have been mounted on the edge of the display glass panel (but not integrated with it). This invention enables the integration of the source driver with the glass itself because a D-to-A converter is not required in the source driver, and because of the low-frequency sampling transmission of the SSVT signal; for example, the SSVT video signal arrives at the decoder at a frequency far below 3 GHz for digital video signals.

[0016] SSVT video signals can be transmitted along the edge of the display glass using relatively simple lines and are insensitive to interference, which is very different from the existing Vx1 interface. The lower sampling rate makes it possible to design the analog electronics (far less complex) required for the source drivers on the edge of the TFT panel itself on the display panel glass. Building the source driver circuitry on the glass edge allows these circuits to be integrated onto the glass: a decoder (which receives analog samples directly via the SSVT signal); a grading library (which collects analog voltages); level shifters and amplifiers (which provide the correct voltage range and voltage inversion); and column drivers (which provide the necessary current to charge the display source line capacitors).

[0017] This invention can be used on any active matrix display substrate. It is best suited for substrates with high mobility (e.g., low-temperature polycrystalline silicon (LTPS) or indium ionomer oxide (IGZO) TFTs). The resulting display panel can be connected to the GPU via signal cables and power supplies of arbitrary length. No further electronics connecting to the glass are required, providing significant opportunities for further reductions in edge width and module thinning.

[0018] This invention is particularly applicable to high-resolution, high dynamic range displays used in computer systems, televisions, monitors, machine vision systems, automotive displays, virtual or augmented reality displays, and the like. Attached Figure Description

[0019] The present invention and its further advantages can be better understood by referring to the following description taken in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 This demonstrates the use of conversion and encoding within the display unit to transmit SSVT analog video signals to the display panel.

[0021] Figure 2 An example of a source driver is shown.

[0022] Figure 3 A detailed view of the decoding unit of the source driver is shown.

[0023] Figure 4 It is the logic diagram of one of the four decoders.

[0024] Figure 5 This is a diagram showing a representative decoder track circuit.

[0025] Figure 6 The implementation of the integrated source driver functionality in various embodiments is shown.

[0026] Figure 7A The placement of the source driver components on the display panel glass is shown.

[0027] Figure 7BThe placement of the entire source driver on the display panel glass is shown.

[0028] Figure 8 The placement of the SSVT signal is shown when implementing Embodiment 3.

[0029] Figure 9 An array of source drivers that can be integrated with the display glass of a display unit is shown.

[0030] Figure 10 Showing from Figure 9 One of the decoders.

[0031] Figure 11 It shows Figure 9 The collector in the process.

[0032] Figure 12 This demonstrates how analog values ​​can be encoded within an encoder and then transmitted via an electromagnetic path.

[0033] Figure 13 A novel encoding technique suitable for signal samples as digital values ​​is shown.

[0034] Figure 14 It shows the use of Figure 12 Decoding of the analog input level encoded by the encoder.

[0035] Figure 15A The use of the analog encoder and the corresponding analog decoder is shown.

[0036] Figure 15B The use of a digital encoder and a corresponding analog decoder is shown.

[0037] Figure 15C This demonstrates the use of a digital decoder to decode an encoded analog signal that has arrived via an electromagnetic path on a transmission medium.

[0038] Figure 16 A simulation of the SSVT waveform transmitted via the electromagnetic path is shown.

[0039] Figure 17 This is a block diagram showing the transmission of video samples within a mobile phone.

[0040] Figure 18 This illustrates a specific embodiment of how a collector and amplifier can be implemented for one of the decoders. Detailed Implementation

[0041] Existing technology transmits digital video signals to a display panel within a display unit. For the purposes of this disclosure, "display panel" refers to the internal portions (commonly referred to as "glass") of a display unit that realize the pixels that generate light for viewing, while "display unit" refers to the entire (typically) rectangular housing that includes the display panel, panel assembly, frame, drivers, cables, and associated electronic components for generating video images. Generally, a mass-producible display panel containing O(N^2) pixels is controlled by O(N) voltages, each updating O(N) times (the reciprocal of the frame rate) for each display interval.

[0042] Digital video signals are typically input to the System-on-Chip (SoC) of the display unit via an HDMI connector; input can also be via an RJ45 connector, etc. The SoC transmits digital signals to the display panel via the V-by-One HS standard, or via MLVDS, DDI, etc. The display unit includes a timing controller (TCON), bit serial transmission (e.g., SerDes, LVDS, or CEDS), and any number of DACs (Digital-to-Analog Converters) within the source drivers of the display panel, which convert digital signals into analog signals for input to the pixels of the display panel. Control signals from the SoC to the TCON provide video framing flags (Vsync, Hsync, etc.), configuration parameters, gate driver control signals, FRC grayscale, driver parameter settings, backlight control, contrast control, etc.

[0043] In addition to the drawbacks mentioned above, this type of display connection digital transmission suffers from higher EMI / RFI issues due to its reliance on high-speed digital circuitry, requires high power, is difficult to synchronize, and must be implemented using relatively expensive integrated circuit processes. Furthermore, for example, an 8K V-by-One HS requires 48 3.5Gbps wire pairs.

[0044] Furthermore, these shortcomings also exist in local site video connections and the aforementioned display connections. The GPU generates video signals, which are digitally transmitted to the display unit (via V-by-OneHS, MLVDS, DDI, etc.), where a DAC within the source driver converts the signal back into an analog signal. Typically, the GPU chip is located on the system / microprocessor board, as close to the microprocessor as possible.

[0045] Existing source drivers typically have 900 to 1000 outputs, or more, and there are one to twenty such source drivers within a typical display unit. Each source driver has a digital section and an analog section including a DAC. The DAC outputs a voltage directly to the glass of the display via a buffer to drive the source of each pixel, as is known in the prior art. Most of each source driver is used by digital electronics that require a data rate ten times higher than the associated analog signal to be supplied to the column lines of the display. This is disadvantageous because the total power consumed by any (digital or analog) circuitry depends linearly on the switching frequency, typically the clock frequency.

[0046] Therefore, it is recognized that performing the digital-to-analog conversion of digital video signals as close as possible to the SoC, GPU, or digital video processor will not only eliminate the need for a DAC within the source driver of the display panel, but will also realize the aforementioned advantages of transmitting analog signals instead of digital signals within the display unit. Furthermore, it is further recognized that integrating the novel source driver (decoding analog video signals) of this disclosure with the display panel itself can produce further advantages.

[0047] The digitization of the video signal is performed at the system's signal source (usually at the GPU), and then the digital signal is transmitted to the display source driver, typically using a combination of high-performance cabling systems. The digital signal is then converted back to an analog signal to be loaded onto the display pixels. Therefore, the sole purpose of digitization is the transfer of data from the video source to the display pixels.

[0048] Furthermore, it was recognized that performing D-to-A conversion at points requiring less power is much easier than performing it at the endpoints that must drive the display panel. Therefore, instead of transmitting the digital signal all the way from the video source to the display panel that needs to generate the analog signal, we transmit the analog signal to the display at a sampling rate that is typically much lower than that used for digitization. This means that we can now sample only a few megabits per second in the case of analog signals, instead of sending gigabits of data per second over multiple lines, thus reducing the bandwidth of the channels that must be used.

[0049] Therefore, we recognize the advantage of (as much as possible) avoiding digitization and transmitting analog signals from the video source to the source driver, from within the display unit to the source driver, or from an intermediate location to the source driver. This transmission can be accomplished using SSVT encoding, resulting in precise analog voltages being decoded again at the source driver. Analog data has higher precision, thus eliminating the need for high bit depths. This means the sampling rate is at least ten times lower than digital transmission, leaving more bandwidth for expansion. Furthermore, the bits in digital data must be well-defined, meaning they are sensitive to errors and noise and need to be able to detect high and low points very accurately, whereas the proposed analog transmission is less sensitive. This means the quality of the cable (e.g., from one side to the other in the display unit) does not need to be very high.

[0050] We further recognize that existing source drivers for input digital signals are located at the edge of the display panel glass (but not within the glass), and the size and complexity of these source drivers (primarily due to their D-to-A converters) prevent their integration with the display panel glass. Therefore, we realize that our novel source driver, which decodes analog signals to generate the required voltage on the display panel, can be integrated with the display glass itself due to its smaller size and complexity, and we disclose the systems and techniques for performing this integration.

[0051] Display connectivity - conversion within the display unit

[0052] As described above, digital video signals can be converted to analog video signals near the SoC of the display unit. In this embodiment, the conversion and encoding of digital video signals into analog SSVT signals occurs within the display unit itself, thereby improving display connectivity. The digital video signal is input to the SoC via an HDMI connector (or an RJ45 connector, etc.). The digital signal is then transmitted via Vx1 to an integrated circuit, where an SSVT transmitter converts the digital video signal into a spread spectrum video transmission (SSVT) signal, which is then transmitted to the display panel. As described above, control signals from the SoC provide gate driver control signals, FRC grayscale, driver parameter settings, backlight control, contrast control, etc. The display panel is associated with an SSVT receiver (implemented as any number of integrated circuits) embedded within the source driver, which then decodes the analog SSVT signal into the analog signal desired by the display panel, as will be described in more detail below. In one embodiment, the display panel driver chipset includes both of the aforementioned integrated circuits.

[0053] The advantages of this embodiment are: no DAC (digital-to-analog converter) is needed on the display panel; mature IC technology can be used; EMI / RFI emissions are far below the prescribed limits; only half the power is required; synchronization is easier; and an 8K display only requires 8 wire pairs at 1.6 GHz or 18 wire pairs at 680 MHz. In contrast, existing technologies for transmitting digital video signals from a system-on-a-chip (SoC) within the display unit (e.g., must be implemented in relatively expensive IC processes, and EMI / RFI emissions are a problem due to reliance on high-speed digital circuitry; and an 8K / 60Hz display would require 8 wire pairs at 16 Gbps or 36 wire pairs at 3.5 Gbps.

[0054] Local site video connectivity - conversion outside the display unit

[0055] As described above, digital video signals can be converted to analog video signals near the digital video processor of a local site video system. In this embodiment, the conversion and encoding of the digital video signal into an analog SSVT signal occurs outside the display unit; therefore, the input to the display unit is an analog SSVT signal. The core AI / ML GPU generates the digital video signal, and an SSVT transmitter converts the digital signal into an analog signal and encodes it into an SSVT signal, which is transmitted to the display unit, and thus to the display panel. The display unit includes an SSVT receiver embedded within a source driver, which then decodes the SSVT signal into the analog signal desired by the display panel, as will be described in more detail below.

[0056] The GPU that processes video data can be located within a computer. Once converted and encoded by an SSVT transmitter, the analog signal is transmitted to the display unit. The display unit may be nearby, 20 meters away, or even further. Therefore, the information path from the graphics processor or video processor (which may actually be the computer) goes directly to the display unit via numerous transport connections, without any digitization occurring anywhere along that data path. Initially, the video signal may originate from a camera or similar device, from where it is transmitted to the GPU. The video signal may also originate from a camera, video processor, or internet modem, where it can also be converted to an analog signal using an SSVT transmitter.

[0057] Advantageously, a DAC (Digital-to-Analog Converter) is not required within the display unit. Furthermore, the further upstream the display unit from which we perform D-to-A conversion and encoding to the SSVT signal (i.e., not within the display unit itself), the greater the benefit we gain, because we do not need to perform compression to transmit compressed digital video signals over the HDMI cable. In this particular embodiment, we process the full-resolution display information in the GPU, then perform conversion and encoding on the GPU chip, and then all transmission is via the relatively low-frequency SSVT signal until it reaches the display unit. In this case, we process the entire display resolution from the GPU source to the display unit endpoint at full frame rate without any internal compression.

[0058] Display connectivity details

[0059] Figure 1 A display panel 550 is shown that transmits SSVT video signals to a display unit 500. In one embodiment, the conversion and encoding of digital video signals into analog SSVT signals occurs within the display unit 500 itself, thereby improving display connectivity. The SoC and TCON of the display unit are not shown. There may be three or more commercial implementations: a discrete implementation where the SSVT transmitter is embedded in a mixed-signal integrated circuit, and the TCON and SoC are discrete components (the SSVT transmitter is inserted between a legacy TCON and the source driver described herein); a hybrid implementation where the SSVT transmitter is integrated with the TCON in a single IC, and the SoC is discrete; and a fully integrated implementation where as much functionality as possible is integrated into a custom mixed-signal integrated circuit (the SSVT transmitter is integrated with the TCON and SoC).

[0060] In this example, display panel 550 is located within panel frame 551 as shown, which is located within a 55” HDR 4K60 display unit. Display panel 550 can be any size display panel, can be one or more displays in a VR headset, can be a head-up display (HUD) where the display projects onto a windshield, sun visor screen, etc.

[0061] Using SSVT signals within the display unit offers significant advantages, even if the input signal is not SSVT, i.e., it is a digital video signal. In existing display units, HDMI signals are decompressed to obtain complete, full-bit-rate digital data, which must be transmitted from the receiving end of the display unit to all locations within the unit. For 64-inch or 80-inch monitors, these connections can be quite long; the digital data must be transmitted from one side of the unit where the input is located to the other side where the final display source driver is located. Therefore, it is advantageous to internally convert the digital signal to SSVT and then send that SSVT signal to all locations within the display unit where the source driver is located. Advantages include the ability to use lower frequencies, lower EMI signals, and the benefits of embedded synchronous / low-latency initialization.

[0062] Figure 1 The diagram also shows an SSVT transmitter 540 that generates an SSVT signal 592 for the source driver 586. This includes a rigid PCB 582 and various flexible PCBs 584, each holding a source driver 586 that generates a source voltage for the display panel. As will be described in more detail below, a signal 608 optionally provides information about the display panel to the transmitter 540 to assist in the encoding of the SSVT signal. How these source drivers 586 are integrated with the panel glass is described below.

[0063] The generation of the gate driver control signal 590 for the gate driver 560 can be performed by a timing controller (or by other specific hardware) and can be based on synchronization information from the source driver. Many variations of the gate control signal are possible. The gate signal is a separate signal at the source (start-up pulse + clock + control), but can be transmitted along with the SSVT signal, such as... Figure 2 and 3As shown (but not requiring encoding). It can also be extracted from the embedded clock signal of the SSVT signal (decoder -> framing -> aligner). However, with modern "gate-on-array" panels, the gate signal needs to be modified into multiple clock pulses via a dedicated clock generation IC, reducing the likelihood of extraction from the SSVT clock signal (but proper aligner functionality can still be used). Therefore, in an alternative embodiment, the gate signal 590 does not travel with the SSVT signal. Typically, the source driver input timing is coordinated upstream of the TCON with the gate driver timing. In one particular implementation, the wiring loop transmits the gate driver control signal in parallel with the source driver signal, but the gate driver control signal does not enter the source driver and is not generated by the source driver. However, signal 590 can propagate through the flexible foil connected to the source driver, or even through the source driver itself in another embodiment. The various embodiments below illustrate the gate signal traveling via the source driver, although such an arrangement is not required.

[0064] SSVT encoder example

[0065] Typically, the SSVT transmitter and SSVT receiver (in this case, embedded in the source driver 586) are connected via a transmission medium. In various embodiments, the transmission medium can be a cable (such as HDMI, flat cable, fiber optic cable, metallic cable, non-metallic carbon rail flexible cable), or it can be wireless. The transmission medium may have multiple EM paths, one path per encoder. The SSVT transmitter includes a distributor and multiple encoders. The SSVT receiver will include multiple decoders, the same number as the encoders. The number of paths on the transmission medium can be widely any number, from one to more than one. In this example, the medium will be a combination of cables, traces on a PCB, internal IC connections, and other media used by those skilled in the art.

[0066] During operation, a time-series video sample stream containing color values ​​and pixel-related information is received from a video source at the display unit 500 and passed to the SSVT transmitter 540 via the SoC and TCON (where the SoC performs processing known in the art). The number and content of the input video samples received from the video source depend on the color space operated at the source (and the samples may be black and white). Regardless of the color space used, each video sample represents the amount of light sensed or measured in the specified color space.

[0067] When the input digital video sample stream is received within the SSVT transmitter, the input digital video samples are repeatedly (1) assigned to encoder input vectors according to a predetermined arrangement (one vector per encoder), and (2) encoded by applying SSDS-based modulation to each of the multiple encoder input vectors using orthogonal coding to generate multiple composite SSVT signals with noise-like characteristics (one analog signal per encoder). The analog SSVT signals are then transmitted over the transmission medium (3), one signal per path.

[0068] For illustrative purposes, one possible permutation implemented by the allocator to construct four vectors V0, V1, V2, and V3 is an arrangement where each vector includes N color information samples. In this example, the exposure color information for the two sets of samples is "RGB". The exposure RGB samples of this sample set are assigned to vectors V0, V1, V2, and V3 from left to right. In other words, the "R", "G", and "B" values ​​of the leftmost sample and the "R" signal of the next set of samples are assigned to vector V0, while the next (from left to right) "G", "B" and the next sample's "R" and "G" values ​​are assigned to V1, the next (from left to right) "B", "R", "G", and "B" values ​​are assigned to vector V2, and the next (from left to right) "R", "G", "R", and "R" values ​​are assigned to vector V3. Once the fourth vector V3 has been assigned its signal, the above process is repeated until each of the four vectors V0, V1, V2, and V3 has N samples. In various embodiments, the number of N samples can vary widely.

[0069] As an example, consider an embodiment with N=60. In this example, the total number of N samples included in the four vectors V0, V1, V2, and V3 is 240 (60 × 4 = 240). The four encoder input vectors V0, V1, V2, and V3, when fully established, include samples from 80 different sample sets (where S = 3) (240 / 3 = 80). In other words:

[0070] • Vector V0 includes samples P0,N0 to P0,N N-1 ;

[0071] • Vector V1 includes samples P1,N0 to P1,N N-1 ;

[0072] • Vector V2 includes samples P2,N0 to P2,N N-1 ;as well as

[0073] Vector V3 includes samples P3,N0 to P3,N N-1 .

[0074] It should be understood that the above examples are illustrative only and should not be construed as restrictive. The number of samples N can be greater than or less than 60. Furthermore, it should be understood that the exposed color information for each sample set can be any color information (e.g., Y, C, Cr, Cb, etc.), not limited to RGB. The number of EM paths on the transmission medium can also vary widely. Correspondingly, the number of vectors V and the number of encoders can also vary widely from 1 to any number greater than 1. It should also be understood that any permutation scheme can be used to construct the input vector.

[0075] Then, use the methods described in this article and as follows Figure 12-16 The encoding scheme shown encodes each vector of N samples by its corresponding encoder, producing L output levels in parallel. As previously mentioned, the encoding can be analog (with the DAC placed before the encoder) or digital (where the L levels are converted to analog by the DAC before transmission). The L analog output levels are then transmitted as part of the SSVT signal through its EM path to the SSVT receiver, in this case, the SSVT receiver is embedded in the source driver 586.

[0076] Display panel source driver

[0077] Figure 2 A display source driver 586 (others not shown) in an array of source drivers is illustrated. As shown, multiple source drivers can be cascaded; these multiple source drivers then drive the display panel. As shown, source driver 586 does not require a DAC (in the signal path, used to convert digital samples into analog samples for display), which is necessary in prior art source drivers. The input to the SSVT receiver of each source driver is an analog SSVT signal 592, which has been encoded upstream as described above. In an alternative embodiment, each source driver would have its own SSVT signal.

[0078] Each SSVT receiver (e.g., 611, 612, etc.) includes a decoder, a reconstruction library, and a hierarchy library (such as...). Figure 3 The decoder 0 that receives the SSVT signal 702 and its corresponding reconstruction and hierarchical libraries are part of this. Each SSVT receiver decodes the SSVT signal (described in more detail below) and outputs a large number of reconstructed analog voltage samples 612 in parallel from its collector 746 (the number of output samples corresponds to the number of outputs from the source driver). Since these analog outputs 612 may not be within the voltage range required by the display panel, they can be input to a level shifter 620, which uses analog transformation to shift the voltage to the voltage range used to drive the display panel, and amplification may also occur. Any suitable level shifter known in the art can be used, such as latch-type or inverter-type. Level shifting typically occurs in column drivers.

[0079] For example, the voltage range from the SSVT receiver can be 0 to 1V, and the voltage range from the level shifter can be -8 to +8V (using the inversion signal 622 to instruct the level shifter to toggle the voltage every other frame, i.e., one frame will be -8 to 0V, and the next frame will be 0V to +8V). In this way, the SSVT signal does not need to toggle its voltage every frame; the SSVT receiver provides a positive voltage range (e.g.), and the level shifter toggles the voltage every other frame as intended by the display panel. The SSVT receiver can also implement line inversion and dot inversion. The inversion signal tells the level shifter which voltage toggle. Some display panels, such as OLEDs, do not require this voltage toggle every other frame; in this case, the inversion signal is unnecessary, and the level shifter does not toggle the voltage every other frame. Display panels such as LCDs do require this voltage toggle. The inversion signal 622 is recovered from the SSVT receiver, which will be explained below.

[0080] The inputs to the level shifter 620 can also be gain and gamma values; gain determines how much amplification is applied, and the gamma curve links luminous flux to perceived brightness, linearizing the human optical perception of luminous flux. Typically, in prior art source drivers, gain and gamma are setpoints determined by the manufacturing characteristics of the display panel. In the analog level shifter 620, gain and gamma can be implemented as follows. In one embodiment, gamma is implemented in the digital portion of the system, and level shifting and gain are implemented in the source driver by setting the output stage amplification. In the case of gamma, it can also be implemented in the output driver by implementing non-linear amplification characteristics. (Another gamma correction is also performed in the timing controller or on-chip system, but this gamma correction is not described here.)

[0081] Once shifted, the samples are fed into amplifier 621, which amplifies each sample to the correct voltage range required for a particular display panel. Once amplified, the samples are output 634 and used to drive the source electrodes in the corresponding columns of the display panel, as known in the art.

[0082] In order for the SSVT signal to be correctly encoded for final display on a specific display panel, the GPU (or other display controller) or any entity performing SSVT encoding requires various physical characteristics or properties of that display panel. These physical characteristics are labeled 608 and include resolution, subdivision, backlight layout, color profile, aspect ratio, and gamma curve. Resolution is a constant for a specific display panel; subdivision refers to the way the plane of the panel is divided into regions in a regular, predetermined manner, in pixels; backlight layout refers to the resolution and diffusion characteristics of the backlight panel; color profile is the precise luminance response of all primary colors, providing accurate colors for the image; and the aspect ratio of the display panel will have discrete, known values.

[0083] These physical characteristics of a specific display panel can be transmitted, hard-connected, or provided to a specific display controller in various ways. Figure 1 In one example shown, signal 608 provides the values ​​of these physical characteristics directly from the display panel (or from another location within the display unit) to SSVT transmitter 540. Alternatively, an SSVT transmitter embedded within a specific display unit hardcodes these values ​​within the transmitter. Or, a specific display controller is used only for a specific type of display panel, and its characteristic values ​​are hardcoded into that display controller.

[0084] The input to the display panel can also be a backlight signal 604 indicating when and at what level the backlight LEDs are turned on. In other words, it is typically a low-resolution representation of the image, meaning that the backlight LEDs need to be lit to illuminate the display and blurred to blur the display. The backlight signal is a monochrome signal, which can also be embedded in the SSVT signal. For example, it can be another parallel and independent video signal that travels with other parallel video signals, R, G, and B (e.g.), and can be low or high resolution.

[0085] The SSVT receiver 611 outputs a gate driver control signal 606, which shares timing control information with the gate driver 560 at the left edge of the display panel to synchronize the gate driver with the source driver. Typically, each SSVT receiver includes a timing acquisition circuit that acquires the same timing control information for the gate driver, and one or more source driver flexible foils (typically the leftmost and / or rightmost source drivers) pass this timing control information to the gate driver. The timing control information for the gate driver can be embedded in the SSVT signal and recovered from it using established spread spectrum techniques.

[0086] Traditional source drivers typically use COF (Flexible On-Board or Foil On-Board) IC packages directly connected to the glass. These drivers can be replaced with the new source drivers described in this article, thereby converting existing display panels to support SSVT. The inputs of these ICs are typically connected together via a PCBA, providing input signals from video sources and timing controllers. These can be located close to or far from the display panel, transmitting video and control signals via inexpensive wiring.

[0087] As will be explained in more detail below, portions of these source drivers can be integrated with the panel glass in various embodiments.

[0088] Details of SSVT decoding and integration with source drivers

[0089] On the receiving side, the decoder of each source driver is responsible for decoding the differential EM-level signal stream received on the transmission medium back into a format suitable for display. Once in the appropriate format, the video content contained in the sample can be displayed frame by frame on the video display. Therefore, video captured from any video source can be recreated via the video sink.

[0090] Figure 3 A detailed logical view of the SSVT receiver of the source driver array is shown. This is a logical view because typically each source driver will include a decoder 780 and its corresponding collector (reconstruction library 782 and hierarchical library 786). P represents the number of input electromagnetic pairs, each carrying an SSVT signal independent of the others, except that they are isochronous signals, known to be generated synchronously with each other by the encoders on the transmitting side. The decoder 780 performs the inverse transform of its paired encoder on the transmitting side and reconstructs its input differential level signal into an output vector of N reconstructed samples (although single-ended inputs can be used instead of differential inputs). The collector 746 assigns the decoder output vector samples (or "reconstructed samples") to their predetermined positions in the analog samples 612. These samples 612 from each decoder correspond to the column groups driven by each source driver.

[0091] P decoders 780 (marked 0 to P-1) are arranged to receive differential SSVT signals 0 to SSVT signals respectively. P-1 702-704. In response, each decoder 780 produces N difference pairs of reconstructed samples (sample 0 to sample 704). N-1 The number of samples N is equal to the number of orthogonal codes used in the previous encoding, that is, N orthogonal codes were used, which means N codes from the codebook.

[0092] Reconstruction library 782 reconstructs N samples (sample 0 to sample 1) of each decoder output vector at the end of each decoding interval. N-1 The differential pairs of the received voltage signals are sampled and stored. Then, these differential pairs of the received voltage signals are used as samples (samples) for each output vector. N-1 Outputting from sample 0. Each reconstruction library can also be converted from a differential pair to a single-ended voltage. Since differential pairs are used to maintain accuracy at low voltages (they are more resistant to external influences than single-ended voltages), it is best to convert to single-ended voltage as late as possible in the signal chain (by establishing a reference ground level). Therefore, the conversion to single-ended voltage does not need to occur in the reconstruction library, but can occur later, for example in a column driver, or, for example, within a level shifter. Conversions are typically performed on all signals (sampling, control signals, etc.) and can occur at different locations depending on the signal type and implementation.

[0093] Each hierarchical library 786 receives all reconstructed samples (samples) from the output vector of each decoder.n-1 The samples are moved to sample 0 and used as an analog output buffer, as will be described in more detail below. Once the samples are moved to the tier library 786, they are triggered by latch signal 632, which is derived from the decoded SSVT signal. The latch signals can be daisy-chained between the source drivers. Once the samples are released from the tier library, they are sent to level shifter 620.

[0094] It also includes a channel aligner 787 and a hierarchy controller 789, which receive framing and aperture information from each decoder 780. In response, the hierarchy controller 789 coordinates the timing of the hierarchy library 786 to ensure that all samples originate from the common time interval of the SSVT transmitter's transmitted level signals. Therefore, the individual channels of the transmission medium do not need to have the same length, as the channel aligner 787 and the hierarchy controller 789 compensate for any timing differences. A gate driver control signal 606 provides timing information to the gate driver (or to intermediate circuitry), which in turn provides the gate driver with correct timing and control signals, and may originate from the channel aligner 787.

[0095] Therefore, in a particular embodiment where P=24, there are 24 decoders, each located within a source driver, which is implemented in a separate integrated circuit. Furthermore, in this embodiment, N=960, indicating that each decoder decodes 960 video samples for display (excluding any control signals).

[0096] Figure 4 This is a logic diagram for one of the decoders 780. Decoder 780 includes a differential amplifier 1092 and a sample-and-hold circuit 1094, which are arranged to receive, sample, and hold one of the differential EM-level signals received via a transmission medium. The sampled EM-level signal is then provided to each of N decoder track circuits 1096 (tracks...). n-1 To track 0). The sequence controller 1098 provides the same SSDS chip for each of the N decoder track circuits 1096 applied to the transmitting side. As a result, differential sample output (samples) is generated. n-1 Sample 0) is provided to the reconstruction library 782. Therefore, from sample 0... n-1 The demodulated sample to sample 0 is the same as the one before modulation on the transmitting side.

[0097] Each decoder 780's sequence controller 1098 also generates multiple control signals, including a gating signal, an end-of-library (EOB) signal, an aperture signal, and a framing signal. The EOB signal is provided to the reconstruction library 782 and indicates the time when the hierarchical library 786 is completely filled with samples. When this occurs, the EOB signal is asserted that the next set of reconstructed samples (N) is expected to be filled. n-1When N0 is reached, the decoder track 1096 and the grading library 786 are cleared. The aperture control signal is provided to the sample and hold circuit 1094, and the framing signal is provided to the channel aligner 787 and the grading controller 789.

[0098] refer to Figure 5 A diagram of a representative decoder track circuit 1096 is shown. The decoder track circuit 1096 includes a multiplier section and an accumulator section. The multiplier section includes a first pair of switches S1-S1, a second pair of switches S2-S2, a third pair of switches S3-S3, and a pair of capacitors C1-C1 located on the first (positive) and second (negative) power rails, respectively. The accumulator section includes additional transistor pairs S4-S4, S5-S5, S6-S6, and S7-S7, an operational amplifier, and a pair of capacitors C1-C1 located on the first (positive) and second (negative) power rails, respectively. F and C F .

[0099] For each demodulation cycle, a differential EM level signal pair is received at the first level input (level +) and the second level input (level -). The differential EM level signal pair is demodulated by conditionally inverting the phase by multiplying the value of the chip received from the corresponding code by (1) or negative (-1).

[0100] If the chip value is (+1), then when clk1 is activated, transistor pairs S1-S1 and S3-S3 are closed, while S2-S2 remains open. Therefore, the voltage values ​​of the first-level input (level +) and the second-level input (level -) are passed to and stored on the two capacitors C1 and C2 on the positive and negative rails, respectively. In other words, the input value is multiplied by (+1) and no inversion occurs.

[0101] If the chip value is -1, switches S1-S1 are open, while when clk1 is activated, switches S2-S2 and S3-S3 are closed. Therefore, the voltage values ​​received at the positive or first (+) terminal and the negative or second (-) terminal are swapped. In other words, the input voltage value provided at the first or positive terminal is directed to and stored in capacitor C1 on the lower negative rail, while the voltage value provided at the second or (-) terminal is switched to and stored in capacitor C1 on the upper positive rail. Therefore, the voltage value received at the input terminal is inverted or multiplied by (-1).

[0102] When clk1 transitions to the inactive state, the accumulated charge on C1 remains unchanged. When clk2 transitions to the active state, transistor pair S4-S4 is turned on, while transistor pairs S5-S5 and S6-S6 are closed. The accumulated charge on capacitor C1 on the upper or positive rail and capacitor C1 on the lower or negative rail is then supplied to the differential input of the operational amplifier. The output of the operational amplifier is the raw + / - sample pair before transmission-side encoding.

[0103] When clk2 is activated, the accumulated charge on capacitors C1 and C1 is transferred to capacitors CF and CF on the upper or positive rail and the lower or negative rail, respectively. During each demodulation cycle, the charge on capacitors C1 and C1 on the upper and lower rails accumulates on capacitors CF and CF on the upper and lower rails, respectively. When both clk1 and the EOB signal are activated, transistors S7-S7 are closed, short-circuiting each plate of capacitors CF and CF. This removes the accumulated charge, and capacitors CF and CF are reset and ready for the next demodulation cycle.

[0104] Since each decoder 780 has N decoder track circuits 1096, N decoded or original + / - sample pairs are recreated each demodulation cycle. These N + / - sample pairs are then fed to the reconstruction library 782, and then to the hierarchical library 786.

[0105] Decoder track 1096 reconstructs the input level samples over L consecutive cycles, demodulating each consecutive input level with consecutive chips of the track's code. The result of each of the L demodulations is accumulated on the feedback capacitor CF. When the EOB is asserted during clk1, corresponding to the first demodulation cycle of the decoding cycle, CF is cleared after the EOB so that it can start accumulating again from zero volts or other reset voltage. In various embodiments, the value of L is a predetermined parameter. Generally, the higher the parameter L, the greater the process gain and the better the electroelasticity of the SSVT signal propagating over the transmission medium. On the other hand, the higher the parameter L, the higher the frequency required for SSVT modulation, which may affect signal quality due to insertion loss caused by the transmission medium. The above demodulation cycle is repeated on each decoder 780.

[0106] Integration of source driver with display panel glass

[0107] Display panels (such as LCD panels) are made of a glass substrate on which thin-film transistors (TFTs), i.e., field-effect transistors, are formed using thin-film deposition techniques. These TFTs are used to realize the pixels of the display. It is now recognized that these TFTs (along with appropriate capacitors and resistors, and other suitable analog components) can also be used to create logic circuits to implement the elements of the novel source driver described herein, which are then integrated with the glass. These elements are integrated at the extreme edges of the glass, just outside the pixel display area, but within a perimeter seal of the glass. Therefore, the source driver disclosed herein can be integrated with the glass using these transistors, capacitors, resistors, etc., and this can be done in the embodiments described below. Thus, the source driver (or its elements) previously located outside and at the edges of the display panel glass is now moved to the display panel glass itself. Furthermore, the gate driver function for the gate driver can also be moved to the display panel glass.

[0108] Figure 6 Examples illustrate the integration of source driver functionality in various embodiments. Depending on the quality of the transistors used on the glass, various elements of the source driver can be integrated with the glass. As is known in the art, TFTs (e.g.) can handle frequencies ranging from low to high frequencies. There are three main technologies used for TFT manufacturing: amorphous silicon (a-Si); oxide (indium gallium zinc oxide (“IGZO” or similar materials), which can conventionally handle frequencies from about 50 kHz to 100 kHz and up to about 200 kHz, depending on the voltage used (for some components, oxides can handle frequencies up to 1 MHz at 50 volts); and low-temperature polycrystalline silicon (LTPS), which can handle frequencies on the order of about 5 MHz up to about 10 MHz, depending on the voltage used. Furthermore, crystalline silicon TFTs implemented using CMOS technology may be able to handle even higher frequencies. Other types of TFTs can also be used.

[0109] If higher-quality, faster TFT transistors are used, the higher-frequency portion of the source driver can be integrated with the glass. Furthermore, smaller device size will allow transistors to switch faster, enabling the implementation of components using these devices on glass. For example, the channel length of the TFT affects its size; preferably, the channel length of oxide TFTs is less than about 0.2 μm, and the preferred channel length of LTPS TFTs is less than about 0.5 μm. Reducing the channel length by 50% will increase the speed fourfold. Additionally, implementation can depend on the type of display; lower resolution 2K, 1K, and smaller display sizes may use components that do not require the high frequencies of 4K and 8K displays. Typically, amorphous silicon transistors are not used because they tend to have threshold shift and are unstable.

[0110] For example, in the first embodiment 102, since the level shifter 620 only requires a relatively low frequency clock, the level shifter 620 and amplifier 621 are integrated with the glass. Because the level shifter switches once per line, they require a switching frequency of approximately 50 kHz for a 2K display, 100 kHz for a 4K display, and so on. Therefore, the integrated first embodiment can use a TFT that can operate at a clock frequency of at least approximately 50 kHz, assuming a 2K panel (100 kHz for a 4K panel, and so on). Therefore, IGZO or LTPS TFTs can be used in the first embodiment.

[0111] In the second embodiment 104 using faster transistors, the level shifter 620, amplifier 621, and collector 786 can also be integrated with the glass. The collector 786 requires a higher clock frequency because each collector manipulates a pixel sequence, and a switching frequency of approximately 50 MHz is needed for a 2K display, and 100 MHz for a 4K display, and so on. Therefore, the integrated second embodiment can use a TFT that can operate at a clock frequency of at least approximately 50 MHz, assuming the panel is 2K. Thus, an LTPS TFT can be used for a 2K panel in the second embodiment.

[0112] In the third embodiment 106, which uses even faster transistors, the entire source driver, including the decoder 780, collector, amplifier, and level shifter, can be integrated with the glass because the decoder may require a higher clock frequency, at least about 300 MHz. Therefore, the third embodiment can use a TFT capable of operating at a clock frequency of at least about 300 MHz, assuming a 2K panel and that the TFT is implemented on the glass at a resolution of about 100 nm. Depending on the implementation and specific type of TFT used, a lower clock frequency can be used.

[0113] Note that the source driver disclosed herein does not require the use of any digital-to-analog converter to convert video samples, and therefore the high-frequency clock required for decoding is still about ten times lower than the frequency of the digital drive signal required in prior art source drivers (digital drive is about 3 GHz).

[0114] Figure 7A The placement of the gate driver and source driver on the display panel glass is shown. Typically, the display panel is implemented using two glass substrates: a top (or ordinary) glass and a bottom (or active) glass, with the bottom glass being smaller than the top glass. The TFTs are implemented on the bottom glass, which is the subject of the following description, and the accompanying drawings only show the bottom glass. The display panel glass 150 itself is shown (for clarity, the panel frame or enclosed display unit is not shown), having two rectangular regions 130 and 132, each a few millimeters wide on either side of the display panel glass (in this example, an LCD panel). In this embodiment, the gate driver is also integrated using on-glass TFT devices as switching elements. Since gate drivers are typically implemented as simple shift registers, these shift registers can be located in regions 130 or 132.

[0115] A rectangular region 140, also located on the glass itself, is shown, in which the source driver elements may be located. The source driver function may be partially or completely integrated with the glass by using an on-glass TFT switch in this region 140. In a first embodiment, the amplifier (and level shifter) are integrated onto the glass (formed in region 140), while in a second embodiment, the amplifier (and level shifter) and the collector are integrated (also formed in region 140).

[0116] Because the source drivers disclosed herein do not require digital signals, D / A converters, and associated circuitry for processing video samples, their lower processing frequency and smaller size allow them to be integrated onto the glass. Therefore, for example, given that a typical 64-inch 4K TV panel has a pixel width of 80µm (an 8K display has a pixel width of 40µm), there is sufficient width to integrate the drivers directly onto the glass, as the size of the output amplifier is expected to fit within this space. Specific TFTs can be selected based on the pixel width of the particular implementation.

[0117] Interconnect printed circuit board 182 receives SSVT signal 602 via flexible PCB 184 and transmits SSVT signal 602 to a source driver located on integrated circuit 186a and partially integrated with the glass in TFT 186b. This transmission of the SSVT signal is implemented for embodiments 1 and 2, since a portion of each source driver (at least the decoder) will still be located within the flexible PCB 184 on IC 186a. As shown, each integrated circuit 186a transmits analog signal 187 to a corresponding circuit on glass 186b. The nature of these analog signals will depend on whether embodiment 1 or embodiment 2 is implemented. Embodiment 3 is implemented as follows. Gate clocks 190 and 192 are transmitted to the gate driver via circuit board 182 and flexible PCB 184. As is known in the art, PCB 184 is attached to panel glass 150.

[0118] Figure 7B A source driver 186 implemented entirely on glass is shown. In this third embodiment, the source driver functionality is fully integrated on the glass, which also includes a decoder. As shown, the flexible PCB 184 includes only the SSVT signal 602 and lacks source driver functionality such as decoders, collectors, level shifters, and amplifiers; all source driver functionality is implemented in the TFTs (and other analog components) on the glass. Although not shown, each other source driver may have its own PCB 184 and SSVT signal 602 (from a corresponding SSVT transmitter); in one particular embodiment, there are 24 such source drivers.

[0119] Figure 8Another embodiment of placing the SSVT signal 602 in implementing Embodiment 3 is shown. As previously described, in Embodiment 3, all functions of the source driver (including the decoder) are integrated with the glass, thus eliminating the need to transmit the SSVT signal 602 via a large circuit board 182 (the length of the display) and then via numerous flexible PCBs 184, as... Figure 7A and 7B As shown. Therefore, a smaller printed circuit board 183 and a single flexible PCB 185 are attached to one location on the display panel glass 150, and the SSVT signal 602 is transmitted to the glass via 183 and 185, and then propagates along the glass, where it is transmitted to each source driver on the glass within region 140. Furthermore, the integrated circuit 186 is not required on the flexible PCB because all the functionality of each source driver is now on the glass. As shown, the SSVT signal 602 is transmitted in parallel to each source driver, while... Figure 2 and Figure 6 One implementation is shown in which the SSVT signal 602 is passed to each source driver via a daisy chain.

[0120] Alternative embodiments integrated with display panel glass

[0121] Figure 9 A source driver array 700, which can be integrated with the display glass of a display unit, is shown. As shown, 24 wire pairs 702-708 each carry SSVT signals, which originate from an integrated timing controller with an SSVT transmitter or the SSVT transmitter itself, and arrive at decoders 712-718 at an input frequency of 720 MHz. The decoders decode these input signals, each producing 64 analog samples (or signals), which are input to collectors 722-728 at a frequency of 11.25 MHz. Each collector then collects a set of 64 samples per decoding interval, and outputs 960 signals at a frequency of 750 kHz every 15 decoding intervals (64 × 15 = 960). Each set of 960 signals is then input to amplifiers 732-738 for amplification, and these signals are then output as analog levels at 750 kHz through 960 wires to the columns of the display panel, thereby producing the pixels of the image initially encoded upstream by the SSVT transmitter. The number of line pairs, decoders, collectors, amplifiers, and signals is specific to this example, and other source-driven arrays and display panels may have different values. Level shifters that may be included within the amplifier module are not shown in this figure.

[0122] In this example, the frequencies used for the 8K display unit (comprising 24 source drivers) are: 720MHz for the decoder, 11.25MHz for the collector, and 750kHz for the amplifier. The frequencies used for the 4K display unit (comprising 12 source drivers) are: 360MHz for the decoder, 5.62MHz for the collector, and 375kHz for the amplifier; and the frequencies used for the HD display unit (comprising 6 source drivers) are: 180MHz for the decoder, 2.8MHz for the collector, and 185kHz for the amplifier.

[0123] In this example, the integrated implementation can be as follows. In Embodiment 1, we integrate only the amplifiers 732-738 on the glass (including the level shifter), leaving the low-voltage analog driver IC outside the glass. Therefore, there will be the same number of external connections as with the "non-integrated" driver. The frequency specification of the TFT used on the glass is approximately 200-750kHz (depending on the size of the display unit). In Embodiment 2, we also integrate the collectors 722-728 with the amplifiers (and level shifters), the collectors handling low MHz input signals, e.g., approximately 11MHz for an 8K display unit. The number of external connections will be reduced (only 64 per driver instead of 960). Alternatively, several of the external ICs 186a (which house the decoder) can be integrated into a large single IC (e.g., combined every six ICs), resulting in fewer external connections (e.g., combining the decoders of six drivers together results in 384 outputs – this is not a problem for interconnection since a typical driver has 960 outputs), and resulting in only four external ICs instead of 24. In Example 3, we integrate all components of the source driver onto the glass: decoders 712-718, collectors and amplifiers (and level shifters). The frequency specifications of the TFTs used are approximately 720MHz for the 8K cells, 360MHz for the 4K cells, and 180MHz for the HD cells. Only a few external connections will be required, such as the 48 SSVT lines 702-708, plus the power supply connection.

[0124] Figure 10 Showing from Figure 9 One of the decoders.

[0125] Figure 11 It shows Figure 9 The collector 742 is used in the decoding process. As shown in the figure, during each decoding interval, 64 analog samples 840 from each decoder are input into each collector 842. Once collector 742 is full, each group of 960 signals from each collector 842 is output as analog signal 844. Collector 746 thus acts as a line buffer.

[0126] Specific embodiments of collectors and amplifiers

[0127] Figure 18 A specific embodiment of how a collector and amplifier can be implemented for one of the decoders is shown. In this particular example, the source driver drives an LCD display, and the various components shown are specific to this type of display. However, the invention is also applicable to other types of displays. A portion of a collector is shown that stores 64 samples [63:0] and amplifies 64 samples; the collector and amplifier portions shown are copied to output 960 analog samples, such as... Figure 11 As shown.

[0128] The diagram shows the input of a sample difference pair 252, fed into storage units (collectors) for samples 258 and 259 in A / B sampling; each storage array A or B holds 960 storage units (only 64 are shown in the diagram), and all incoming samples from the decoder are stored in array A or B (using...). Figure 11 (The example uses 64 samples at a time). Once all 960 samples are stored in array A or B, they can be used as follows: Figure 11 The parallel output is shown to the amplifier. In one embodiment, each of these memory cells in memory array A or B is a switched capacitor or a sampling capacitor; the array may also be referred to as an analog latch.

[0129] Once stored (e.g., in array A), these 960 samples are output in parallel, while the next set of 960 analog samples is stored in another array (e.g., B). Therefore, when one set of 960 samples stored in the collector is driven to the amplifier from either array A or B, the next set of 960 samples is stored in the other array of the collector. Thus, this embodiment of the collector is a two-stage latch—one stage outputs while the other is filled. This embodiment is used when the inputs to a library are serial or not fully parallel, thereby avoiding latency. In another embodiment, the first stage simply outputs in parallel to the second stage when full, and then resumes filling.

[0130] In an alternative embodiment, the collector has only a single stage, for example, only a storage array A, and once that array is filled, it outputs its contents in parallel and then continues to fill with new samples. This embodiment can be used when the stage can be filled fast enough that there is no significant delay in the parallel sample output. Figure 11 A single-stage collector is shown.

[0131] One of the 64 preamplifiers 260 shown in the figure is also illustrated, each preamplifier 260 being associated with one of the memory cells of array A or B. Once the array outputs its sample, all 960 preamplifiers of the source driver will simultaneously amplify the sample. Depending on the implementation, the preamplifiers may be optional.

[0132] Also shown in this figure is one of the 64 level shifters 262, which converts differential signals to single-ended signals, adds offset, changes the polarity of the signal, and provides amplification. Depending on the implementation, the level shifter (or a portion thereof) may be optional; for example, the conversion to a single-ended signal may occur elsewhere. Each preamplifier output is fed to one of the level shifters.

[0133] High-voltage driver 264 (also known as column driver) is one of 64 such drivers in this figure; it multiplies the input signal to provide the voltage (positive or negative) desired by the display. Column short circuit 268 provides a short circuit known in the art for LCD displays. Finally, the desired voltage is output to the column at 270, for a total of 960 outputs (only 64 are shown in the figure). The level shifter 262, high-voltage driver 264, and short circuit 268 assembly can also be referred to as “column drivers.” Preamplifier 260, level shifter 262, and high-voltage driver 264 can be considered as amplification stages before each column, and in this case, are pipe amplifiers or simply amplifiers. Essentially, components 260, 262, and 264 all provide amplification and other functions depending on the type of display. Other types of displays may have different configurations.

[0134] Mobile phone specific embodiments

[0135] Figure 17 This is a block diagram of transmitting video samples within a mobile phone. Due to the high refresh rate of 4K smartphone displays, MIPI receivers, SRAM, digital image processing, and the extensive use of analog signals requiring approximately 1000 digital-to-analog converters, existing OLED DDIC devices, such as those used in mobile phones, require improvements to their existing technology displays.

[0136] The SSVT receiver 240 described below can be used as follows: Figure 3 The implementation shown is as described above, and may include the twelve source drivers described herein, each of which may be implemented on the display panel glass 210 in the various embodiments disclosed herein.

[0137] The split OLED DDIC architecture shown in the figure has the following advantages: achieving optimal DDIC-TCON and DDIC-SD partitioning; providing short-distance MIPI transmission from the SoC; optimizing the digital DDIC-TCON for SRAM and image processing; providing a simplified DDIC with full analog capabilities; and requiring only a small number of digital-to-analog converters in the DDIC-TCON integrated with the SSVT transmitter.

[0138] The image shows a mobile phone (or smartphone) 200, which can be any similar handheld mobile device used for communication and displaying images or videos. Device 200 includes a display panel 210, a conventional mobile SoC 220, an integrated DDIC-TCON (Display Driver IC - Timing Controller) and SSVT transmitter module 230, and an integrated analog DDIC-SD (DDIC Source Driver) and SSVT receiver 240. The mobile SoC 220 and module 230 are shown external to the mobile phone for ease of explanation, although they are internal components of the phone.

[0139] Mobile SoC 220 is any standard SoC used in mobile devices, and transmits digital video samples to module 230 via MIPIDSI 224 (Mobile Industrial Processor Interface Display Serial Interface) in a manner similar to the Vx1 input signals discussed above. Module 230 includes a DDIC-TCON integrated with an SSVT transmitter. After reading this disclosure and referring to the foregoing figures, those skilled in the art will understand how the SSVT transmitter is implemented to output any number of analog SSVT signals 234. In this example, the SSVT transmitter outputs 12 pairs of SSVT signals at 380 Msps. The timing and framing control signals from module 230 to the gate driver of display panel 210 are not shown. Typically, for mobile phones, the DDIC is located on the bottom narrow edge of the phone, while the SoC is located in the middle of the device. Therefore, the integrated DDIC-TCON / SSVT transmitter is located close to the SoC, within a range of about 10 cm or less, or even about 1-2 cm or less. Since the transmission of digital data occurs at extreme frequencies, it is advantageous to minimize the length of the conductor. For tablets, the distance should be approximately 25-30 centimeters or less.

[0140] These analog SSVT signals are received at the integrated analog DDIC-SD and SSVT receiver 240. A description of how to integrate the source driver with the SSVT receiver to receive any number of analog SSVT signals and generate voltages for driving the display panel can be found herein and in application number 17 / 900,570 (HYFYP009) cited above. Advantageously, module 240 does not require any digital-to-analog converter.

[0141] The analog DDIC-SD Rx 240 can be a single integrated circuit with 12 source drivers (each processing a single pair), or it can be 12 discrete integrated circuits, each acting as a source driver and processing one of the 12 signal pairs.

[0142] SSVT signal, encoding and decoding

[0143] As previously described, various embodiments of the present invention disclose encoding analog signals for transmitting video information within (or to) a display unit, thereby eliminating the need for a DAC within the source driver and integrating the source driver (or a portion thereof) onto the display panel glass, among other advantages.

[0144] For the purposes of this disclosure, an electromagnetic signal (EM signal) is a variable representing electromagnetic energy whose amplitude varies with time. EM signals propagate from a transmitter to a receiver through EM paths, such as wire pairs (or cables), free space (or wireless), light, or waveguides (optical fibers). EM signals can be independently represented as continuous or discrete in each of the time and amplitude dimensions. A “pure analog” signal is a continuous-time, continuous-amplitude EM signal; a “digital” signal is a discrete-time, discrete-amplitude EM signal; and a “sampled analog” signal is a discrete-time, continuous-amplitude EM signal. This invention discloses a novel discrete-time, continuous-amplitude EM signal, called a “spread spectrum video transmission” (SSVT) signal, which is an improvement on existing SSDS-CDMA signals. SSVT refers to the transmission of electromagnetic signals through one or more EM paths using an improved spread spectrum direct sequence (SSDS) based modulation technique.

[0145] Code Division Multiple Access (CDMA) is a well-known channel access protocol commonly used in radio communication technologies, including cellular phones. CDMA is an example of multiple access where several different transmitters can simultaneously transmit information through a single communication channel. In telecommunications applications, CDMA allows multiple users to share a given frequency band without interference from other users. CDMA uses Spread Spectrum Direct Sequence (SSDS) coding, which relies on a unique code to encode each user's data. By using this unique code, transmissions from multiple users can be combined and sent without interference between users. At the receiving end, the same unique code is used to demodulate the transmission for each user, thereby recovering the data for each user individually.

[0146] SSVT signals differ from CDMA signals. When a stream of input video (e.g.,) samples is received at the encoder, they are encoded by applying SSDS-based modulation to each of the multiple encoder input vectors to generate an SSVT signal. The SSVT signal is then transmitted over the transmission medium. At the receiving end, the incoming SSVT signal is decoded by applying appropriate SSDS-based demodulation to reconstruct the encoded samples. Thus, the original stream of time-ordered video samples containing color and pixel-related information is delivered from a single video source to a single video destination, unlike CDMA, which transmits data from multiple users to multiple receivers.

[0147] Figure 12 A simplified example is illustrated, showing how signal samples (analog values ​​in this case) are encoded within an encoder and then transmitted via an electromagnetic path. Shown are N analog values ​​902-908 as input vectors, representing the voltage of individual pixels within a video frame. These voltages can represent the luminance of a black-and-white image or the luminance of a specific color value within a pixel (e.g., the R, G, or B color value of a pixel); that is, each value represents the amount of light sensed or measured in a specified color space. While pixel voltages are used in this example, this encoding technique can be used with voltages representing any of a variety of signals from sensors (such as LiDAR values, sound values, tactile values, aerosol values, etc.), and analog values ​​can represent other samples such as current. Signal samples as digital values ​​can also be encoded, and this digital encoding is explained below. Furthermore, although only one encoder and one EM path are shown, embodiments of the invention are applicable to multiple encoders, each transmitting via an EM path.

[0148] Preferably, for efficiency, these voltages range from 0 to 1V, but different ranges are possible. These voltages are typically taken from pixels in a row of a frame in a specific order, but another convention can be used to select and sort these pixels. Regardless of which convention is used to select and sort these pixels for encoding, the decoder will use the same convention at the receiving end to decode these voltages in the same order and then place them in the resulting frame to which they belong. Similarly, if the frame is color and uses RGB, the convention in this encoder could be to encode all R pixel voltages first, then the G and B voltages, or the convention could be that voltages 902-906 are the RGB values ​​of the pixels in that row, and the next three voltages 908-912 represent the RGB values ​​of the next pixel, and so on. Again, the same convention used by this encoder to sort and encode the voltages will be used by the decoder at the receiving end. Any specific convention for sorting the analog values ​​902-908 (whether by color value, by row, etc.) can be used as long as the decoder uses the same convention. As shown in the figure, any number of N analog values ​​902-908 can be presented at once for encoding using codebook 920, limited only by the number of entries in the codebook.

[0149] As previously stated, codebook 920 has any number of N codes 932-938; in this simple example, the codebook has four codes, meaning that four analog values ​​902-908 are encoded at a time. More codes, such as 127 codes, 255 codes, etc., can be used, but fewer codes are preferred due to practical considerations such as circuit complexity. As is known in the art, codebook 920 comprises N mutually orthogonal codes, each of length L; in this example, L = 4. Typically, each code is an SSDS code, but not necessarily the extended code discussed herein. As shown, each code is divided into L time intervals (also called “chips”), and each time interval includes the binary value of that code. As shown in code representation 942, code 934 can be represented in the conventional binary form “1100”, but the same code can also be represented as “1 1 -1-1”, as shown in code representation 944, for ease of use when modulating values, as will be explained below. Codes 932 and 936-938 can also be represented as 942 or 944. Note that each code of length L is not associated with different computing devices (such as telephones), different people, or different transmitters as in CDMA.

[0150] Therefore, in order to transmit four analog values ​​902-908 to the receiver (with a corresponding decoder) via transmission medium 34, the following technique is used. Each analog value is modulated by each chip in the representation 944 of its corresponding code; for example, the value 902 (i.e., .3) is modulated sequentially in time by each chip in the representation 944 of code 932 948. Modulation 948 can be a multiplication operator. Thus, modulating .3 with code 932 produces the sequence ".3, .3, .3, .3". Modulating .7 with code 934 becomes ".7, .7, -.7, -.7"; the value "0" becomes "0, 0, 0, 0"; and the value "1" becomes "1, -1, 1, -1". Typically, the first chip of each code modulates its corresponding analog value, and then the next chip of each code modulates its analog value, but implementations may also modulate a particular analog value by all chips of its code before moving to the next analog value.

[0151] At each time interval, the modulated analog values ​​are summed 951 (perpendicularly sensed in this diagram) to obtain analog output levels 952-958; for example, the summation of the modulated values ​​for these time intervals results in output levels of 2, 0, .6, and -1.4. These analog output levels 952-958 can be further normalized or amplified to align with the voltage limits of the transmission line, and then can be transmitted sequentially as if generated sequentially on the electromagnetic path of the transmission medium (e.g., differential twisted pair). The receiver then receives those output levels 952-958 in that order and decodes them using the same codebook 920 using the inverse of the encoding scheme shown herein. The resulting pixel voltages 902-908 can then be displayed in frames on the display at the receiving end according to the conventions used. Thus, the analog values ​​902-908 are effectively synchronously encoded and transmitted in a sequential sequence of L analog output levels 952-958 through a single electromagnetic path. As shown and described herein, many encoders and electromagnetic paths can also be used. Furthermore, the number of N samples that can be encoded in this way depends on the number of orthogonal codes used in the codebook.

[0152] Advantageously, even though the use of robust SSDS techniques (such as spreading codes) leads to a significant bandwidth reduction, the use of mutually orthogonal codes, modulation and summation of each sample via chips of their corresponding codes, and parallel transmission of N samples using L output levels result in a significant bandwidth gain. Compared to conventional CDMA techniques where binary bits are serially encoded and then summed, this invention first modulates the entire sample (i.e., the entire analog or digital value, not a single bit) via each chip in the corresponding code, and then sums these modulations at each time interval of the code to obtain the resulting analog voltage level for each specific time interval, thereby utilizing the amplitude of the resulting waveform. These analog output levels, rather than a binary representation, are transmitted through the transmission medium. Furthermore, this invention facilitates the transmission of analog voltages from one video source to another video destination, i.e., from end to end, unlike CDMA techniques, which allow multiple accesses from different people, different devices, or different sources and transmission to multiple destinations. Moreover, the transmission of sample values ​​does not require compression.

[0153] Figure 13 This novel encoding technique is illustrated as a sample signal applied as a digital value. Here, digital values ​​902'-908' are digital representations of voltage. Using different examples of voltage, value 902' is "1101", value 904' is "0011", value 906' is "0001", and value 908' is "1000". Each digital value is modulated (digitally multiplied) by the representation 944 of each code, i.e., multiplied by "1" or "-1", depending on the chip of the code corresponding to the digital value to be modulated. Considering only the first time interval 940 for each code, and adding the most significant bit (MSB) as the sign bit, modulating "1101" produces "01101" (MSB "0" indicates a positive value), modulating "0011" produces "00011", modulating "0001" produces "00001", and modulating "1000" produces "01000". These modulated values ​​are labeled on the first time interval. (Although not shown, the negative value is generated by modulation with a -1 chip and can be represented in binary using a suitable binary representation for negative values.)

[0154] Summing digitally, these modulated values ​​in the first time interval produce the digital value 952' "011001" (again, the MSB is the sign bit); the other digital values ​​954'-958' are not shown in this example but are calculated in the same way. Considering a base-10 summation, it can be verified that the sum of the modulated values ​​13, 3, 1, and 8 is indeed 25. Although not shown in this example, the additional MSB would typically be used for the resulting level 952'-958', as the sum may require more than 5 bits. For example, with 64 codes, if values ​​902'-908' are represented using 4 bits, then level 952'-958' could be represented using up to 10 bits (adding 64 log2 bits). Alternatively, if 32 modulated values ​​are summed, then five more bits would be added. The number of bits required for the output level will depend on the number of codes.

[0155] Output level 950' can first be normalized to fit the DAC's input requirements, and then sequentially fed into DAC959 to convert each digital value into its corresponding analog value for transmission over the EM path. DAC 959 can be a MAX5857 RF DAC (including a clock-multiplying PLL / VCO and a 14-bit RF DAC core, and can bypass complex paths to directly access the RF DAC core), followed by a bandpass filter and then a variable gain amplifier (VGA), not shown. In some cases, the number of bits used at level 950' is greater than the number of bits allowed by DAC 959; for example, level 952' is represented by 10 bits, but DAC 959 is an 8-bit DAC. In these cases, an appropriate number of LSBs will be discarded, while the remaining MSBs are processed by the DAC without loss of visual quality of the resulting image on the display.

[0156] Advantageously, the entire digital value is modulated, and then these modulated digital values ​​are digitally summed to produce a digital output level for conversion and transmission. This technique differs from CDMA, which modulates each binary bit of the digital value and then sums these modulated bits to produce the output. For example, assuming there are B bits in each digital value, using CDMA would require a total of B*L output levels to be transmitted, while with this novel digital (or analog) coding technique, only L output levels need to be transmitted, thus offering an advantage.

[0157] Figure 14 Showing the use Figure 12The encoder decodes the analog input levels. As shown, L input levels 950 are received via a single electromagnetic path through transmission medium 34. As described herein and previously noted, codebook 920 includes N orthogonal codes 932-938, which will be used to decode the input levels 950 to produce an output vector of N analog values ​​902-908, i.e., the same analog values ​​902-908 encoded above. As indicated by the vertical arrows, to perform decoding, each input level 952-958 is modulated 961 by each chip of each code corresponding to a specific index in the output vectors 902-908. Consider levels 952-958 modulated by the first code 932, which produces a series of modulated values ​​“2, 0, .6, -1.4”. Modulation of levels 952-958 by the second code 934 produces a series of modulated values ​​“2, 0, -.6, 1.4”. "2,0,-.6,-1.4" is generated by modulation of the third code 936, and "2,0,.6,1.4" is generated by modulation of the fourth code 938.

[0158] Next, as indicated by the horizontal arrows, the modulated values ​​for each series are summed to produce one of the analog values ​​902-908. For example, summing the first series produces the analog value "1.2" (which becomes ".3" after normalization using a scaling factor "4"). Similarly, the modulated values ​​for the other three series are summed to obtain the analog values ​​"2.8", "0", and "4", and after normalization, the output vector of analog values ​​902-908 is obtained. Each code can modulate the input level and then sum the series, or all codes can modulate the input level before summing each series. Therefore, the output vector of N analog values ​​902-908 is transmitted in parallel using L output levels.

[0159] Examples of decoding digital input levels are not shown in these examples, but those skilled in the art will find it straightforward to perform such decoding after reading the encoding of the digital values ​​described above.

[0160] Figure 15A , 15B Figures 15C and 15C show that encoders and decoders can operate on analog or digital samples; various analog and digital encoders and decoders have been previously described above. As mentioned above, depending on the situation, there can be more than one EM path and correspondingly more than one encoder / decoder pair and a corresponding number of DACs or ADCs.

[0161] Figure 15AThe use of an analog encoder and a corresponding analog decoder is illustrated. The input to the analog encoder 900 is either an analog sample 970 or a digital sample 971 already converted into analog form by a DAC 972 located at the analog encoder. In this way, the analog or digital sample arriving at the analog encoder can be encoded for transmission via an electromagnetic path over a transmission medium. The analog decoder 900' decodes the encoded analog sample to produce an analog sample 970 for output. The analog sample 970 can be used as is or converted into a digital sample using an ADC (not shown).

[0162] Figure 15B The use of a digital encoder and a corresponding analog decoder is illustrated. The input to the digital encoder 901 is either a digital sample 971 or an analog sample 970 that has already been converted to digital by the ADC 973 located at the digital encoder. Since the encoder is digital, the DAC 959 located at the encoder converts the encoded sample to analog before transmission through the electromagnetic path. In this way, analog or digital samples arriving at the digital encoder can be encoded for transmission through the electromagnetic path over the transmission medium. The analog decoder 900' decodes the encoded analog sample to produce an analog sample 970 for output. The analog sample 970 can be used as is or converted to digital using an ADC (not shown).

[0163] Figure 15C This illustrates the use of a digital decoder to decode an encoded analog signal that has arrived via an electromagnetic path over a transmission medium. The encoded analog signal can be transmitted using either the analog encoder or the digital encoder described above. An ADC 974 located at the digital decoder 976 receives the encoded analog samples transmitted via the electromagnetic path and converts the samples into digital samples. These encoded digital samples are then decoded by the digital decoder 976 into digital samples 978 (corresponding to the values ​​of the input vectors of the samples initially encoded before transmission via the electromagnetic path). The digital samples 978 can be used as is or converted back to analog samples using a DAC.

[0164] Figure 16The diagram illustrates the analog (similar to an idealized oscilloscope trace) of the SSVT waveform 602 transmitted via an electromagnetic path (such as from one of encoders 250-256 or from one of DACs 460-466) after being output from an analog encoder (or after digital encoding and then conversion by a DAC). The vertical scale represents voltage, and the horizontal scale represents 100ps oscilloscope measurement time intervals. Note that the SSVT signal 602 is an analog waveform, not a digital signal (i.e., the signal does not represent binary digits), and in this embodiment, a voltage range from approximately -15V to approximately +15V can be transmitted. The voltage values ​​of the analog waveform are (or at least can be) fully analog. Furthermore, the voltage is not limited to a single maximum value, but high values ​​are impractical.

[0165] As previously described, analog voltage levels are sequentially transmitted along the electromagnetic path, each level being the sum of modulated samples at each time interval, such as the analog output levels 952-958 above or the digital output levels 952'-958' above (after passing through the DAC). When transmitted, these output levels then appear as waveforms such as waveform 602. Specifically, voltage level 980 represents the sum of modulated samples in a specific time interval (i.e., the output level). Using a simple example, sequential voltage levels 980-986 represent the transmission of four output levels. In this example, 32 codes are used, meaning 32 samples can be transmitted in parallel; therefore, voltage levels 980-986 (followed by multiple subsequent voltage levels, depending on the number of chips L in the code) form the parallel transmission of 32 coded samples (such as pixel voltages from a video source). After this transmission, the next set of L voltage levels of waveform 602 represents the transmission of the next 32 samples. Generally speaking, waveform 602 represents encoding analog or digital values ​​into analog output levels, and transmitting those levels at discrete time intervals to form a composite analog waveform.

[0166] Due to phenomena such as attenuation, reflections caused by impedance mismatch, and intrusive signal impact, each electromagnetic path degrades the electromagnetic signal propagating through it. Therefore, measurements of the input level at the receiving terminal will always contain errors regarding the corresponding output level available at the transmitting terminal. Compensation can be achieved by scaling the input level at the receiver (or normalizing or amplifying the output level at the transmitter), as is known in the art. Additionally, due to process gain (i.e., increased electroelasticity due to the increase in L), the decoded input level at the decoder is normalized using a scaling factor of the code length to recover the transmitted output level, as is known in the art. Furthermore, while L>=N>=2 is preferred as described herein, in some cases L may be less than N, i.e., N>L>=2.

[0167] Although the invention has been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications can be made within the scope of the appended claims. Therefore, the described embodiments should be considered illustrative rather than restrictive, and the invention should not be limited to the details given herein, but should be defined by the full scope of the following claims and their equivalents.

Claims

1. A source driver for a display unit, comprising: The decoder receives an analog signal representing the video stream's encoded sample values ​​and outputs the decoded sample values ​​during the decoding interval; A collector that inputs the decoded sample values ​​during a plurality of decoding intervals and outputs a set of decoded sample values ​​in parallel after the plurality of decoding intervals, wherein the decoder and the collector are implemented outside the edge of the display panel of the display unit; as well as Multiple amplifiers, which input the set of decoded sample values ​​and output voltages to the pixels of the display panel, wherein the multiple amplifiers are implemented using at least transistors on the glass substrate of the display panel.

2. The source driver of claim 1, wherein the analog signal is an ordered sequence of continuous amplitude analog levels.

3. The source driver of claim 1, wherein the plurality of amplifiers are located on the glass substrate of the display panel between the pixel display area and the perimeter of the glass substrate.

4. The source driver of claim 1, wherein the source driver does not include a digital-to-analog converter for converting video samples.

5. The source driver of claim 1, wherein the transistor is capable of operating at the clock frequency required by the amplifier.

6. The source driver of claim 5, wherein the transistor is a thin-film transistor (TFT), and is a low-temperature polycrystalline silicon (LTPS) transistor or an indium gallium zinc oxide (IGZO) transistor.

7. The source driver of claim 1, wherein the pixels of the display panel are implemented using transistors of the same type used to implement the amplifier.

8. The source driver of claim 1, wherein the display unit is a display of a mobile phone.

9. The source driver of claim 1, further comprising: Multiple level shifters, each associated with and operating on one of the amplifiers to shift the voltage, wherein the level shifters are also implemented using at least transistors on the glass substrate of the display panel, and wherein the transistors are capable of operating at the clock frequency required by the level shifters.

10. A source driver for a display unit, comprising: At least one decoder receives an analog signal representing a video stream of encoded sample values ​​and outputs decoded sample values ​​during a decoding interval, the decoder being implemented outside the edge of the display panel of the display unit; A collector that inputs the decoded sample values ​​during a plurality of said decoding intervals and outputs a set of decoded sample values ​​after said plurality of decoding intervals; as well as Multiple amplifiers input the set of decoded sample values ​​and output voltages to the pixels of the display panel, wherein the collector and the amplifiers are implemented using at least transistors on the glass substrate of the display panel.

11. The source driver of claim 10, wherein the analog signal is an ordered sequence of continuous amplitude analog levels.

12. The source driver of claim 10, wherein the collector and the amplifier are located on the glass substrate of the display panel between the pixel display area and the perimeter of the glass substrate.

13. The source driver of claim 10, wherein the source driver does not include a digital-to-analog converter for converting video samples.

14. The source driver of claim 10, wherein the transistor is capable of operating at a first clock frequency required by the amplifier and a second clock frequency required by the collector.

15. The source driver of claim 14, wherein the transistor is a thin-film transistor (TFT), and is a low-temperature polycrystalline silicon (LTPS) transistor or an indium gallium zinc oxide (IGZO) transistor.

16. The source driver of claim 10, wherein the pixels of the display panel are implemented using transistors of the same type used to implement the collector and the amplifier.

17. The source driver of claim 10, wherein the display unit is a display of a mobile phone.

18. The source driver of claim 10, further comprising: Multiple level shifters, each associated with and operating on one of the amplifiers to shift the voltage, wherein the level shifters are also implemented using at least transistors on the glass substrate of the display panel, and wherein the transistors are capable of operating at the clock frequency required by the level shifters.

19. A source driver for a display unit, comprising: At least one decoder receives an analog signal representing the video stream of encoded sample values ​​and outputs the decoded sample values ​​during a decoding interval; A collector that inputs the decoded sample values ​​during a plurality of said decoding intervals and outputs a set of decoded sample values ​​after said plurality of decoding intervals; as well as Multiple amplifiers input the set of decoded sample values ​​and output voltages to pixels of a display panel, wherein the decoder, the collector, and the amplifiers are implemented using at least transistors on a glass substrate of the display panel.

20. The source driver of claim 19, wherein the analog signal is an ordered sequence of continuous amplitude analog levels.

21. The source driver of claim 19, wherein the decoder, the collector, and the amplifier are located on the glass of the display panel between the pixel display area and the perimeter of the glass.

22. The source driver of claim 19, wherein the source driver does not include a digital-to-analog converter for converting video samples.

23. The source driver of claim 19, wherein the transistor is capable of operating at a first clock frequency required by the amplifier, a second clock frequency required by the collector, and a third clock frequency required by the decoder.

24. The source driver of claim 23, wherein the transistor is a thin-film transistor (TFT), and is a low-temperature polycrystalline silicon (LTPS) transistor or an indium gallium zinc oxide (IGZO) transistor.

25. The source driver of claim 19, wherein the pixels of the display panel are implemented using transistors of the same type used to implement the amplifier, the collector, and the decoder.

26. The source driver of claim 19, wherein the display unit is a display of a mobile phone.

27. The source driver of claim 19, further comprising: Multiple level shifters, each associated with and operating on one of the amplifiers to shift the voltage, wherein the level shifters are also implemented using at least transistors on the glass substrate of the display panel, and wherein the transistors are capable of operating at the clock frequency required by the level shifters.

28. A display unit, comprising: The display panel has a glass substrate; as well as Multiple source drivers, each source driver including: The decoder receives an analog signal representing the video stream's encoded sample values ​​and outputs the decoded sample values ​​during the decoding interval; A collector that inputs the decoded sample values ​​during a plurality of said decoding intervals and outputs a set of decoded sample values ​​after said plurality of decoding intervals; and Multiple amplifiers input the set of decoded sample values ​​and output voltage to the pixels of the display panel.

29. The display unit of claim 28, wherein the decoder and the collector are implemented outside the edge of the display panel of the display unit, wherein the amplifier is implemented using at least transistors on the glass substrate of the display panel, and wherein the transistors are capable of operating at a clock frequency required by the amplifier.

30. The display unit of claim 28, wherein the decoder is implemented outside the edge of the display panel of the display unit, wherein the collector and the amplifier are implemented using at least transistors on the glass substrate of the display panel, and wherein the transistors are capable of operating at a clock frequency required by the collector and a clock frequency required by the amplifier.

31. The display unit of claim 28, wherein the decoder, the collector, and the amplifier are implemented using at least transistors on the glass substrate of the display panel, and wherein the transistors are capable of operating at a clock frequency required by the decoder, a clock frequency required by the collector, and a clock frequency required by the amplifier.

32. The display unit of claim 28, wherein the analog signal is an ordered sequence of continuous amplitude analog levels.

33. The display unit of claim 29, wherein the plurality of amplifiers are located on the glass substrate of the display panel between the pixel display area and the perimeter of the glass substrate.

34. The display unit of claim 28, wherein the source driver does not include a digital-to-analog converter for converting video samples.

35. The display unit of claim 29, wherein the transistor is a thin-film transistor (TFT), and is a low-temperature polycrystalline silicon (LTPS) transistor or an indium gallium zinc oxide (IGZO) transistor.

36. The display unit of claim 30, wherein the transistor is a thin-film transistor (TFT), and is a low-temperature polycrystalline silicon (LTPS) transistor or an indium gallium zinc oxide (IGZO) transistor.

37. The display unit of claim 31, wherein the transistor is a thin-film transistor (TFT), and is a low-temperature polycrystalline silicon (LTPS) transistor or an indium gallium zinc oxide (IGZO) transistor.

38. The display unit of claim 29, wherein the pixels of the display panel are implemented using transistors of the same type used to implement the amplifier.

39. The display unit of claim 28, wherein the display unit is a display of a mobile phone.

40. The display unit of claim 29, further comprising: Multiple level shifters, each associated with and operating on one of the amplifiers to shift the voltage, wherein the level shifters are also implemented using at least transistors on the glass substrate of the display panel, and wherein the transistors are capable of operating at the clock frequency required by the level shifters.

41. The source driver of claim 1, wherein the collector is a two-stage collector.

42. The source driver of claim 10, wherein the collector is a two-stage collector.

43. The source driver of claim 19, wherein the collector is a two-stage collector.

44. The display unit of claim 28, wherein the collector is a two-stage collector.

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