Non-consistent master node, on-chip interconnection network, data processing method and device

Abstract

The present application discloses a non-consistent master node, an on-chip interconnection network, a data processing method and a device, and relates to the technical field of integrated circuits. The non-consistent master node comprises: a CHI, multiple AXIs, a protocol conversion module and an address mapping routing module; the multiple AXIs are respectively connected to the address mapping routing modules, and each AXI is connected to a second node with an AXI; the CHI is used to receive a first data processing transaction; the protocol conversion module is connected to the CHI, and is used to obtain a first data processing transaction in an AXI format; the address mapping routing module is connected to the protocol conversion module, and is used to determine the AXI corresponding to the first data processing transaction in an AXI format from the multiple AXIs; the AXI is used to send the first data processing transaction in an AXI format to the second node connected thereto, thereby realizing that a single non-consistent master node supports multiple second nodes, simplifies the system architecture, and reduces the design complexity and hardware resource consumption.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a non-consistent master node, an on-chip interconnection network, a data processing method and related devices. Background Art

[0002] In the field of high-performance integrated circuit design, especially in the field of complex system-on-chip design, efficient data transmission between devices in the system-on-chip and the interconnection architecture of the system-on-chip are crucial. However, in conventional technology, the design of the system-on-chip usually focuses more on the design of a single or limited number of interfaces, which limits the scalability and flexibility of the system-on-chip. In particular, when different bus protocols are involved between devices, for example, the bus protocols between the processor and the peripherals include CHI (Coherent Hub Interface) and AXI (Advanced eXtensible Interface), traditional designs often face challenges.

[0003] Traditional SoCs that use HNI (Non-coherent Home Node) architecture only support a single AXI Slave device (which can be understood as a slave device that supports the AXI protocol), which means that in a SoC containing multiple AXI interfaces, the SoC processor needs multiple HNI instances or complex bridge logic to implement communication with each AXI Slave device through the CHI bus. This SoC design not only increases the consumption of hardware resources, but also may lead to a sharp increase in system design complexity, affecting overall performance.

[0004] Therefore, the traditional system-on-chip using HNI architecture has problems such as insufficient scalability and flexibility and high system design complexity. A new HNI design method is urgently needed to overcome these technical obstacles and improve the overall performance and efficiency of the system. Summary of the invention

[0005] In view of the above problems, the present application provides a non-consistent master node, an on-chip interconnection network, an electronic device, a data processing method and related devices to achieve the purpose of improving scalability and flexibility and avoiding high complexity of system design.

[0006] The specific plan is as follows:

[0007] In a first aspect, the present application provides a non-coherent master node, comprising: a coherent hub interface CHI, a plurality of advanced extensible interfaces AXI, a protocol conversion module, and an address mapping routing module; wherein: the plurality of AXIs are respectively connected to the address mapping routing modules, and each AXI is also used to connect to a second node having an AXI;

[0008] The CHI is used to receive a first data processing transaction from a first node;

[0009] The protocol conversion module is connected to the CHI and is used to convert the format of the first data processing transaction to obtain the first data processing transaction in AXI format;

[0010] The address mapping routing module is connected to the protocol conversion module, and is used to determine the AXI corresponding to the first data processing transaction in the AXI format from the plurality of AXIs;

[0011] AXI is used to send a first data processing transaction in an AXI format to a second node connected thereto.

[0012] In some possible implementations, the non-consistent master node further includes: a transaction scheduling module connected to the CHI and the protocol conversion module, configured to determine a priority order of the first data processing transaction;

[0013] The protocol conversion module is used to perform format conversion on the first data processing transaction based on the priority order of the first data processing transaction to obtain the first data processing transaction in AXI format.

[0014] In some possible implementations, the inconsistency master node further includes: a data cache module connected to the CHI, the protocol conversion module and the address mapping routing module, for caching data processing transactions after format conversion by the protocol conversion module.

[0015] In some possible implementations, when the address mapping routing module determines the AX corresponding to the first data processing transaction in the AXI format from the multiple AXIs, it is used to:

[0016] Based on the address of the data processing transaction, the AXI corresponding to the first data processing transaction in AXI format is screened out from the address mapping table, where the address mapping table is a correspondence between the address range of the data processing transaction and the identifier of the AXI.

[0017] In some possible implementations, the CHI is further used to receive a second data processing transaction from a third node;

[0018] The transaction scheduling module is used to determine the priority order of the first data processing transaction and the priority order of the second data processing transaction in parallel;

[0019] The protocol conversion module is further used to convert the format of the second data processing transaction based on the priority order of the second data processing transaction to obtain the second data processing transaction in AXI format;

[0020] The address mapping routing module is also used to determine the AXI corresponding to the second data processing transaction in the AXI format from the multiple AXIs;

[0021] The AXI corresponding to the second data processing transaction in the AXI format is used to send the second data processing transaction in the AXI format to a third node connected thereto.

[0022] A second aspect of the present application provides an on-chip interconnection network, including: multiple routers, multiple routers are connected in pairs to form a router network, the routers in the router network are connected to non-consistent master nodes, and are also connected to any one or a combination of computing nodes and storage nodes, the non-consistent master nodes are such as the first aspect and any possible implementation method thereof.

[0023] A third aspect of the present application provides an electronic device, comprising an on-chip interconnect network as provided in the second aspect.

[0024] A fourth aspect of the present application provides a data processing method, comprising:

[0025] Obtaining a first data processing transaction from a first node;

[0026] Performing format conversion on the first data processing transaction to obtain the first data processing transaction in an advanced extensible interface AXI format;

[0027] Determine, from a plurality of advanced extensible interfaces (AXIs), an AXI corresponding to a first data processing transaction in an AXI format;

[0028] The first data processing transaction in the AXI format is sent to the second node via the AXI corresponding to the first data processing transaction in the AXI format.

[0029] The fifth aspect of the present application provides a computer program product, including computer-readable instructions. When the computer-readable instructions are executed on a device, the device implements the data processing method provided in the fourth aspect.

[0030] The sixth aspect of the present application provides a computer storage medium, which carries one or more computer programs. When the one or more computer programs are executed by a device, the device can implement the data processing method provided in the fourth aspect.

[0031] By means of the above technical solution, the non-consistent master node provided by the present application includes multiple advanced extensible interfaces AXI, each AXI is also used to connect a second node with AXI, the scalability and flexibility of the non-consistent master node are enhanced, and a single non-consistent master node supports multiple second nodes, which significantly reduces the demand for additional non-consistent master nodes, simplifies the system architecture, reduces the design complexity and hardware resource consumption. In addition, the non-consistent master node also includes an address mapping routing module, which is used to determine the AXI corresponding to the first data processing transaction in the AXI format from multiple AXIs, which can ensure that the data processing transactions received by the non-consistent master node through CHI can all be determined by the address mapping routing module The corresponding AXI is sent to the external node. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0033] Figure 1 A network topology diagram of a NoC provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of the structure of an HNI module provided in an embodiment of the present application;

[0035] Figure 3 A flowchart of a data processing method provided in an embodiment of the present application;

[0036] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation method section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0038] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0039] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0040] For ease of understanding, some technical terms involved in the embodiments of the present application are explained and described below.

[0041] 1. NoC: The full name is Network-on-Chip, which draws on the design concept of computer networks and designs the communication mechanism inside the chip into a micro network.

[0042] 2. AXI protocol: It stands for Advanced eXtensible Interface, which is a high-performance, high-bandwidth, low-latency on-chip bus protocol integrated in the AMBA bus architecture. AXI is a communication standard optimized for multi-core, high-complexity, and high-data exchange requirements in SoC (System-on-Chip) design. It is designed to improve system performance and simplify interconnectivity. It achieves high-efficiency, high-bandwidth, and low-latency data interaction through separate channel design, support for unaligned transmission, burst transmission, and excellent transmission access management, so it has a rich ecology and is widely used.

[0043] 3. CHI protocol: It refers to Coherent Hub Interface, which is an on-chip interconnect technology designed for high-performance multi-core systems. It optimizes data consistency management through packet transmission mode, ensures data synchronization in multi-processor environments, and supports complex system architectures and flexible topology designs. The layered and modular design of the CHI protocol allows NoC to be configured according to demand, compatible with components such as multi-level caches, multi-processor cores and accelerators, and adapts to a wide range of application scenarios. Support for multiple network topologies enhances the scalability and adaptability of the system, balancing performance, latency and energy consumption.

[0044] 4. HNI: Non-coherent Home Node, a special home node design that focuses on I / O transaction sequence management. It operates in the NoC system and is not responsible for cache consistency maintenance, but processes specific types of requests to ensure the correctness of the I / O operation sequence execution. As a key component of NoC design, HNI acts as a hub and plays the role of conversion between protocols to complete the intercommunication of CHI and AXI transactions.

[0045] 5. XP: Crossbar Router, a router in the on-chip network, is responsible for routing data packets to designated network nodes based on transaction IDs.

[0046] For example, Figure 1 It is demonstrated that an embodiment of the present application provides a NoC network architecture.

[0047] like Figure 1 As shown, the NoC includes: XP 101, computing node 102, storage node 103 and HNI module 104; wherein: Figure 1 The exemplary display shows that the NoC includes 4 XP101s, and the 4 XP101s are connected in pairs to form a router network. Among the 4 XP101s, one XP101 is connected to the computing node 102 and the storage node 103, and the other XP101 is connected to the computing node 102 and the HNI module 104, but this does not constitute a limitation on the network architecture of the NoC provided in the embodiment of the present application.

[0048] It is known that the NoC may also include more or fewer XP101, and the XP101 in the NoC may form a router network in a two-to-two connection manner; and the XP101 in the NoC may also be connected to the computing node 102, the storage node 103, the HNI module 104 or other nodes according to actual needs. In some embodiments, one XP101 may be connected to any two nodes among the computing node 102, the storage node 103, the HNI module 104 and other nodes. In other embodiments, when one XP101 is connected to an HNI module, it may be connected to one or more HNI modules.

[0049] XP101 is a routing node or router, which is mainly responsible for completing data communication tasks between computing nodes in NoC.

[0050] In some embodiments, the computing node 102 includes a processor, ie, an IP core, such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0051] In some embodiments, the storage node 103 includes random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), etc.

[0052] The HNI module 104 serves as a bridge for connecting to the XP101 and also for connecting to the AXI Slave device.

[0053] It should be noted that an AXI Slave device may refer to a device having an AXI interface, such as a storage device, a serial port device, and a display device.

[0054] In an application scenario, an XP101 in a NoC Figure 1 As shown, the computing node 101 and the HNI module 104 are connected respectively, and the HNI module 104 is connected to the AXI Slave device. The computing node 101 uses the CHI protocol to send a request message to XP101, and XP101 routes the request message to the HNI module 104 connected to it. After receiving the request message, the HNI module 104 can convert the format of the request message between the CHI protocol and the AXI protocol, and send the converted AXI protocol request message to the AXI Slave device, thereby achieving seamless connection between the CHI protocol and the AXI protocol.

[0055] Figure 2 An HNI module provided by an embodiment of the present application is shown.

[0056] The HNI module provided in the embodiment of the present application can be provided with multiple AXI interfaces, each of which can be used to connect an AXI Slave device, so that multiple AXI Slave devices can be efficiently supported, and there is no need for the NoC to deploy multiple HNI modules or complex bridging logic to support multiple AXI Slave devices, which will not increase hardware resources or design complexity. That is, the embodiment of the present application supports multiple AXI Slave devices by designing a single HNI module, which significantly reduces the need for additional HNI modules, simplifies the system architecture, and reduces design complexity and hardware resource consumption.

[0057] It can be seen from this that the HNI module provided in the embodiment of the present application is structurally innovative, realizes scalable design, allows configuration and management of multiple AXI interfaces, and breaks through the limitations of traditional one-to-one. This not only simplifies system design, but also improves integration and reduces the need for additional bridging logic.

[0058] For example, Figure 2 As shown, the HNI module includes: a CHI interface 201 , a transaction scheduling module 202 , a protocol conversion module 203 , an address mapping routing 204 , a data cache module 205 , and four independent AXI interfaces 206 .

[0059] The CHI interface 201 is connected to the XP101 in the NoC and can be used to receive the request message routed by the XP101, which can refer to a read or write request message. Each AXI interface 206 can be connected to an AXI Slave device. For example, Figure 2 In the example, the four AXI interfaces 206 of the HNI module are respectively connected to the four AXI Slave devices slave1 to slave4.

[0060] The transaction scheduling module 202 is used to connect to the CHI interface 201, and can sort the request messages received by the CHI interface 201 according to the priority order of the transactions, so as to process the request messages according to the priority order of the transactions.

[0061] In some embodiments, the transaction scheduling module 202 may also be configured with a priority reordering function. In some application scenarios, when the transaction scheduling module 202 receives a transaction request message, it may reorder the transaction request message based on the priority reordering function to obtain the priority of the transaction request message.

[0062] The protocol conversion module 203 integrates a protocol conversion hardware module, and is used to connect the CHI interface 201 and the address mapping router 204, and can complete the mutual conversion between CHI transactions and AXI transactions.

[0063] An address mapping table is integrated inside the HNI module, and the address mapping table includes: the correspondence between the address range of the transaction and the AXI interface, wherein the address in the address range of the transaction can refer to the address carried by the request message. Based on this, the address mapping routing 204, also known as the address mapping routing module, is used to automatically match the corresponding AXI interface from the address mapping table according to the transaction address, so as to realize routing the request message received by the CHI interface 201 to the corresponding AXI Slave device through the AXI interface.

[0064] The data cache module 205 is used to connect the address mapping route 204 and the CHI interface 201 , and can temporarily store the read and write data converted by the address mapping route 204 , and can also provide the temporarily stored data to the CHI interface 201 .

[0065] In some embodiments, the AXI interface includes five channels, namely: a read address channel (read address channel, referred to as AR), a read data channel (read data address channel, referred to as R), a write address channel (write address channel, referred to as AW), a write data channel (write data channel, referred to as W), and a write response channel (write response channel, referred to as B). From the perspective of reading and writing, the five channels can be divided into two groups (AR, R; AW, W, B), and from the perspective of data and address control, the five channels can be divided into three groups (R, W; AR, AW; B).

[0066] Based on the five channels of the AXI interface, the HNI module provided in the embodiment of the present application can efficiently manage concurrent transactions of multiple AXI Slave devices. Figure 1 and Figure 2 A data read request and a data write request are used as examples for explanation.

[0067] The computing node 102 sends a data read request for reading a specific data block in the cache, and the data read request is sent to the XP 101 based on the CHI protocol. After receiving the data read request, the XP 101 routes it to the HNI module according to the transaction ID of the data read request.

[0068] In some application scenarios, such as Figure 1As shown, the data read request received by XP101 is used to read a specific data block in the cache connected to HNI module 104. After receiving the data read request, XP101 can send the data read request to HNI module 104. In other application scenarios, the data read request received by XP101 is used to read a specific data block in the cache connected to other HNI modules connected to XP101. In this way, after receiving the data read request, XP101 can send the data read request to the HNI module through the transit routing of other XP101 based on the transaction ID of the data read request.

[0069] In some embodiments, the data read request includes a status bit, and the status bit is used to indicate the priority order of the data read request. For example, the status bit may indicate that the data read request is a high priority, a medium priority, or a low priority.

[0070] The CHI interface 201 of the HNI module receives the data read request sent by XP. In some embodiments, the channels of XP and the CHI interface 201 include: RXREQ, RXRSP, RXDAT, TXRSP and TXDAT. XP sends data to the CHI interface 201 through the three channels of RXREQ, RXRSP and RXDAT, and the CHI interface 201 sends data to XP through TXRSP and TXDAT.

[0071] The transaction scheduling module 202 obtains the data read request received by the CHI interface 201, and determines the priority of the data read request based on the status bit in the data read request. When the priority is high, the transaction scheduling module 202 can process the data read request as an immediate queued transaction; of course, when the priority is medium or low, the processing order of the data read request will be after the high priority transaction.

[0072] The protocol conversion module 203 obtains the data read request received by the CHI interface 201 based on the priority order of the data read request, and converts the data read request into the AXI format. The address mapping routing 204 obtains the data read request in the AXI format, decodes the address of the data read request, and matches the corresponding AXI interface 206 in the address mapping table based on the decoded address. The data read request in the AXI format converted by the protocol conversion module 203 is sent to the peripheral device, i.e., the AXI Slave device, through the AXI interface 206 matched by the address mapping routing 204.

[0073] Since the HNI module includes multiple AXI interfaces 206 , the HNI module can also implement concurrent processing of transactions based on the multiple AXI interfaces 206 .

[0074] Exemplarily, the address mapping route 204 matches the data read request corresponding to Figure 2The second AXI interface 206 is shown, and the data read request in the AXI format converted by the protocol conversion module 203 is sent to slave2 through the second AXI interface 206. In another exemplary embodiment, when the computing node 102 sends the data read request, Figure 1 Another computing node 102 (i.e. Figure 1 The compute node connected to XP101 in the lower left corner of the display also sends a data write request, which is used to write data to slave1. The data write request is passed Figure 1 The lower left corner XP101 , the upper left corner XP101 , and the upper right corner XP101 are shown routed to the HNI module 104 .

[0075] The CHI interface 201 of the HNI module 104 receives the data write request sent by XP, and the transaction scheduling module 202 queues the data write request according to the priority. It should be noted that the transaction scheduling module 202 can intelligently allocate its own resources and obtain the priority order of the data read request and the data write request in parallel.

[0076] The protocol conversion module 203 obtains the data write request received by the CHI interface 201 based on the priority order of the data write request, and converts the data write request into the AXI format. The address mapping routing 204 obtains the data write request in the AXI format, decodes the address of the data write request, and matches the first AXI interface 206 corresponding to it in the address mapping table based on the decoded address. In addition, when the priority order of the data read request and the data write request is the same, the protocol conversion module 203 and the address mapping routing 204 can also be considered to complete the format conversion and matching AXI interface operations for the data read request and the data write request in parallel.

[0077] The data read request in the AXI format converted by the protocol conversion module 203 is sent to slave2 through the second AXI interface 206, while the data write request in the AXI format converted by the protocol conversion module 203 is sent to slave1 through the first AXI interface 206. In this way, the concurrent processing of the two transactions of the data read request and the data write request is realized, and efficient resource reuse is realized, unnecessary idle waiting is reduced, and power consumption is reduced.

[0078] Specifically, the data read request in AXI format converted by the protocol conversion module 203 is sent to slave2 through the AR channel of the second AXI interface 206 , and the data write request in AXI format converted by the protocol conversion module 203 is sent to slave1 through the AW channel of the first AXI interface 206 .

[0079] The computing node sends a data read request to read data from slave 2. After receiving the data read request, slave 2 returns the data to the data cache module 205 of HNI through the R channel. After the data cache module 205 formats the data according to the CHI protocol according to the protocol conversion module 203, it returns it to XP101 through the channel of the CHI interface 201, and then returns it to the computing node.

[0080] When the HNI module receives the data indicated by the data write request sent by XP through the CHI interface 201, the protocol conversion module 203 converts it into the AXI format, the data cache module 205 caches it, and then transmits the data to slave1 through the first AXI interface 206W channel to complete the write operation. Afterwards, slave1 returns a confirmation message through the B channel, and the protocol conversion module 203 of the HNI module converts it into a CHI format message, sends it back to XP through the CHI interface, and then sends it back to the computing node.

[0081] based on Figure 1 and Figure 2 The NoC and HNI modules are shown. The embodiment of the present application also provides a data processing method, which can be understood as being executed by the HNI module in the NoC.

[0082] like Figure 3 As shown, the data processing method provided in the embodiment of the present application includes:

[0083] S301: Obtain data processing transactions of a first node.

[0084] In this step, the data processing transaction is a data processing transaction that is communicated between the first node and the second node. The first node is the initiator of the data processing transaction, and the second node is the responder of the data processing transaction. The first node can be understood as Figure 1 A computing node in the NoC shown, as described above, the data processing transactions sent by the computing node can be routed to the HNI module via one or more XP101. The second node is an AXI Slave device connected to the HNI module.

[0085] The data processing transaction is a transaction for processing data, and may include a data read request, a data write request, data to be written, etc. The data processing transaction is in CHI format.

[0086] S302: Determine the priority order of data processing transactions.

[0087] After the HNI module obtains the data processing transaction, it first determines the priority order of the data processing transaction based on the status bit of the data processing transaction, wherein the status bit is used to indicate the priority order of the data processing transaction.

[0088] In some application scenarios, after the HNI module obtains the data processing transaction and obtains the priority order of the data processing transaction, when it is determined that the NoC meets the conditions for reordering the transaction priority order, the priorities of multiple data processing transactions in the pending stage in the HNI module are reordered. Of course, the priority order of the data processing transaction of the first node is also adjusted.

[0089] The specific implementation of the HNI module executing step S302 can be found in the above content and will not be described again here.

[0090] S303: based on the priority order of the data processing transactions, when it is determined that the processing timing of the data processing transaction to be processed has arrived, convert the data processing transaction into the AXI format.

[0091] From the foregoing, it can be seen that the data processing transaction is in CHI format, and the responder of the data processing transaction, that is, the second node, usually includes an AXI interface and can only receive data processing transactions in AXI format. Therefore, the HNI module converts the data processing transaction into AXI format when it determines that the processing timing of the data processing transaction has arrived based on the priority order of the data processing transaction.

[0092] The specific implementation of the HNI module executing step S303 can be found in the above content and will not be described again here.

[0093] S304: Determine the AXI interface corresponding to the data processing transaction.

[0094] As can be seen from the foregoing, the HNI module includes multiple AXI interfaces, which enables efficient support for multiple AXI Slave devices. There is no need for the NoC to deploy multiple HNI modules or complex bridging logic to support multiple AXI Slave devices, which will not increase hardware resources or design complexity.

[0095] Therefore, after the HNI module obtains the data processing transaction in AXI format, it needs to determine the AXI interface corresponding to the data processing transaction from multiple AXI interfaces, and then send the data processing transaction to the AXI Slave device corresponding to the data processing transaction through the AXI interface.

[0096] In some embodiments, the HNI module is configured with an address mapping table, and the HNI module selects the AXI interface corresponding to the data processing transaction from the address mapping table based on the address of the data processing transaction.

[0097] The specific implementation of the HNI module executing step S304 can be found in the above content and will not be described again here.

[0098] S305 . Send the data transmission transaction to the second node through the AXI interface corresponding to the data processing transaction.

[0099] The HNI module sends the data transmission transaction to the second node through the AXI interface corresponding to the data processing transaction.

[0100] The specific implementation of the HNI module executing step S305 can be found in the above content and will not be described again here.

[0101] An embodiment of the present application further provides an electronic device, which includes a NoC. The NoC may be as shown in the above content, and the structure of the HNI module in the NoC and the data processing method executed may also be as shown in the above content.

[0102] The electronic device in the embodiments of the present application may be a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, an augmented reality (AR) / virtual reality (VR) device, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), etc., and the embodiments of the present application do not impose any restrictions on this.

[0103] Figure 4 An optional hardware structure diagram of an electronic device is shown.

[0104] refer to Figure 4 As shown, the electronic device may include a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), a microphone 162 (optional), an earphone jack 163 (optional), a processor 170, an external interface 180, a power supply 190 and other components. It can be understood that Figure 4 These are merely examples of electronic devices and do not constitute a limitation on the electronic device. The electronic device may include more or fewer components than those shown in the figure, or may combine certain components, or have different components.

[0105] The radio frequency unit 110 (optional) can be used for receiving and sending information or receiving and sending signals during a call, for example, after receiving the downlink information of the base station, it is sent to the processor 170 for processing; in addition, the designed uplink data is sent to the base station. Generally, the RF circuit includes but is not limited to an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier (Low Noise Amplifier, LNA), a duplexer, etc. In addition, the radio frequency unit 110 can also communicate with network devices and other devices through wireless communication. The wireless communication can use any communication standard or protocol, including but not limited to Global System of Mobile communication (Global System of Mobile communication, GSM), General Packet Radio Service (General Packet Radio Service, GPRS), Code Division Multiple Access (Code Division Multiple Access, CDMA), Wideband Code Division Multiple Access (Wideband Code Division Multiple Access, WCDMA), Long Term Evolution (Long Term Evolution, LTE), email, Short Messaging Service (SMS), etc.

[0106] It should be understood that the radio frequency unit 110 is optional and can be replaced by other communication interfaces, such as a network port.

[0107] The memory 120 can be used to store instructions and data. The memory 120 can mainly include an instruction storage area and a data storage area. The data storage area can store various data, such as multimedia files, texts, etc.; the instruction storage area can store software units such as operating systems, applications, instructions required for at least one function, or their subsets and extensions. It can also include a non-volatile random access memory; provide the processor 170 with hardware, software and data resources including management of computing and processing equipment, and support control software and applications. It is also used for the storage of multimedia files, and the storage of running programs and applications.

[0108] The processor 170 is the control center of the electronic device. It uses various interfaces and lines to connect various parts of the entire electronic device. By running or executing instructions stored in the memory 120 and calling data stored in the memory 120, it performs various functions of the electronic device and processes data, thereby controlling the electronic device as a whole. Optionally, the processor 170 may include one or more processing units; preferably, the processor 170 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 170.

[0109] In some embodiments, the processor and the memory may be implemented on a single chip, which adopts a NoC architecture.

[0110] The input unit 130 can be used to receive input digital or character information, and generate key signal input related to the user settings and function control of the portable multifunctional device. Specifically, the input unit 130 may include a touch screen 131 (optional) and / or other input devices 132. The touch screen 131 can collect the user's touch operations on or near it (such as the user's operation on or near the touch screen using any suitable object such as fingers, joints, stylus, etc.), and drive the corresponding connection device according to a pre-set program. The touch screen can detect the user's touch action on the touch screen, convert the touch action into a touch signal and send it to the processor 170, and can receive and execute commands sent by the processor 170; the touch signal at least includes contact point coordinate information. The touch screen 131 can provide an input interface and an output interface between the electronic device and the user. In addition, the touch screen can be implemented using multiple types such as resistive, capacitive, infrared, and surface acoustic wave.

[0111] In addition to the touch screen 131, the input unit 130 may also include other input devices. Specifically, the other input devices 132 may include, but are not limited to, one or more of a physical keyboard, a function key (such as a volume control key, a switch key, etc.), a trackball, a mouse, a joystick, etc. Among them, the other input devices 132 can receive input data, etc.

[0112] The display unit 140 may be used to display information input by a user or provided to a user, various menus of the electronic device, an interactive interface, file display, and / or playback of any multimedia file.

[0113] The electronic device also includes a power source 190 (such as a battery) for supplying power to various components. Preferably, the power source can be logically connected to the processor 170 through a power management system, so that the power management system can manage functions such as charging, discharging, and power consumption.

[0114] The electronic device also includes an external interface 180, which may be a standard Micro USB interface or a multi-pin connector, and may be used to connect the electronic device to communicate with other devices, or may be used to connect a charger to charge the electronic device.

[0115] Although not shown, the electronic device may further include a flash, a wireless fidelity (WiFi) module, a Bluetooth module, sensors with different functions, etc., which are not described in detail here.

[0116] The present application also provides a computer program product, which includes one or more computer instructions. When the computer instructions are executed on an electronic device, the process or function described in the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0117] A computer-readable storage medium is also provided in an embodiment of the present application. The storage medium carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement any data processing method provided in the embodiment of the present application.

Claims

1. An inconsistency master node, characterized in that: include: A coherent hub interface CHI, multiple advanced extensible interfaces AXI, a protocol conversion module and an address mapping routing module; wherein: the multiple AXIs are respectively connected to the address mapping routing modules, and each AXI is also used to connect to a second node with AXI; the CHI, the multiple advanced extensible interfaces AXI, the protocol conversion module and the address mapping routing module are all integrated in the non-coherent master node; The CHI is used to receive a first data processing transaction from a first node; The protocol conversion module is connected to the CHI and is used to perform format conversion on the first data processing transaction to obtain a first data processing transaction in AXI format; The address mapping routing module is connected to the protocol conversion module and is used to determine the AXI corresponding to the first data processing transaction in the AXI format from the multiple AXIs; The AXI is used to send a first data processing transaction in the AXI format to a second node connected thereto.

2. The non-consistent master node according to claim 1, characterized in that: Also includes: a transaction scheduling module connected to the CHI and the protocol conversion module, used to determine the priority order of the first data processing transaction; The protocol conversion module is used to perform format conversion on the first data processing transaction based on the priority order of the first data processing transaction to obtain the first data processing transaction in AXI format.

3. The non-consistent master node according to claim 2, characterized in that: Also includes: The data cache module connected to the CHI, the protocol conversion module and the address mapping routing module is used to cache the data processing transactions after the format conversion is performed by the protocol conversion module.

4. The non-consistent master node according to any one of claims 1 to 3, characterized in that: When the address mapping routing module is executed to determine the AX corresponding to the first data processing transaction in the AXI format from the plurality of AXIs, it is used to: Based on the address of the data processing transaction, the AXI corresponding to the first data processing transaction in the AXI format is screened out from the address mapping table, wherein the address mapping table is a correspondence between the address range of the data processing transaction and the identifier of the AXI.

5. The non-consistent master node according to claim 2, characterized in that: The CHI is also used to receive a second data processing transaction from a third node; The transaction scheduling module is used to determine the priority order of the first data processing transaction and the priority order of the second data processing transaction in parallel; The protocol conversion module is further used to perform format conversion on the second data processing transaction based on the priority order of the second data processing transaction to obtain the second data processing transaction in AXI format; The address mapping routing module is further used to determine the AXI corresponding to the second data processing transaction in the AXI format from the multiple AXIs; The AXI corresponding to the second data processing transaction in the AXI format is used to send the second data processing transaction in the AXI format to a third node connected thereto.

6. An on-chip interconnect network, characterized in that: include: Multiple routers are connected in pairs to form a router network, wherein the routers in the router network are connected to non-consistent master nodes and are also connected to any one or a combination of computing nodes and storage nodes, and the non-consistent master node is as described in any one of claims 1 to 5.

7. An electronic device, characterized in that: Comprising the on-chip interconnect network as claimed in claim 6.

8. A data processing method, characterized in that: Applied to an incoherent master node; the incoherent master node is integrated with a coherent hub interface CHI, multiple advanced extensible interfaces AXI, a protocol conversion module and an address mapping routing module; wherein: the multiple AXIs are respectively connected to the address mapping routing modules, and each AXI is also used to connect to a second node with AXI; the method comprises: Acquire a first data processing transaction from a first node through the CHI; Performing format conversion on the first data processing transaction by the protocol conversion module to obtain a first data processing transaction in an advanced extensible interface AXI format; Determine, by the address mapping routing module, from a plurality of advanced extensible interfaces AXI, the AXI corresponding to the first data processing transaction in the AXI format; The first data processing transaction in the AXI format is sent to the second node via the AXI corresponding to the first data processing transaction in the AXI format.

9. A computer program product, characterized in that The device comprises computer-readable instructions, which, when executed on a device, enable the device to implement the data processing method according to claim 8.

10. A computer storage medium, characterized in that: The computer storage medium carries one or more computer programs, and when the one or more computer programs are executed by the device, the device can implement the data processing method as claimed in claim 8.

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