Source driving chip and display system

Abstract

The embodiment of the application discloses a kind of source electrode driving chip and display system, belong to display technical field.The source electrode driving chip has first input and first output, the source electrode driving chip includes lock signal control circuit, and the lock signal control circuit is connected between the first input and the first output;The lock signal control circuit is used to control the lock signal of the first input by first level switching second level based on the lock signal of the first output when the source electrode driving chip occurs exception, and the second level is less than the first level.In the application, when one source electrode driving chip in display system appears abnormal condition, each source electrode driving chip will reset, can avoid having liquid crystal molecule long time receiving same driving voltage and leading to polarization, also can avoid that source electrode driving chip decodes unnecessarily to configuration signal and leads to configuration failure or dead machine.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a source driver chip and display system. Background Technology

[0002] Current display systems typically include components such as a TCON (Timing Controller), SD (Source Driver), and an LCD panel. The source driver circuit may contain multiple SDICs (Source Driver Integrated Circuits). The timing controller can transmit signals to the source driver circuit via a point-to-point communication protocol to deliver display data to the source driver circuit. The source driver circuit then controls the rotation direction of the liquid crystal molecules to control whether polarized light is emitted from each pixel, thereby achieving the display purpose.

[0003] It is important to note that point-to-point communication protocols employ a locking mechanism. Before transmitting display data, the source driver chip needs to recover clock data. If clock data recovery is successful, the source driver chip locks and outputs a high-level lock signal. If recovery fails, it unlocks and outputs a low-level lock signal. If multiple source driver chips are cascaded in the source driver circuit, and all chips are locked, if one chip malfunctions, the malfunctioning chip and all cascaded chips following it will reset. However, the other source driver chips preceding the malfunctioning chip will not reset. This could cause the liquid crystal molecules corresponding to these non-reset source driver chips to become polarized due to receiving the same driving voltage for an extended period, leading to malfunction of the display system. Summary of the Invention

[0004] This application provides a source driver chip and a display system, which can avoid the problem in related technologies where, after one source driver chip malfunctions and is reset, the liquid crystal molecules corresponding to the unreset source driver chip receive the same driving voltage for a long time, leading to polarization. The technical solution is as follows:

[0005] On one hand, a source driver chip is provided, the source driver chip having a first input terminal and a first output terminal, the source driver chip including a lock signal control circuit, the lock signal control circuit being connected between the first input terminal and the first output terminal;

[0006] The lock signal control circuit is used to control the lock signal at the first input terminal to switch from a first level to a second level based on the lock signal at the first output terminal when the source driver chip malfunctions, wherein the second level is lower than the first level.

[0007] Optionally, the lock signal control circuit includes a switch and a switch control circuit;

[0008] The switch is connected between the first input terminal and the first output terminal. The input terminal of the switch control circuit is connected to the first input terminal, and the output terminal of the switch control circuit is connected to the control terminal of the switch.

[0009] The switch control circuit is used to detect the lock signal at the first input terminal after the source driver chip is powered on and stabilized. When the lock signal at the first input terminal is detected to be a first level lock signal, the switch is controlled to open. When the lock signal at the first input terminal is detected to be a second level lock signal, the switch is controlled to close.

[0010] Optionally, the switch control circuit includes a switch controller and a first resistor;

[0011] The power supply terminal of the switch controller is used to connect to a second external power source, the input terminal of the switch controller is used to connect to the first input terminal, the output terminal of the switch controller is connected to the control terminal of the switch, one end of the first resistor is connected to the input terminal of the switch controller, and the other end of the first resistor is grounded.

[0012] Optionally, the source driver chip further includes an anomaly detection module and a lock signal driving circuit;

[0013] The input terminal of the lock signal driving circuit is connected to the anomaly detection module, and the output terminal of the lock signal driving circuit is connected to the first output terminal.

[0014] The anomaly detection module is used to output a first-level lock signal to the input terminal of the lock signal driving circuit when the source driver chip is detected to be working normally, and to output a second-level lock signal to the input terminal of the lock signal driving circuit when the source driver chip is detected to be malfunctioning.

[0015] The lock signal driving circuit is used to control the lock signal at the second output terminal to be a lock signal at the first level when a lock signal at the first level is received, and to control the lock signal at the second output terminal to be a lock signal at the second level when a lock signal at the second level is received.

[0016] Optionally, the lock signal driving circuit includes an inverter, a MOS (Metal Oxide Semiconductor) transistor, and a second resistor;

[0017] The input terminal of the inverter is connected to the anomaly detection module, the output terminal of the inverter is connected to the gate of the MOS transistor, the source of the MOS transistor is grounded, the drain of the MOS transistor is connected to the first output terminal, one end of the second resistor is connected to the drain of the MOS transistor, and the other end of the second resistor is grounded.

[0018] On the other hand, a display system is provided, the display system including a plurality of source driver chips and a timing controller;

[0019] The source driver chip has a first input terminal, a first output terminal, and a second input terminal. Multiple source driver chips are cascaded through the first input terminal and the first output terminal. The first input terminal of the first cascaded source driver chip is used to connect to a first external power supply. The first output terminal of the last cascaded source driver chip is connected to the timing controller. The second input terminal of the source driver chip is connected to the timing controller.

[0020] Among them, for the target source driver chip in the cascaded second to last source driver chip, the target source driver chip includes a lock signal control circuit, which is connected between the first input terminal and the first output terminal of the target source driver chip;

[0021] The lock signal control circuit of the target source driver chip is used to control the lock signal at the first input terminal to switch from a first level to a second level based on the lock signal at the first output terminal when the target source driver chip malfunctions, wherein the second level is lower than the first level.

[0022] Optionally, the lock signal control circuit includes a switch and a switch control circuit;

[0023] The switch is connected between the first input terminal and the first output terminal of the target source driver chip. The input terminal of the switch control circuit is connected to the first input terminal of the target source driver chip, and the output terminal of the switch control circuit is connected to the control terminal of the switch.

[0024] The switch control circuit is used to detect the lock signal at the first input terminal of the target source driver chip after the target source driver chip is powered on and stabilized. When the lock signal at the first input terminal of the target source driver chip is detected to be a first-level lock signal, the switch is controlled to open. When the lock signal at the first input terminal of the target source driver chip is detected to be a second-level lock signal, the switch is controlled to close.

[0025] Optionally, the switch control circuit includes a switch controller and a first resistor;

[0026] The power supply terminal of the switch controller is used to connect to a second external power source, the input terminal of the switch controller is used to connect to the first input terminal, the output terminal of the switch controller is connected to the control terminal of the switch, one end of the first resistor is connected to the input terminal of the switch controller, and the other end of the first resistor is grounded.

[0027] Optionally, the target source driver chip further includes an anomaly detection module and a lock signal driving circuit;

[0028] The input terminal of the lock signal driving circuit is connected to the anomaly detection module, and the output terminal of the lock signal driving circuit is connected to the first output terminal.

[0029] The anomaly detection module is used to output a first-level lock signal to the input terminal of the lock signal driving circuit when the source driver chip is detected to be working normally, and to output a second-level lock signal to the input terminal of the lock signal driving circuit when the source driver chip is detected to be malfunctioning.

[0030] The lock signal driving circuit is used to control the lock signal at the second output terminal to be a lock signal at the first level when a lock signal at the first level is received, and to control the lock signal at the first output terminal to be a lock signal at the second level when a lock signal at the second level is received.

[0031] Optionally, the lock signal driving circuit includes an inverter, a MOSFET, and a second resistor;

[0032] The input terminal of the inverter is connected to the anomaly detection module, the output terminal of the inverter is connected to the gate of the MOS transistor, the source of the MOS transistor is grounded, the drain of the MOS transistor is connected to the first output terminal, one end of the second resistor is connected to the drain of the MOS transistor, and the other end is grounded.

[0033] Optionally, the display system further includes a third resistor, one end of which is connected to the first output terminal of the last cascaded source driver chip, and the other end is connected to a third external power supply.

[0034] The technical solution provided in this application can bring at least the following beneficial effects:

[0035] In this embodiment, a latch signal control circuit is added to the source driver chip. This allows the latch signal at the first input terminal to switch from a first level to a second level based on the latch signal at the first output terminal when the source driver chip malfunctions. This triggers other source driver chips cascaded before the first input terminal to reset. Therefore, this avoids the problem of polarization caused by liquid crystal molecules in other source driver chips cascaded before the first input terminal receiving the same driving voltage for an extended period. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram showing the connection relationship between a timing controller and multiple source driver chips.

[0038] Figure 2 This is a schematic diagram of the structure of a source driver chip provided in an embodiment of this application;

[0039] Figure 3 This is a schematic diagram of another source driver chip provided in an embodiment of this application;

[0040] Figure 4 This is a schematic diagram of another source driver chip provided in an embodiment of this application;

[0041] Figure 5 This is a schematic diagram of another source driver chip provided in an embodiment of this application;

[0042] Figure 6 This is a schematic diagram of another source driver chip provided in an embodiment of this application;

[0043] Figure 7 This is a schematic diagram of some signal waveforms after a source driver chip is powered on, provided in an embodiment of this application.

[0044] Figure 8 This is a schematic diagram of another source driver chip provided in an embodiment of this application;

[0045] Figure 9 This is a schematic diagram of another source driver chip provided in an embodiment of this application;

[0046] Figure 10 This is a schematic diagram of another source driver chip provided in an embodiment of this application;

[0047] Figure 11 This is a schematic diagram of the structure of a display system provided in an embodiment of this application;

[0048] Figure 12 This is a flowchart of a display system provided in an embodiment of this application. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0050] Current display systems typically include a timing controller and multiple source driver chips. The timing controller and source driver chips usually communicate via a point-to-point communication protocol, which contains a locking mechanism. For example... Figure 1 As shown, in this case, there are two types of transmission lines between the timing controller and multiple source driver chips (three are used as an example in the figure). One type is a data transmission line ( Figure 1 The solid line between the timing controller and multiple source driver chips is used by the timing controller to send training signals, configuration signals, and display data to the source driver chips. One type is the lock signal transmission line (…). Figure 1 The dashed lines between multiple source driver chips (and between the timing controller and the rightmost source driver chip) are used to transmit lock signals so that the timing controller knows whether the current source driver chip is in normal working condition.

[0051] like Figure 1 As shown, each source driver chip has a first input terminal (LOCK IN) and a first output terminal (LOCK OUT). Multiple source driver chips are cascaded through their first input and first output terminals. The first input terminal of the first cascaded source driver chip is connected to an external power supply, and the first output terminal of the last cascaded source driver chip is connected to a timing controller. Each source driver chip has an internal input terminal, which can be called the PHY LOCK internal terminal. Figure 1 (Not shown in the image). The lock's internal drive terminal is affected by an anomaly detection module within the source drive chip (…). Figure 1 (Not shown in the image) control.

[0052] in, Figure 1 The connection relationship of the display system shown can be called the "LOCK Cascade" mode.

[0053] After power-on, the anomaly detection module inputs a low-level lock signal to the internal driver terminal of the lock, causing the first output terminal of each source driver chip to also be a low-level lock signal. The timing controller first sends a training signal to each source driver chip. After multiple source driver chips receive the training signal, they extract the clock information from the training signal to complete clock data recovery. This ensures that the source driver chips can correctly sample the display data after receiving it, thus enabling subsequent processing and transmission of the display data. When the anomaly detection module detects that the source driver chip has successfully completed clock data recovery, it outputs a high-level lock signal, and the first output terminal of each source driver chip also becomes high accordingly. When the timing controller detects that the output of the first output terminal of the last source driver chip changes from a low-level lock signal to a high-level lock signal, it sends a configuration signal to each source driver chip. After receiving the configuration signal, each source driver chip sets its configuration parameters. Only after sending the configuration signal will the timing controller begin sending display data to the source driver chips, which then display the image on the LCD panel according to the display driver signal.

[0054] After the source driver chip completes clock data recovery, the anomaly detection module monitors the bit error rate of the configuration signal and display data. When the bit error rate exceeds a set threshold, the anomaly detection module considers the source driver chip to be malfunctioning and outputs a low-level latch signal, causing the first output terminal of the source driver chip to output a low-level latch signal. Additionally, if an external anomaly such as a power outage occurs suddenly after the source driver chip completes clock data recovery, the first output terminal of the source driver chip will also output a low-level latch signal.

[0055] After the output of the first source driver chip changes from a high-level latch signal to a low-level latch signal, the chip automatically resets, clearing its configuration parameters and clock data. Simultaneously, the first input of the source driver chip cascaded after this chip also receives a low-level latch signal, causing its first output to also output a low-level latch signal. This process continues, with all other source driver chips cascaded after this chip outputting low-level latch signals and resetting. However, the source driver chips cascaded before this chip are unaware of this abnormality. Therefore, their first outputs remain high-level latch signals, and they continue to operate normally without resetting.

[0056] When the timing controller detects that the output of the last source driver chip changes from a high-level latch signal to a low-level latch signal, it retransmits the training signal. Furthermore, the timing controller simultaneously sends the training signal to all source driver chips. Thus, for source driver chips that haven't been reset, since they are still operating normally, they will treat the received training signal as display data to drive the corresponding liquid crystal molecules. If the malfunctioning source driver chip fails to recover within a certain period, and the timing controller cannot detect the last source driver chip's output changing from a low-level latch signal to a high-level latch signal, the timing controller will continue to send the training signal. Consequently, these unreset source driver chips may drive the corresponding liquid crystal molecules at the same voltage for an extended period, potentially causing polarization of the liquid crystal molecules and preventing them from functioning properly.

[0057] Additionally, it should be noted that point-to-point communication protocols include those with and without scramble encryption. For example, the commonly used CEDS (Clock Embedded Differential Signaling) communication protocol does not use scramble encryption, while the CHPI (Common Hardware Description Language Procedural Interface) communication protocol does use scramble encryption. Furthermore, the training and configuration signals sent by the timing controller are unencrypted. Whether encryption is used for the displayed data is determined by the configuration signal sent by the timing controller, which informs the source driver chip, which then configures the parameters accordingly.

[0058] In the above scenario, suppose a source driver chip suddenly malfunctions. After the timing controller resends the training signal, the original source driver chip and other source driver chips cascaded after it recover their clock data. The timing controller then sends a configuration signal to each source driver chip. Since each source driver chip can recognize this signal as a configuration signal, those that have already been reset will directly configure their parameters based on it. However, for source driver chips that have not been reset, if they used scramble encryption in their previous configuration, they will decode the received configuration signal using scramble encryption and then configure their parameters based on the decoded data. Because the configuration signal sent by the timing controller is not encrypted, the data used by these unreset source driver chips for parameter configuration may be incorrect. This could lead to configuration failures or system crashes, preventing these unreset source driver chips from functioning normally.

[0059] Based on this, embodiments of this application provide a source driver chip and a display system including such a source driver chip, which enables each source driver chip to be reset when one source driver chip malfunctions, thereby solving the above-mentioned problem.

[0060] The source driver chip provided in the embodiments of this application will be described in detail below. In the accompanying drawings, the latch signal transmission lines are represented by dashed lines.

[0061] This application provides a source driver chip, such as... Figure 2 As shown, the source driver chip 1 has a first input terminal a and a first output terminal b. The source driver chip 1 includes a latch signal control circuit 11, which is connected between the first input terminal a and the first output terminal b.

[0062] The lock signal control circuit 11 is used to control the lock signal of the first input terminal a to switch from a first level to a second level based on the lock signal of the first output terminal b when the source driver chip 1 malfunctions. The second level is lower than the first level.

[0063] For example, the first level is the high level "1" in a digital signal, and the second level is the low level "0" in a digital signal.

[0064] In this context, "source driver chip 1 malfunction" refers to a sudden abnormality that occurs during the normal operation of the source driver chip 1 after clock data recovery. Examples include a sudden power loss during parameter configuration or an excessively high bit error rate during data transmission.

[0065] In some embodiments, such as Figure 3As shown, the source driver chip 1 also includes an anomaly detection module 12 and a lock signal driving circuit 13; the input terminal s1 of the lock signal driving circuit 13 is connected to the anomaly detection module 12, and the output terminal s2 of the lock signal driving circuit 13 is connected to the first output terminal b.

[0066] The anomaly detection module 12 is used to output a first-level lock signal to the input terminal s1 of the lock signal driving circuit 13 when the source driver chip 1 is detected to be working normally, and to output a second-level lock signal to the input terminal s1 of the lock signal driving circuit 13 when an anomaly is detected in the source driver chip 1. The detailed working principle of the anomaly detection module 12 is the same as that of the anomaly detection module described above, and will not be repeated here.

[0067] The lock signal driving circuit 13 is used to control the lock signal at the first output terminal b to be a lock signal at the first level when a lock signal at the first level is received, and to control the lock signal at the first output terminal b to be a lock signal at the second level when a lock signal at the second level is received.

[0068] When a source driver chip malfunctions, the lock signal at the first output terminal of the source driver chip switches from a first level to a second level under the action of the fault detection module and the lock signal driving circuit. This causes other source driver chips cascaded after the source driver chip to also be reset. In this embodiment, when a source driver chip malfunctions, the newly added lock signal control circuit can control the lock signal at the first input terminal of the source driver chip to also switch from a first level to a second level. This allows other source driver chips cascaded before the source driver chip to also be reset. This avoids the situation where, when multiple source driver chips are cascaded, there are still source driver chips that have not been reset when one source driver chip malfunctions. Consequently, it can prevent the polarization phenomenon of the liquid crystal molecules corresponding to the unreset source driver chips.

[0069] In some embodiments, such as Figure 4 As shown, the lock signal control circuit 11 includes a switch 111 and a switch control circuit 112. The switch 111 is connected between the first input terminal a and the first output terminal b. The input terminal k1 of the switch control circuit 112 is connected to the first input terminal a, and the output terminal k2 of the switch control circuit 112 is connected to the control terminal z1 of the switch 111.

[0070] The switch control circuit 112 is used to detect the lock signal of the first input terminal a after the source driver chip 1 is powered on and stabilized. When the lock signal of the first input terminal a is detected to be a first level lock signal, the switch 111 is opened. When the lock signal of the first input terminal a is detected to be a second level lock signal, the switch 111 is closed.

[0071] It should be noted that when the source driver chip 1 is not powered on, switch 111 is in the open state. The switch control circuit 112 only detects the latch signal at the first input terminal a after each power-on and stabilization, and controls switch 111 to close or remain in the open state based on the latch signal at the first input terminal a, thus completing the initialization of switch 111. After the initialization of switch 111 is complete, the switch control circuit 112 controls switch 111 to always remain in the open or closed state.

[0072] There are other cascaded source driver chips before the source driver chip 1. After power-on, the latch signal of the first input terminal a of the source driver chip 1 is a second-level latch signal. Therefore, the switch control circuit 112 of the source driver chip 1 will control the switch 111 to close.

[0073] When the source driver chip 1 malfunctions, the latch signal at its first output terminal b switches from a first level to a second level. Since the switch 111 between the first input terminal a and the first output terminal b is closed, the second-level latch signal at the first output terminal b can be directly transmitted to the first input terminal a, that is, to the first output terminal of the source driver chip cascaded before the source driver chip 1. Following the same transmission process, the second-level latch signal is finally transmitted to the first output terminal of the first source driver chip. Thus, when the source driver chip 1 malfunctions, the latch signal at the first output terminal b of each source driver chip cascaded before the source driver chip 1 can change to the second level, allowing these other source driver chips cascaded before the malfunctioning source driver chip 1 to be reset.

[0074] In some embodiments, such as Figure 5 As shown, the switch control circuit 112 includes a switch controller u1 and a first resistor r1. The power supply terminal g of the switch controller u1 is used to connect to a second external power supply, the input terminal u11 of the switch controller u1 is used to connect to the first input terminal a, the output terminal u12 of the switch controller u1 is connected to the control terminal z1 of the switch 111, and one end of the first resistor r1 is connected to the input terminal u11 of the switch controller u1, and the other end is grounded.

[0075] The switch controller u1 triggers the detection of the signal at the first input terminal a after the power supply terminal g is powered on and stabilized, and controls the switch 111 to open or close according to the signal at the first input terminal a.

[0076] Normally, the resistance of the first resistor r1 is relatively large so that the static current on the first resistor r1 is small, thus avoiding unnecessary power consumption inside the source driver chip.

[0077] In some embodiments, such as Figure 6As shown, the switch controller u1 includes a D (Data) flip-flop f1, a logic AND circuit f2, a first inverter f3, a second inverter f4, a Schmitt trigger f5, and a data selector f6.

[0078] In this circuit, the data input terminal D of D flip-flop f1 is connected to the first input terminal a, the clock signal input terminal clk of D flip-flop f1 is connected to the output terminal of the AND circuit f2, and the output terminal Q of D flip-flop f1 is connected to the first inverter f3. The two input terminals of the AND circuit f2 are connected to the output terminal of the second inverter f4 and the power supply terminal g, respectively. The input terminal of the second inverter f4 is connected to the fault detection module 12. The output terminal of the first inverter f3 is connected to the first data input terminal D1 of the data selector f6, the second data input terminal D2 of the data selector f6 is grounded, the selection terminal sel of the data selector f6 is connected to the output terminal of the Schmitt trigger f5, and the output terminal of the data selector f6 is the output terminal u12 of the switch controller u1. The input terminal of the Schmitt trigger f5 is connected to the power supply terminal g.

[0079] It should be noted that in this example, switch 111 is a high-level enabled switch, such as a switch designed using an NPN transistor.

[0080] After power-on, the signal waveforms at the power supply terminal g, output terminal u12, first input terminal b of the source driver chip 1, and the signal waveform output by the anomaly detection module 12 are as follows: Figure 7 As shown below, the working principle of the switch controller, and Figure 7 The changes in the signal waveform are explained.

[0081] like Figure 7 As shown, after power is applied to the power supply terminal g of the switch controller u1, the voltage at the power supply terminal g does not immediately become high. Instead, it gradually rises from a low level and stabilizes at a high level after a certain period of time, reaching a stable power-on state. Furthermore, the Schmitt trigger f5 outputs a high level when the received voltage level is higher than its set threshold, and outputs a low level when the received voltage level is lower than its set threshold. Also, the rising edge of the D flip-flop f1 is valid. That is, the D flip-flop f1 is triggered only when the clock signal input terminal clk changes from low to high, updating its output data to the data input terminal D; otherwise, the output of the D flip-flop f1 remains unchanged.

[0082] Therefore, at the initial power-on, the signal received by Schmitt trigger f5 does not reach its set threshold, so Schmitt trigger f5 outputs a low level. The selection terminal sel of data selector f6 receives a low level, and at this time, data selector f6 outputs the signal of the second data input terminal D2, i.e., outputs a low level, and switch 111 is in the open state. Furthermore, at the initial power-on, although the abnormal detection module 12 outputs a low-level lock signal, causing the second inverter f4 to output a high level, since the power supply terminal g is at a low level at this time, the logic AND circuit f2 outputs a low level, and the clock signal input terminal clk of D flip-flop f1 is at a low level. At this time, D flip-flop f1 is not triggered and will not update the output data to the data currently input to its data input terminal D (i.e., the signal of the first input terminal a). The output of D flip-flop f1 remains unchanged at this time, which is the initial state of D flip-flop f1 when it is first powered on. This initial state can be any value depending on the specific design of D flip-flop f1, and this embodiment does not limit it. Since the output of data selector f6 is only related to the signal at its second data input terminal D2, the output of data selector f6 is not affected regardless of the output value of D flip-flop f1.

[0083] After power-on stabilization, the signal received by Schmitt trigger f5 reaches its set threshold, and Schmitt trigger f5 outputs a high level. The selection terminal sel of data selector f6 receives a high level, and at this time, data selector f6 outputs the signal of the first data input terminal D1, that is, the signal output by the first inverter f3. At this time, since the second inverter f4 outputs a high level and the power supply terminal g is also at a high level, the logic AND circuit f2 outputs a high level, and the clock signal input terminal clk of D flip-flop f1 changes from a low level to a high level, triggering D flip-flop f1. At this time, D flip-flop f1 detects the input data of its data input terminal D and outputs the same data as the current input of its data input terminal D.

[0084] Assuming there are other cascaded source driver chips preceding the source driver chip 1, as described above, after power-on and before clock data recovery, the first input terminal a of the source driver chip 1 is at a low level. As deduced above, after power-on stabilization, the output of D flip-flop f1 is the same as the current input of its data input terminal D. Therefore, the output of D flip-flop f1 is the same as the output of the first input terminal a, which is low, causing the first inverter f3 to output a high level, i.e., the first data input terminal D1 of the data selector f6 is high. As also deduced above, after power-on stabilization, the output of the data selector f6 is exactly the signal of the first data input terminal D1. Therefore, the data selector f6 outputs a high level, causing switch 111 to close.

[0085] After clock data recovery is complete, the anomaly detection module 12 outputs a high-level lock signal, causing the second inverter f4 to output a low level. Therefore, the AND circuit f2 outputs a low level (in an AND circuit, if any input is low, the output is low). At this time, the clock signal input clk of the D flip-flop f1 changes from high to low, and the D flip-flop f1 is not triggered, maintaining its current output (low level) and not changing with the data input D. In other words, although the first input a of the source driver chip 1 changes from low to high after clock recovery, causing the data input D of the D flip-flop f1 to change from low to high, the output of the D flip-flop f1 remains low, thus keeping the data selector f6's current output (high level) and keeping switch 111 closed.

[0086] If the source driver chip 1 malfunctions at some point, as described above, the latch signal at the first output terminal b will go low. Since switch 111 is closed, the latch signal at the first input terminal a will also go low. Figure 7 (The signal waveform is not shown in this case). Simultaneously, when the source driver chip 1 malfunctions, the fault detection module 12 outputs a low-level lock signal. At this time, the second inverter f4 outputs a high level, and the power supply terminal g is also high. Therefore, the logic AND circuit f2 outputs a high level, and the clock signal input terminal clk of the D flip-flop f1 changes from low to high. The D flip-flop f1 is triggered, and the output of the output terminal Q is the same as the current input of the data input terminal D. That is, at this time, the output of the D flip-flop f1 will again maintain the same level as the first input terminal a. Since the lock signal of the first input terminal a is low at this time, the D flip-flop f1 still outputs a low level, thus causing the data selector f6 to still output a high level, thereby keeping the switch 111 in the closed state.

[0087] Therefore, it can be seen that after the switch controller u1 controls the switch 111 to close after power-on stabilization, the switch 111 will always be in the closed state, whether the source drive chip 1 is in the process of normal operation after power-on stabilization but before clock data recovery is completed, or in the process of normal operation when an abnormality suddenly occurs.

[0088] It should be noted that, Figure 6 This is merely one example of a switch controller u1; the switch controller u1 is not limited to this. Figure 6 The components and their connections are shown. It is important to note that... Figure 6In the switch controller u1 shown, the input terminal of the second inverter f4 is connected to the anomaly detection module 12. The function of this anomaly detection module 12 in the switch controller u1 is to provide a rising edge trigger signal to the D flip-flop f1 after power-on stabilization. This allows the D flip-flop f1 to detect the signal at the first input terminal a after power-on stabilization, thereby triggering the switch controller u1 to detect the signal at the first input terminal a after power-on stabilization and control the switch 111 to open or close based on the signal at the first input terminal a. Therefore, the connection of the anomaly detection module 12 is not necessary; other methods can also be used to provide a suitable trigger signal to the D flip-flop f1.

[0089] In some embodiments, such as Figure 8 As shown, Figure 3 The lock signal driving circuit 13 shown includes an inverter u2, a MOSFET Q1, and a second resistor r2. The input terminal u21 of the inverter u2 is connected to the abnormal detection module 12, the output terminal u22 of the inverter u2 is connected to the gate G of the MOSFET Q1, the source S of the MOSFET Q1 is grounded, the drain D of the MOSFET Q1 is connected to the first output terminal b, and one end of the second resistor r2 is connected to the drain D of the MOSFET Q1, while the other end is grounded.

[0090] In this embodiment, the resistance value of the second resistor r2 is not specifically limited.

[0091] When the anomaly detection module 12 outputs a first-level lock signal, the inverter u2 outputs a second-level signal to the gate of MOSFET Q1, and MOSFET Q1 is not turned on. At this time, due to the presence of the second resistor r2, the first output terminal b is in a high-impedance state. It is necessary to determine whether the lock signal output by the first output terminal b is at the first level or the second level based on the lock signal at the first input terminal of the next source driver chip cascaded with the source driver chip 1. This process will be described in detail in the later embodiment of the display system, and will not be elaborated here.

[0092] When the anomaly detection module 12 outputs a second-level lock signal, the MOS transistor Q1 is turned on, and the first output terminal b is grounded through the turned-on MOS transistor Q1, and the first output terminal b outputs a second-level lock signal.

[0093] It should be noted that, Figure 8 This is merely one example of the lock signal drive circuit 13, and the lock signal drive circuit 13 is not limited to this. Figure 8 The components and their connections.

[0094] In some embodiments, such as Figure 9As shown, the source driver chip 1 also includes a lock detection circuit 14 and a reset circuit 15. The input terminal t1 of the lock detection circuit 14 is connected to the first output terminal b, and the output terminal t2 of the lock detection circuit 14 is connected to the input terminal h1 of the reset circuit 15.

[0095] The lock detection circuit 14 is used to send a reset signal to the reset circuit 15 when it detects that the signal at the first output terminal b has changed from a first-level lock signal to a second-level lock signal. In other words, when the source driver chip 1 malfunctions, the lock detection circuit 14 sends a reset signal to the reset circuit 15.

[0096] The reset circuit 15 is used to control the internal reset of the source driver chip 1 after receiving the reset signal.

[0097] In some embodiments, such as Figure 9 As shown, the output terminal h2 of the reset circuit 15 is connected to the anomaly detection module 12. In this scenario, the reset circuit 15 controls the internal reset of the source driver chip 1, which may include: controlling the configuration parameters of the source driver chip 1 and clearing and resetting the restored clock data, etc.

[0098] Assuming multiple source driver chips are all operating normally, if source driver chip 1 suddenly experiences an abnormality during normal operation, the other source driver chips cascaded before it will not experience any abnormalities. Therefore, the lock signals output by the abnormality detection modules in these source driver chips will not change to the second level. (Based on the above...) Figure 3 According to the corresponding description, when a source driver chip 1 malfunctions due to a closed switch, the lock signal at the first output terminal of each source driver chip cascaded before source driver chip 1 changes from a first level to a second level. At this time, the lock detection circuit 14 in the source driver chip cascaded before source driver chip 1 sends a reset signal to its own reset circuit 15. In this scenario, while performing an internal reset of these source driver chips cascaded before source driver chip 1, the reset circuit 15 also controls the lock signal output by the fault detection module of these source driver chips cascaded before source driver chip 1 to change from a first level to a second level.

[0099] When the source driver chip 1 suddenly malfunctions during normal operation, since the internal fault detection circuit of the source driver chip 1 has already output a second-level lock signal, the reset circuit 15 does not need to control the lock signal output by the fault detection module 12 of the source driver chip 1 to change from the first level to the second level when performing the internal reset of the source driver chip 1.

[0100] In summary, the source driver chip 1 provided in this application embodiment can be as follows: Figure 10As shown, the source driver chip 1 has a first input terminal a and a first output terminal b. Furthermore, the source driver chip 1 includes a lock signal control circuit 11 (not shown in the figure), an anomaly detection module 12, a lock signal drive circuit 13, a lock detection circuit 14, and a reset circuit 15. The lock signal control circuit 11 includes a switch 111 and a switch control circuit 112. The switch control circuit 112 includes a switch controller u1 and a first resistor r1. The power supply terminal g of the switch control circuit is connected to a second external power supply (not shown). The lock signal drive circuit 13 includes an inverter u2, a MOSFET Q1, and a second resistor r2.

[0101] Figure 10 The remaining connections of the internal circuitry of the source driver chip shown, as well as the connections of each terminal of the source driver chip, are described above and will not be repeated here. Figure 10 The source driver chip shown can implement all the functions described above.

[0102] In this embodiment, the switch design enables the signal at the first output terminal of the source driver chip cascaded before the source driver chip to change to the second level when one source driver chip malfunctions. This allows other source driver chips cascaded before the source driver chip to be reset, preventing the polarization of liquid crystal molecules from causing malfunctions.

[0103] The following is a detailed description of a display system provided in an embodiment of this application.

[0104] This application provides a display system, such as... Figure 11 As shown, the display system includes multiple source driver chips (three are shown as an example, but two or more are also possible) and a timing controller. Each source driver chip has a first input terminal a, a first output terminal b, and a second input terminal c. These multiple source driver chips are cascaded through the first input terminal a and the first output terminal b. The first input terminal a of the first cascaded source driver chip is used to connect to a first external power supply. The first output terminal b of the last cascaded source driver chip is connected to the timing controller. The second input terminal c of each source driver chip is also connected to the timing controller. Furthermore, the first output terminal b of the last cascaded source driver chip is connected to the lock signal detection terminal d of the timing controller, and the second input terminal c of each source driver chip is connected to the data output terminal e of the timing controller.

[0105] The first external power supply is typically 1.8V, which enables the signal at the first input terminal of the first source driver chip to be a first-level signal.

[0106] Specifically, the target source driver chip in the cascaded second to last source driver chips is the source driver chip provided in the above embodiment. This target source driver chip can be one chip in the cascaded second to last source driver chips, or it can be multiple chips in the cascaded second to last source driver chips.

[0107] In some embodiments, the internal structures of the multiple source driver chips in the display system are identical, all being the source driver chip structures provided in the above embodiments. This facilitates the fabrication of the display system.

[0108] In addition, such as Figure 11 As shown, the display system also includes a third resistor r3. One end of the third resistor r3 is connected to the first output terminal b of the last source driver chip, and the other end is connected to a third external power supply. The specific value of this third resistor r3 is not limited in this embodiment.

[0109] The following describes the workflow of this display system, using the internal structure of each source driver chip as an example. Figure 10 The internal structure of the source driver chip 1 shown is used as an example for explanation. The workflow of this display system can be referred to... Figure 12 .

[0110] First, it should be noted that in this display system, the timing controller and multiple source driver chips transmit data through a point-to-point communication protocol.

[0111] After the display system is powered on, the anomaly detection module outputs a low-level latch signal, causing the first output terminal b of all source driver chips to be a second-level latch signal (i.e., a low-level latch signal). Inverter u2 outputs a first-level signal, MOSFET Q1 is turned on, and the first output terminal b of each source driver chip is grounded through the turned-on MOSFET Q1, thus outputting a second-level latch signal. Since the first output terminal b of each source driver chip is connected to the first input terminal a of the next source driver chip, the latch signals of the first input terminals a of the second to last source driver chips are all at the second level. Additionally, since the first input terminal a of the first source driver chip is connected to a first external power supply, the latch signal of the first input terminal a of the first source driver chip is at the first level.

[0112] After power-on stabilization, as explained in the previous embodiment describing the working principle of the switch control circuit 112 and the switch controller u1, all the D flip-flops f1 of the switch control circuit 112 of the source driver chips are triggered. The output of the D flip-flop f1 of each source driver chip remains the same as the signal at the first input terminal a of that source driver chip. At the same time, the output of the data selector f6 remains the same as the output of the first inverter f3. For the first source driver chip, the D flip-flop f1 detects that the latch signal at the first input terminal a of the first source driver chip is at the first level. Therefore, the D flip-flop f1 in the first source driver chip also outputs the first level, and the first inverter f3 outputs the second level, causing the data selector f6 to output the second level. Since the data selector f6 cannot control the switch 111 to close, the switch 111 in the first source driver chip remains in the open state. For the second to the last source driver chips, the D flip-flop f1 detects that the latch signal at the first input terminal a of its corresponding source driver chip is at the second level. Therefore, the D flip-flop f1 also outputs the second level, the first inverter f3 outputs the first level, and the data selector f6 outputs the first level, thus closing its own switch 111. Therefore, switches 111 in the second to the last source driver chips are closed. This completes the initialization of the multiple source driver chips.

[0113] At this time, the timing controller's lock signal detection terminal d detects that the lock signal output by the first output terminal b of the last source driver chip is at the second level. The timing controller will send a training signal to each source driver chip through the data output terminal e. After receiving the training signal, each source driver chip will restore the clock data. When the anomaly detection module detects that the source driver chip has successfully restored the clock data, it will output a high-level lock signal. The inverter u2 inside each source driver chip will output a second-level signal to the gate of the MOS transistor Q1, and the MOS transistor will change from the on state to the off state.

[0114] As mentioned in the above embodiment of the source driver chip, in this case, for one of the source driver chips, its first output terminal b is in a high-impedance state. Due to the presence of the third resistor r3 and its connected third external power supply, current flows from the third external power supply through the third resistor r3 to the second resistor r2 in the last source driver chip. Correspondingly, the first output terminal b of the last source driver chip outputs a first-level latch signal (i.e., a high-level latch signal). Since the switch 111 in the last source driver chip is closed, the latch signal at the first input terminal a of the last source driver chip is also at the first level. Therefore, it can be determined that the latch signal at the first output terminal b of the penultimate source driver chip is also at the first level. By analogy, it can be seen that after all source driver chips have completed clock data recovery, the latch signal at the first output terminal b of each source driver chip is at the first level.

[0115] When the timing controller detects that the lock signal output from the first output terminal b of the last source driver chip changes from the second level to the first level through the lock signal detection terminal d, the timing controller considers that the multiple source driver chips have entered the normal working state. The timing controller will send a configuration signal to each source driver chip. After receiving the configuration signal, each source driver chip will configure its own configuration parameters.

[0116] After sending the configuration signal, the timing controller begins to send display data to multiple source driver chips. Each source driver chip drives the liquid crystal molecules in the LCD panel according to the received display data to achieve the purpose of displaying images.

[0117] Suppose that during the normal operation of multiple source driver chips, one of them suddenly malfunctions. At this time, the fault detection module 12 inside the malfunctioning source driver chip outputs a low-level latch signal. This causes the MOSFET Q1 inside the source driver chip to turn on again, and the latch signal output from the first output terminal b of the source driver chip becomes a second level. Therefore, the latch signals at the first input terminal a of all subsequent source driver chips connected to this source driver chip all become the second level. After this, the latch detection circuit 14 inside the source driver chip sends a reset signal to its own reset circuit 15. The reset circuit 15 then controls the internal reset of the source driver chip, clearing and resetting its configuration parameters and restored clock data.

[0118] For the source driver chips connected after the one experiencing the abnormal situation, since all internal switches 111 are closed, the latch signal output from its first output terminal b also changes to the second level. Similarly, the latch signal at the first output terminal b of each source driver chip cascaded after the one experiencing the abnormal situation is also at the second level.

[0119] Simultaneously, since the internal switch of the source driver chip experiencing the abnormal situation is in a closed state, when the latch signal output from the first output terminal b of the source driver chip is at the second level, the latch signal from the first input terminal a of the source driver chip is also at the second level. Therefore, for the source driver chips connected before this one, it can be determined that the latch signal at their first output terminal b is at the second level. By analogy, it can be determined that the latch signal at the first output terminal b of each source driver chip cascaded before the one experiencing the abnormal situation is also at the second level.

[0120] For source driver chips that do not exhibit any abnormalities (including other source driver chips cascaded before and after the source driver chip that exhibits an abnormality), the internal lock detection circuit 14 will detect that the lock signal at the first output terminal b changes from the first level to the second level. It will then send a reset signal to its own reset circuit 15. The reset circuit 15 will control the internal reset of the source driver chip it is in, control the lock signal output by the internal abnormality detection module 12 to change from the first level to the second level, and control the configuration parameters and restored clock data of the source driver chip it is in to clear and reset, etc.

[0121] As described above, when a source driver chip malfunctions, each source driver chip will undergo an internal reset. When the timing controller detects that the lock signal output from the first output terminal b of the last source driver chip changes from the first level to the second level, the timing controller will resend the training signal to each source driver chip through the data output terminal e, causing each source driver chip to re-recover its clock data. After the clock data is recovered, each source driver chip will reconfigure its parameters according to the configuration signal sent by the timing controller, and then drive the corresponding liquid crystal molecules according to the display data sent by the timing controller, thus returning to normal operation.

[0122] The workflow of the display system provided in this application embodiment has been described above. As can be seen from the above, in the display system provided in this application embodiment, when one source driver chip malfunctions, each source driver chip will be reset. Therefore, the problem of polarization caused by liquid crystal molecules receiving the same driving voltage for a long time will not occur. Furthermore, since each source driver chip resets when one source driver chip malfunctions, the problem of configuration failure or system crash caused by unnecessary decoding of configuration signals by the source driver chips will not occur.

[0123] Optionally, in this display system, the second to last cascaded source driver chips have the same structure, and all of them are the source driver chip structures provided in the above embodiments. The structure of the first cascaded source driver chip can be other structures, as long as the first input terminal and the first output terminal of the first cascaded source driver chip are not directly connected.

[0124] In this embodiment, when multiple source driver chips are cascaded, a switch inside each source driver chip enables the lock signal from the first output terminal of the second to the last source driver chip to be transmitted to the first input terminal. This ensures that when one source driver chip malfunctions, the lock detection circuit of each source driver chip can detect the change in the lock signal from the first level to the second level at the first output terminal, thereby resetting each source driver chip. This avoids the problem of polarization caused by liquid crystal molecules receiving the same driving voltage for an extended period, and also avoids configuration failures or system crashes caused by unnecessary decoding of configuration signals by the source driver chips. Furthermore, in the display system provided in this embodiment, the connections between the timing controller and multiple source driver chips, as well as between each source driver chip, are more convenient than... Figure 1 The "LOCK Cascade" mode shown remains unchanged. Therefore, when using the display system provided in this application embodiment, the original printed circuit board can be maintained, and only the source driver circuit chip needs to be replaced. It is evident that the display system provided in this application embodiment is suitable for widespread application.

[0125] It should be understood that "at least one" as mentioned herein refers to one or more, and "multiple" refers to two or more. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. In addition, in order to clearly describe the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and the terms "first," "second," etc., are not necessarily different.

[0126] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in the embodiments of this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0127] The above descriptions are embodiments provided in this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A source driver chip, characterized in that, The source driver chip has a first input terminal and a first output terminal. The source driver chip includes a lock signal control circuit, and the lock signal control circuit includes a switch and a switch control circuit. The switch is connected between the first input terminal and the first output terminal. The input terminal of the switch control circuit is connected to the first input terminal, and the output terminal of the switch control circuit is connected to the control terminal of the switch. The switch control circuit is used to detect the lock signal at the first input terminal after the source driver chip is powered on and stabilized. When the lock signal at the first input terminal is detected to be a first level lock signal, the switch is controlled to open. When the lock signal at the first input terminal is detected to be a second level lock signal, the switch is controlled to close. The switch control circuit is also used to control the lock signal at the first input terminal to switch from a first level to a second level based on the lock signal at the first output terminal when the source driver chip malfunctions, wherein the second level is lower than the first level.

2. The source driver chip as described in claim 1, characterized in that, The switch control circuit includes a switch controller and a first resistor; The power supply terminal of the switch controller is used to connect to a second external power source, the input terminal of the switch controller is used to connect to the first input terminal, the output terminal of the switch controller is connected to the control terminal of the switch, one end of the first resistor is connected to the input terminal of the switch controller, and the other end of the first resistor is grounded.

3. The source driver chip as described in claim 1, characterized in that, The source driver chip also includes an anomaly detection module and a lock signal driving circuit; The input terminal of the lock signal driving circuit is connected to the anomaly detection module, and the output terminal of the lock signal driving circuit is connected to the first output terminal. The anomaly detection module is used to output a first-level lock signal to the input terminal of the lock signal driving circuit when the source driver chip is detected to be working normally, and to output a second-level lock signal to the input terminal of the lock signal driving circuit when the source driver chip is detected to be malfunctioning. The lock signal driving circuit is used to control the lock signal at the first output terminal to be a first-level lock signal when a first-level lock signal is received, and to control the lock signal at the first output terminal to be a second-level lock signal when a second-level lock signal is received.

4. The source driver chip as described in claim 3, characterized in that, The lock signal driving circuit includes an inverter, a metal-oxide-semiconductor MOSFET, and a second resistor. The input terminal of the inverter is connected to the anomaly detection module, the output terminal of the inverter is connected to the gate of the MOS transistor, the source of the MOS transistor is grounded, the drain of the MOS transistor is connected to the first output terminal, one end of the second resistor is connected to the drain of the MOS transistor, and the other end of the second resistor is grounded.

5. A display system, characterized in that, The display system includes multiple source driver chips and a timing controller; The source driver chip has a first input terminal, a first output terminal, and a second input terminal. Multiple source driver chips are cascaded through the first input terminal and the first output terminal. The first input terminal of the first cascaded source driver chip is used to connect to a first external power supply. The first output terminal of the last cascaded source driver chip is connected to the timing controller. The second input terminal of the source driver chip is connected to the timing controller. Among them, for the target source driver chip in the cascaded second to last source driver chip, the target source driver chip includes a lock signal control circuit, the lock signal control circuit includes a switch and a switch control circuit, the switch is connected between the first input terminal and the first output terminal, the input terminal of the switch control circuit is connected to the first input terminal, and the output terminal of the switch control circuit is connected to the control terminal of the switch; The switch control circuit of the target source driver chip is used to detect the lock signal at the first input terminal of the target source driver chip after the target source driver chip is powered on and stabilized. When the lock signal at the first input terminal of the target source driver chip is detected to be a first level lock signal, the switch is controlled to open. When the lock signal at the first input terminal of the target source driver chip is detected to be a second level lock signal, the switch is controlled to close. The switching control circuit of the target source driver chip is further configured to control the lock signal of the first input terminal to switch from a first level to a second level based on the lock signal of the first output terminal when the target source driver chip malfunctions, wherein the second level is less than the first level.

6. The system as described in claim 5, characterized in that, The switch control circuit includes a switch controller and a first resistor; The power supply terminal of the switch controller is used to connect to a second external power source, the input terminal of the switch controller is used to connect to the first input terminal, the output terminal of the switch controller is connected to the control terminal of the switch, one end of the first resistor is connected to the input terminal of the switch controller, and the other end of the first resistor is grounded.

7. The system as described in claim 6, characterized in that, The target source driver chip also includes an anomaly detection module and a lock signal driver circuit; The input terminal of the lock signal driving circuit is connected to the anomaly detection module, and the output terminal of the lock signal driving circuit is connected to the first output terminal. The anomaly detection module is used to output a first-level lock signal to the input terminal of the lock signal driving circuit when the source driver chip is detected to be working normally, and to output a second-level lock signal to the input terminal of the lock signal driving circuit when the source driver chip is detected to be malfunctioning. The lock signal driving circuit is used to control the lock signal at the first output terminal to be a first-level lock signal when a first-level lock signal is received, and to control the lock signal at the first output terminal to be a second-level lock signal when a second-level lock signal is received.

8. The system as described in claim 7, characterized in that, The lock signal driving circuit includes an inverter, a metal-oxide-semiconductor MOSFET, and a second resistor. The input terminal of the inverter is connected to the anomaly detection module, the output terminal of the inverter is connected to the gate of the MOS transistor, the source of the MOS transistor is grounded, the drain of the MOS transistor is connected to the first output terminal, one end of the second resistor is connected to the drain of the MOS transistor, and the other end is grounded.

9. The system as described in claim 5, characterized in that, The display system also includes a third resistor, one end of which is connected to the first output terminal of the last cascaded source driver chip, and the other end is connected to a third external power supply.

Images