A sub-nanosecond high-voltage pulse generation circuit with low jitter and high reliability

Abstract

The application relates to an ultra-wideband system, in particular to a sub-nanosecond high-voltage pulse generation circuit with low jitter and high reliability. Compared with a conventional sub-nanosecond high-voltage pulse circuit based on a DSRD, the application adopts multi-stage LC coupling, so that the current drop rate and current on the DSRD device are higher, the current rise rate on the load resistor RL is higher, the voltage pulse front time generated is shorter, the pulse peak voltage is higher, the overshoot voltage on the switch tube is lower, the switch tube does not need to be used at a reduced capacity, the switch tube is not in the output loop, the overcurrent capacity and internal resistance of the switch tube do not need to be considered, the switch tube does not need to be controlled by the conduction time and the turn-off time, the control requirement of the semiconductor switch tube is reduced, and the number of voltage sources is reduced to one.

Description

Technical Field

[0001] This invention relates to ultra-wideband systems, and in particular to a sub-nanosecond high-voltage pulse generation circuit with low jitter and high reliability characteristics. Background Technology

[0002] Ultra-wideband (UWB) systems, such as UWB precision-guided radar systems, UWB wireless communications, and high-power electromagnetic pulse weapons, all require UWB pulse signal sources. UWB systems transmit information using very short pulses (typically in the nanosecond to sub-nanosecond range). Therefore, UWB systems require high-frequency, low-jitter, high-interference-resistance pulse power switches with switching times reaching nanosecond or even picosecond levels. Furthermore, the pulse switches must possess high peak power, high pulse repetition frequency, and high reliability. Currently, the drift step recovery diodes (DSRDs) proposed by the Ioffe Institute of Physics and Technology in Russia are among the most promising semiconductor pulse switches capable of generating high-voltage pulse signals due to their excellent ultrafast recovery characteristics. The design of the high-voltage pulse generation circuit that matches the DSRD device is an important factor affecting pulse performance. Currently reported high-voltage pulse generation circuits contain many passive components. The switching transistors in the high-voltage pulse generation circuits are usually directly connected to the inductors. During the operation of the DSRD device, due to the influence of the parameter matching of passive components, the source and drain voltages of the switching transistors will oscillate during the discharge process. This causes jitter in the output waveform under high-frequency output conditions. In severe cases, it may exceed the voltage withstand of the switching transistors themselves, causing damage to the switching transistors, affecting the reliability of the high-voltage pulse generation circuit, and thus causing high-frequency output failure. Summary of the Invention

[0003] The purpose of this invention is to address the problems of large high-frequency output waveform jitter and voltage overshoot of the switching transistor in conventional sub-nanosecond high-voltage pulse generation circuits based on DSRD devices, and to propose a low-jitter, high-reliability sub-nanosecond high-voltage pulse generation circuit based on DSRD devices.

[0004] The technical solution of the present invention:

[0005] A sub-nanosecond high-voltage pulse generation circuit with low jitter and high reliability includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first semiconductor switch Q1, a second semiconductor switch Q2, a Zener diode D1, a transformer T1, a first inductor L1, a second inductor L2, a DSRD device, and a load resistor RL; wherein,

[0006] One end of the first capacitor C1 is connected to the input pulse signal, and the other end is connected to the gate of the first semiconductor switch Q1 and one end of the first resistor R1;

[0007] The other end of the first resistor R1 is connected to the source of the first semiconductor switch Q1, one end of the second resistor R2, and ground;

[0008] The other end of the second resistor R2 is connected to the cathode of the Zener diode D1 and the gate of the second semiconductor switch Q2.

[0009] The anode of the Zener diode D1 is connected to one end of the secondary side of transformer T1, and the other end of the secondary side of transformer T1 is connected to the source of the second semiconductor switch Q2, one end of the second capacitor C2, and ground.

[0010] The other end of the second capacitor C2 is connected to the drain of the second semiconductor switch Q2, one end of the fourth capacitor C4, one end of the third resistor R3 and one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the power supply.

[0011] The other end of the third resistor R3 is connected to one end of the third capacitor C3 and the drain of the first semiconductor switch Q1. The other end of the third capacitor C3 is connected to one end of the primary side of the transformer T1. The other end of the primary side of the transformer T1 is grounded.

[0012] The other end of the fourth capacitor C4 is connected to one end of the fifth capacitor C5 and one end of the first inductor L1, and the other end of the first inductor L1 is grounded.

[0013] The other end of the fifth capacitor C5 is connected to one end of the second inductor L2, and the other end of the second inductor L2 is connected to one end of the sixth capacitor C6 and the cathode of the DSRD device. The anode of the DSRD device is grounded.

[0014] The other end of the sixth capacitor C6 is connected to one end of the load resistor RL as the output terminal, and the other end of the load resistor RL is grounded.

[0015] Furthermore, the first semiconductor switch Q1 and the second semiconductor switch Q2 are any one of MOSFET, IGBT, GTO, and transistor.

[0016] Furthermore, the first semiconductor switch Q1 includes a driving circuit for the semiconductor switching device.

[0017] In the circuit of this invention, diode D1 can be omitted.

[0018] The beneficial effects of this invention are as follows: Compared with conventional sub-nanosecond high-voltage pulse circuits based on DSRD, this invention uses multi-stage LC coupling, which results in a higher current drop rate and current on the DSRD device, thus a higher current rise rate on the load resistor RL, a shorter voltage pulse leading-out time and a higher pulse peak voltage, and a lower overshoot voltage on the switching transistor. It eliminates the need to derating the switching transistor, and since the switching transistor is not in the output circuit, there is no need to consider its overcurrent capability and internal resistance. Furthermore, it eliminates the need to control the switching transistor's on-time and off-time, reducing the control requirements on the semiconductor switching transistor, and the number of voltage sources is reduced to one. Attached Figure Description

[0019] Figure 1 This is a circuit diagram of a conventional sub-nanosecond high-voltage pulse generation circuit.

[0020] Figure 2 This is a circuit diagram of the sub-nanosecond high-voltage pulse generation circuit of the present invention;

[0021] Figure 3 This is a schematic diagram of the working state of the sub-nanosecond high-voltage pulse generation circuit of the present invention during the forward pumping stage.

[0022] Figure 4 This is a schematic diagram of the working state of the reverse pumping stage of the sub-nanosecond high-voltage pulse generation circuit of the present invention.

[0023] Figure 5 This is a comparison diagram of the voltage simulation waveforms of the conventional and the sub-nanosecond high-voltage pulse generation circuits of this invention.

[0024] Figure 6 This is a schematic diagram of the pressure conditions of a semiconductor switching transistor. Detailed Implementation

[0025] The present invention will now be described in detail with reference to the accompanying drawings.

[0026] like Figure 1 The diagram shows a conventional sub-nanosecond high-voltage pulse generation circuit based on DSRD. (Example:) Figure 2The circuit diagram shown illustrates the sub-nanosecond high-voltage pulse generation circuit of this invention. The circuit connections are as follows: the gate of switch Q1 is connected in series with isolation capacitor C1 via node 2; C1 is connected to an input pulse signal via node 1; voltage divider resistor R1 is connected to the source and gate of switch Q1 via nodes 3 and 2, and the source of switch Q1 is grounded to GND; voltage divider resistor R2 is connected in series with voltage divider resistor R1 via nodes 3 and 5; the cathode of diode D1 is connected in series with R2 via node 5; the anode of diode D1 is connected in series with the secondary side of transformer T1 via node 6; the other end of the secondary side of transformer T1 is connected to the source of switch Q2 via node 7 and grounded to GND; simultaneously, capacitor C2 is connected in parallel with the source and drain of switch Q2 via nodes 7 and 8; the drain of switch Q2 is connected in series with resistor R4 via node 8; the other end of R4 is connected to power supply VDRAIN via node 14; R4 is connected in series with resistor R3 and capacitor C4 via node 8; R3 is connected to... The drain of the switching transistor Q1 and capacitor C3 are connected in series through node 4. The other side of capacitor C3 is connected to the primary side of transformer T1 through node 9. The other side of the primary side of transformer T1 is grounded to GND. Capacitor C4 is connected in series with energy storage inductor L1 and energy storage capacitor C5 through node 10. The other side of L1 is grounded to GND through node 11. The other end of capacitor C5 is connected to energy storage inductor L2 through node 12. The other side of L2 is connected in series with the cathode of DSRD device DUT and isolation capacitor C6 through node 15. The anode of DSRD device DUT is grounded to GND through node 13. The other side of C6 is connected in series with load resistor RL and output voltage detection through node 17. The other side of load resistor RL is grounded to GND through node 16. Semiconductor switches Q1 and Q2 can be semiconductor switching devices such as MOSFET, IGBT, GTO, and transistor. Semiconductor switches Q1 and Q2 can include the driving circuit of semiconductor switching devices. Diode D1 can be omitted.

[0027] The sub-nanosecond high-voltage pulse generation circuit provided by this invention operates on the following principle:

[0028] exist Figure 2 In the circuit structure shown, the circuit operation is divided into two stages: the first stage is the forward pumping stage, and the second stage is the reverse pumping stage. The schematic diagram of the circuit operation during the forward pumping stage is shown below. Figure 3As shown, initially, semiconductor switch Q1 is off, and power supply VDRAIN charges C4 and C3. When the input signal charges C1 to the turn-on voltage of semiconductor switch Q1, Q1 turns on, and C3 begins to discharge. The first path, consisting of capacitor C3, semiconductor switch Q1, and the primary side of transformer T1, is connected. Due to the induction effect of the transformer, current appears on the secondary side of transformer T1. At the same time, due to the voltage division effect of R1 and R2, semiconductor switch Q2 reaches the turn-on voltage, and the second path, consisting of the secondary side of transformer T1, Zener diode D1, and semiconductor switch Q2, is connected. Due to the conduction of the second path, capacitor C4 begins to discharge, and the third path, consisting of capacitor C4, semiconductor switch Q2, and inductor L1, begins to conduct. Due to the potential change, the fourth path, consisting of inductor L2, DSRD device DUT, and capacitor C5, is connected, discharging into capacitor C4. At this time, DSRD device D1 is forward-biased, and charge carriers are injected into the drift region.

[0029] The circuit operation diagram during the reverse pumping phase is shown below. Figure 4 As shown, due to the negative half-cycle of the LC resonance, the currents of capacitors C4 and C5 begin to reverse. At the same time, due to the freewheeling function of inductor L1, the stored energy is discharged through channels five, six, and seven. In the early stage of the reverse pumping phase, since the drift region of the DSRD device DUT still stores the carriers injected in the previous stage, the resistance is relatively small. Therefore, the current in the LC circuit first flows into channel seven, and the DSRD device DUT conducts in reverse. During the process of extracting carriers in the drift region of the DUT, the resistance of the DUT increases, and the current in channel six gradually increases, thereby generating a high-voltage pulse on the load resistor RL. The pulse leading edge time can reach the nanosecond level or even the sub-nanosecond level.

[0030] A simulation comparison was performed between a conventional sub-nanosecond high-voltage pulse generation circuit based on DSRD and the circuit of this invention. Both circuits use the same DSRD device and the same type of switching transistor, and the output waveforms are as follows: Figure 5 As shown, the sub-nanosecond high-voltage pulse generation circuit of this invention outputs a voltage pulse leading-edge time of less than 500 ps, ​​and both the leading-edge time and period of the output voltage pulse are small, significantly better than conventional circuits. Meanwhile, from... Figure 6 As demonstrated in the voltage testing of the semiconductor switching transistors, the voltage across the switching transistors in the pulse generation circuit of this invention is significantly reduced during circuit operation. Therefore, the sub-nanosecond high-voltage pulse generation circuit of this invention is suitable for ultra-wideband systems.

Claims

1. A sub-nanosecond high-voltage pulse generation circuit with low jitter and high reliability characteristics, characterized in that, This includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first semiconductor switch Q1, a second semiconductor switch Q2, a Zener diode D1, a transformer T1, a first inductor L1, a second inductor L2, a DSRD device, and a load resistor RL; wherein, One end of the first capacitor C1 is connected to the input pulse signal, and the other end is connected to the gate of the first semiconductor switch Q1 and one end of the first resistor R1; The other end of the first resistor R1 is connected to the source of the first semiconductor switch Q1, one end of the second resistor R2, and ground; The other end of the second resistor R2 is connected to the cathode of the Zener diode D1 and the gate of the second semiconductor switch Q2. The anode of the Zener diode D1 is connected to one end of the secondary side of transformer T1, and the other end of the secondary side of transformer T1 is connected to the source of the second semiconductor switch Q2, one end of the second capacitor C2, and ground. The other end of the second capacitor C2 is connected to the drain of the second semiconductor switch Q2, one end of the fourth capacitor C4, one end of the third resistor R3 and one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the power supply. The other end of the third resistor R3 is connected to one end of the third capacitor C3 and the drain of the first semiconductor switch Q1. The other end of the third capacitor C3 is connected to one end of the primary side of the transformer T1. The other end of the primary side of the transformer T1 is grounded. The other end of the fourth capacitor C4 is connected to one end of the fifth capacitor C5 and one end of the first inductor L1, and the other end of the first inductor L1 is grounded. The other end of the fifth capacitor C5 is connected to one end of the second inductor L2, and the other end of the second inductor L2 is connected to one end of the sixth capacitor C6 and the cathode of the DSRD device. The anode of the DSRD device is grounded. The other end of the sixth capacitor C6 is connected to one end of the load resistor RL as the output terminal, and the other end of the load resistor RL is grounded.

2. The sub-nanosecond high-voltage pulse generation circuit with low jitter and high reliability as described in claim 1, characterized in that, The first semiconductor switch Q1 and the second semiconductor switch Q2 are any one of MOSFET, IGBT, GTO, and transistor.

3. The sub-nanosecond high-voltage pulse generation circuit with low jitter and high reliability as described in claim 2, characterized in that, The first semiconductor switch Q1 includes a driving circuit for the semiconductor switching device.

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