Time-to-digital converter circuit with narrow pulse measurement capability

Abstract

The present disclosure provides a time-to-digital converter circuit with narrow pulse measurement capability, which can be applied to the fields of laser radar ranging, nuclear medicine, nuclear physics experiments and the like which need to measure the pulse width of a signal. The time-to-digital converter circuit with narrow pulse measurement capability comprises: an inverter configured to perform inversion processing on a to-be-measured pulse signal to obtain an inverted signal; a reset circuit configured to provide a first reset signal and a second reset signal; a first flip-flop configured to receive the inverted signal and the first reset signal, and output a first adjustment signal based on the inverted signal and the first reset signal; a second flip-flop configured to receive the to-be-measured pulse signal and the second reset signal, and output a second adjustment signal based on the to-be-measured pulse signal and the second reset signal; and a pulse width measurement circuit configured to determine a first time of the first adjustment signal and a second time of the second adjustment signal, and obtain the pulse width of the to-be-measured pulse signal based on the first time and the second time.

Description

Technical Field

[0001] This disclosure relates to fields such as lidar ranging, nuclear medicine, and nuclear physics experiments that require the measurement of signal pulse width, and specifically to a time-to-digital converter circuit with narrow pulse measurement capability. Background Technology

[0002] In many fields such as nuclear medicine and nuclear physics experiments, it is often necessary to measure the pulse width of signals. For example, knowing the accurate pulse width helps to obtain information about the energy deposition of particles during detection, thereby enabling particle energy spectrum measurement or particle species identification. Related technologies often employ waveform digitization methods and time-to-digital converters to measure the pulse width of signals.

[0003] Waveform digitization requires an ultra-high sampling rate analog-to-digital converter (ADC) to sample the waveform under test. Then, an electronics module uses an interpolation algorithm to interpolate the sampled discrete waveform to obtain the time information of the threshold points. However, the ultra-high sampling rate ADC used in this method is very expensive, and the amount of data it generates is enormous. This places high demands on the data throughput of subsequent electronics modules, such as digital processing modules. Especially in multi-channel applications, multiple ultra-high sampling rate ADCs need to work simultaneously, generating large amounts of data for the backend digital processing module. This places immense pressure on the backend digital processing module, placing high demands on hardware and software performance and resulting in huge equipment costs.

[0004] The time-to-digital converters (TD-SCDMA) in related technologies, including the tapped delay line (TDL) circuit, can only capture the rising edge of the signal under test. To enable pulse width measurement, three methods are typically employed: First, the signal under test is directly fed into the TDL. The rising and falling edges are then measured independently using two separate encoding circuits. However, this method is resource-intensive and lacks the flexibility to employ multiple measurements to improve time accuracy. Second, a NOT gate is used to convert the falling edge to a rising edge, followed by separate measurements in two different TD-SCDMA converters. This method also incurs significant resource overhead. Third, a single TD-SCDMA converter is used to capture both the rising and falling edges of the signal and measures them in different clock cycles. However, this method may increase dead time and reduce the measurement throughput and accuracy of the TD-SCDMA.

[0005] Furthermore, the aforementioned three time-to-digital converters have strict limitations on the pulse width of the signal under test, making them unsuitable for nanosecond-level narrow pulse measurements. They also require extensive preliminary testing and are not compatible with the wide variety of FPGA (Field-Programmable Gate Array) devices. Additionally, their complex logic consumes significant logic resources, reducing system integration and increasing power consumption and cost. Summary of the Invention

[0006] In view of the above problems, this disclosure provides a time-to-digital converter circuit with narrow pulse measurement capability.

[0007] One aspect of this disclosure provides a time-to-digital converter circuit with narrow pulse measurement capability, comprising:

[0008] An inverter is used to invert the pulse signal under test to obtain an inverted signal;

[0009] A reset circuit is used to provide a first reset signal and a second reset signal;

[0010] A first flip-flop is configured to receive an inverted signal and a first reset signal, and output a first adjustment signal based on the inverted signal and the first reset signal. The first flip-flop is configured to output a first adjustment signal with a level of the first level when the inverted signal changes from a second level to a first level and no first reset signal is received.

[0011] The second trigger is used to receive the pulse signal to be measured and the second reset signal, and to output the second adjustment signal based on the pulse signal to be measured and the second reset signal. The second trigger is used to output the second adjustment signal with the level state of the first level when the pulse signal to be measured changes from the second level to the first level and no second reset signal is received.

[0012] The pulse width measurement circuit is used to determine the first moment when the first adjustment signal jumps to the first level and the second moment when the second adjustment signal jumps to the first level, and to obtain the pulse width data of the pulse signal to be measured based on the first moment and the second moment.

[0013] According to the time-to-digital converter circuit with narrow pulse measurement capability disclosed herein, since an inverter is used to invert the pulse signal to be measured to obtain an inverted signal, and a first flip-flop is used to adjust the inverted signal, when the inverted signal jumps from the second level to the first level and no first reset signal is received, a first adjustment signal with the first level is output. This allows the falling edge of the pulse signal to be identified, and the duration of the first adjustment signal at the first level, even with the pulse width of the first adjustment signal, meets the identification requirements of subsequent circuits. Similarly, a second flip-flop is used to adjust the pulse signal to be measured, so that the adjusted second adjustment signal has the first level for a duration... Even if the pulse width of the second adjustment signal is sufficient to meet the recognition requirements of subsequent circuits, the pulse width of the pulse signal under test can be measured by using devices such as inverters, reset circuits, first and second flip-flops, and pulse width measurement circuits. This at least partially solves the problems of high cost or high resource consumption, low accuracy, poor flexibility, strict requirements on signal pulse width, and high power consumption in related technologies, which are caused by only being able to capture the rising edge of the signal under test. It achieves the beneficial effects of measuring pulse width data with fewer and lower cost devices, resulting in lower resource consumption, lower system power consumption and cost, and less stringent requirements on the pulse width of the signal under test, thus making it widely applicable. Attached Figure Description

[0014] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0015] Figure 1 A schematic diagram of a time-to-digital converter circuit with narrow pulse measurement capability according to a first embodiment of the present disclosure is shown.

[0016] Figure 2 A schematic diagram of a time-to-digital converter circuit with narrow pulse measurement capability according to a second embodiment of the present disclosure is shown.

[0017] Figure 3 A schematic diagram illustrating the output signal of a time-to-digital converter circuit with narrow pulse measurement capability according to a second embodiment of the present disclosure is shown.

[0018] Figure 4 A schematic diagram illustrating the connection relationship between the delay chain circuit and the encoding circuit according to a second embodiment of the present disclosure is shown.

[0019] Figure 5 A schematic diagram illustrating an output sequence according to a second embodiment of the present disclosure is shown.

[0020] Figure 6 A first timing diagram according to a second embodiment of the present disclosure is schematically shown;

[0021] Figure 7 A second timing diagram according to a second embodiment of the present disclosure is schematically shown;

[0022] Figure 8 A third timing diagram according to a second embodiment of the present disclosure is schematically shown;

[0023] Figure 9A This schematically illustrates a first correspondence between the different number of edge variations included in the first and second signals according to a second embodiment of the present disclosure and the pulse width measurement error;

[0024] Figure 9B The diagram schematically illustrates a second correspondence between the different number of edge variations included in the first and second signals according to a second embodiment of the present disclosure and the pulse width measurement error. Detailed Implementation

[0025] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of an action, step, operation, and / or component, but do not exclude the presence or addition of one or more other actions, steps, operations, or components.

[0027] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0028] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0029] Time-to-Digital Converters (TDCs) can convert time interval information into high-resolution digital signals. They are widely used in positron emission tomography (PET), light detection and ranging (LiDAR), autonomous vehicles, time-of-flight (ToF) imaging, cutting-edge particle physics experiments, and space experiments. They also have broad application prospects in aerospace, deep space exploration, geological mapping, medical imaging, and radar scanning.

[0030] Especially in modern nuclear physics experiments, the time-over-threshold (TOT) method is used to measure the time of particle event signals, that is, to measure the pulse width of the particle event signals, which helps to improve the accuracy and reliability of particle identification. The pulse width of these particle event signals to be measured is on the order of nanoseconds (ns), requiring the time-to-digital converter to have high precision and narrow pulse measurement capabilities.

[0031] Currently, the widely adopted techniques for achieving high-precision narrow pulse time over-threshold measurement are waveform digitization and time-to-digital converter methods.

[0032] In view of the above, embodiments of this disclosure provide a time-to-digital converter circuit with narrow pulse measurement capability, which is effective in that it includes: an inverter for inverting the pulse signal to be measured to obtain an inverted signal; a reset circuit for providing a first reset signal and a second reset signal; a first flip-flop for receiving the inverted signal and the first reset signal, and outputting a first adjustment signal based on the inverted signal and the first reset signal, wherein the first flip-flop is used to output a first adjustment signal with a level state of the first level when the inverted signal changes from a second level to a first level and no first reset signal is received; a second flip-flop for receiving the pulse signal to be measured and the second reset signal, and outputting a second adjustment signal based on the pulse signal to be measured and the second reset signal, wherein the second flip-flop is used to output a second adjustment signal with a level state of the first level when the pulse signal to be measured changes from a second level to a first level and no second reset signal is received; and a pulse width measurement circuit for determining a first moment when the first adjustment signal changes to the first level and a second moment when the second adjustment signal changes to the first level, and obtaining pulse width data of the pulse signal to be measured based on the first moment and the second moment.

[0033] The following will be through Figures 1-9B A time-to-digital converter circuit with narrow pulse measurement capability according to a disclosed embodiment is described in detail.

[0034] Figure 1 A schematic diagram of a time-to-digital converter circuit with narrow pulse measurement capability according to a first embodiment of the present disclosure is shown.

[0035] like Figure 1 As shown, the time-to-digital converter circuit 100 with narrow pulse measurement capability includes: an inverter 110, a reset circuit 120, a first flip-flop 130, a second flip-flop 140, and a pulse width measurement circuit 150.

[0036] Inverter 110 is used to invert the pulse signal to be measured to obtain an inverted signal.

[0037] The reset circuit 120 is used to provide a first reset signal and a second reset signal.

[0038] The first flip-flop 130 is used to receive an inverted signal and a first reset signal, and output a first adjustment signal based on the inverted signal and the first reset signal. The first flip-flop is used to output a first adjustment signal with a level of the first level when the inverted signal changes from a second level to a first level and no first reset signal is received.

[0039] The second flip-flop 140 is used to receive the pulse signal to be measured and the second reset signal, and to output a second adjustment signal based on the pulse signal to be measured and the second reset signal. The second flip-flop is used to output a second adjustment signal with the level state of the first level when the pulse signal to be measured changes from the second level to the first level and no second reset signal is received.

[0040] The pulse width measurement circuit 150 is used to determine the first moment when the first adjustment signal jumps to the first level and the second moment when the second adjustment signal jumps to the first level, and to obtain the pulse width data of the pulse signal to be measured based on the first moment and the second moment.

[0041] According to embodiments of this disclosure, the first level is a high level and the second level is a low level. Specifically, the first level can be represented by 1 and the second level can be represented by 0.

[0042] According to embodiments of this disclosure, the moment when the level state transitions from the second level to the first level, or the moment when the signal transitions to the first level, can be the arrival time of the rising edge of the signal. The moment when the level state transitions from the first level to the second level, or the moment when the signal transitions to the second level, can be the arrival time of the falling edge of the signal.

[0043] According to embodiments of this disclosure, the rising edge represents a transition from a second level to a first level, and the falling edge represents a transition from a first level to a second level. The rising and falling edges of any signal can be defined in the manner described above.

[0044] According to embodiments of this disclosure, the first moment represents the arrival time of the rising edge of the first adjustment signal, and the second moment represents the arrival time of the rising edge of the second adjustment signal.

[0045] According to embodiments of this disclosure, both the first reset signal and the second reset signal can be asynchronous reset signals.

[0046] According to embodiments of this disclosure, the pulse width data of the pulse signal under test can be the time difference between the arrival time of the rising edge and the arrival time of the falling edge of the pulse signal under test. For example, if the arrival time of the rising edge is 7.542ns and the arrival time of the falling edge is 11.644ns, then the pulse width data is 11.644-7.542=4.102ns.

[0047] According to an embodiment of the present disclosure, the input terminal of the inverter 110 is used to receive the pulse signal to be measured, and the inverter 110 is used to invert the pulse signal to be measured so that the falling edge of the pulse signal to be measured is converted into the rising edge of the inverted signal.

[0048] According to embodiments of this disclosure, the pulse signal to be measured can be a positive pulse. After inversion processing, the pulse signal to be measured becomes a negative pulse, and the inverted signal is a negative pulse.

[0049] According to an embodiment of this disclosure, the first input terminal of the first flip-flop 130 is connected to the output terminal of the inverter 110 to receive an inverted signal. The second input terminal of the first flip-flop 130 is connected to the reset circuit 120 to receive a first reset signal. The first flip-flop 130 is not limited; it can be a D flip-flop (DFF), and its first input terminal can be the clk port and its second input terminal can be the clk port.

[0050] According to an embodiment of this disclosure, after the inverted signal enters the first flip-flop 130 through the first input terminal, the first flip-flop 130 is used to continuously output a first adjustment signal with a level of the first level when the inverted signal transitions from a second level to a first level and no first reset signal is received. Until the first flip-flop 130 receives the first reset signal, the first flip-flop 130 switches from continuously outputting the first adjustment signal with a level of the first level to continuously outputting the first adjustment signal with a level of the second level, until the moment when the inverted signal transitions from the second level to the first level again is reached.

[0051] According to an embodiment of this disclosure, the reset circuit 120 is used to generate a first reset signal when it is detected that the duration of the first level of the first adjustment signal meets the conditions for subsequent identification, thereby solving the problem that the pulse width of the inverted signal is too narrow to meet the requirements of subsequent processing.

[0052] According to an embodiment of this disclosure, the first input terminal of the second flip-flop 140 is used to receive the pulse signal to be measured. The second input terminal of the second flip-flop 140 is connected to the reset circuit 120 and is used to receive the second reset signal. The second flip-flop 140 is not limited; it can be a D flip-flop, with its first input terminal being the clk port and its second input terminal being the clk port.

[0053] According to an embodiment of this disclosure, after the pulse signal under test enters the second flip-flop 140 through the first input terminal, the second flip-flop 140 is used to continuously output a first adjustment signal with a level of the first level when the pulse signal under test changes from a second level to a first level and no first reset signal is received. Until the second flip-flop 140 receives a second reset signal, the second flip-flop 140 switches to continuously outputting a second adjustment signal with a level of the second level.

[0054] According to an embodiment of this disclosure, the reset circuit 120 is used to generate a second reset signal when the duration of the first level of the second adjustment signal is found to meet the conditions for subsequent identification, thereby solving the problem that the pulse width of the pulse signal under test is too narrow to meet the requirements for subsequent processing.

[0055] According to embodiments of this disclosure, the pulse width can also be referred to as the overthreshold time.

[0056] According to embodiments of this disclosure, the pulse width measurement circuit 150 can be a device, circuit, or the like capable of handling computational tasks.

[0057] According to the embodiments of this disclosure, the time-to-digital converter circuit with narrow pulse measurement capability obtained by the above-described device has a circuit structure that is easier to implement, consumes fewer resources, and uses a wide variety of resources. It can be well applied in various FPGA and application-specific integrated circuit (ASIC) products. It is easy to implement and has excellent performance, which can effectively solve the low-cost, high-precision, and multi-channel requirements for measuring the pulse width of analog signals under test in fields such as high-energy nuclear physics and lidar.

[0058] According to the embodiments of this disclosure, it can be seen from the above effects that the time-to-digital converter circuit with narrow pulse measurement capability in this disclosure can also be called a resource-saving time-to-digital converter circuit structure with narrow pulse width measurement capability.

[0059] According to the time-to-digital converter circuit with narrow pulse measurement capability disclosed herein, an inverter is used to invert the pulse signal to be measured to obtain an inverted signal, and a first flip-flop is used to adjust the inverted signal. When the inverted signal transitions from a second level to a first level and no first reset signal is received, a first adjustment signal with a level of the first level is output. This allows the falling edge of the pulse signal to be identified, and the duration of the first adjustment signal at the first level, even with the pulse width of the first adjustment signal, meets the identification requirements of subsequent circuits. Similarly, a second flip-flop is used to adjust the pulse signal to be measured, so that the adjusted second adjustment signal has a level of the first level. The duration of the pulse width of the second adjustment signal is sufficient to meet the recognition requirements of subsequent circuits. Therefore, the pulse width of the pulse signal under test can be measured using devices such as inverters, reset circuits, first and second flip-flops, and pulse width measurement circuits. This at least partially solves the problems of high cost or high resource consumption, low accuracy, poor flexibility, strict pulse width requirements, and high power consumption in related pulse width measurement methods that can only capture the rising edge of the signal under test. It achieves the beneficial effects of measuring pulse width using fewer and lower-cost devices, resulting in lower resource consumption, lower system power consumption and cost, and less stringent requirements on the pulse width of the signal under test, thus broadening its applicability.

[0060] Figure 2 A schematic diagram of a time-to-digital converter circuit with narrow pulse measurement capability according to a second embodiment of the present disclosure is shown.

[0061] like Figure 2 As shown, the pulse width measurement circuit 150 includes: a first delay chain circuit 210, a second delay chain circuit 220, a sorting circuit 230, an encoding circuit 240, a pulse width calculation circuit 250, and a counter 260. That is, the time-to-digital converter circuit with narrow pulse measurement capability includes an inverter 110, a reset circuit 120, a first flip-flop 130, a second flip-flop 140, a first delay chain circuit 210, a second delay chain circuit 220, a sorting circuit 230, an encoding circuit 240, a pulse width calculation circuit 250, and a counter 260.

[0062] According to embodiments of this disclosure, the devices and circuits included in the aforementioned time-to-digital converter circuit with narrow pulse measurement capability can all be implemented using an FPGA.

[0063] According to embodiments of this disclosure, a time-to-digital converter circuit with narrow pulse measurement capability may further include a comparator. The input of the comparator is used to receive the analog signal to be measured. The comparator is used to compare the voltage amplitude of the analog signal to be measured at multiple times with a preset amplitude to obtain a comparison result. The comparator is also used to output the pulse signal to be measured based on the comparison result.

[0064] According to embodiments of this disclosure, the output of the comparator can be connected to the input of the inverter and the second flip-flop respectively, for inputting the pulse signal to be measured into the inverter and the second flip-flop. The output of the comparator can also be connected to the input interface of the FPGA, for inputting the pulse signal to be measured into the inverter and the second flip-flop through the input interface. The input interface 410 can be the input / output interface (I / O Pin) of the FPGA.

[0065] According to embodiments of this disclosure, the simulated signal to be tested includes a hit signal generated by the detector.

[0066] According to embodiments of this disclosure, a comparator is used to compare the level of the analog signal under test with a preset threshold. If the level of the analog signal under test is higher than the preset threshold, the comparator outputs a pulse signal under test with a high level. If the level of the analog signal under test is lower than the preset threshold, the comparator outputs a pulse signal under test with a low level.

[0067] According to embodiments of this disclosure, the preset threshold is not limited and can be set differently according to actual conditions. By adjusting the preset threshold, different detectors can be adapted, making the time-to-digital converter circuit with narrow pulse measurement capability of the system more versatile. Simultaneously, the preset threshold can be adjusted according to different physical requirements to measure the pulse width of the same analog signal under test at different preset thresholds.

[0068] According to embodiments of this disclosure, the comparator compares the level of the analog signal under test at each time with a preset threshold, thereby outputting the pulse signal under test at each time.

[0069] According to embodiments of this disclosure, a comparator can convert an analog signal into a digital signal, and the pulse width of the digital signal contains the pulse width information of the analog signal.

[0070] According to embodiments of this disclosure, the pulse signal to be measured can also be obtained by any means other than a comparator.

[0071] According to embodiments of this disclosure, the output terminals of the first delay chain circuit 210 and the second delay chain circuit 220 are respectively connected to the input terminal of the reset circuit 120 and the input terminal of the sorting circuit 230.

[0072] Figure 3 The schematic diagram illustrates the output signal of a time-to-digital converter circuit with narrow pulse measurement capability according to a second embodiment of the present disclosure.

[0073] like Figure 3 As shown, since two identical pulse signals to be tested are transmitted to the inverter 110 and the second flip-flop 140, the two signal processing processes can be performed in parallel, resulting in a simple structure and a short dead time.

[0074] According to the embodiments of this disclosure, the cooperation of the first flip-flop 130, the second flip-flop 140 and the reset circuit 120 at least partially solves the shortcomings of the time-to-digital converter circuit with narrow pulse measurement capability in the related art, which cannot detect the pulse width and cannot measure the time interval between the rising and falling edges of narrow pulses (on the order of 100ps-1ns). This makes the pulse width of the pulse signal under test not limited by the pulse width limit allowed by the access interface and the identification requirements of the delay chain circuit, effectively widening the pulse width range for measuring the pulse signal under test.

[0075] According to embodiments of this disclosure, the measurement range of the pulse width of the pulse signal under test depends on the stability of the clock source.

[0076] According to embodiments of this disclosure, the signal waveforms output by devices such as inverter 110, first flip-flop 130, and second flip-flop 140 are as follows: Figure 3 As shown, through Figure 3 The function of each component can be clearly seen, as shown below.

[0077] According to embodiments of this disclosure, since the pulse width of the pulse signal under test is narrow, and the pulse width is the time difference between the arrival time of the rising edge and the arrival time of the falling edge of the pulse signal under test, and the delay chain circuit can usually only measure the arrival time of the rising edge of the pulse signal under test, and the pulse width of the pulse signal under test is required to meet the target range, that is, greater than one system clock cycle and less than two system clock cycles, the pulse signal under test is transmitted to the inverter 110 and the second flip-flop 140 respectively. The inverter 110 is used to invert the pulse signal under test so that the rising edge of the inverted signal is the falling edge of the pulse signal under test, which at least partially solves the problem that the delay chain cannot measure the falling edge.

[0078] According to embodiments of this disclosure, for a signal input to the first delay chain circuit 210 or the second delay chain circuit 220, the pulse width of the signal is typically greater than one system clock cycle and less than two system clock cycles before it can be recognized by the first delay chain circuit 210 or the second delay chain circuit 220.

[0079] According to an embodiment of this disclosure, the first flip-flop 130 can be a flip-flop that sets the D port high, used to set the Q port output level to a high level as a first adjustment signal when the rising edge of the inverted signal arrives. The reset circuit 120 is used to generate a second reset signal after determining that the Q port output high level time of the first flip-flop 130 meets the recognition requirements of the pulse width of the first adjustment signal by the first delay chain circuit 210. Thus, the second flip-flop 140 is used to set the Q port output level to a low level as a first adjustment signal based on the first reset signal, thereby enabling the first delay chain circuit 210 to recognize the first adjustment signal and solving the problem that the pulse width of the pulse signal to be measured is too narrow to be recognized by the first delay chain in the first delay chain circuit 210.

[0080] According to an embodiment of this disclosure, the second flip-flop 140 can be a flip-flop that sets the D port high, used to set the Q port output level to a high level as a second adjustment signal when the rising edge of the pulse signal to be measured arrives. The reset circuit 120 generates a second reset signal after determining that the time when the Q port outputs a high level of the second flip-flop 140 meets the pulse width requirement of the second delay chain circuit 220 for the second adjustment signal. Thus, the second flip-flop 140 sets the Q port output level to a low level as a second adjustment signal based on the second reset signal, so that the delay chain can recognize the second adjustment signal, solving the problem that the pulse width of the pulse signal to be measured is too narrow to be recognized by the second delay chain 230.

[0081] According to embodiments of this disclosure, the arrival time of the rising edge of the second adjustment signal can be considered as the arrival time of the rising edge of the pulse signal to be measured.

[0082] According to embodiments of this disclosure, the arrival time of the rising edge of the first adjustment signal can be considered as the arrival time of the falling edge of the measurement pulse signal.

[0083] According to the embodiments of this disclosure, since there is a fixed circuit structure between the comparator, inverter 110, first flip-flop 130, and second flip-flop 140, there may be a small, fixed, static time difference between the arrival time of the rising edge of the pulse signal under test and the arrival time of the rising edge of the second adjustment signal, and between the arrival time of the falling edge of the pulse signal under test and the arrival time of the rising edge of the first adjustment signal. When the power supply of the circuit system is stable and the temperature change is small, this time difference can be ignored or can be corrected in subsequent calibration.

[0084] According to embodiments of this disclosure, by using two delay chains to measure the first moment of the rising edge and the second moment of the falling edge of the same pulse signal under test, and using an encoding circuit for fine timestamp encoding in a 240-minute time division service, system hardware resources can be effectively saved, achieving the same or better measurement accuracy as using two sets of time-to-digital converter circuits with narrow pulse measurement capabilities.

[0085] According to embodiments of this disclosure, the pulse width measurement circuit further includes: a first delay chain circuit 210 and a second delay chain circuit 220; the first delay chain circuit 210 includes a first delay chain 211, in which a first signal including a plurality of level transitions is latched; in response to the first delay chain 211 receiving a first adjustment signal whose level state changes from a second level to a first level, the first signal is triggered and propagates in the first delay chain 211, and the first delay chain 211 is used to perform delay processing on the first signal; the first delay chain circuit 210 further includes a first trigger sequence 212, the first trigger sequence 212 being used to adjust the first signal in the first delay chain 210. The propagation position in 11 is sampled and latched, and a first sequence is output; the second delay chain circuit 220 includes a second delay chain 221, which latches a second signal including multiple level transitions. In response to the second delay chain 221 receiving a second signal whose level state changes from a second level to a first level, the second signal is triggered and propagates in the second delay chain 221. The second delay chain 221 is used to perform delay processing on the second signal; the second delay chain circuit 220 also includes a second trigger sequence 222, which is used to sample and latch the propagation position of the second signal in the second delay chain 221, and output a second sequence.

[0086] According to embodiments of this disclosure, the delay chain structure in the first delay chain circuit 210 and the second delay chain circuit 220 is not limited, and can be a normal delay chain structure, a multi-chain averaging delay chain structure, or a Wave Union A-type delay chain structure.

[0087] According to embodiments of this disclosure, if a multi-chain averaging delay chain structure is used, it can be a multi-chain averaging delay chain structure that improves the accuracy of time measurement by averaging multiple measurements.

[0088] According to embodiments of this disclosure, the first delay chain and the second delay chain can be delay chains with the same structure or delay chains with different structures.

[0089] Figure 4 A schematic diagram illustrating the connection relationship between the delay chain circuit and the encoding circuit according to a second embodiment of the present disclosure is shown.

[0090] like Figure 4As shown, the delay chain circuit includes a first delay chain circuit 210 and a second delay chain circuit 220. The first delay chain circuit 210 includes a first delay chain 211 and a first flip-flop sequence 212. The second delay chain circuit 220 includes a second delay chain 221 and a second flip-flop sequence 222. The first delay chain 211 can be represented by TDL Chain0, the first flip-flop sequence 212 can be represented by DFF Bank 0, the second delay chain 221 can be represented by TDL Chain1, and the second flip-flop sequence 222 can be represented by DFF Bank 1.

[0091] According to an embodiment of this disclosure, the output terminal of the first delay chain circuit 210 is the output terminal of the first flip-flop sequence 212, the output terminal of the second delay chain circuit 220 is the output terminal of the second flip-flop sequence 222, and both the output terminals of the first delay chain circuit 210 and the second delay chain circuit 220 are connected to the sorting circuit 230.

[0092] According to embodiments of this disclosure, both the first delay chain 211 and the second delay chain 222 may include multiple delay units, and both the first trigger sequence 212 and the second trigger sequence 231 may include multiple D triggers.

[0093] According to an embodiment of this disclosure, the first delay chain circuit 210 may include a first signal latch module, which latches a first signal. The output of the first signal latch module may be connected to the first delay chain 211, that is, when the first signal is triggered, it enters the first delay chain 211 for propagation. The first signal includes multiple level transitions, that is, multiple edge transitions. The number of edge transitions included in the first signal is not limited and can be determined according to the actual situation.

[0094] According to an embodiment of this disclosure, the second delay chain circuit 220 may include a second signal latch module, which latches a second signal. The output of the second signal latch module may be connected to the second delay chain 221, that is, when the second signal is triggered, it enters the second delay chain 221 for propagation. The second signal includes multiple level transitions, that is, multiple edge transitions. The number of edge transitions included in the second signal is not limited and can be determined according to the actual situation.

[0095] According to embodiments of this disclosure, the first flip-flop sequence 212 and the second flip-flop sequence 222 can sample and latch the signal propagation position at the system clock frequency.

[0096] According to embodiments of this disclosure, the propagation position of the first signal in the first delay chain can be recorded by the first trigger sequence 212, and the propagation position of the second signal in the second delay chain can be recorded by the second trigger sequence 222.

[0097] According to embodiments of this disclosure, the first signal and the second signal can be sawtooth waveform signals.

[0098] According to an embodiment of this disclosure, the internal processing of the first adjustment signal by the first delay chain circuit 210 is as follows: the first signal triggered by the rising edge of the first adjustment signal propagates in the first delay chain 221 until the next rising edge of the system clock arrives. It is then sampled and latched by the first flip-flop sequence associated with the first delay chain 221, thereby obtaining a series of thermometer codes, i.e., the first sequence. Based on the position where the high and low levels change in the first sequence, it can be determined how many units each edge of the first signal has propagated in the first delay chain 211, thereby obtaining the waveform propagation time information of the first signal. Then, the first sequence is encoded by the encoding circuit 240 to obtain the first propagation duration. The second delay chain circuit 220 is processed in the same way.

[0099] According to the embodiments of this disclosure, since the first signal is triggered by the rising edge of the first adjustment signal to propagate in the first delay chain 211 and ends propagation at the time when the next rising edge of the system clock arrives, the time when the rising edge of the first adjustment signal arrives can be determined by determining the propagation time of the first signal in the first delay chain 211 and the total time of the current system clock. The same applies to the second adjustment signal.

[0100] According to embodiments of this disclosure, the first delay chain circuit 210 or the second delay chain circuit 220 requires two system clock cycles to output the first sequence or the second sequence. For example, the first cycle is used to complete the propagation and sampling latching of the first signal in the first delay chain circuit 210, and the second cycle is used to complete the reset of the first delay chain circuit 210.

[0101] According to the embodiments of this disclosure, the purpose of resetting the first delay chain 211 is to allow the waveform of the current first signal to pass through the entire structure of the first delay chain 221 completely, so that the first delay chain 221 returns to its initial state and is ready to receive the next first signal and perform the next time measurement.

[0102] According to embodiments of this disclosure, as can be seen from the above, a first delay chain circuit 210 or a second delay chain circuit 220 can complete a time measurement at most once within every two adjacent system clock cycles, that is, generate a first sequence or a second sequence once. Therefore, the signal throughput rate of the first delay chain 220 and the second delay chain 230 is... , where T is one system clock cycle.

[0103] According to embodiments of this disclosure, the reset circuit 120 is configured to receive a first target value sent by the first delay chain circuit 210 and perform valid value identification on the first target value to obtain a first identification result. The reset circuit 120 is configured to generate a first reset signal when the first identification result indicates that the first target value is a valid value, wherein the first target value is a value at a preset position in the first sequence. The reset circuit 120 is also configured to receive a second target value sent by the second delay chain circuit 220 and perform valid value identification on the second target value to obtain a second identification result. The reset circuit 120 is configured to generate a second reset signal when the second identification result indicates that the second target value is a valid value, wherein the second target value is a value at a preset position in the second sequence.

[0104] According to embodiments of this disclosure, the reset circuit 120 can be a reset logic (Clear Logic).

[0105] According to embodiments of this disclosure, the first delay chain circuit 210 can send the value located at a preset position in the generated first sequence to the reset circuit 120, and the second delay chain circuit can do the same.

[0106] According to the embodiments of this disclosure, the method for valid value identification of the reset circuit 120 is not limited. Different valid value identification methods can be used depending on the first sequence and the second sequence output by different delay chain structures. For example, the first delay chain 211 adopts a Wave Union A-type delay chain structure. When the target value is 0, the first target value is considered to be a valid value.

[0107] According to embodiments of this disclosure, the reset circuit 120 generates a first reset signal if it considers the first target value to be valid, and generates a second reset signal if it considers the second target value to be valid.

[0108] According to an embodiment of the present disclosure, the first flip-flop 130 is further configured to: when the first flip-flop 130 receives a first reset signal, the output terminal of the first flip-flop 130 is configured to output a first adjustment signal with a level state of a second level.

[0109] According to an embodiment of this disclosure, when the first flip-flop 130 receives a first reset signal, the output terminal of the first flip-flop 130 will output a first adjustment signal with a level state of second level until the moment when the inverted signal jumps from the second level to the first level arrives, that is, the rising edge of the inverted signal arrives. After the rising edge of the inverted signal arrives, the first flip-flop 130 will continue to output the first adjustment signal with a level state of first level.

[0110] According to an embodiment of the present disclosure, the second flip-flop 140 is further configured to: when the second flip-flop 140 receives a second reset signal, the output terminal of the second flip-flop 140 is configured to output a second adjustment signal with a level state of the second level.

[0111] According to the embodiments of this disclosure, if the reset circuit 120 detects that the first target value is valid, it can determine that the rising edge of the first adjustment signal has been input to the first delay chain circuit 210, and the high level given by the first adjustment signal has met the pulse width requirement of the first delay chain circuit 210 for the input signal. Then, by giving the first reset signal through the reset circuit 120, the high level of the first adjustment signal can be ended, so that the first adjustment signal is a signal that the first delay chain circuit 210 can recognize. The logic for generating the second reset signal is similar, so the second adjustment signal output by the second flip-flop 140 also satisfies the recognition condition of the second delay chain circuit 220.

[0112] Figure 5 A schematic diagram of the output first sequence according to a second embodiment of the present disclosure is shown.

[0113] like Figure 5 As shown, according to an embodiment of this disclosure, the first delay chain 211 includes a plurality of delay cells i, i=1, 2...n. When a first adjustment signal, whose level transitions from low to high, enters the first delay chain 211, the first signal is triggered and propagates in the first delay chain 211, stopping propagation at the arrival of the next rising edge of the system clock, thus obtaining the propagation of the first signal in the first delay chain. The propagation position of the first signal in the first delay chain is sampled and latched by the first flip-flop sequence 212 represented by DFF Bank1, thereby outputting a first sequence from the first flip-flop sequence, which represents the propagation position of the first signal in the first delay chain 211.

[0114] According to an embodiment of this disclosure, the level state of the first adjustment signal changes from a second level to a first level in the first system clock cycle; the level state of the second adjustment signal changes from a second level to a first level in the second system clock cycle; the pulse width measurement circuit 150 further includes an encoding circuit 240.

[0115] The encoding circuit 240 is used to encode the first sequence and the second sequence respectively to obtain the first propagation duration of the first signal in the first delay chain circuit and the second propagation duration of the second signal in the second delay chain circuit; wherein, the first propagation duration represents the duration from the first moment to the moment when the second level jumps to the first level in the third system clock cycle, and the third system clock cycle is the next system clock cycle of the first system clock cycle; the second propagation duration represents the duration from the second moment to the moment when the second level jumps to the first level in the fourth system clock cycle, and the fourth system clock cycle is the next system clock cycle of the second system clock cycle.

[0116] According to embodiments of this disclosure, the encoding circuit 240 is not limited and can be a time-division multiplexing encoding circuit.

[0117] According to the embodiments of this disclosure, since the first signal is triggered by the rising edge of the first adjustment signal to propagate in the first delay chain 211, the triggering time of the first signal is the arrival time of the rising edge of the first adjustment signal. Since the first signal stops propagating in the first delay chain 211 in the next system clock cycle, by determining the propagation time of the first signal in the first delay chain 211, the length of the time period from the arrival time of the rising edge of the first adjustment signal to the arrival time of the rising edge of the next system clock cycle can be determined. Thus, the arrival time of the rising edge of the first adjustment signal can be determined by the total length of a system time cycle, the number of cycles of the current system clock cycle, and the length of the time period. The method for determining the arrival time of the rising edge of the second adjustment signal is similar.

[0118] According to embodiments of this disclosure, since both the first signal and the second signal include multiple edge-changing edges, taking the first signal as an example, by determining the propagation position of an edge-changing edge in the first delay chain 211, the propagation duration of the first signal in the first delay chain 211 can be determined. By determining the propagation positions of each edge-changing edge in the first delay chain, the propagation duration of multiple first signals in the first delay chain 211 can be determined. Furthermore, by averaging the propagation times, a more accurate first propagation duration can be obtained.

[0119] According to embodiments of this disclosure, the reason for including multiple edge-to-edge transitions in the second signal is the same as that in the first signal, namely, to obtain a more accurate second propagation duration.

[0120] According to embodiments of this disclosure, the encoding circuit 240 may include multiple lookup table matrices and adders. The process of determining the propagation duration through the encoding circuit 240 can be as follows: Specifically, taking a first sequence as an example, the encoding circuit 240 encodes the first sequence to obtain the propagation position of the first signal in the first delay chain 211. Since the first signal includes multiple edge-to-edge signals, each edge-to-edge signal has its own propagation position. By adding the multiple propagation positions, the total propagation position can be obtained. By mapping the total propagation position to the propagation position and propagation duration relationship diagram, the first propagation duration can be obtained. The method for obtaining the second propagation duration using the second sequence is similar.

[0121] According to embodiments of this disclosure, a propagation position and propagation duration relationship diagram characterizes the correspondence between the propagation position and propagation duration of a signal, and this propagation position and propagation duration relationship diagram is determined by the code density method.

[0122] According to embodiments of this disclosure, when the first delay chain 211 and the second delay chain 221 are the same, the relationship diagram between the propagation position and the propagation duration corresponding to the first delay chain 211 and the second delay chain 221 is the same; otherwise, it is different.

[0123] According to an embodiment of this disclosure, the input terminal of the sorting circuit 230 is connected to the output terminals of the first delay chain circuit 210 and the second delay chain circuit 220, respectively, and the output terminal of the sorting circuit 230 is connected to the input terminal of the encoding circuit 240. The sorting circuit is used to sort the first sequence and the second sequence.

[0124] According to the embodiments of this disclosure, if the encoding circuit 240 receives a first sequence and a second sequence with valid values ​​within the same system clock cycle, the encoding circuit 240 will be unable to determine the sequence to be encoded first, which may cause the encoding circuit 240 to become disordered. However, if the first sequence and the second sequence are sorted by the sorting circuit 230 and then output to the encoding circuit 240 in two system clock cycles, the above problem will not exist.

[0125] According to an embodiment of the present disclosure, the sorting circuit 230 is further configured to: upon receiving a first target value and a second target value, identify the first target value and the second target value respectively to obtain a third identification result; and, if the third identification result indicates that both the first target value and the second target value are valid values, sort the first sequence and the second sequence to obtain a sorting result, wherein the sorting circuit is further configured to input the first sequence and the second sequence sequentially into the encoding circuit based on the sorting result.

[0126] According to embodiments of this disclosure, by identifying the first target value and the second target value, it can be determined whether the first sequence and the second sequence need to be encoded, thereby avoiding inputting sequences that do not need to be encoded into the encoding circuit 240 and avoiding inputting the first sequence and the second sequence into the encoding circuit 240 within one system clock cycle.

[0127] According to embodiments of this disclosure, if the first target value is determined to be valid, it can be determined that the first sequence can be encoded; if the second target value is determined to be valid, it can be determined that the second sequence can be encoded.

[0128] According to embodiments of this disclosure, if both the first sequence and the second sequence can be encoded, the first sequence and the second sequence can be randomly sorted, and the sequence with the first sorting result is output in the current system clock cycle, and the remaining sequence is output in the next system clock cycle. For example, if the sorting result is to output the first sequence first and then the second sequence, the first sequence is immediately input into the encoding circuit and the second sequence is stored until the next system clock cycle, when the second sequence is input into the encoding circuit.

[0129] According to embodiments of this disclosure, the sorting circuit 230 can add an identifier value at a preset identifier position of the first sequence and the second sequence, thereby enabling the encoding circuit 240 to determine the delay chain circuit corresponding to each of the first sequence and the second sequence by the identifier value. For example, the encoding circuit 240 determines that the first sequence is output by the first delay chain module by determining the identifier value in the first sequence.

[0130] According to embodiments of this disclosure, specifically, the sorting circuit 230 can concatenate the identifier value and the first sequence, and add identifier information to enable the encoding circuit to distinguish the identifier value and the first sequence. The specific output format of the sorting circuit 230 is not limited; for example, it can be output in the form of a table.

[0131] According to embodiments of this disclosure, the sorting circuit 230 is further configured to: input the first sequence into the encoding circuit when the third identification result indicates that the first target value is valid and the second target value is not valid; or, input the second sequence into the encoding circuit when the third identification result indicates that the second target value is valid and the first target value is not valid.

[0132] According to embodiments of this disclosure, when the third identification result indicates that only the first target value is valid or only the second target value is valid, the sequence with valid values ​​is input into the encoding circuit 240, and the sequence without valid values ​​is discarded. For example, if the first target value is valid but the second target value is not valid, it is determined that the first sequence can be encoded while the second sequence does not need to be encoded. In this case, the first sequence can be input into the encoding circuit, and the second sequence can be discarded.

[0133] According to embodiments of this disclosure, since the encoding circuit 240 is a time-division multiplexing encoding circuit, the first sequence and the second sequence can be sorted by the sorting circuit 230, so that they are input to the encoding circuit 240 at different system clock cycles, thereby reducing the use of the encoding circuit and achieving lower resource consumption.

[0134] According to embodiments of this disclosure, since the encoding circuit 240 is divided into multiple serially connected parts, each part operates under the system clock and can complete its operation and conversion within one system clock cycle, the encoding circuit 240 can accept a set of sequences for operation in each system clock cycle, and its data throughput is [data throughput rate missing]. Therefore, the highest time measurement rate of a delay chain structure is... Therefore, an encoding circuit 240 can encode sequences generated by at least two delay chains without blocking.

[0135] According to an embodiment of the present disclosure, the pulse width measurement circuit 150 further includes a counter 260; the counter 260 is used to record a first system clock cycle and a second system clock cycle, and input the first system clock cycle and the second system clock cycle into the pulse width calculation circuit 250.

[0136] According to an embodiment of this disclosure, the counter 260 is used to record the number of system clock cycles by inputting the system clock, that is, to record the first system clock cycle in which the pulse signal under test is located when the pulse signal under test changes from a low level to a high level, and the second system clock cycle in which the pulse signal under test is located when the pulse signal under test changes from a high level to a low level, and to input the first system clock cycle and the second system clock cycle into the pulse width calculation circuit 250 for storage, so as to be used in subsequent calculations.

[0137] According to embodiments of this disclosure, counter 260 can be used to record the number of system clock cycles at which the rising edge of the pulse signal under test arrives and the number of system clock cycles at which the falling edge of the pulse signal under test arrives.

[0138] According to embodiments of this disclosure, the pulse width calculation circuit 250 can be a separate calculation module or a subordinate module in the encoding circuit 240.

[0139] According to an embodiment of this disclosure, the pulse width measurement circuit further includes a pulse width calculation circuit. The pulse width calculation circuit 250 is specifically used to: determine a first moment based on a first system clock cycle and a first propagation duration; determine a second moment based on a second system clock cycle and a second propagation duration; and perform target calculation on the first moment and the second moment to determine the pulse width of the pulse signal to be measured.

[0140] According to embodiments of this disclosure, the total duration of the first system clock cycle can be obtained by multiplying the number of cycles of the first system clock cycle by the total length of a system clock cycle. For example, if the number of cycles of the first system clock cycle is 2 (i.e., the second system clock cycle), and each system clock cycle is 2ns, then the total duration of the first system clock cycle is 4ns. The first moment can be determined by subtracting the first propagation duration from the total duration of the first system clock cycle. The calculation method for the second moment is similar.

[0141] According to an embodiment of this disclosure, after obtaining the first time and the second time, the pulse width of the pulse signal to be measured can be obtained by subtracting the first time and the second time.

[0142] According to the embodiments of this disclosure, specifically, for example: the number of cycles of the second system clock cycle is 4, which is the 4th system clock cycle; the number of cycles of the first system clock cycle is 6, which is the 6th system clock cycle; one system clock cycle is 2ns; the second propagation duration is 0.356ns; the first propagation duration is 0.458ns; then the arrival time of the falling edge is 6×2ns-0.356=11.644ns; the arrival time of the rising edge is 4×2ns-0.458ns=7.542ns; then the pulse width is 11.644ns-7.542ns=4.102ns.

[0143] Figure 6 A first timing diagram according to a second embodiment of the present disclosure is illustrated schematically.

[0144] like Figure 6 As shown, by observing the rising edge position of the pulse signal under test (i.e., the position where it jumps from the second level to the first level) and the rising edge position of the second adjustment signal, it can be seen that the arrival times of the rising edges of the pulse signal under test and the second adjustment signal are basically the same. Similarly, by observing the falling edge position of the pulse signal under test (i.e., the position where it jumps from the first level to the second level) and the rising edge position of the second adjustment signal, it can be seen that the arrival times of the falling edge of the pulse signal under test and the rising edge position of the second adjustment signal are basically the same.

[0145] According to embodiments of this disclosure, valid0 is a valid value included in the second sequence, and valid1 is a valid value included in the first sequence. Figure 6 It can be seen that the first sequence and the second sequence, which include valid values, are not output in one system clock cycle in this embodiment. Therefore, the sorting circuit 230 can directly output the first sequence and the second sequence in the corresponding system clock cycle.

[0146] Figure 7 A second timing diagram according to a second embodiment of the present disclosure is illustrated schematically.

[0147] like Figure 7 As shown, the first sequence and the second sequence, which include valid values, are output in one system clock cycle. Therefore, the sorting circuit 230 can sort the first sequence and the second sequence and output the first sequence and the second sequence in two system clock cycles.

[0148] Figure 8 A third timing diagram according to a second embodiment of the present disclosure is illustrated schematically.

[0149] like Figure 8 As shown, in the second embodiment, the time-to-digital converter circuit with narrow pulse measurement capability operates at a system clock frequency of 400MHz and is used to measure the pulse width data of the analog signal under test output from the detector. The preset threshold is 0.7V. Initially, the detector does not detect an event and outputs 0V, not exceeding the preset threshold, so comparator 210 outputs a low level. During cycle 0225, the level of the analog signal under test output by the detector gradually increases, exceeding the preset threshold of 0.7V. The external comparator immediately outputs a high level, generating a rising edge signal that enters the FPGA through the FPGA I / O interface where the time-to-digital converter circuit with narrow pulse measurement capability is located. It is then split into two paths. One path's pulse signal under test becomes a falling edge signal (i.e., inverted signal) after passing through inverter 110, and cannot trigger the first flip-flop 130. The other rising edge triggers the second flip-flop 140, causing its Q port to output a preset high level from the D port. The second adjustment signal, whose output level is high, immediately propagates in the second delay chain 221 until the next rising edge of the system clock arrives, i.e., at the start of cycle 0226. It is then sampled and latched by the DFF sequence connected to the delay unit in the second flip-flop 140. The latched second sequence represents the propagation position of the waveform of the second signal triggered by the rising edge of the second adjustment signal within the second flip-flop 140. This second sequence is sent to the sorting circuit 230 for sorting. Since only one second sequence is sent to the sorting circuit 230 in cycle 0226, the sorting circuit 230 directly sends the data from the second delay chain circuit 220 to the subsequent encoding circuit 240 for encoding. In cycle 0227, the fine timestamp data of the rising edge arrival time, i.e., the second moment information of the second adjustment signal transitioning to the first level, is obtained, which is 0.25 system clock cycles. Therefore, the rising edge arrival time is cycle 0225.25.

[0150] Similarly, within system cycle 0228, the analog signal level output by the detector gradually decreases until it reaches the preset threshold of 0.7V. The external comparator 210 immediately outputs a low level, generating a falling edge that enters the FPGA through the FPGA I / O interface of the time-to-digital converter circuit with narrow pulse measurement capability. This edge is then split into two paths. Since it is a falling edge, it cannot trigger the second flip-flop 140. On the other path, the falling edge becomes a rising edge after passing through the inverter 110, triggering the first flip-flop 130. This causes its Q port to output the preset high level of the D port. The first adjustment signal, with a high level output from the first flip-flop 130, immediately propagates in the first delay chain 211 until the next rising edge of the system clock arrives, i.e., the start of cycle 0229. It is then sampled and latched by the DFF sequence connected to the delay unit in the first delay chain 211. The latched first sequence represents the propagation position of the waveform of the first signal triggered by the falling edge in the first delay chain 211. The first sequence is sent to the sorting circuit 230 for sorting. Since only one data point from the first sequence is sent to the sorting circuit 230 in cycle 0229, the sorting circuit 230 directly sends the data sent by TDL1 to the subsequent encoding circuit 240 for encoding. In cycle 022A, the fine timestamp data of the rising edge arrival time, i.e., the first moment information of the first adjustment signal transitioning to the first level, is obtained, which is 0.75 system clock cycles in this case. Therefore, the rising edge arrival time is cycle 0228.75.

[0151] Therefore, the pulse width data of the pulse signal to be measured can be obtained as (0228.75-0225.25)*2.5ns=8.75ns.

[0152] Figure 9A The diagram schematically illustrates a first correspondence between the different number of edge variations included in the first and second signals according to a second embodiment of the present disclosure and the pulse width measurement error.

[0153] like Figure 9A As shown, the horizontal axis of the first correspondence graph is the test pulse width, which is in ns, and the vertical axis is the root mean squared (RMS) error, which is in ps (pico seconds).

[0154] According to embodiments of this disclosure, since the time-to-digital converter circuit with narrow pulse measurement capability in this disclosure can be used to measure the pulse width of a test pulse signal, the time-to-digital converter circuit with narrow pulse measurement capability in this disclosure can be referred to as TOT TDC.

[0155] According to embodiments of this disclosure, in Figure 9AThe orange line represents the RMS error of a time-to-digital converter (TD-SCDMA) circuit with narrow pulse measurement capability for test pulse signals of various test pulse widths when both the first and second signals have 2 edge-to-edge (TOT) TDC. The red line represents the RMS error of the same circuit when both the first and second signals have 4 edge-to-edge (TOT) TDC. The purple line represents the RMS error of the same circuit when both the first and second signals have 6 edge-to-edge (TOT) TDC. The blue line represents the RMS error of the same circuit when both the first and second signals have 8 edge-to-edge (TOT) TDC.

[0156] According to embodiments of this disclosure, in Figure 9A In the illustrated embodiment, a pulse pattern generator is used to generate test pulse signals with pulse widths ranging from 520 ps to 2 ns. Each test pulse signal is repeated 5000 times. The RMS error of the time-to-digital converter circuit with narrow pulse measurement capability of this disclosure is calculated for each pulse width of the test pulse signal under the condition of a first signal and a second signal with different edge-to-edge numbers.

[0157] According to embodiments of this disclosure, by Figure 9A It can be seen that when the number of edge-to-edge changes in both the first and second signals is 8, the time-to-digital converter circuit with narrow pulse measurement capability has the smallest RMS error for test pulse signals with different test pulse widths. Therefore, in actual selection, the signal with more edge-to-edge changes can be fixed in the delay chain based on the above experimental results.

[0158] Figure 9B The diagram schematically illustrates a second correspondence between the different number of edge variations included in the first and second signals according to a second embodiment of the present disclosure and the pulse width measurement error.

[0159] like Figure 9B As shown, the horizontal and vertical axes, as well as the different colored lines, all have the same meaning as... Figure 9A Same. Figure 9BThe present invention generates test pulse signals with pulse widths ranging from 1ns to 1000ns and step sizes of 5ns using a pulse pattern generator. The time-to-digital converter circuit with narrow pulse measurement capability is used to calculate the RMS error of the test pulse signals with various pulse widths under the condition of first and second signals with different edge-to-edge quantities.

[0160] According to embodiments of this disclosure, by Figure 9B It can be seen that, when the number of edge-to-edge changes included in both the first and second signals is 8, the time-to-digital converter circuit with narrow pulse measurement capability has the smallest RMS error for test pulse signals with different test pulse widths.

[0161] According to embodiments of this disclosure, by Figure 9A and Figure 9B The average RMS errors for 2-edge TOT TDC, 4-edge TOT TDC, 6-edge TOT TDC, and 8-edge TOT TDC are 5.3ps, 4.4ps, 4.1ps, and 3.7ps, respectively.

[0162] According to the embodiments of this disclosure, the inventors of this disclosure also conducted an experimental comparison between the TDC in related technologies and the TDC in this disclosure. The comparison results are shown in Tables 1 and 2 below. It should be noted that the TDC in this disclosure is only one embodiment, and different models of FPGAs can be used to obtain the TDC in this disclosure according to different actual situations.

[0163]

[0164] Table 1

[0165] According to embodiments of this disclosure, Table 1 shows related techniques for measuring the pulse width of signals as presented in papers published in 2015, 2016, and 2021. It can be seen that the FPGA models used in the related techniques published in 2015 and 2016 are Virtex-5 and EP3-500, respectively. By observing the RSM error, it can be seen that the RSM error of both is larger than that of the 2-edge TOT TDC, 4-edge TOT TDC, 6-edge TOT TDC, and 8-edge TOT TDC of this disclosure. Furthermore, by observing the measurable narrowest pulse width and system dead time of both, it can be seen that the minimum pulse width of the measurable pulse signal is larger than that of the TOT TDC of this disclosure, which may result in the inability to measure pulse signals with smaller pulse widths, and the system dead time is also longer.

[0166] According to embodiments of this disclosure, the FPGA model used in the related technology published in 2021 is Ultrascale, which has a process node of 16nm (Newton Metre). The TOT TDC of this disclosure uses Kintex-7 FPGA with a process node of 28nm. Since Ultrascale has a smaller process node, it is more expensive, while Kintex-7, which has a higher process node, is cheaper. The TOT TDC obtained by using this disclosure can achieve RMS error, measurable narrowest pulse width, system dead time, etc., which are close to those of Ultrascale FPGA, thus achieving a certain cost saving effect.

[0167] According to embodiments of this disclosure, in some embodiments, implementing the time-to-digital converter circuit with narrow pulse measurement capability of this disclosure using an Ultrascale type FPGA will achieve better results.

[0168]

[0169] Table 2

[0170] According to embodiments of this disclosure, related technologies 1 to 5 in Table 2 all use one channel of TDC to measure the rising edge arrival time and another channel of TDC to measure the falling edge arrival time. That is, two channels of TDC are required to complete the over-threshold time measurement. The TDC type characterizes the structure type of the delay chain used by the TDC and the number of edge-changing signals included in the latched signal in the delay chain. For example, WUA indicates that the delay chain used is a Wave Union A-type delay chain structure, and 2 edge indicates the number of edge-changing signals included in the latched signal in the delay chain.

[0171] According to embodiments of this disclosure, in some embodiments, l-TDL TOT, WU-A(4 edge), and DualTDL TOT are equivalent to 4-edge TOT TDC, and the same applies to lTDL TOT, WU-A(6 edge), DualTDL TOT, WU-A(8 edge), and DualTDL TOT.

[0172] According to embodiments of this disclosure, both LUT and FF are logic resources inside the FPGA. LUT represents a lookup table and FF represents a latch. The number of LUTs and FFs in Table 2 are the number included in one channel.

[0173] According to embodiments of this disclosure, the TDC implemented using a Kintex-7 FPGA in Related Art 1 exhibits the same RMS error as the WU-A (4-edge), DualTDL TOT of this disclosure. However, the number of LUTs and FFs used in the WU-A (4-edge), DualTDL TOT of this disclosure is only 25.0% and 80.8% of that in Related Art 1, respectively. Similarly, the WU-A (8-edge), DualTDL TOT of this disclosure has similar RMS errors to the Multichain (4-chain) in Related Art 2 and the TDC implemented using a Kintex-7 FPGA in Related Art 4, while the FFs used in this disclosure are only 73.2% and 58.8% of those, respectively.

[0174] Furthermore, the WU-A (8 edge), DualTDL TOT of this disclosure, and the WU-A (8 edge) in related technology 3 all employ a WU-A type delay chain, and the number of edge-to-edge transitions of the latched signals in the delay chain is 8. However, this disclosure saves 31.1% and 38.9% of the number of LUTs and FFs, respectively, compared to the related technologies. Compared to the WU-A (4 edge) implemented in related technology 5, the WU-A (4 edge) and DualTDL TOT of this disclosure save 91.7% and 87.9% of the number of LUTs and FFs, respectively.

[0175] Those skilled in the art will understand that the effective embodiments and / or claims described in this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the effective embodiments and / or claims described in this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0176] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A time-to-digital converter circuit having narrow pulse measurement capability, characterized by, include: An inverter is used to invert the pulse signal under test to obtain an inverted signal; A reset circuit is used to provide a first reset signal and a second reset signal; A first trigger is configured to receive the inverted signal and the first reset signal, and output a first adjustment signal based on the inverted signal and the first reset signal, wherein the first trigger is configured to output the first adjustment signal with a level of the first level when the inverted signal changes from a second level to a first level and the first reset signal is not received; The second trigger is used to receive the pulse signal under test and the second reset signal, and output a second adjustment signal based on the pulse signal under test and the second reset signal. The second trigger is used to output the second adjustment signal with the level state of the first level when the pulse signal under test changes from the second level to the first level and the second reset signal is not received. A pulse width measurement circuit is used to determine the first moment when the first adjustment signal jumps to the first level and the second moment when the second adjustment signal jumps to the first level, and to obtain the pulse width data of the pulse signal to be measured based on the first moment and the second moment.

2. The time-to-digital converter circuit with narrow pulse measurement capability according to claim 1, characterized in that, The pulse width measurement circuit includes: a first delay chain circuit and a second delay chain circuit; The first delay chain circuit includes a first delay chain, in which a first signal including a plurality of level transitions is latched. In response to the first delay chain receiving a first adjustment signal whose level state changes from a second level to a first level, the first signal is triggered and propagates in the first delay chain. The first delay chain is used to perform delay processing on the first signal. The first delay chain circuit further includes a first flip-flop sequence, which is used to sample and latch the propagation position of the first signal in the first delay chain and output a first sequence. The second delay chain circuit includes a second delay chain, in which a second signal including a plurality of level transitions is latched. In response to the second delay chain receiving a second signal whose level state transitions from a second level to a first level, the second signal is triggered and propagates in the second delay chain. The second delay chain is used to perform delay processing on the second signal. The second delay chain circuit further includes a second flip-flop sequence, which is used to sample and latch the propagation position of the second signal in the second delay chain and output a second sequence.

3. The time-to-digital converter circuit with narrow pulse measurement capability according to claim 2, characterized in that, The reset circuit is used to receive a first target value sent by the first delay chain circuit and to identify the first target value as a valid value to obtain a first identification result. The reset circuit is used to generate the first reset signal when the first identification result indicates that the first target value is a valid value. The first target value is a value at a preset position in the first sequence. The reset circuit is further configured to receive a second target value sent by the second delay chain circuit, and to perform valid value identification on the second target value to obtain a second identification result, wherein the reset circuit is configured to generate a second reset signal when the second identification result indicates that the second target value is a valid value, and the second target value is a value located at the preset position in the second sequence.

4. The time-to-digital converter circuit with narrow pulse measurement capability according to claim 3, characterized in that, The first trigger is also used for: When the first trigger receives the first reset signal, the output of the first trigger is used to output a first adjustment signal with a level state of the second level; The second trigger is also used for: When the second flip-flop receives the second reset signal, the output of the second flip-flop is used to output a second adjustment signal with a level of the second level.

5. The time-to-digital converter circuit with narrow pulse measurement capability according to claim 3, characterized in that, The level of the first adjustment signal changes from the second level to the first level in the first system clock cycle; The level of the second adjustment signal changes from the second level to the first level during the second system clock cycle; The pulse width measurement circuit further includes: an encoding circuit; The encoding circuit is used to encode the first sequence and the second sequence respectively to obtain the first propagation time of the first signal in the first delay chain circuit and the second propagation time of the second signal in the second delay chain circuit; Wherein, the first propagation duration represents the duration from the first moment to the moment when the second level transitions to the first level during the third system clock cycle, and the third system clock cycle is the next system clock cycle after the first system clock cycle; the second propagation duration represents the duration from the second moment to the moment when the second level transitions to the first level during the fourth system clock cycle, and the fourth system clock cycle is the next system clock cycle after the second system clock cycle.

6. The time-to-digital converter circuit with narrow pulse measurement capability according to claim 5, characterized in that, The pulse width measurement circuit further includes: a sorting circuit; The input terminal of the sorting circuit is connected to the output terminals of the first delay chain circuit and the second delay chain circuit, and the output terminal of the sorting circuit is connected to the input terminal of the encoding circuit. The sorting circuit is used to sort the first sequence and the second sequence.

7. The time-to-digital converter circuit with narrow pulse measurement capability of claim 6, wherein, The sorting circuit is also used for: Upon receiving the first target value and the second target value, valid value identification is performed on the first target value and the second target value respectively to obtain a third identification result; When the third identification result indicates that both the first target value and the second target value are valid values, the first sequence and the second sequence are sorted to obtain a sorting result. The sorting circuit is further used to input the first sequence and the second sequence into the encoding circuit in sequence based on the sorting result.

8. The time-to-digital converter circuit with narrow pulse measurement capability of claim 7, wherein, The sorting circuit is also used for: If the third recognition result indicates that the first target value is valid and the second target value is not valid, the first sequence is input to the encoding circuit. Alternatively, if the third identification result indicates that the second target value is valid and the first target value is not valid, the second sequence is input into the encoding circuit.

9. The time-to-digital converter circuit with narrow pulse measurement capability according to claim 5, characterized in that, The pulse width measurement circuit further includes: a counter; The counter is used to record the first system clock cycle and the second system clock cycle, and inputs the first system clock cycle and the second system clock cycle into the pulse width calculation circuit.

10. The time-to-digital converter circuit with narrow pulse measurement capability according to claim 9, characterized in that, The pulse width measurement circuit further includes the pulse width calculation circuit, which is specifically used for: The first moment is determined based on the first system clock cycle and the first propagation duration; The second moment is determined based on the second system clock cycle and the second propagation duration; The target calculation is performed on the first time point and the second time point to determine the pulse width data of the pulse signal to be measured.

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