Predictive hub assignment data structure

Abstract

The present disclosure relates to predictive center allocation data structures. An apparatus includes a memory resource configured to store a data entry in a data storage resource including a first data structure and a second data structure, and a processing device coupled to the memory resource. The processing device is configured to determine a predicted address location in the first data structure, compare the predicted address location to at least one address threshold, change the predicted address location to a changed predicted address location, determine an equivalent address location in a second data structure equivalent to the changed predicted address location, and write the data entry to the equivalent address location in the second data structure.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to digital logic circuits, and more specifically, to predictive central allocation data structures. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] On one hand, this disclosure relates to an apparatus comprising: a memory resource configured to store data entries in a data structure including a first data structure and a second data structure; and a processing means coupled to the memory resource, wherein the processing means is configured to: determine a predicted address location in the first data structure for a data entry; compare the predicted address location with at least one address threshold; change the predicted address location to a modified predicted address location based on the comparison of the predicted address location with the at least one address threshold; determine an equivalent address location in the second data structure that is equivalent to the modified predicted address location; and write the data entry to the equivalent address location in the second data structure.

[0004] On the other hand, this disclosure relates to a method comprising: determining a predicted physical address location in a first data structure for a data entry; comparing the predicted physical address location with at least one address threshold; changing the predicted physical address location to a modified predicted address location; determining an equivalent address location in a second data structure that is equivalent to the modified predicted address location in the first data structure; and writing a first data entry to the equivalent physical address location in the second data structure.

[0005] On the other hand, this disclosure relates to a non-transitory computer-readable storage medium comprising, when executed by a processing device, instructions causing the processing device to: determine a predicted address location in a first data structure for a first data entry, the predicted address location being at an off-center physical address in the first data structure, wherein the first data structure is a complete data structure; compare the predicted address location with an upper address threshold and a lower address threshold; change the predicted address location to a modified predicted address location in a permissible physical address region extending from the upper address threshold to the lower address threshold in response to: determining that the predicted address location exceeds the upper address threshold; or determining that the predicted address threshold is less than the lower address threshold; determining an equivalent address location in a second data structure equivalent to the modified predicted address location in the first data structure; and writing the first data entry to the equivalent address location in the second data structure. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This describes an example memory subsystem according to some embodiments of the present disclosure.

[0009] Figures 3A to 3C Examples illustrate a series of operations that can be performed using a predictive central allocation data structure according to some embodiments of this disclosure.

[0010] Figure 4 Examples of memory resources having multiple address locations according to some embodiments of this disclosure are described.

[0011] Figure 5 This is a flowchart corresponding to a method for predictive central allocation of data structures according to some embodiments of the present disclosure.

[0012] Figure 6 This is an example block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0013] This disclosure relates to predictive central allocation data structures, and more particularly, to memory subsystems comprising predictive allocation data structure components, also referred to herein as "predictive central allocation circuitry." The predictive central allocation data structures may be stored in one or more memory resources associated with the memory subsystem. The memory subsystem may be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is, for example, a storage system such as a solid-state drive (SSD). The following is combined with... Figure 1 Examples describing storage devices and memory modules are provided. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] During operation, data is written to and retrieved from the memory subsystem. Some data is written to permanent memory devices (which may be similar to or analogous to "non-volatile memory" devices) within the memory subsystem for long-term storage, while other data is written to non-permanent memory devices (which may be similar to or analogous to "volatile" memory devices) within the memory subsystem for fast, short-term retrieval. Still other data is written to various memory resources and / or caches within the memory subsystem to assist in the execution of operations involving the memory subsystem. For example, various memory resources and / or caches may be utilized during the operation of the memory subsystem to provide read caches, write-through caches, write-back caches, and / or write-around caches. Additionally, some memory resources and / or caches of the memory subsystem may be allocated to store various tables used during the operation of the memory subsystem. One such example is a logical-to-physical (L2P) table used to map logical addresses used by the host system to physical addresses of the memory subsystem in which data is physically stored. Another such example is a database containing an organized collection of data stored within memory resources and / or caches.

[0015] In some conventional methods, when data is written to such memory resources and / or caches, the data is typically written sequentially (e.g., in ascending or descending order) to the physical addresses of the memory resources and / or caches in the order in which the data was received. For example, if a data entry vector [51,7,300,12,3] is to be written to a memory resource and / or cache, then if the data is ordered in ascending order, the first data entry (51) is typically written to the first physical address (or “zero address”) of the memory resource and / or cache. As used herein, the first data entry refers to the initial data entry written to the data structure before any subsequent data entries are written to the data structure.

[0016] When the second data entry (7) is written to the memory resource and / or cache, the first data entry (51) is shifted to the second physical address (or "first address location") of the memory resource and / or cache, and the second data entry (7) may be written to the first physical address (or "zero address location") of the memory resource and / or cache. When the third data entry (300) is written to the memory resource and / or cache, the first data entry (51) may be shifted to the third physical address (or "second address location") of the memory resource and / or cache, the second data entry (7) may be shifted to the second physical address (or "first address location") of the memory resource and / or cache, and the third data entry (300) may be written to the first physical address (or "zero address location") of the memory resource and / or cache. This pattern may be repeated for the remaining data entries (e.g., the fourth data entry (12) and the fifth data entry (3) in this particular instance).

[0017] It should be noted that the above examples are used in methods where sorting of data is not required. The following examples are illustrative of some conventional methods where data is sorted when written to memory resources and / or caches. Given the same data entry vector [51,7,300,12,3], the first data entry (51) is typically written to the first physical address (or "zero address") of the memory resources and / or cache. When the second data entry (7) is written to the memory resources and / or cache, the first data entry (51) may be shifted to the second physical address (or "first address") of the memory resources and / or cache, and the second data entry (7) may be written to the first physical address (or "zero address") of the memory resources and / or cache.

[0018] Continuing this example, because the third data entry (300) is greater than the first and second data entries (e.g., has a larger value), the third data entry is written to the third physical address (or "second address location") of the memory resource and / or cache. Now, the fourth data entry (12) is smaller than the first data entry (51) and the third data entry (300) (e.g., has a lower value), but larger than the second data entry (7). The first data entry (51) and the third data entry (300) are shifted to the third physical address (or "second address location") and the fourth physical address (or "third address location") of the memory resource and / or cache, respectively, and the fourth data entry (12) is written to the second physical address (or "first address location") of the memory resource and / or cache. Finally, because the fifth data entry (3) is smaller than the first to fourth data entries, each of the first to fourth data entries is shifted up one address position (e.g., the third data entry (300) is shifted to the fifth physical address (or "fourth address position"), the first data value (51) is shifted to the fourth physical address (or "third address position"), the fourth data value (12) is shifted to the third physical address (or "second address position"), and the second data value (7) is shifted to the second physical address (or "first address position"). Finally, the fifth data value (3) is written to the first physical address (or "zeroth address position"). Thus, the final order of the data entries in this method is allocated such that the data entries are organized in ascending order. It will be understood that the final order of the data entries in this method can be organized in descending order using an operation similar to that described above.

[0019] It will be understood that the repeated shifting in the above examples requires multiple reads, writes, overwrites, and rewrites of data entries to maintain the data entries within a data structure within (a number of) memory resources and / or (a number of) caches, especially when the data entries are maintained in an ordered manner (e.g., based on ascending or descending order of the data entry's value). These shifts of data entries, and thus the reads and writes, can become expensive in terms of computational resource overhead (e.g., power, time, bandwidth, etc.) and can therefore degrade the overall performance of computing systems employing such methodologies.

[0020] Some other methods attempt to address the aforementioned drawbacks by initially writing data (e.g., the first data entry) to a central or eccentric address in memory resources and / or cache (in the absence of an address threshold). A central address is an address location substantially physically equidistant from the first physical address and the last physical address of the memory resource. An eccentric address is an address location in the memory resource that is neither the first physical address, nor the last physical address, nor the central address. However, such methods can lead to multiple reads, writes, overwrites, and rewrites of data entries, especially when data entries are maintained in an ordered manner (e.g., ascending or descending based on the numerical value of the data entries). That is, depending on the type and / or order of the data entries stored in the data structure, starting from a fixed point in the data structure (e.g., the central address) may not be appropriate. For example, data entries may be largely randomized or may have some ordered manner (e.g., ascending or descending). In such cases, initially writing data entries to the central address may result in an excessive number of subsequent shifts of the data entries (e.g., in response to other data entries being written to the data structure). Furthermore, in the absence of an address threshold, using an eccentric approach may tend to write initial data entries to physical addresses that are too close to the first or last physical address of the data structure. Therefore, any subsequent data entries written to the data structure may result in an excessive number of data entries being shifted, for example, to maintain data entries in a sequential manner. As mentioned, the shifting (e.g., reading and writing) of data entries (e.g., the data entry initially written to the center address) can become expensive in terms of computational resource overhead (e.g., power, time, bandwidth, etc.) and thus degrade the overall performance of computing systems employing such methodologies.

[0021] To address the aforementioned and other shortcomings, the method presented herein employs a predictive center-assignment data structure. This structure determines a predicted address location, compares the predicted address location with at least one address threshold, changes the predicted address location to the modified predicted address location, determines the equivalent address location of the modified predicted address location, and writes a data entry (e.g., an initial data entry) to the equivalent address location. The method can use data entries from a complete data structure (e.g., a first data structure) as the basis for determining the predicted address location for data entries to be written to subsequent data structures (e.g., a new unfilled data structure). It should be noted that, unlike previous methods, the predicted address location (and equivalent address location) may not be the first or last physical address of the data structure. Furthermore, unlike previous methods, the predicted address location (and equivalent address location) may be an address location other than the center address of the data structure. In other words, the predictive center-assignment data structure presented herein allows the first data entry to be written to an off-center address location, as described herein. Therefore, at least by determining the predicted address location in at least the first data structure and then writing the data entry to the equivalent address location in the second data structure (e.g., which may be an off-center address location that is neither the first physical address nor the last physical address), the embodiments described herein can exhibit less shifting of data entries (e.g., reading and writing).

[0022] However, the predicted address location (e.g., an off-center address location) can be compared to at least one address threshold to ensure that the predicted address location in the data structure is sufficiently close to the center address location. In other words, the predicted address location can be compared to at least one address threshold to ensure that the predicted address location in the data structure is sufficiently far from both the first address location and the last address location. For clarity, the embodiments herein will be described generally with respect to comparing a predicted address location to at least one address threshold; however, it will be understood that embodiments in which equivalent address locations can be compared to at least one address threshold are considered within the scope of this disclosure. In any case, the embodiments described herein employing at least one address threshold can reduce computational resource overhead (e.g., power, time, bandwidth, etc.) and thus enable an overall performance enhancement of the computing system employing such a methodology.

[0023] Furthermore, in some embodiments, the predicted address location may be based on multiple predicted address locations in multiple complete data structures. For example, the predicted address location may be based on a predicted location in a first data structure and a predicted address location in at least one additional data structure. For example, when the predicted locations are the same (e.g., equidistant from a first address location in the corresponding data structure), the predicted address location may be located at the predicted location in the first data structure and the predicted address location in at least one additional data structure. Alternatively, when the predicted address locations are different (e.g., located at different corresponding distances from the first address location in the corresponding data structure), the predicted address location may be located at the midpoint between several predicted address locations. In any case, such embodiments that employ multiple data structures to predict the predicted address location can enhance the accuracy of the predicted address location and thereby achieve further enhancements in the overall performance of the computing system employing such a methodology.

[0024] Furthermore, in some embodiments, the predicted address location can be changed based on the number and / or direction of subsequent shifts experienced by a first data entry previously written to and shifted within a complete data structure. That is, determining the number and / or direction of any previous shifts of a data entry within the complete data structure allows for further enhancement of the predicted address location. For example, the basic predicted address location (e.g., predicted based on data entries in at least one complete data structure) can be changed based on the number and / or direction of subsequent shifts from a first data entry in at least one complete data structure to different address locations in at least one complete data structure. For example, in response to determining that an earlier data entry (e.g., a first data entry) written to a corresponding address location in the corresponding complete data structure experiences a certain amount of subsequent shifts toward the first address location in the corresponding complete data structure, the basic predicted address location can be shifted toward the first address location in the data structure, and other possibilities as detailed herein. Such embodiments can enhance the accuracy of the predicted address location and thereby achieve further reductions in computational resource performance and further enhancements in the overall performance of computing systems employing such methodologies. In such embodiments, the predicted address may change based on the amount and / or direction of subsequent shifts and may subsequently be compared with at least one address threshold, as described herein.

[0025] For clarity, the embodiments described herein will generally pertain to predicting the address location for a first (initial) data entry to be written into a data structure. However, it will be understood that embodiments in which the address locations of at least one additional data entry (e.g., a second data entry, a third data entry, etc.) expected to be written into the data structure are considered within the scope of this disclosure. Predicting at least one additional address location (in addition to the first data entry) can further enhance the overall performance of computing systems employing such a methodology.

[0026] For clarity, the embodiments herein will be described generally with respect to predictive center allocation data structures for writing data into memory resources, but it will be understood that embodiments utilizing caching are considered within the scope of this disclosure. As will be described in more detail herein, a predictive center allocation data structure is a data structure and / or technique for writing data into a data structure, wherein a first data entry is written to an address location in the memory resource that is neither the first physical address of the memory resource (e.g., “zero address location”) nor the last physical address of the memory resource (e.g., the Nth address location, where N is the total number of address locations in the memory resource). In some embodiments, the first data entry may be written to an address location other than an address location substantially physically equidistant from the first physical address and the last physical address of the memory resource. That is, in some embodiments, the first data entry may be written to an address location other than an address location located in the middle of the physical address space of the memory resource.

[0027] As used herein, the term "substantially" means that the characteristic need not be absolute, but should be sufficiently close to achieve the advantages of the characteristic. For example, "substantially equidistant" is not limited to the situation where an address location substantially equidistant from the first physical address and the last physical address of the memory resource is not absolutely equidistant from the first physical address and the last physical address of the memory resource, but is equidistant from the first physical address and the last physical address of the memory resource within manufacturing constraints, operating conditions, etc., to achieve a characteristic of being "equidistant" from the first physical address and the last physical address of the memory resource. For example, if there are an even number of physical address locations in the memory resource, then a physical address location substantially equidistant from the first physical address and the last physical address of the memory resource may not be at the exact physical center of the physical address location, but can be substantially equidistant so that components of the device operate as if the characteristic were the same or equal. However, it should be further considered that, given the context of this disclosure, such characteristics may be completely identical or completely equal.

[0028] To maintain an ordered (ascending) data structure in memory resources, a second data entry can be written to an address in memory resources located between the first physical address and the address where the first data entry was written (if the second data entry has a smaller value than the first data entry), or the second data entry can be written to an address in memory resources located between the last physical address and the address where the first data entry was written (if the second data entry has a larger value than the first data entry). It will be understood that to maintain an ordered (descending) data structure in memory resources, a second data entry can be written to an address in memory resources located between the first physical address and the address where the first data entry was written (if the second data entry has a larger value than the first data entry), or the second data entry can be written to an address in memory resources located between the last physical address and the address where the first data entry was written (if the second data entry has a smaller value than the first data entry).

[0029] In other words, and as described in more detail herein, when a subsequent data entry has a smaller value than a previous entry, the subsequent data entry is written to an address closer to the first physical address in the memory device for an ordered ascending data structure. Conversely, when a subsequent data entry has a larger value than a previous entry, the subsequent data entry is written to an address closer to the last physical address in the memory device for an ordered ascending data structure. For an ordered descending data structure, when a subsequent data entry has a smaller value than a previous entry, the subsequent data entry is written to an address closer to the last physical address in the memory device, and when a subsequent data entry has a larger value than a previous entry, the subsequent data entry is written to an address closer to the first physical address in the memory device.

[0030] As described in more detail herein, as data entries populate the data structure, each subsequent data entry can be written into the data structure at an address location based on the relative value of each data entry with respect to the value of a previously written data entry. This allows for a reduction in the number of shift operations (shifts) required to maintain the data structure in an ordered state compared to the conventional methods described above. Therefore, by writing data entries into the predictive central allocation data structure according to this disclosure, the performance (e.g., overall functionality) of the computing system in which embodiments of this disclosure operate can be improved compared to the conventional methods described above, at least because the number of expensive shift operations required to maintain data entries in the data structure is reduced compared to such methods.

[0031] Figure 1This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0032] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0033] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, server, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing device.

[0034] In other embodiments, the computing system 100 may be deployed on or otherwise included in a computing device, such as a desktop computer, laptop computer, server, web server, mobile computing device, vehicle (e.g., airplane, drone, train, car, or other means of transport), Internet of Things (IoT) capable device, embedded computer (e.g., a computer included in a vehicle, industrial equipment, or networked business device), or such computing device including memory and processing power. As used herein, the term "mobile computing device" generally refers to a handheld computing device having a slate or tablet form factor. Generally, a slate form factor may include a display screen between approximately 3 inches and 5.2 inches (diagonally measured), while a tablet form factor may include a display screen between approximately 5.2 inches and 7 inches (diagonally measured). However, instances of "mobile computing device" are not limited thereto, and in some embodiments, "mobile computing device" may refer to IoT devices and other types of edge computing devices.

[0035] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including, for example, electrical, optical, magnetic, and similar connections.

[0036] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110.

[0037] Host system 120 includes processing unit 121. Processing unit 121 may be a central processing unit (CPU) configured to execute an operating system. In some embodiments, processing unit 121 includes a complex instruction set computer architecture, such as x86 or other architectures suitable for use as the CPU of host system 120.

[0038] Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR) interfaces, Low Power Double Data Rate (LPDDR) interfaces, or any other interfaces. The physical host interface may be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 For example, memory subsystem 110 is described. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or a combination of communication connections.

[0039] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0040] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-situ write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0041] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. One type of memory cell (e.g., a single-level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells (e.g., SLC, MLC, TLC, QLC, PLC, or any combination thereof). In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, where a page may refer to a logical unit of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0042] Although non-volatile memory components (such as three-dimensional cross-point arrays of non-volatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND)) are described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0043] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0044] The memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0045] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0046] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and translate them into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations associated with memory device 130, such as wear leveling operations, discard item collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.). The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions for accessing memory devices 130 and / or 140 and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0047] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140.

[0048] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0049] Memory subsystem 110 may include predictive central allocation circuitry system 113. Although not shown in the accompanying drawings for the sake of clarity... Figure 1While illustrated herein, the predictive central allocation circuitry system 113 may include various circuitry systems to facilitate the aspects of this disclosure described herein. In some embodiments, according to this disclosure, the predictive central allocation circuitry system 113 may include dedicated circuitry systems in the form of ASICs, FPGAs, state machines, hardware processing devices, and / or other logic circuitry systems that allow the predictive central allocation circuitry system 113 to coordinate and / or perform operations to write data (e.g., data entries) to a predictive central allocation data structure of memory resources.

[0050] In some embodiments, the memory subsystem controller 115 includes at least a portion of the predictive central allocation circuitry system 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the predictive central allocation circuitry system 113 is part of the host system 110, an application, or an operating system. The predictive central allocation circuitry system 113 may reside on the memory subsystem 110 and / or the memory subsystem controller 115. As used herein, the term "resides on" means something is physically located on a particular component. For example, "resides on memory subsystem 110" means that the hardware circuitry system including the predictive central allocation circuitry system 113 is physically located on the memory subsystem 110. The term "resides on" may be used interchangeably with other terms herein, such as "deployed on" or "located on".

[0051] Figure 2 This describes an example memory subsystem 210 according to some embodiments of the present disclosure. An example system, which may be referred to as a "device" in alternative embodiments, includes a memory subsystem controller 215 and a predictive central allocation circuitry system 213 (referred to as a "control circuitry system 213" in alternative embodiments), which may be related to the present description. Figure 1 The memory subsystem controller 115 and predictive central allocation circuitry system 113 described herein are similar. The memory subsystem 210 further includes memory resources 216, which include multiple address locations 218-1, 218-2, 218-3, 218-4 to 218-N (hereinafter collectively referred to as "address locations 218") that together form the address space 235 of the memory resources 216.

[0052] Address location 218 may be a physical address location corresponding to one or more memory cells of memory resource 216. In some embodiments, 256 (256) address locations 218, 512 (512) address locations 218, etc., may be provided within memory resource 216. However, it will be understood that memory resource 216 may contain more or less these enumerated numbers of address locations based on the size, memory density, and / or architecture of memory resource 216 and / or memory subsystem 210, and other factors. In some embodiments, address location 218 may be logically defined, for example, by the means described herein. Figure 1 The host system 120 described herein is used for addressing.

[0053] Address location 218 can be configured to store data entries in data structure 232 (e.g., a predictive central allocation data structure). As used herein, "data structure" refers to a specific format for organizing and / or storing data, which may or may not be organized into rows and columns. Instances of data structures include arrays, files, records, tables, trees, linked lists, hash tables, etc. In some embodiments, data structure 232 may be configured to store a logical-to-physical (L2P) mapping table, but embodiments are not limited to this particular instance.

[0054] ADDRESS LOCATION_0 218-1 may be referred to herein as the “first physical address”, “zero address location”, or “lowest physical location” of memory resource 216. ADDRESS LOCATION_N 218-N may be referred to herein as the “last physical address”, “Nth address location”, or “highest physical location” of memory resource 216.

[0055] like Figure 2 As shown, memory resource 216 resides on memory subsystem 210. Figure 2 In this example, memory resource 216 may reside on memory subsystem 210 and not on any other component of the memory subsystem. The embodiments are not limited thereto, and although not explicitly illustrated for the sake of clarity in the accompanying drawings, memory resource 216 may reside (or partially reside) on any component of memory subsystem 210. For example, memory subsystem 210 may reside on... Figure 1 The memory subsystem controller 215, control circuit system 213, memory device 130, local media controller 135 and / or memory device 140 described herein.

[0056] In a non-limiting example, the device (e.g., memory subsystem 210) includes memory resource 216 and processing means (e.g., predictive central allocation circuitry system 213). The device may be a system-on-a-chip, but embodiments are not limited thereto. As described herein, in some embodiments, the processing means may write a first data entry to address location 218 of memory resource 216, where address location 218 is neither a first physical address 218-1 nor the last physical address 218-N of memory resource 216. For example, in some embodiments, the processing means is configured to write the first data entry to address location 218 of memory resource 216 by writing the data entry to address location 218 of memory resource 216 other than address locations substantially physically equidistant from the first physical address 218-1 and the last physical address 218-N of memory resource 216, where address location 218 is neither the first physical address 218-1 nor the last physical address 218-N of memory resource 216. Furthermore, in some embodiments, the processing apparatus is configured to write the first data entry to an address location 218 of the memory resource 216 that is equivalent to a modified predicted address location (determined based on a comparison of the predicted address location with at least one address threshold), as described herein. Thus, compared to other methods (e.g., methods that write the first data entry to address locations substantially physically equidistant from the first physical address 218-1 and the last physical address 218-N of the memory resource 216 in all examples, and / or methods that do not employ at least one address threshold), the method described herein achieves reduced power consumption and / or improved performance.

[0057] As described in more detail herein, memory resource 216 may contain N address locations, and (1) a first physical address 218-1 is the zeroth address location of memory resource 216 and the last address location 218-N is the Nth address location of memory resource 216, or (2) a first physical address 218-1 is the Nth address location of memory resource 216 and the last address location 218-N is the zeroth address location of memory resource 216. Additionally, in some embodiments, the memory resource is configured to store data entries in data structure 232. In some embodiments, the data entries include logical-to-physical mapping entries associated with the memory subsystem 210 in which memory resource 216 is deployed.

[0058] In another non-limiting instance, non-transitory computer-readable storage media (e.g., those described herein) Figure 6 The machine-readable storage medium 624 described herein includes a processing device (e.g., the one described herein) Figure 6When the predictive central distribution circuit system 213 and / or processing device 602 described herein are executed, the processing device causes the processing device to perform the following instructions (e.g., as described herein). Figure 6 Instruction 626 described herein: for a data entry, determine a predicted address location in a first data structure; compare the predicted address location with at least one address threshold; based on the comparison between the predicted address location and at least one address threshold, change the predicted address location to a modified predicted address location; determine an equivalent address location in a second data structure that is equivalent to the modified predicted address location; and write the data entry to the equivalent address location in the second data structure.

[0059] Next, the processing device may (1) write the second data entry to the memory resource to address location 218, which is physically located between the first physical address of the memory resource and the address where the first data entry was written, when the second data entry has a value smaller than the value of the first data entry, or (2) write the second data entry to the memory resource 216 to address location 218, which is physically located between the address where the first data entry was written and the last physical address of the memory resource 216, when the second data entry has a value larger than the value of the first data entry.

[0060] Continuing with this non-limiting example, the instructions may be further executed by the processing device to determine that the second data entry has a smaller value than the first data entry and (1) when the third data entry has a smaller value than the second data entry, write the third data entry to memory resource 216, to address location 218, which is physically located between the first physical address of memory resource 216 and the address location where the second data entry is written; (2) when the third data entry has a larger value than the second data entry but smaller than the first data entry, write the third data entry to memory resource 216, to address location 218, which is physically located between the address location where the first data entry is written and the address location where the second data entry is written; or (3) when the third data entry has a larger value than the first data entry, write the third data entry to memory resource 216, to address location 218, which is physically located between the last physical address of memory resource 216 and the address location where the first data entry is written.

[0061] The embodiments are not limited thereto. In some embodiments, the instructions may be further executed by the processing device to determine that the second data entry has a value greater than the value of the first data entry and (1) when the third data entry has a value smaller than the second data entry and larger than the first data entry, write the third data entry to memory resource 216 to address location 218, which is physically located between the address location where the first data entry is written and the address location where the second data entry is written; (2) when the third data entry has a value greater than the second data entry, write the third data entry to memory resource 216 to address location 218, which is physically located between the address location where the second data entry is written and the last physical address of memory resource 216; or (3) when the third entry has a value smaller than the first data entry, write the third data entry to memory resource 216 to address location 218, which is physically located between the address location where the first data entry is written and the first physical address location.

[0062] As described in more detail herein, the instructions may be further executed by the processing device to cause the processing device to write a first data entry, a second data entry, or one or more subsequent data entries, or any combination thereof, into the memory resource in data structure 232. For example, the instructions may be further executed by the processing device to cause the processing device, as part of an operation for writing logical-physical mapping information associated with the memory subsystem 210 in which memory resource 216 is deployed, to write a first data entry, a second data entry, or one or more subsequent data entries, or any combination thereof, into the memory resource.

[0063] In some embodiments, the instructions may be further executed by the processing device to cause the processing device to receive a command for locating a specific data entry that has been written to memory resource 216. In such instances, the specific data entry may be one of a first data entry, a second data entry, or a subsequently written data entry stored in memory resource 216. The instructions may be further executed by the processing device to cause the processing device to perform a search (e.g., a binary search) involving each data entry that has been written to memory resource 216 to locate the specific data entry.

[0064] Figures 3A to 3C Examples of a series of operations that can be performed using instances of the complete data structure 331 and the predictive center allocation data structure 332 according to some embodiments of this disclosure are described.

[0065] Figure 3AAn example of a complete data structure 331 is described below. As used herein, a complete data structure refers to a data structure having data entries written to each of the address locations in the data structure. For example, a series of data entries (e.g., a vector) [4,7,35,43,47,49,50,257,287] has previously been written to each of the address locations 317-1, 317-2, 317-3, 317-4, 317-5, 317-6, 317-7, 317-8 to 317-9 of memory resource 315. Therefore, memory resource 315 contains a complete data structure 331. The complete data structure 331 can be written using the same allocation mechanism or different allocation mechanisms. For example, the complete data structure 331 can be a predictive center allocation data structure (as described herein) written using a predictive center allocation mechanism, or it can be a different type of data structure (e.g., a center allocation data structure), etc.

[0066] Memory resource 315 can be used in this article Figure 2 The memory resource 216 described herein is similar to that described in this paper, and address location 317 is also similar to that described in this paper. Figure 2 The address location 218 described herein is similar. Therefore, address location 317-1 can be referred to as the "first physical address," "zeroth address location," or "lowest physical location" of memory resource 315, while address location 317-9 can be referred to as the "last physical address," "Nth address location," or "highest physical location" of memory resource 315. Figure 3A In the examples described herein, address location 317-5 indicates that in the address space (e.g., in this article in...). Figure 2 The address location at the center of the address space 235 described herein is, and may be referred to as, the address location of the memory device that is substantially physically equidistant from the first physical address 317-1 and the last physical address 317-9 of the memory resource 315. Address locations 317-2, 317-3, 317-4, 317-6, 317-7, and 317-8 may be referred to as off-center address locations, which are not the first physical address 317-1 of the memory resource 315, not the last physical address 317-9 of the memory resource 315, and not the center physical address 317-5 of the memory resource 315.

[0067] exist Figure 3A In this process, a first operation is performed to determine the predicted address location. For example, the predicted address location can be determined for the first data entry

[51] in a series 322 (e.g., a vector) [51, 9, 2, 12, 3, etc.] of data entries to be written to, for example, a new data structure of memory resource 316, namely address locations 318-1, 318-2, 318-3, 318-4, 318-5, 318-6, 318-7, 318-8 to 318-9. Figure 3A As explained, the first data entry

[51] can be determined as being located in memory resource 315 between the first data entry

[50] written to the first physical address (317-7) and the second data entry

[257] written to the second physical address (317-8). Therefore, the predicted address location can be determined as the address location in the second data structure that is equivalent to the first physical address [317-7] of the first data structure to which the first existing data entry

[50] is written or the second physical address [317-8] of the first data structure to which the second existing data entry

[257] is written. If an additional physical address is available in memory resource 315, then the first data entry

[51] can be written to the additional physical address and one or more data entries (e.g., the first data entry

[50] and the second data entry

[257] ) can be shifted accordingly within memory resource 315.

[0068] Therefore, the physical address at which the first data entry

[51] will be written to memory resource 315 can be determined as a predicted address location in memory resource 316. For example, the predicted address location can be determined as an address location in the second data structure that is equivalent to the first physical address of the first data structure to which the first existing data entry (e.g., the immediately preceding data entry) is written or the second physical address of the first data structure to which the second existing data entry (e.g., the immediately preceding data entry) is written. For example, the predicted address location may be equivalent to the first address location when the value of the data entry is equal to the value of the data entry in the first address location, or the predicted address location may be equivalent to the second address location when the value of the data entry is equal to the value of the data entry in the second address location. Alternatively, the data value associated with the predicted address location may be between the value of the data entry written to the first address location in the first data structure and the value of the data entry written to the second address location in the first data structure, and the equivalent address of the first address location or the second address location may be determined as described herein.

[0069] It should be noted that in some embodiments, the predicted address location may be an off-center address location (e.g., physical address (317-7)). As mentioned, making the predicted address location an off-center physical address location can reduce computational resource overhead (e.g., power, time, bandwidth, etc.) and thus enhance the overall performance of the computing system employing such a methodology.

[0070] In some embodiments, the eccentric address location may be the eccentric address location closest to the center address location (317-5) of the first and second address locations (e.g., when the data value to be written is a value between the data value written to the first address location and the data value written to the second address location). For example, continuing the above example, if the predicted address location is located between the physical address location (317-7) (the first address location) and the physical address location (317-8) (the second address location), then the physical address location (317-7) can be determined as the predicted address location because the physical address location (317-7) is closer to the center address location (317-5). Therefore, the predicted address location may be an eccentric address location relatively close to the center address (317-5), thereby providing the benefits associated with the center address allocation and also taking into account previously written data (e.g., written to an existing full address structure) to mitigate any subsequent shifts of the initial data entry for the equivalent address in another data address structure.

[0071] The first operation may further include comparing the predicted address location with at least one address threshold and changing the predicted address location to a modified predicted address location based on the comparison. For example, as Figure 3A As explained, memory resources may include multiple address thresholds, including a first address threshold 335-1 (e.g., an upper address threshold) and a second address threshold 335-2 (e.g., a lower address threshold). Figure 3A As explained, in some embodiments, the first address threshold 335-1 and the second address threshold 335-2 may be equidistant from the central physical address location 317-5. However, in some embodiments, the first address threshold 335-1 and the second address threshold 335-2 may be at different distances from the central physical address 317-5.

[0072] For example, address thresholds (or "restrictions") for the first address threshold 335-1 and the second address threshold 335-2 may be associated with a given physical address and / or a pointer associated with the given physical address. For example, a processing device (e.g., as described herein) Figure 1 and Figure 2 The predictive center distribution circuit system 113 / 213 described herein and / or the system described herein are as follows: Figure 1 The processor 117 described herein may associate an address threshold with a given physical address and / or a pointer associated with a given physical address, and may store or otherwise maintain the association in a memory resource such as the memory resource described herein.

[0073] Address thresholds can define permissible physical addresses for predicted address locations (e.g., address locations 317-4 and 317-6, such as...). Figure 3A(As explained in the text). For example, the lower address threshold 335-2 can define an allowable address region containing addresses 317-4, 317-5, 317-6, 317-7, 317-8, and 317-9 (excluding addresses 317-1, 317-2, and 317-3), while the upper address threshold 335-1 can define an allowable address region containing addresses 317-1, 317-2, 317-3, 317-4, 317-5, and 317-6 (excluding addresses 317-7, 317-8, and 317-9). Therefore, when the lower address threshold 335-2 and the upper address threshold 335-1 are used together, they can define an allowable address region containing addresses 317-4, 317-5, and 317-6 (excluding addresses 317-1 to 317-3 and 317-7 to 317-9). In some embodiments, the upper address threshold 335-1 and / or the lower address threshold 335-2 may be shifted, for example, to be closer to or less close to the center address 317-5. That is, the number and / or location of addresses included in the permissible address area can be changed by shifting the positions of the upper address threshold 335-1 and / or the lower address threshold 335-2.

[0074] In some embodiments, address thresholds (e.g., upper address threshold 335-1 and lower address threshold 335-2) may define a permissible physical address range between address thresholds. Although Figure 3A This specifies the number of three physical addresses (317-4, 317-5, and 317-6) included in the allowable address area, but any number of physical address locations less than the total number of physical addresses in memory resource 315 may be included in the allowable address area.

[0075] In some embodiments, the permissible address region may include one or more off-center addresses relatively close to the center address 317-5. For example, in some embodiments, the permissible address region may include physical addresses 317-3, 317-4, 317-6 and / or 317-7, or it may include physical addresses 317-2, 317-3, 317-4, 317-6, 317-7, and 317-8. In some embodiments, the permissible address region may only include off-center physical addresses and not the center address 317-5.

[0076] However, in some embodiments, the permissible address range may contain at least the center address (317-5). For example, in some embodiments, the permissible address range may contain only the center address (317-5), or it may contain the center address (317-5) and at least one additional address (e.g., 317-4 and / or 317-6, etc.). For example, the permissible address range may contain physical addresses (317-5 and 317-6), (317-4 and 317-5), (317-4, 317-5 and 317-6), (317-3, 317-4, 317-5, 317-6 and 317-7), or (317-2, 317-3, 317-4, 317-5, 317-6, 317-7 and 317-8), and other possibilities.

[0077] The predicted address location (317-7) can be compared with at least one address threshold and / or a permissible address range. For example, it can be determined that the predicted address location (317-7) exceeds the upper address threshold 335-1 or the predicted address threshold is less than the lower address threshold 335-2. Therefore, the predicted address location can be determined to be farther from the center address than at least one of the address thresholds (e.g., the first address threshold 335-1). As mentioned, making the predicted address location too far from the center address and / or too close to the first physical address 317-1 or the last physical address 317-9 can increase the number of subsequent shifts of the data entry and thus degrade performance. Therefore, in response to determining that the predicted address location is outside the permissible address area (e.g., not one of physical addresses 317-4 or 317-6), the predicted address location (e.g., 317-7) can be changed to a modified predicted address location (317-6) that is within the permissible address area and is the address closest to the predicted address location (the initial predicted address location at 317-7) within the permissible address area. Thus, in some embodiments, the modified predicted address location may be closer to the center address location than the predicted address location. In this way, the method described herein can demonstrate various benefits of skewed data allocation and also avoid writing initial entries to physical locations that are too close to the first address location 317-1 or the last address location 317-9. As detailed herein, address thresholds can define one or more permissible physical address areas (e.g., extending from an upper address threshold to a lower address threshold) in which initial data entries (or subsequent data entries) can be written. For example, in some embodiments, the address threshold may define two or more permissible address regions, each containing a corresponding physical address to which an initial data entry (or subsequent data entry) can be written. For example, a first permissible address region may contain physical addresses located between the center address and the first physical address but excluding both the center address and the first physical address, while a second address region may contain physical addresses located between the center address and the last physical address but excluding either the center address or the last physical address, and other possibilities.

[0078] First operation (and combination) Figures 3B to 3C The described subsequent operations can be performed by a processing device (e.g., the one described herein). Figure 1 and Figure 2 The predictive center allocation circuit system 113 / 213 described herein, and / or the system described herein in Figure 1 The processor 117 described herein controls the process. A first data entry (51) may be written to an address location (e.g., address location 317-6) of the memory resource 315, which is not the first physical address of the memory resource 315 (e.g., address location 317-1), not the last physical address of the memory resource 315 (e.g., address location 317-9), and not the center physical address of the memory resource (e.g., address location 317-5).

[0079] exist Figures 3B to 3C In the non-limiting example described herein, data entry series 322 (e.g., vector) [51,9,2,12,3] are written to address locations 318-1, 318-2, 318-3, 318-4, 318-5, 318-6, 318-7, 318-8 to 318-9 of memory resource 316. Figures 3A to 3C In the non-limiting example described herein, data entries are organized in a complete data structure 331 and in a predictive center allocation data structure 332, such that data entries are sorted in ascending order from the data entry with the lowest value to the data entry with the highest value (e.g., data entries with a lower value than previously written data entries are written to an address location closer to the first physical address, while data entries with a higher value than previously written data entries are typically written to an address location closer to the last physical address). However, it will be understood that embodiments in which data entries are organized in the predictive center allocation data structure 332 such that data entries are sorted in descending order from the data entry with the highest value to the data entry with the lowest value will be considered. It will be further understood that... Figures 3A to 3C The non-limiting examples shown are merely illustrative and provided to illustrate operations that can be performed using the predictive central allocation data structure of this disclosure. Therefore, the embodiments are not limited to... Figures 3A to 3C The specific non-restrictive examples described herein.

[0080] Memory resource 316 can be used in this paper Figure 2 The memory resource 216 described herein is similar to that described in this paper, and address location 318 is also similar to that described in this paper. Figure 2The address location 218 described herein is similar. Therefore, address location 318-1 can be referred to as the "first physical address," "zeroth address location," or "lowest physical location" of memory resource 316, while address location 318-9 can be referred to as the "last physical address," "Nth address location," or "highest physical location" of memory resource 316. Figures 3A to 3C In the examples described herein, address location 318-5 indicates that in the address space (e.g., in this article in...). Figure 2 The address location at the center of the address space 235 described herein, and may be referred to as the address location of the memory device that is substantially physically equidistant from the first physical address 318-1 and the last physical address 318-9 of the memory resource 316.

[0081] In some embodiments, the modified predicted address location may be further modified based on the amount, direction, or both of the shift of the first data entry written to the complete data structure. For example, the modified predicted address location may be further modified (e.g., 317-6) based on the amount, direction, or both of the shift of the first data entry written to memory resource 315 (the first data structure). If the first data entry written to memory resource 315 is subsequently shifted (e.g., shifted up, shifted down, etc.) in response to subsequent data entries being written to the memory resource, this may indicate that the modified predicted address location should be located elsewhere in memory resource 315. As mentioned, a reduction in the number of data shifts can improve performance, and therefore further modification of the modified predicted address location based on the amount, direction, or both of the shift of the first data entry written to the complete data structure can reduce the amount of data shifting in the new data structure to which the first data entry will be written. For example, a first data entry written to memory resource 315 that is subsequently shifted toward the last physical address in memory resource 315 (e.g., shifted one physical address at a time) may indicate that the predicted address location (e.g., from...) should be... Figure 3A The address 317-6 described herein is replaced with another address (e.g., 317-7) that is physically closer to the last physical address (e.g., 317-9) in memory resource 315, and thus mitigates any subsequent shifts of the first data entry once written to memory resource 316. In other words, the predicted address location (and therefore the equivalent address location) can be shifted in the same direction and by the same number of shifts as the first data value previously written to the complete data structure.

[0082] exist Figure 3BIn this process, an equivalent address can be determined and a second operation can be performed to write the first data entry (51) into the equivalent memory resource 316. Similar to the predicted address location in the complete data structure, the equivalent address location can be equidistant from the first address location, the last address location, and / or the center address location in the new data structure. For example, the modified predicted address location (317-6) in memory resource 315 can be equidistant from each of the first address location, the last address location, and the center address location in memory resource 315 by a first distance, which is the same as the second distance equidistant from each of the first address location, the last address location, and the center address location in memory resource 316. For example, the modified predicted address location (317-6) is located in memory resource 315 at a physical address location one physical address location lower than the center address (317-5), and the equivalent address location (318-6) is also located in memory resource 316 at a physical address location one physical address location lower than the center physical address (318-5).

[0083] Determining the predicted address location, determining the modified predicted address location, determining the equivalent address location, and the first operation (and, for example, combining...). Figures 3A to 3C The subsequent operations described herein (follow-up operations) can be performed by a processing device (e.g., the one described herein). Figure 1 and Figure 2 The predictive center allocation circuit system 113 / 213 described herein, and / or the system described herein in Figure 1 The processor 117 described herein controls the process. A first data entry (51) is written to an address location (e.g., address location 318-6) of the memory resource 316, which is neither the first physical address of the memory resource 316 (e.g., address location 318-1) nor the last physical address of the memory resource 316 (e.g., address location 318-9).

[0084] Figure 3C The explanation has been provided. Figure 3BThe data entry series 322 (e.g., vectors) [51, 9, 2, 12, 3, etc.] at address location 318 of memory resource 316 are written in various operations following the second operation described herein. For example, a third operation may be performed to write a second data entry (9) from series 322 to memory resource 316 at physical address location 318-5, the second data entry having a lower value than the first data entry (51). Similarly, each of the other data entries [51, 9, 2, 12, 3, 7, 298, 300, 297] may be written to a corresponding physical address location in memory resource 316. In some embodiments, subsequent operations may write data entries at a corresponding physical address location adjacent to the data entry written to the data structure. In other words, in some embodiments, the second entry may be written to an address location (e.g., address location 318-5) immediately adjacent to the address location where the first data entry was written (e.g., address location 318-6). However, in some embodiments, subsequent data entries may be written to a physical address location that is at least one physical address location away from the physical address location where the previous data entry was written.

[0085] Figure 3C This describes the memory resource 316 and the predictive central allocation data structure 332 at a point in time after the Yth operation has been performed to write the data entry to the memory resource 316 and the upper part (e.g., the address position above the address position where the first data entry was written) is full. Figure 3C As shown, the Y+1 operation is performed to write data entry (297) to memory resource 316. To write data entry (297) to memory resource 316 while maintaining the predictive central allocation data structure 332 in an ordered manner, a bulk shift operation involving data entries (300) and (298) is performed to shift data entry (300) from address location 318-8 to address location 318-9 and data entry (298) from address location 318-7 to 318-8. The process of shifting data entries to open address space for subsequent data entries having values ​​between the groups of data entries at sequential address locations written to memory resource 316 is referred to herein as a “bulk shift operation” or, for brevity, a “bulk shift.” This bulk shift operation opens address unit 318-7 and, as... Figure 3C As shown, data entries (297) are written to address units 318-7, thereby maintaining the ordered nature of the predictive central allocation data structure 332.

[0086] Although not in Figures 3A to 3CAs explicitly shown, if a data entry has a value higher (or lower) than the largest (or smallest) data entry written to data structure 332, then the contents of data structure 332 can be shifted accordingly to free up address positions for writing the data entry. For example, if a subsequent data entry (e.g., a data entry with the value (1)) arrives with a value lower than any of the data entries in data structure 332, then the contents of data structure 332 can be shifted toward the last physical address 318-9 to allow data entry (1) to be written to data structure 332. It will be understood that a similar operation can be performed if a data entry with a value higher than any other data value in data structure 332 is received while writing data values ​​to the last physical location of data structure 332.

[0087] One of the main advantages of maintaining the ordered nature of the predictive center assignment data structure 332 is that it allows the use of binary search (also known as logarithmic search) to locate specific data entries within the predictive center assignment data structure 332. As will be understood, binary search is a technique in which the search interval used to search for a specific entry in a categorized (e.g., ordered) data structure is repeatedly divided into two halves. This technique allows for minimizing search queries in ordered data structures because the search interval typically converges quickly to locate the specific data entry.

[0088] Figure 4 Examples of memory resources 416 having multiple address locations 418-1 to 418-N according to some embodiments of this disclosure are described below. Memory resource 416 may be related to the memory resources described herein. Figure 2 and Figures 3A to 3C The memory resources 216 / 316 described herein are similar, and the address locations may be the same as those described herein. Figure 2 and Figures 3A to 3C The address locations described are similar to 218 / 318. Figure 4 The text describes an eccentric entry 422, a central entry 424, a lower entry 426, and an upper entry 428. Each of these entries corresponds to a data entry that has been written to memory resource 416 and has a corresponding pointer 423, 425, 427, and 429 associated with it.

[0089] The eccentric entry 422 may correspond to a first data entry written to memory resource 416, such as a data entry written to an address that is not the first physical address 418-1, not the last physical address 418-N, and not the address location of the center entry 424 (in this case, address location 418-6). A pointer 423 may be assigned to this address location to indicate the location in memory resource 416 where the eccentric data entry is written. In some embodiments, the equivalent address location may be, for example, where the data of eccentric entry 422 can be written to the eccentric address location in memory resource 416.

[0090] However, in some embodiments, the equivalent location may be another location where data is written, such as center entry 424, first physical address 418-1, or last physical address 418-N. For example, when the data value to be written to the data structure is less than or greater than any data value in the existing data structure (the existing complete data structure), the equivalent location may be determined as the default location, such as center entry 424, first physical address 418-1, or last physical address 418-N.

[0091] The center entry 424 may correspond to the first data entry written to memory resource 416, such as a data entry written to an address location equidistant from the first physical address 418-1 and the last physical address 418-N (in this case, address location 418-6). Pointer 425 may be assigned to this address location to indicate the position in memory resource 416 where the center data entry is written.

[0092] The next pointer 427 can be assigned to write the next entry 426 (e.g., for an ordered ascending data structure, e.g., Figure 2 The address location where the data structure 232, the complete data structure 331, and / or the predictive center allocation data structure 332 (as described herein) has the lowest value and is therefore physically closest to the first physical address 418-1. Similarly, the up pointer 429 can be assigned to the address location where the up entry 428 (e.g., for an ordered ascending data structure, the data entry with the highest value and therefore physically closest to the last physical address 418-N) is written.

[0093] Pointers 423, 425, 427, and 429 can be dynamically moved as memory resources are filled with data entries. For example, pointer 425 can be moved to align with center entry 424 (e.g., a data entry equidistant from lower entry 426 and upper entry 428), and lower pointer 427 and upper pointer 429 can be moved, for an ordered ascending data structure, to align with the data entry having the lowest value and the data entry having the highest value, respectively. It will be understood that, for an ordered descending data structure, lower pointer 427 and upper pointer 429 can be moved to align with the data entry having the lowest value and the data entry having the highest value, respectively.

[0094] Pointers 423, 425, 427, and 429 can be used in conjunction with determining the address location 418 in the data structure for writing data entries. For example, pointer 427 can be checked to determine whether the data entry to be written to memory resource 416 has a larger or smaller value than the data entry to be written to the address location associated with the next entry 426. If the value of the data entry to be written to memory resource 416 is smaller than the value of the data entry to be written to the address location associated with the next entry 426, then the data entry to be written to memory resource 416 can be written to an address location that is physically closer to a first physical address of said memory resource (for ordered ascending data structures), and pointer 427 can be moved to point to the newly written data entry.

[0095] Similarly, pointer 429 can be checked to determine whether the value of the data entry written to the address location associated with the previous entry 428 is larger or smaller than the value of the data entry written to the address location associated with the previous entry 428. If the value of the data entry to be written to memory resource 416 is greater than the value of the data entry written to the address location associated with the previous entry 428, then the data entry to be written to memory resource 416 can be written to an address location that is physically closer to the last physical address of the memory resource (for ordered ascending data structures), and pointer 429 can be moved to point to the newly written data entry.

[0096] Figure 5 This is a flowchart corresponding to a method 550 for predictive central allocation of data structures according to some embodiments of the present disclosure. Method 550 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing means) or a combination thereof. In some embodiments, method 550 is performed by… Figure 1 Predictive center distribution circuit system 113 and / or Figure 2 The predictive central allocation circuitry system 213 performs this operation. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other processes are possible.

[0097] At operation 552, method 550 includes determining a predicted address location in a data structure for a data entry. The predicted address location may be determined based on at least one complete data structure (previously populated data structure), as described herein. As mentioned, the predicted address location may be neither the first physical address nor the last physical address of the data structure. In some embodiments, the predicted address location may be neither the first physical address nor the last physical address of the data structure, nor an address location substantially equidistant from both the first and last physical locations of the data structure. Therefore, the predicted address location may be an off-center address location (e.g., as...). Figure 4 The eccentric address location described in the document is 418-7.

[0098] In some embodiments, the predicted address location may be based on an individual complete data structure, such as Figure 3A The data structure 331. The predicted address location determined based on individual complete data structures can be easily determined with relatively little latency, little computational burden and / or little power consumption.

[0099] In some embodiments, a complete data structure may be the data structure that precedes the second data structure (the most recently populated individual data structure) among a plurality of complete data structures. In other words, a complete data structure may be the data structure that is most recently populated and immediately precedes it.

[0100] However, in some embodiments, the data structure may be a different individual data structure contained within multiple filled data structures, such as the oldest data structure among multiple filled data structures (the first filled data structure). For example, the predicted address location in the first data structure (the complete first data structure) may be determined as an address location between the first physical address of the first data structure to which the first existing data entry is written and the second physical address of the second data structure to which the second existing data entry is written. That is, the data value to be written to the data structure (the new unfilled data structure) (the new data value) may be compared with the data value written in the complete data structure to determine where the data value will be written in the complete data structure if another open address location is available in the complete data structure. Therefore, the address location to be written in the complete data structure if another address location is available in the complete data structure may be determined as the predicted address location.

[0101] However, in some embodiments, predicted address locations can be determined based on multiple complete (previously populated) data structures. Predicted address locations determined based on multiple complete data structures can have enhanced accuracy and thus enable further enhancements in subsequent power consumption reduction and / or computational burden reduction. As mentioned herein, the data structures may have the same number of address locations and / or the corresponding data stored therein may be configured in the same manner (e.g., in ascending, descending, etc.). In some embodiments, each of the complete data structures may have the same number of address locations and the corresponding data stored therein may be configured in the same manner. Therefore, the average of the predicted address locations in the multiple complete data structures can be easily determined. Similarly, a new data structure (to which a first data entry will be written) may have the same number of address locations and the corresponding data stored therein may be configured in the same manner as the complete data structures. For example, a new data structure (to which a first data entry will be written) may have the same number of address locations and the corresponding data stored therein may be configured in the same manner as the complete data structures.

[0102] In some embodiments, the predicted address position may be equal to the average address position, which is the average of corresponding address positions in two or more complete data structures, each having the same number of address positions but storing different data. For example, a first predicted address position may be determined for a first complete data structure (having a total of "N" address positions). For example, the first data structure (first complete data structure) may contain N address positions, where the first physical address is the zeroth address position of the first data structure and the last address position is the Nth address position of the first data structure, or where the first physical address is the Nth address position of the first data structure and the last address position is the zeroth address position of the first data structure. Similarly, a second predicted address position may be determined for an additional complete data structure (which also has a total of "N" address positions but contains data different from the first data structure). For example, a second data structure (second complete data structure) may contain N address positions, where the first physical address is the zeroth address position of the second data structure and the last address position is the Nth address position of the second data structure, or where the first physical address is the Nth address position of the second data structure and the last address position is the zeroth address position of the second data structure. In such embodiments, the number of N address locations in the first data structure may be equal to the number of N address locations in the second data structure.

[0103] As mentioned, a first predicted address location and a second predicted address location can be determined. In some embodiments, the first predicted address location, the second predicted address location, or both may be eccentric address locations. The average of the predicted address locations in the first complete data structure and the predicted address locations in the additional complete data structure can be determined as the average address location. The average address may be equidistant from the predicted address locations in the first complete data structure and the additional complete data structure. The average address location may be specified as the predicted address location.

[0104] At operation 554, method 550 includes comparing the predicted address location with at least one address threshold, as described herein. For example, the predicted address location may be compared with an upper address threshold, a lower address threshold, or both, as described herein. However, other mechanisms for determining the predicted address location are possible. For example, the predicted address location may be a weighted average of predicted address locations in a first complete data structure and predicted address locations in additional complete data structures, RMS, etc. Therefore, in some embodiments, the predicted address location in a given data structure may be assigned a weight different from the weight assigned to predicted address locations in different data structures. For example, in some embodiments, the predicted location may be based on the predicted location in a first data structure and the predicted location in at least one additional data structure, the first data structure being the most recently filled, immediately preceding data structure. In such examples, the weight associated with the predicted location in the first data structure may be greater than the weight associated with the predicted address location in at least one additional data structure (e.g., which contains data entries older than those in the first data structure). Therefore, the allocation of more recent data entries in the first data structure can be given higher priority (weight) than older data entries, resulting in a more accurate prediction of the location of the predicted address.

[0105] At operation 556, method 550 includes changing the predicted address location to a modified predicted address location based on the comparison at 554, as described herein. For example, the predicted address location may be changed to a modified predicted address location that is less than an upper address threshold and greater than a lower address threshold. For example, the predicted address location may be changed to an eccentric physical address in the data structure that is less than an upper address threshold of the data structure and greater than a lower address threshold of the data structure, as described herein.

[0106] At operation 558, method 550 includes determining an equivalent address location in a data structure that is equivalent to the modified predicted address location. For example, an equivalent address location in a second data structure that is equivalent to the modified predicted address location in a first data structure may be determined, as per [reference to...]. Figure 3B As described.

[0107] In some embodiments, the distance (number of physical address locations) of the equivalent address location from the first physical address in the second data structure is the same as the distance of the modified predicted address from the first physical address in the first data structure. Similarly, the distance (number of physical addresses) of the equivalent address location from the last physical address in the second data structure may be the same as the distance of the modified predicted address from the last physical address in the first data structure. The distance of the equivalent address location from the center physical address in the second data structure may be the same as the distance of the modified predicted address from the center physical address in the first data structure.

[0108] Similar to predicted and modified predicted address locations, the equivalent address location may be neither the first physical address nor the last physical address of the data structure. In some embodiments, the equivalent address location may be neither the first physical address nor the last physical address of the data structure, nor an address location substantially equidistant from the first and last physical locations of the data structure. Therefore, the equivalent address location may be an off-center address location.

[0109] At operation 560, method 550 includes writing data entries to a data structure (e.g., in this paper...). Figure 2 The data structure 232 and / or described herein Figures 3B to 3C The equivalent address location in the predictive center allocation data structure 332 described herein is neither a memory resource (e.g., in this paper) Figure 2 , 3A The first data entry is written to a physical location that is neither the lowest physical location (e.g., the first physical address) of the memory resource 216 / 316 / 416 as described in 3C and 4, nor the highest physical location (e.g., the last physical address) of the memory resource, nor the center physical address location. As discussed above, writing the first data entry to an address location that is neither the lowest physical location, nor the highest physical location, nor the center address location of the memory resource may include an address location where the first data entry is written to the memory resource as an off-center address location.

[0110] Figure 6 This is a block diagram of an example computer system in which embodiments of this disclosure may operate. For example, Figure 6 An example machine illustrating computer system 600 may be executed within said machine, providing a set of instructions for causing said machine to perform any one or more methodologies discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1 (Operation of the predictive central distribution circuitry system 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0111] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying the action to be taken by that machine. Furthermore, while a single machine is described, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any of the methodologies discussed herein.

[0112] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0113] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing combinations of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as an Application-Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communicating via network 620.

[0114] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which one or more sets of instructions 626 or software embodying any of the methodologies or functions described herein are stored. The instructions 626 may also reside wholly or at least partially within the main memory 604 and / or the processing device 602 during execution by the computer system 600, which also constitute the machine-readable storage medium. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0115] In one embodiment, instruction 626 includes instructions for implementing a circuit system corresponding to a predictive central allocation system (e.g., Figure 1 The predictive central distribution circuit system 113) contains functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be understood as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be understood as any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more methodologies of this disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0116] Some portions of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, considered as a self-consistent sequence of operations that leads to a desired result. These operations are those that require physical manipulation of physical quantities. Typically, though not required, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for general reasons, it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0117] However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device, which manipulates and converts data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0118] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0119] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods. The architectures of many such systems will appear as described below. Furthermore, this disclosure does not refer to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0120] This disclosure may be provided as a computer program product or software that may include machine-readable media having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0121] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. An apparatus for predictive central allocation of data structures, comprising: A memory resource configured to store data entries in a data structure containing a first data structure and a second data structure; and Processing device coupled to the memory resource, wherein the processing device is configured to: For the first data entry, determine the predicted address location in the first data structure; The predicted address location is compared with at least one address threshold; The predicted address location is changed to a modified predicted address location based on the comparison between the predicted address location and the at least one address threshold. Determine the equivalent address location in the second data structure that is equivalent to the modified predicted address location; Write the first data entry to the equivalent address location in the second data structure; Receive a command to locate a specific data entry that has been written to the second data structure, wherein the specific data entry is one of the first data entry, the second data entry, or a subsequently written data entry written to the second data structure; and Perform a search involving each data entry that has been written into the second data structure to locate the specific data entry.

2. The device according to claim 1, wherein the first data entry includes the first data entry of the second data structure.

3. The device according to claim 1, wherein the modified predicted address location is an address location other than the address location in the first data structure that is equidistant from the first physical address of the first data structure and the last physical address location of the first data structure.

4. The device according to claim 1, wherein the first data structure is a complete data structure.

5. The device according to claim 1, wherein the first data structure and the second data structure are each configured as an ordered ascending data structure or as an ordered descending data structure.

6. The device of claim 1, wherein the predicted address location is a physical location in the first data structure, the modified predicted address location is a different physical location in the first data structure, and the equivalent address location is a physical location in the second data structure that is equivalent to the physical location of the modified predicted address location in the first data structure.

7. The device according to claim 1, wherein the first data structure is directly preceding the second data structure among a plurality of data structures.

8. The device according to claim 1, wherein: The first data structure includes N address locations, and The first physical address is the zeroth address position of the first data structure and the last address position is the Nth address position of the first data structure, or The first physical address is the Nth address position of the first data structure, and the last address position is the zeroth address position of the first data structure; and The second data structure includes N address locations, and The first physical address is the zeroth address position of the second data structure and the last address position is the Nth address position of the second data structure, or The first physical address is the Nth address position of the second data structure and the last address position is the zeroth address position of the second data structure, wherein the number of the N address positions in the first data structure is equal to the number of the N address positions in the second data structure.

9. The device of claim 1, wherein the data entry includes a logical-to-physical mapping entry associated with a memory subsystem in which the memory resources are deployed.

10. The device of claim 1, wherein the altered predicted address position in the first data structure is further modified based on the number, direction, or both of shift operations involving the first data entry written to the first data structure.

11. A method for predictive center allocation data structures, comprising: Determine the predicted physical address location in the first data structure for each data entry; The predicted physical address location is compared with at least one address threshold; Change the predicted physical address location to the modified predicted address location; Determine the equivalent address location in the second data structure that is equivalent to the modified predicted address location in the first data structure; Write the first data entry to the equivalent address location in the second data structure; Receive a command to locate a specific data entry that has been written to the second data structure, wherein the specific data entry is one of the first data entry, the second data entry, or a subsequently written data entry written to the second data structure; and Perform a search involving each data entry that has been written into the second data structure to locate the specific data entry.

12. The method of claim 11, wherein the equivalent address location further includes address locations in the second data structure other than address locations equidistant from the lowest physical location and the highest physical location of the second data structure.

13. The method of claim 11, further comprising determining the predicted physical address location based on the predicted location in the first data structure and the predicted address location in at least one additional data structure.

14. The method of claim 13, wherein the first data structure is the most recently filled, immediately preceding data structure, and wherein the weight associated with the predicted position in the first data structure is greater than the weight associated with the predicted address position in the at least one additional data structure.

15. The method of claim 11, wherein the at least one address threshold further comprises a plurality of address thresholds, the plurality of address thresholds comprising: The upper address threshold is located between the highest physical location of the first data structure and the center physical location of the first data structure; and The lower address threshold is located between the lowest physical location of the first data structure and the central physical location of the first data structure.

16. A non-transitory computer-readable storage medium comprising, when executed by a processing means, instructions that cause the processing means to perform the following: For a first data entry, a predicted address position in a first data structure is determined, wherein the predicted address position is at an off-center physical address in the first data structure, and wherein the first data structure is a complete data structure. The predicted address position is compared with the upper address threshold and the lower address threshold; The predicted address location is changed to a modified predicted address location within the permissible physical address range extending from the upper address threshold to the lower address threshold in response to the following: It is determined that the predicted address location exceeds the upper address threshold; or It is determined that the predicted address position is less than the next address threshold; Determine the equivalent address location in the second data structure that is equivalent to the modified predicted address location in the first data structure; Write the first data entry to the equivalent address location in the second data structure; Receive a command to locate a specific data entry that has been written to the second data structure, wherein the specific data entry is one of the first data entry, the second data entry, or a subsequently written data entry written to the second data structure; and Perform a search involving each data entry that has been written into the second data structure to locate the specific data entry.

17. The non-transitory computer-readable storage medium of claim 16, wherein the predicted address location in the first data structure is at an off-center physical address that is neither the first physical address, nor the last physical address, nor the center physical address in the first data structure.

18. The non-transitory computer-readable storage medium of claim 17, wherein the equivalent address location in the second data structure is at the off-center physical address in the second data structure that is neither the first physical address, nor the last physical address, nor the center physical address.

19. The non-transitory computer-readable storage medium of claim 16, further comprising, when executed by the processing means, causing the processing means to perform the following instructions: as part of an operation for writing logical-physical mapping information associated with a memory subsystem in which memory resources containing the second data structure are deployed, writing the first data entry, the second data entry, or one or more subsequent data entries, or any combination thereof, into the second data structure.

Images