A BP neural network circuit and a multiply-accumulate circuit therein

Abstract

The application discloses a BP neural network circuit and a multiply-accumulate circuit in the same. The multiply-accumulate circuit comprises a multiplier, a first adder, a logic operator and an accumulator. The multiplier is used for multiplying two data to be processed in a current period to obtain a first calculation result. The first adder is used for adding the first calculation result and a multiply-accumulate result of a previous period stored in the accumulator to obtain a second calculation result. The logic operator is used for outputting the second calculation result when a first control signal is valid. The accumulator is connected with the logic operator and is used for caching the second calculation result as the multiply-accumulate result of the current period until all multiply-accumulate tasks are completed. The circuit has simple structure, small area and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a BP neural network circuit and the multiply-accumulate circuit therein. Background Technology

[0002] Backpropagation (BP) neural networks have important applications in petroleum engineering and oilfield information technology, oilfield analysis instruments, and transformer fault diagnosis. The MAC multiply-accumulate module in BP neural networks has a significant impact on the data analysis speed and accuracy of oilfield analysis instruments and transformer fault diagnosis.

[0003] In existing technologies, the common approach for the MAC multiply-accumulate module in a BP neural network is to use a multi-stage pipeline to increase computational throughput by utilizing a larger circuit area. However, for applications with lower performance requirements but higher area constraints, using a multi-stage pipeline to improve performance is ineffective. Therefore, how to implement the MAC multiply-accumulate module in a BP neural network with a smaller circuit area to improve the speed and accuracy of fault diagnosis and data analysis in oilfield information systems and oilfield analytical instruments has become an urgent problem to be solved in this field. Summary of the Invention

[0004] The purpose of this invention is to provide a solution that further reduces the area of ​​the MAC multiply-accumulate circuit structure in a BP neural network while still fulfilling the MAC multiply-accumulate function.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a multiply-accumulate circuit for a BP neural network, comprising: a multiplier for multiplying two data to be processed in the current cycle to obtain a first calculation result; an adder for adding the first calculation result to the multiply-accumulate result of the previous cycle stored in the accumulator to obtain a second calculation result; a logic arithmetic unit for performing a logic operation on the second calculation result and a first control signal for controlling the state of the multiply-accumulate circuit, such that the second calculation result is output when the first control signal is valid; and an accumulator connected to the logic arithmetic unit for caching the second calculation result as the multiply-accumulate result of the current cycle until all multiply-accumulate tasks are completed.

[0006] Preferably, the number of bits in the multiplier is the sum of the number of bits in the first data to be processed and the number of bits in the second data to be processed.

[0007] Preferably, the number of bits in the adder is greater than the sum of the number of bits in the first data to be processed and the number of bits in the second data to be processed; the number of bits in the accumulator is greater than the sum of the number of bits in the first data to be processed and the number of bits in the second data to be processed.

[0008] Preferably, the multiplier is further configured to pad the high-order bits of the first calculation result with zeros before feeding it into the adder.

[0009] Preferably, the logic arithmetic unit employs multiple AND operators, wherein the first input terminal of each AND operator is connected to the output terminal of each bit addition unit of the adder, and the second input terminal of each AND operator is connected to a logic signal line used to transmit the first control signal.

[0010] Preferably, the logic unit is further configured to clear the accumulator when the first control signal is invalid.

[0011] Preferably, when the current period is the first period, the first control signal is invalid; when the current period is the second period or a period sequence after the second period, the first control signal is valid.

[0012] Preferably, the accumulator includes a plurality of D flip-flops, each D flip-flop being connected to the AND operator.

[0013] Preferably, the corresponding multiplication and accumulation result for each cycle is represented by the following expression:

[0014]

[0015] Where i represents a periodic sequence, a i b represents the first data to be processed in the i-th cycle. i This represents the second data to be processed in the i-th cycle, and k represents the total number of multiply-accumulate operations required for the current multiply-accumulate task.

[0016] On the other hand, embodiments of the present invention also provide a BP neural network circuit, wherein the BP neural network analog circuit includes the multiply-accumulate circuit as described above.

[0017] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

[0018] This invention proposes a BP neural network circuit and its multiply-accumulate circuit. The circuit structure of this invention is simple, has a small area, and low power consumption; it can perform one multiply-accumulate operation per cycle, and the result of the MAC multiply-accumulate operation in the BP neural network can be obtained in k+1 clock cycles.

[0019] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0021] Figure 1 This is a schematic diagram of the overall structure of the multiply-accumulate circuit for a BP neural network according to an embodiment of this application.

[0022] Figure 2 This is a schematic diagram of the specific structure of the multiply-accumulate circuit for a BP neural network according to an embodiment of this application. Detailed Implementation

[0023] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples, so that the process of how the present invention uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that, as long as there is no conflict, the various embodiments and features in the various embodiments of the present invention can be combined with each other, and the resulting technical solutions are all within the protection scope of the present invention.

[0024] Furthermore, the steps illustrated in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in a different order than that shown here.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0026] Backpropagation (BP) neural networks have important applications in petroleum engineering and oilfield information technology, oilfield analysis instruments, and transformer fault diagnosis. The MAC multiply-accumulate module in BP neural networks has a significant impact on the data analysis speed and accuracy of oilfield analysis instruments and transformer fault diagnosis.

[0027] In existing technologies, the common approach for the MAC multiply-accumulate module in a BP neural network is to use a multi-stage pipeline to increase computational throughput by utilizing a larger circuit area. However, for applications with lower performance requirements but higher area constraints, using a multi-stage pipeline to improve performance is ineffective. Therefore, how to implement the MAC multiply-accumulate module in a BP neural network with a smaller circuit area to improve the speed and accuracy of fault diagnosis and data analysis in oilfield information systems and oilfield analytical instruments has become an urgent problem to be solved in this field.

[0028] To address the aforementioned technical problems, this application proposes a BP neural network circuit and its multiply-accumulate circuit. This invention uses only one multiplier, a set of adders, a set of AND gates, and a set of u-bit accumulators, featuring a simple circuit structure, small area, and low power consumption. Each cycle can perform one multiply-accumulate operation, and the result of the MAC multiply-accumulate operation in the BP neural network can be obtained in k+1 clock cycles.

[0029] Figure 1 This is a schematic diagram of the overall structure of the multiply-accumulate circuit for a BP neural network according to an embodiment of this application. The following refers to... Figure 1 The overall structure of the (MAC) multiply-accumulate circuit described in the embodiments of the present invention will be explained. For example... Figure 1 As shown, the MAC multiply-accumulate circuit described in this embodiment of the invention includes: a multiplier, an adder, a logic unit, and an accumulator.

[0030] The multiplier performs a multiplication operation on two data points to be processed in the current cycle to obtain a first calculation result. An adder is connected to the multiplier. The adder adds the first calculation result to the multiply-accumulate result stored in the accumulator from the previous cycle to obtain a second calculation result. A logic unit is connected to the adder and performs a logic operation on the current second calculation result and a first control signal used to control the state of the multiply-accumulate circuit, so that the second calculation result is output when the first control signal is valid. The accumulator is connected to the logic unit. The accumulator caches the second calculation result obtained from the logic unit as the multiply-accumulate result for the current cycle until all multiply-accumulate tasks are completed. The multiply-accumulate task refers to the multiply-accumulate operations involved in the MAC multiply-accumulate module of the BP neural network across multiple cycles.

[0031] Furthermore, the number of bits in the multiplier is the sum of the number of bits in the first data to be processed and the number of bits in the second data to be processed. In this embodiment of the invention, the multiplier is an n+m bit multiplier. Here, n represents the number of bits in the first data to be processed, a, and m represents the number of bits in the second data to be processed, b. The n+m bit multiplier is used to perform multiplication, and the result of the multiplication is denoted as the first calculation result mul. Specifically, the two inputs of the multiplier are an n-bit first data to be processed, a, and an m-bit second data to be processed, b, both of arbitrary values. The output of the multiplier is an m+n bit first calculation result mul.

[0032] It should be noted that the structure of the multiplier in this embodiment of the invention can be any general multiplier structure, wherein the output of the multiplier is an m+n bit mul.

[0033] Furthermore, the number of bits in the adder is greater than the sum of the number of bits in the first data to be processed and the number of bits in the second data to be processed. In this embodiment of the invention, the bit width of the adder is u bits, where u > m + n. The first input of the adder is the first calculation result mul, and the other input of the adder is the u-bit multiplication-accumulation result data Q stored in the accumulator in the previous cycle. Moreover, the output of the u-bit adder is the result of the addition process; that is, the output of the adder is the result of the multiplication-accumulation operation, denoted as the second calculation result mac. Finally, the second calculation result mac is fed into the input of the accumulator.

[0034] The multiplier described in this embodiment of the invention is further used to pad the high-order bits of the first calculation result with zeros before sending it to one input of the adder. Specifically, the multiplier pads the high-order bits of mul to the u-bit, and then sends the first calculation result at the u-bit to one input of the adder.

[0035] In this embodiment of the invention, the logic arithmetic unit is implemented using an AND gate. The two inputs of the AND gate are the second calculation result (accumulation result) mac from the adder output and the first control signal (sel signal). The first control signal is a logic signal. Thus, the AND gate performs decision logic control on the output of the second calculation result by operating on the result of the operation between the second calculation result and the first logic control signal. The first control signal is used to characterize the real-time state of the entire multiply-accumulate circuit. When the first control signal is 0, it indicates initialization control of the entire multiply-accumulate circuit; when the first control signal is 1, it indicates that the multiply-accumulate circuit is subjected to multiply-accumulate calculations according to a preset cycle, so that the multiply-accumulate result calculated in each cycle is cached in the accumulator.

[0036] Specifically, the logic unit is also used to clear the accumulator by outputting zero data through a bitwise AND operation when the first control signal is invalid. In one embodiment, the first control signal is invalid when the current period is the first period. In another embodiment, the first control signal is valid when the current period is the second period or a period sequence following the second period. In this case, the second calculation result is directly output through a bitwise AND operation and sent directly to the accumulator.

[0037] Finally, the first input of the accumulator is connected to the output of the logic unit, the second input of the accumulator is the clock signal clk, and the output of the accumulator is connected to the input of the adder. In this embodiment of the invention, the number of bits in the accumulator (i.e., a u-bit accumulator) is greater than the sum of the number of bits in the first data to be processed and the number of bits in the second data to be processed. Therefore, the accumulator is used to cache the second calculation result obtained in each cycle as the multiplication-accumulation result of the current cycle, thus waiting for the arrival of the next clock cycle and storing the second calculation result data mac, to await the next multiplication-accumulation operation. The following expression represents the corresponding multiplication-accumulation result obtained in each cycle:

[0038]

[0039] Where i represents a periodic sequence, a i b represents the first data to be processed in the i-th cycle. i Let represent the second data to be processed in the i-th cycle, and k represent the total number of multiply-accumulate operations required for the current multiply-accumulate task. It can be seen that the multiply-accumulate circuit can perform one multiply-accumulate operation per cycle, and after k+1 cycles, the final multiply-accumulate result can be obtained.

[0040] Figure 2 This is a schematic diagram of the specific structure of the multiply-accumulate circuit for a BP neural network according to an embodiment of this application. Figure 2 As shown, u one-bit adders (FAs) receive the first calculation result mul of u bits and the accumulated result of the multiplication of u bits in the previous cycle, and output the second calculation result mac of u bits after performing the addition calculation.

[0041] Furthermore, the logic unit described in this embodiment of the invention is implemented using multiple AND gates. The first input of each AND gate is connected to the output of each one-bit addition unit of the adder, and the second input of each AND gate is connected to a logic signal line used to transmit the first control signal.

[0042] Furthermore, the accumulator described in this embodiment of the invention includes multiple D flip-flops. Each D flip-flop is connected to the output of each AND gate arithmetic unit.

[0043] In this invention, each cycle of the multiply-accumulate circuit can perform a multiply-accumulate operation. When the circuit is running, the multiply-accumulate result Q stored in the accumulator is first initialized to all zeros. Specifically, in the first cycle, the logic value of sel is set to 0, at which point the accumulator is cleared; in the second to the (k+1)th cycles, sel is set to 1. At this time, in each cycle, the multiplier input data a is calculated according to the above expression (1). i and data b i The result mul is obtained, and the data mul is added to the multiply-accumulate result of the previous cycle stored in the accumulator to obtain the multiply-accumulate result mac of the current cycle. At this time, the output of the AND gate sel=1 is the data mac. Finally, the data mac is stored in the accumulator, waiting for the next multiply-accumulate operation. After the (k+1)th cycle, all k products have been accumulated, and the result in the accumulator is the calculation result of equation (1).

[0044] On the other hand, based on the above-described multiply-accumulate circuit, embodiments of the present invention also provide a BP neural network circuit (e.g., a BP neural network chip). The BP neural network analog circuit includes the multiply-accumulate circuit as described above.

[0045] This invention discloses a BP neural network circuit and its multiply-accumulate circuit. The circuit structure of this invention is simple, has a small area, and low power consumption; it can perform one multiply-accumulate operation per cycle, and the result of the MAC multiply-accumulate operation in the BP neural network can be obtained in k+1 clock cycles.

[0046] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0047] In the description of this invention, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0048] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0049] It should be understood that the embodiments disclosed herein are not limited to the specific structures, processing steps, or materials disclosed herein, but should be extended to equivalent substitutions of these features as understood by those skilled in the art. It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.

[0050] The phrase "an embodiment" or "an embodiment" used in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Therefore, the phrase "an embodiment" or "an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment.

[0051] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A multiply-accumulate circuit for a BP neural network, characterized in that, include: A multiplier is used to multiply two data points to be processed in the current cycle to obtain the first calculation result; An adder is used to add the first calculation result to the multiply-accumulate result of the previous cycle stored in the accumulator to obtain the second calculation result; A logic arithmetic unit is used to perform a logic operation on the second calculation result and a first control signal for controlling the state of the multiply-accumulate circuit, so that the second calculation result is output when the first control signal is valid; An accumulator, connected to the logic unit, is used to cache the second calculation result as the multiply-accumulate result for the current cycle until all multiply-accumulate tasks are completed. The logic arithmetic unit employs multiple AND operators, wherein the first input terminal of each AND operator is connected to the output terminal of each bit addition unit of the adder, and the second input terminal of each AND operator is connected to a logic signal line used to transmit the first control signal. The logic unit is further configured to clear the accumulator when the first control signal is invalid, wherein the first control signal is invalid when the current period is the first period, and is valid when the current period is the second period or in a period sequence following the second period. The accumulator includes multiple flip-flops, each flip-flop being connected to the AND operator.

2. The multiply-accumulate circuit according to claim 1, characterized in that, The number of bits in the multiplier is the sum of the number of bits in the first data to be processed and the number of bits in the second data to be processed.

3. The multiply-accumulate circuit according to claim 2, characterized in that, The number of bits in the adder is greater than the sum of the number of bits in the first data to be processed and the number of bits in the second data to be processed; The accumulator has more bits than the sum of the number of bits in the first data to be processed and the number of bits in the second data to be processed.

4. The multiply-accumulate circuit according to claim 3, characterized in that, The multiplier is also used to pad the high-order bits of the first calculation result with zeros before feeding it into the adder.

5. The multiply-accumulate circuit according to claim 1, characterized in that, The accumulator includes multiple D flip-flops, each of which is connected to the AND operator.

6. The multiply-accumulate circuit according to any one of claims 1 to 5, characterized in that, The following expression represents the result of multiplication and accumulation for each cycle: in, i A sequence representing a periodicity. Indicates the first i The first data to be processed in each cycle Indicates the first i The second batch of data to be processed in the current cycle k This indicates the total number of multiply-accumulate operations required for the current multiply-accumulate task.

7. A BP neural network circuit, characterized in that, The BP neural network simulation circuit includes the multiply-accumulate circuit as described in any one of claims 1 to 6.

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