Regulator circuit for flyback power converter

Abstract

A voltage regulator for a flyback power converter. The voltage regulator is used to convert an input voltage to an output voltage, which includes first and second upper bridge switches, first and second lower bridge switches, and a control terminal. The control terminal is used to generate a reference voltage or to determine a forced bypass mode. During a buck mode and a boost mode, the output voltage is determined according to the reference voltage. When the input voltage is higher than a first threshold, the voltage regulator operates in the buck mode. When the input voltage is lower than a second threshold, the voltage regulator operates in the boost mode. When the input voltage is lower than the first threshold and higher than the second threshold, the voltage regulator operates in a bypass mode. When a voltage of the control terminal is lower than a third threshold, the voltage regulator operates in the forced bypass mode.

Description

Technical Field

[0001] This invention relates to a voltage regulator circuit, and more particularly to a voltage regulator circuit used in a flyback power converter, characterized by high efficiency and low standby power over a wide voltage range. Background Technology

[0002] U.S. Patent 7,268,525, “Buck-Boost Converter,” discloses a related prior art. Another prior art, U.S. Patent 9,385,606, “Automatic Buck / Boost Mode Selection System for DC-DC Converters,” discloses a converter that can operate in buck, boost, or bypass modes.

[0003] Recent developments have highlighted the need for power supplies capable of operating over a wide input voltage range while consuming minimal power in standby mode to conserve energy. One example is the USB-PD Type-C with EPR (Extended Power Range), which offers a programmable output voltage range from 5V to 48V (up to 240W) to meet the needs of a wide range of applications, including charging batteries for mobile phones, laptops, power tools, and robots. The system must consume minimal power during 5V no-load operation. Therefore, the USB-PD EPR power adapter and its control circuitry must operate efficiently over a wide voltage range with low standby power consumption. This invention aims to provide a voltage regulator circuit that meets these standards. Summary of the Invention

[0004] In one viewpoint, the present invention provides a voltage regulator circuit for converting an input voltage into an output voltage, comprising: a first upper bridge switch coupled to the input voltage and coupled to an inductor via a first switching node; a first lower bridge switch coupled to the first upper bridge switch and coupled to the inductor via the first switching node; a second upper bridge switch coupled to the output voltage and coupled to the inductor via a second switching node; a second lower bridge switch coupled to the second upper bridge switch and coupled to the inductor via the second switching node; and a control terminal for generating... The regulator circuit generates a reference voltage or determines a forced bypass mode, wherein the output voltage is determined according to the reference voltage during a buck mode and a boost mode; wherein the regulator circuit operates in the buck mode when the input voltage is higher than a first threshold; wherein the regulator circuit operates in the boost mode when the input voltage is lower than a second threshold; wherein the regulator circuit operates in a bypass mode when the input voltage is lower than the first threshold and higher than the second threshold; and wherein the regulator circuit operates in the forced bypass mode when the voltage at the control terminal is lower than a third threshold.

[0005] In a preferred embodiment, the voltage regulator circuit further includes a current source coupled to the control terminal; wherein the current source is applied to a resistor connected to the control terminal to determine the voltage level of the reference voltage.

[0006] In a preferred embodiment, the reference voltage is used to generate the first threshold and the second threshold.

[0007] In a preferred embodiment, the level of the first threshold is higher than the level of the second threshold, and the level of the second threshold is higher than the level of the third threshold.

[0008] In a preferred embodiment, when the input voltage is below the first threshold, the forced bypass mode is enabled by pulling the voltage at the control terminal to a low level.

[0009] In a preferred embodiment, the voltage regulator circuit further includes a first hysteresis comparator and a second hysteresis comparator; wherein the first hysteresis comparator is coupled to receive the input voltage and the first threshold to determine whether the voltage regulator circuit operates in the buck mode or the bypass mode; wherein the second hysteresis comparator is coupled to the input voltage and the second threshold to determine whether the voltage regulator circuit operates in the bypass mode or the boost mode when the input voltage is lower than the second threshold.

[0010] In a preferred embodiment, the voltage regulator circuit controls the switching operation with a constant on-time (COT); wherein in the buck mode, the on-time of the first upper bridge switch is reduced in response to the increase in the input voltage, and the first upper bridge switch has a minimum off-time.

[0011] In a preferred embodiment, in the boost mode, the voltage regulator circuit performs switching operations with a fixed on-time control, the on-time of the second lower bridge switch is reduced in response to the increase in the input voltage, and the second lower bridge switch has a minimum off-time.

[0012] In a preferred embodiment, the voltage regulator circuit operates in discontinuous current mode (DCM) in both the buck mode and the boost mode.

[0013] In a preferred embodiment, when the voltage regulator circuit operates in the buck mode, the first lower bridge switch turns off before the inductor is completely demagnetized.

[0014] In a preferred embodiment, when the voltage regulator circuit operates in the boost mode, the second upper bridge switch turns off before the inductor is completely demagnetized.

[0015] In a preferred embodiment, during the bypass mode operation, the first upper bridge switch and the second upper bridge switch are turned on, and the first lower bridge switch and the second lower bridge switch are not turned on.

[0016] In a preferred embodiment, the first upper bridge switch, the second upper bridge switch, the first lower bridge switch, and the second lower bridge switch are not turned on before the operating mode changes between the buck mode, the boost mode, and the bypass mode.

[0017] In a preferred embodiment, the voltage regulator circuit is used to provide a bias power supply to a conversion control circuit within a power supply device, wherein the power supply device is compatible with the USB-PD specification, or the voltage regulator circuit is used to convert an output power supply generated by a power supply device compatible with the USB-PD specification to provide the bias power supply to the conversion control circuit.

[0018] In a preferred embodiment, the power supply device compatible with the USB-PD specification includes a flyback converter.

[0019] In a preferred embodiment, the primary and secondary side controllers of the power supply device, which is compatible with the USB-PD specification, control the control terminal via an optocoupler.

[0020] In a preferred embodiment, one output power supply of the voltage regulator circuit is less than 1 watt.

[0021] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features and effects achieved by the present invention. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a preferred embodiment of the voltage regulator circuit according to the present invention.

[0023] Figure 2 Is it displayed corresponding to Figure 1 The block diagram of a preferred embodiment of the voltage regulator circuit shown indicates that the conversion control circuit and multiple switches are integrated into an integrated circuit.

[0024] Figure 3 This is a schematic diagram of a preferred embodiment of a reference signal generation circuit for generating a reference voltage, a first threshold, and a second threshold according to the present invention.

[0025] Figure 4 This is a characteristic curve of the output voltage relative to the input voltage and the control terminal according to a preferred embodiment of the present invention.

[0026] Figure 5This is a schematic diagram of a preferred embodiment of a mode determination circuit according to the present invention for determining operation in buck mode, boost mode, or bypass mode (and forced bypass mode).

[0027] Figure 6A This is a schematic diagram of a specific embodiment of a display time delay circuit according to the present invention.

[0028] Figure 6B This is according to the present invention, corresponding to Figure 6A The waveform diagram of the time delay circuit shown is shown.

[0029] Figure 7 This is a schematic diagram of a preferred embodiment of the modulation control circuit according to the present invention, wherein the modulation control circuit generates a switching signal for buck mode and boost mode operation.

[0030] Figure 8 This is a schematic diagram of a specific embodiment of the on-time control circuit according to the present invention.

[0031] Figure 9A This is according to the present invention, corresponding to Figure 8 The waveform diagram of the buck mode operation of the on-time control circuit is shown.

[0032] Figure 9B This is according to the present invention, corresponding to Figure 8 The waveform diagram of the boost mode operation of the on-time control circuit is shown.

[0033] Figure 10 This is a schematic diagram showing a preferred embodiment of a drive logic circuit for generating control signals according to the present invention.

[0034] Figure 11 and Figure 12 This is a schematic diagram illustrating a preferred embodiment of a power adapter utilizing a voltage regulator circuit according to the present invention.

[0035] Figure 13 This is a schematic diagram illustrating a preferred embodiment of a power supply device utilizing a voltage regulator circuit according to the present invention.

[0036] Explanation of symbols in the diagram

[0037] 10, 20, 30, 40, 128, 129, 253, 254: Switches

[0038] 15, 25, 35, 45: Body diodes

[0039] 16: Time generation circuit

[0040] 50: Inductor

[0041] 60, 70, 165, 255: Capacitors

[0042] 80, 125, 125, 126, 127, 131, 132, 210, 211: Resistors

[0043] 95: Optical Coupler

[0044] 100: Conversion control circuit

[0045] 101: First buffer circuit

[0046] 102: Second buffer circuit

[0047] 110, 111, 112, 118, 121, 122, 123, 124, 161, 251, 252: Current sources

[0048] 114, 115, 116, 117, 163: Transistors

[0049] 120: Buffer

[0050] 135: First Hysteresis Comparator

[0051] 136: Second Hysteresis Comparator

[0052] 137: Third Hysteresis Comparator

[0053] 139: With the door

[0054] 141: NOR gate

[0055] 142, 166, 168, 218, 275, 311, 312, 352, 354: AND gates

[0056] 143, 162, 167, 217, 264: Inverters

[0057] 145, 216, 265, 320, 321: OR gate

[0058] 151, 152, 153: Time Delay Circuits

[0059] 155: NOR gate

[0060] 200: Integrated Circuits

[0061] 215, 261, 262, 263: Comparators

[0062] 219: Flipper

[0063] 220, 230: Voltage Regulator Circuit

[0064] 250: On-time control circuit

[0065] 270: Pulse Generator

[0066] 351, 353: NAND gates

[0067] 600: Secondary side controller

[0068] 700: Power Factor Correction Converter

[0069] 710: Power Factor Correction Control Circuit

[0070] 900: Flyback Converter

[0071] 901, 902, 907, 910, 911, 912, 913: Voltage Regulator Circuits

[0072] 903: Reference signal generation circuit

[0073] 906: Time Delay Circuit

[0074] 907: Modulation control circuit

[0075] 910: Driver Logic Circuit

[0076] 911, 912, 913: Power supply equipment

[0077] BK: Buck signal

[0078] BT: Boost signal

[0079] CLR: Clear signal

[0080] COT: Fixed On-Time

[0081] DMG: Demagnetizing signal

[0082] FPT: Forced bypass control signal

[0083] GND: Ground pin

[0084] INHB: Inhibition signal

[0085] INHBx: Extended pulse signal

[0086] LX1: First Switching Node

[0087] LX2: Second Switching Node

[0088] n VBBI: Attenuation of input voltage

[0089] n VBBI_min: Minimum voltage

[0090] n VBBO: Attenuation of output voltage

[0091] n VBBO1: The first quasi-

[0092] n VBBO2: Second-in-command

[0093] P1, P2, P3, PLS, SPX: Pulse signals

[0094] PI: Pulse signal

[0095] PO: Output pin

[0096] PT: Forced bypass signal

[0097] RMP: Ramp Signal

[0098] S1, S2, S3, S4: Control signals

[0099] SIN: Input signal

[0100] SOFF, SON: Switching signals

[0101] SOUT: Output signal

[0102] SVL: Signal

[0103] Sx: Control terminal

[0104] Tdly: Delay time

[0105] TDMG: On-time / Demagnetization period

[0106] TINHB: During

[0107] Toff_min: Minimum non-conducting time

[0108] VA, VB, VH: Thresholds

[0109] VAC: Alternating Current Voltage

[0110] VAUX: Auxiliary voltage

[0111] VBBI, VIN: Input voltage

[0112] VBBO: Output voltage

[0113] VCC: Power supply

[0114] VDDPFC, VDDSC: Bias power supply

[0115] Vhys: Hysteresis voltage

[0116] VO: Supply voltage

[0117] VR, VR1: Reference voltage

[0118] VRL: Minimum Reference Voltage

[0119] VREC: Rectified Voltage

[0120] VSx: Control voltage

[0121] VSxSC: Control Voltage

[0122] VT1: First threshold

[0123] VT2: Second threshold

[0124] VT3: Third threshold Detailed Implementation

[0125] The accompanying drawings in this invention are all schematic and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

[0126] Figure 1 This is a schematic diagram of a preferred embodiment of a voltage regulator circuit according to the present invention. In one embodiment, the voltage regulator circuit 901 is used to convert the input voltage VBBI into the output voltage VBBO. The voltage regulator circuit 901 includes a first upper bridge switch (switch 10 with a body diode 15), a first lower bridge switch (switch 20 with a body diode 25), a second upper bridge switch (switch 30 with a body diode 35), a second lower bridge switch (switch 40 with a body diode 45), and a control terminal Sx.

[0127] In one embodiment, such as Figure 1 As shown, switch 10 is coupled to the input voltage VBBI and to inductor 50 via a first switching node LX1. Switch 20 is coupled to switch 10 and to inductor 50 via the first switching node LX1. Switch 30 is coupled to the output voltage VBBO and to inductor 50 via a second switching node LX2. Switch 40 is coupled to switch 30 and to inductor 50 via the second switching node LX2. In this embodiment, switches 10 and 30 are P-type MOSFETs, while switches 20 and 40 are N-type MOSFETs.

[0128] In one embodiment, the voltage regulator circuit 901 further includes a conversion control circuit 100, which generates a plurality of control signals S1, S2, S3, and S4 to control switches 10, 20, 30, and 40, respectively. The conversion control circuit 100 generates the control signals S1, S2, S3, and S4 based on the input voltage VBBI, the output voltage VBBO, and the control voltage VSx at the control terminal Sx. In one embodiment, the control voltage VSx is generated at the control terminal Sx.

[0129] In one embodiment, the control terminal Sx is used to generate a reference voltage VR or to determine a forced bypass mode, wherein the output voltage VBBO is determined based on the reference voltage VR during buck and boost modes. In one embodiment, the input voltage VBBI, the output voltage VBBO, and the control voltage VSx are used to determine whether the voltage regulator circuit 901 operates in buck, boost, bypass, or forced bypass mode, as will be described in detail later.

[0130] When the voltage regulator circuit 901 operates in buck mode, switches 10 and 20 are switched, switch 30 is on, and switch 40 is off. When the voltage regulator circuit 901 operates in boost mode, switches 30 and 40 are switched, switch 10 is on, and switch 20 is off. When the voltage regulator circuit 901 operates in bypass mode or forced bypass mode, switches 10 and 30 are on, and switches 20 and 40 are off. Capacitor 60 is connected to the input voltage VBBI, and capacitor 70 is connected to the output voltage VBBO.

[0131] Figure 2 Is it displayed corresponding to Figure 1 The block diagram of a preferred embodiment of the voltage regulator circuit shown includes a conversion control circuit and multiple switches integrated into an integrated circuit 200. In one embodiment, within the voltage regulator circuit 902, the integrated circuit 200 includes... Figure 1 The conversion control circuit 100 and switches 10-40 are shown. In this embodiment, the control terminal Sx corresponds to a control pin of the integrated circuit 200, the first switching node LX1 corresponds to a first switching pin of the integrated circuit 200, and the second switching node LX2 corresponds to a second switching pin of the integrated circuit 200. The integrated circuit 200 is connected to the input voltage VBBI, the output voltage VBBO, and the ground potential through the pulse signal PI, the output pin PO, and the ground pin GND, respectively.

[0132] In one embodiment, such as Figure 2 As shown, resistor 80 is connected to the control terminal Sx to generate a control voltage VSx, which in turn generates a reference voltage VR. The reference voltage VR is used to determine the voltage level of the output voltage VBBO. The reference voltage VR is further coupled to generate a first threshold voltage VT1 and a second threshold voltage VT2 to determine the operating mode, such as buck mode, boost mode, or bypass mode. During bypass mode, the switching circuits of the regulator circuit 902 (e.g., switches 10-40) are disabled to save power consumption.

[0133] Figure 3This is a schematic diagram of a preferred embodiment of a reference signal generation circuit 903 according to the present invention, used to generate a reference voltage VR, a first threshold VT1, and a second threshold VT2. The current generated by the current source 110 flows through resistor 80 (which, as shown in the diagram...). Figure 2 The voltage level (connected to the control terminal Sx) is used to determine the control voltage VSx, which is further used to determine the voltage level of the reference voltage VR1. In this embodiment, the voltage level of the reference voltage VR1 is close to the voltage level of the control voltage VSx.

[0134] In one embodiment, current source 111 and transistors 114 and 115 are configured as a first buffer circuit 101. A control terminal Sx is connected to the input of the first buffer circuit 101. Current source 112 and transistors 116 and 117 are configured as a second buffer circuit 102. A minimum reference voltage VRL is connected to the input of the second buffer circuit 102. The outputs of the first buffer circuit 101 and the second buffer circuit 102 are connected to current source 118 and buffer 120 in a wired-OR configuration to generate a reference voltage VR1 at the output of buffer 120. In this embodiment, if the control voltage VSx is pulled low to ground, the reference voltage VR1 can still remain at the voltage level of the minimum reference voltage VRL.

[0135] In one embodiment, such as Figure 3 As shown, current source 121 and resistor 126 are connected to reference voltage VR1 to generate a first threshold voltage VT1. Current source 123 and resistor 127 are connected to reference voltage VR1 to generate a second threshold voltage VT2. The first threshold voltage VT1 and the second threshold voltage VT2 can be expressed by the following equations.

[0136] VT1 = VR1 + (I121) R126)

[0137] VT2 = VR1 – (I123) R127)

[0138] In the above equations, I121 and I123 are the current values ​​corresponding to current sources 121 and 123, respectively. R126 and R127 are the resistance values ​​corresponding to resistors 126 and 127, respectively.

[0139] In one embodiment, resistor 125 is connected to a reference voltage VR1 to generate a reference voltage VR. A buck signal BK is used to control switch 128. A boost signal BT is used to control switch 129. During buck mode, the reference voltage VR is further biased by current source 122; conversely, during boost mode, the reference voltage VR is further biased by current source 124.

[0140] In buck mode, the reference voltage VR can be expressed as the following equation.

[0141] VR = VR1 + (I122) R125)

[0142] In boost mode, the reference voltage VR can be expressed as the following equation.

[0143] VR = VR1 - (I124) R125)

[0144] In bypass mode, the reference voltage VR can be expressed as the following equation.

[0145] VR = VR1

[0146] In the above equations, I122 and I124 are the current values ​​corresponding to current sources 122 and 124, respectively. R125 is the resistance value corresponding to resistor 125.

[0147] Figure 4 This is a characteristic curve of the output voltage relative to the input voltage and the control terminal (control voltage VSx) according to a preferred embodiment of the present invention. In one embodiment, an input attenuator is used to divide the input voltage VBBI to generate an attenuated input voltage n. VBBI, where "n" is a real number greater than 0. The output attenuator is used to divide the output voltage VBBO to produce an attenuated output voltage n. VBBO.

[0148] In one embodiment, such as Figure 4 As shown, when the input voltage n decreases When VBBI is higher than the first threshold VT1, the voltage regulator circuit (e.g., 901) operates in buck mode and attenuates the output voltage n. VBBO adjusted to the first quasi-n VBBO1. When the input voltage n decreases When VBBI is below the second threshold VT2, the voltage regulator circuit operates in boost mode and attenuates the output voltage n. VBBO adjusted to the second quasi-n VBBO2. When the input voltage n decreases When VBBI is below the first threshold VT1 and above the second threshold VT2, the voltage regulator circuit operates in bypass mode. When the control voltage VSx is below the third threshold VT3, the voltage regulator circuit operates in forced bypass mode.

[0149] It should be noted that in the above embodiments, the level of the first threshold VT1 is higher than the level of the second threshold VT2, and the level of the second threshold VT2 is higher than the level of the third threshold VT3. In one embodiment, when the input voltage n is attenuated... When VBBI is below the first threshold VT1, the forced bypass mode is enabled by pulling the control voltage VSx to a low level (below VT3).

[0150] In one embodiment, such as Figure 4 As shown, the hysteresis voltage Vhys is used to provide better noise immunity when the operation of the voltage regulator circuit changes from buck mode to bypass mode, or from boost mode to bypass mode. When the input voltage n is attenuated... VBBI is below the minimum voltage n When VBBI_min, the output voltage n decreases. VBBO is set to 0.

[0151] Figure 5 This is a schematic diagram illustrating a preferred embodiment of a mode determination circuit 905 according to the present invention, used to determine whether the operation is in buck mode, boost mode, bypass mode, or forced bypass mode. In one embodiment, resistors 131 and 132 are configured as the aforementioned input attenuators and are used to generate an attenuated input voltage n based on the input voltage VBBI. VBBI.

[0152] In one embodiment, the first hysteresis comparator 135 is used to receive the input voltage VBBI (in this embodiment, the attenuated input voltage n). VBBI and the first threshold VT1 are used to determine whether the voltage regulator circuit operates in buck mode or bypass mode. Specifically, when the input voltage n is attenuated... When VBBI is higher than the first threshold VT1, the first hysteresis comparator 135 is used to generate a buck signal BK through the time delay circuit (TD) 151.

[0153] The second hysteresis comparator 136 is used to receive the input voltage VBBI (in this embodiment, the attenuated input voltage n). The voltage regulator circuit operates in either bypass mode (VBBI) or boost mode (VT2) when the input voltage VBBI is lower than the second threshold VT2. Specifically, when the input voltage n decreases... When VBBI is lower than the second threshold VT2, the second hysteresis comparator 136 is used to generate a boost signal BT through the time delay circuit (TD) 152 and AND gate 142.

[0154] When the control voltage VSx is below the third threshold VT3 and the input voltage n is decayed When VBBI is below the first threshold VT1 (signal SVL is at a high level), the third hysteresis comparator 137 generates a forced bypass signal PT through a time delay circuit (TD) 153, an OR gate 145, and an AND gate 139. Therefore, when the input voltage n is attenuated... When VBBI is below the first threshold VT1, the forced bypass mode can be enabled by pulling the control voltage VSx to a low level. When the control voltage VSx is below the third threshold VT3, the output of the third hysteresis comparator 137 is further used to disable the boost signal BT through AND gate 142 and inverter 143. When the buck signal BK and the boost signal BT are disabled, the forced bypass signal PT is further enabled through OR gate 145 and NOR gate 141.

[0155] In one embodiment, such as Figure 5 As shown, each of the time delay circuits 151, 152, and 153 includes an input terminal IN and two output terminals OUT and PX. The time delay circuits 151, 152, and 153 are further used to generate pulse signals P1, P2, and P3 respectively during the delay time, which is the period from when their output transitions from a low level to a high level. An NOR gate 155 is used to receive pulse signals P1, P2, and P3 (high-level active signals) to generate a pulse signal PLS (low-level active signal).

[0156] Figure 6A A schematic diagram of a specific embodiment of the display time delay circuit 906 according to the present invention. Figure 6B The present invention shows that... Figure 6A The waveform diagram corresponding to the time delay circuit. The time delay circuit 906 corresponds to... Figure 5 Specific embodiments of time delay circuits 151, 152, and 153 are shown. In time delay circuit 906, input signal SIN, output signal SOUT, and pulse signal SPX are coupled to input terminal IN, output terminal OUT, and output terminal PX, respectively.

[0157] In one specific embodiment, current source 161, inverter 162, transistor 163, and capacitor 165 are configured as time generation circuit 16 to determine delay time Tdly. AND gate 166 is used to generate an output signal SOUT based on the input signal SIN and the output of time generation circuit 16. The output signal SOUT is connected to AND gate 168 via inverter 167. AND gate 168 is further used to receive the input signal SIN to generate a pulse signal SPX (e.g., in...). Figure 5 The pulse signals P1, P2, and P3 in the signal.

[0158] In the above embodiments, such as Figure 6BAs shown, when the input signal SIN becomes a high-order level, the pulse signal SPX becomes a high-order level; when the output signal SOUT becomes a high-order level, the pulse signal SPX becomes a low-order level. The pulse signal SPX is used to indicate the delay time Tdly.

[0159] Figure 7 A schematic diagram of a modulation control circuit 907, according to a preferred embodiment of the present invention, for generating a switching signal for buck mode and boost mode operation is shown. In one embodiment, the modulation control circuit 907 is used to generate a switching signal SON for fixed on-time (COT) control. The on-time of the switching signal SON is further adjusted by the voltage level of the input voltage VBBI. The on-time of the switching signal SON decreases as the input voltage VBBI increases.

[0160] In one embodiment, resistors 210 and 211 are configured as output attenuators and used to generate an attenuated output voltage n based on the output voltage VBBO. VBBO. The buck signal BK and the boost signal BT are connected to OR gate 216. The output of OR gate 216 is connected to AND gate 218. When the output voltage n is attenuated... When VBBO falls below the reference voltage VR during buck or boost mode operation, comparator 215 triggers flip-flop 219 to generate a switching signal SON. The switching signal SON determines the on-time of control signals S1 and S4 during buck and boost mode operation.

[0161] The switching signal SOFF is the inverted signal of the switching signal SON. After the switching signal SON is enabled, the on-time control circuit 250 determines the on-time of the switching signal SON and generates a clear signal CLR to reset the flip-flop 219, thereby disabling the switching signal SON. The on-time control circuit 250 generates a clear signal CLR, a demagnetizing signal DMG, and a suppressor signal INHB based on the switching signal SON, the switching signal SOFF, the input voltage VBBI, and the output voltage VBBO. The suppressor signal INHB is connected to an AND gate 218 via an inverter 217. When the switching signal SON is disabled, it cannot be enabled again until the suppressor signal INHB is disabled. Therefore, the period of the suppressor signal INHB determines the maximum switching frequency of the switching signal SON, enabling the voltage regulator circuit to operate in DCM (discontinuous conduction mode).

[0162] Figure 8A schematic diagram of a specific embodiment of the conduction time control circuit 250 is shown according to the present invention. In one embodiment, a switching signal SON controls switch 253 to turn on current source 251 to charge capacitor 255, and a switching signal SOFF controls switch 254 to turn on current source 252 to discharge capacitor 255, thereby generating a ramp signal RMP. When the voltage level of the ramp signal RMP is higher than the threshold VH, comparator 261 and inverter 264 generate a clear signal CLR. The current values ​​(I251) of current source 251 and (I252) of current source 252 can be expressed as follows.

[0163] I251 = I1 + [(VBBI – V1) / Rx]

[0164] I252 = I2 + [(VBBO – V2) / Rx]

[0165] In the above equations, I1 is the minimum charging current, I2 is the minimum discharging current, Rx is a constant value related to the inductance value of inductor 50, V1 is related to the minimum output voltage VBBO in buck mode operation, and V2 is related to the minimum input voltage VBBI in boost mode operation.

[0166] In one embodiment, if the voltage level of the ramp signal RMP is higher than the threshold VA, comparator 262 and OR gate 265 generate a suppression signal INHB. When the switching signal SOFF is enabled and capacitor 255 is discharged, and the voltage level of the ramp signal RMP is discharged to below the threshold VB, comparator 263 triggers pulse generator 270 to generate an extended pulse signal INHBx. The extended pulse signal INHBx is further connected to OR gate 265 to extend the suppression signal INHB. AND gate 275 is used to generate a demagnetizing signal DMG when the switching signal SOFF is enabled and the voltage level of the ramp signal RMP is higher than the thresholds VA and VB. The demagnetizing signal DMG indicates that the inductor 50 is still in the demagnetization period. The duration of the demagnetizing signal DMG is shorter than the complete demagnetization time of the inductor 50.

[0167] Figure 9A The present invention shows a corresponding Figure 8 The waveform diagram shows the buck mode operation of the on-time control circuit. In one embodiment, the voltage regulator circuit (e.g., 901) is configured for fixed on-time (COT) control. Figure 9A As shown, when the voltage regulator circuit operates in buck mode, the on-time of switch 10 (first upper bridge switch) decreases as the input voltage VBBI increases. In one embodiment, switch 10 (first upper bridge switch) has a minimum off-time Toff_min.

[0168] refer to Figure 8 and Figure 9A Specifically, when the voltage regulator circuit operates in buck mode, the level of control signal S3 remains low to turn on switch 30 (P-MOSFET), and the level of control signal S4 remains low to prevent switch 40 from turning on. Switching signal SON controls the charging of capacitor 255 and generates control signal S1, thereby magnetizing inductor 50 during the fixed on-time COT. Switching signal SOFF controls the discharging of capacitor 255. Switching signal SOFF and demagnetizing signal DMG (with on-time TDMG) generate control signal S2 to demagnetize inductor 50 during the demagnetizing period (TDMG). When ramp signal RMP discharges below threshold VB, extended pulse signal INHBx is generated to extend suppression signal INHB. When ramp signal RMP charges above threshold VA, TINHB indicates the period during which suppression signal INHB is enabled. At the end of extended pulse signal INHBx, suppression signal INHB is disabled.

[0169] Figure 9B The present invention shows a corresponding Figure 8 The waveform diagram shows the boost mode operation of the on-time control circuit. In one embodiment, the voltage regulator circuit (e.g., 901) is configured for fixed on-time (COT) control. In one embodiment, as... Figure 9B As shown, when the voltage regulator circuit operates in boost mode, the on-time of switch 40 (the second lower bridge switch) decreases as the input voltage VBBI increases. In one embodiment, switch 40 (the second lower bridge switch) has a minimum off-time Toff_min.

[0170] Reference Figure 8 and Figure 9B Specifically, when the voltage regulator circuit operates in boost mode, the level of control signal S1 remains low to turn on switch 10 (P-MOSFET), and the level of control signal S2 remains low to de-turn on switch 20. Switching signal SON is used to generate control signal S4 to magnetize inductor 50 during the fixed on-time (COT). Switching signal SOFF and demagnetizing signal DMG (with on-time TDMG) are used to generate control signal S3 to demagnetize inductor 50 during the demagnetizing period (TDMG). Further detailed operating procedures can be found in [reference needed]. Figure 9A The description.

[0171] It should be noted that, in one embodiment, the voltage regulator circuit operates in discontinuous conduction mode (DCM) in both buck and boost modes (e.g., Figure 9A and Figure 9B As shown). In one embodiment, as Figure 9AAs shown, when the voltage regulator circuit operates in buck mode, switch 20 (the first lower bridge switch controlled by control signal S2) is not turned on until inductor 50 is completely demagnetized. In one embodiment, as... Figure 9B As shown, when the voltage regulator circuit operates in boost mode, switch 30 (the second upper bridge switch controlled by control signal S3) is not turned on until inductor 50 is completely demagnetized.

[0172] Figure 10 A schematic diagram of a preferred embodiment of a drive logic circuit 910 for generating control signals is shown according to the present invention. In one embodiment, the drive logic circuit 910 is used to generate control signals S1, S2, S3, and S4. Specifically, the output of OR gate 320 is connected to NAND gate 351 to enable control signal S1 to operate in boost mode (i.e., enabled by BT) and bypass mode (i.e., enabled by PT). For buck mode, control signal S1 is generated according to switching signal SON via AND gate 311 (i.e., enabled by BK) and OR gate 320. AND gate 352 is used to generate control signal S2 according to switching signal SOFF and demagnetizing signal DMG to operate in buck mode (i.e., enabled by BK).

[0173] The output of OR gate 321 is connected to NAND gate 353 to enable control signal S3 for buck mode (i.e., enabled via BK) and bypass mode (i.e., enabled via PT) operation. For boost mode, control signal S3 is generated by AND gate 312 (i.e., enabled via BT) and OR gate 321 based on switching signal SOFF and demagnetizing signal DMG. AND gate 354 is used to generate control signal S4 for boost mode operation (i.e., enabled via BT) based on switching signal SON. In one embodiment, when pulse signal PLS is enabled, control signals S1, S2, S3, and S4 are not turned on. Therefore, switches 10, 20, 30, and 40 are not turned on before the operation mode transition.

[0174] Figure 11 and Figure 12 This is a schematic diagram illustrating a preferred embodiment of a power adapter 911, 912 utilizing a voltage regulator circuit according to the present invention. In one embodiment, as... Figure 11 As shown, the USP-PD compliant power supply device 911 (and 912) includes a power factor correction (PFC) converter 700, which converts the rectified voltage VREC to generate the input voltage VIN. The power supply device 911 (and 912) also includes a flyback converter 900, which converts the input voltage VIN to the supply voltage VO.

[0175] In one embodiment, such as Figure 11As shown, the voltage regulator circuit 230 provides a bias power supply VDDPFC to the power factor correction control circuit 710 of the power factor correction converter 700. More specifically, the voltage regulator circuit 230 converts the auxiliary voltage VAUX generated by the auxiliary winding of the transformer 10 of the flyback converter 900 into the bias power supply VDDPFC.

[0176] In another embodiment, such as Figure 12 As shown, the voltage regulator circuit 220 is used to convert the output power (i.e., the supply voltage VO) generated by the USB-PD compatible power supply device 912 to provide a bias power supply VDDSC to the secondary-side controller 600 of the flyback converter 900. More specifically, the voltage regulator circuit 220 is used to convert the supply voltage VO into the bias power supply VDDSC, wherein the control voltage VSxSC is used to control the control terminal Sx of the voltage regulator circuit 220.

[0177] Figure 13 This is a schematic diagram illustrating a preferred embodiment of a power supply device 913 utilizing a voltage regulator circuit according to the present invention. In one embodiment, as... Figure 13 As shown, the secondary-side controller 600 of the power supply device compatible with the USB-PD specification generates a forced bypass control signal FPT to control the control terminal Sx of the voltage regulator circuit 230 via the optocoupler 95.

[0178] It is worth noting that the voltage regulator circuit of this invention provides high-efficiency power conversion, enabling the regulated bias power supply to be less than 1 watt for use in the conversion control circuit of a USB-PD power supply device or any conversion control circuit powered by a USB-PD power supply device. In standby or no-load operation, the output voltage of the USB-PD power supply device is fixed at 5V. By pulling down the voltage at the control terminal Sx, the conversion control circuit can activate the forced bypass mode of the voltage regulator circuit, thereby achieving low standby power consumption.

[0179] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the scope of the invention. The described embodiments are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components of one embodiment can be used to replace corresponding components in another embodiment. Furthermore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the phrase "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many ways to combine them, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A voltage regulator circuit for converting an input voltage into an output voltage, comprising: A first upper bridge switch is coupled to the input voltage and coupled to an inductor via a first switching node; A first lower bridge switch is coupled to the first upper bridge switch and the inductor via the first switching node; A second upper bridge switch is coupled to the output voltage and coupled to the inductor via a second switching node; A second lower bridge switch is coupled to the second upper bridge switch and the inductor via the second switching node; as well as A control terminal is used to generate a reference voltage or determine a forced bypass mode, wherein the output voltage is determined according to the reference voltage during a buck mode and a boost mode; When the input voltage is higher than a first threshold, the voltage regulator circuit operates in buck mode; When the input voltage is lower than a second threshold, the voltage regulator circuit operates in the boost mode; When the input voltage is lower than the first threshold and higher than the second threshold, the voltage regulator circuit operates in a bypass mode. When the voltage at the control terminal is lower than a third threshold and the input voltage is lower than the first threshold, the voltage regulator circuit operates in the forced bypass mode. Wherein, the level of the first threshold is higher than the level of the second threshold, and the level of the second threshold is higher than the level of the third threshold.

2. The voltage regulator circuit as described in claim 1, wherein, It also includes a current source coupled to the control terminal; wherein the current source is applied to a resistor connected to the control terminal to determine the voltage level of the reference voltage.

3. The voltage regulator circuit as described in claim 1, wherein, The reference voltage is used to generate the first threshold and the second threshold.

4. The voltage regulator circuit as described in claim 1, wherein, When the input voltage is below the first threshold, the forced bypass mode is enabled by pulling the voltage at the control terminal to a low level.

5. The voltage regulator circuit as described in claim 1, wherein, It also includes a first hysteresis comparator and a second hysteresis comparator; The first hysteresis comparator is coupled to receive the input voltage and the first threshold to determine whether the voltage regulator circuit operates in the buck mode or the bypass mode. The second hysteresis comparator is coupled to the input voltage and the second threshold, and is used to determine whether the voltage regulator circuit operates in the bypass mode or the boost mode when the input voltage is lower than the second threshold.

6. The voltage regulator circuit as described in claim 1, wherein, The voltage regulator circuit performs switching operations with a fixed on-time control; wherein, in the buck mode, the on-time of the first upper bridge switch is reduced in response to the increase in the input voltage, and the first upper bridge switch has a minimum off-time.

7. The voltage regulator circuit as described in claim 1, wherein, In this boost mode, the voltage regulator circuit performs switching operations with a fixed on-time control, the on-time of the second lower bridge switch is reduced in response to the increase in the input voltage, and the second lower bridge switch has a minimum off-time.

8. The voltage regulator circuit as described in claim 1, wherein, In both the buck and boost modes, the voltage regulator circuit operates in a discontinuous conduction mode.

9. The voltage regulator circuit as described in claim 1, wherein, When the voltage regulator circuit operates in buck mode, the first lower bridge switch turns off before the inductor is completely demagnetized.

10. The voltage regulator circuit as described in claim 1, wherein, When the voltage regulator circuit operates in boost mode, the second upper bridge switch turns off before the inductor is completely demagnetized.

11. The voltage regulator circuit as described in claim 1, wherein, During the bypass mode operation, the first upper bridge switch and the second upper bridge switch are turned on, while the first lower bridge switch and the second lower bridge switch are not turned on.

12. The voltage regulator circuit as described in claim 1, wherein, Before the operating mode changes between the buck mode, the boost mode, and the bypass mode, the first upper bridge switch, the second upper bridge switch, the first lower bridge switch, and the second lower bridge switch are not conducting.

13. The voltage regulator circuit as described in claim 1, wherein, The voltage regulator circuit is used to provide a bias power supply to a conversion control circuit within a power supply device, wherein the power supply device is compatible with the USB-PD specification, or the voltage regulator circuit is used to convert an output power generated by a power supply device compatible with the USB-PD specification to provide the bias power supply to the conversion control circuit.

14. The voltage regulator circuit as described in claim 13, wherein, The power supply device, which is compatible with the USB-PD specification, includes a flyback converter.

15. The voltage regulator circuit as described in claim 14, wherein, The primary and secondary side controllers of this power supply device, which is compatible with the USB-PD specification, control the control terminal via an optocoupler.

16. The voltage regulator circuit as described in claim 1, wherein, The output power of this voltage regulator circuit is less than 1 watt.

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