p-NiO / n-Ga2O3 Hole Super-Injection Low-Resistance Vertical Field-Effect Transistor and its Fabrication Method

Abstract

This invention discloses a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor and its fabrication method, solving the problems of excessive on-resistance and insufficient voltage withstand capability of existing Ga2O3 field-effect transistors. From bottom to top, the invention includes: a drain electrode, a substrate, an epitaxial layer with a raised structure, an Al2O3 layer covering the upper surface of the epitaxial layer steps and the sidewalls of the raised structure, a gate metal layer covering the outside of the Al2O3 layer, a SiO2 layer covering the outside of the gate metal layer, and a source electrode. A NiO thin film layer is disposed between the surface of the raised portion of the epitaxial layer and the source electrode, and the NiO thin film layer and the n-Ga2O3 epitaxial layer form a heterojunction. The fabrication steps include: pre-treating the substrate, fabricating the drain electrode, etching the epitaxial layer, depositing the Al2O3 layer and the gate metal layer, fabricating the p-NiO / n-Ga2O3 heterojunction, depositing the SiO2 layer, and fabricating the source electrode. This invention significantly improves the device's breakdown voltage and greatly reduces its on-resistance by leveraging the hole super-injection effect generated by the p-NiO / n-Ga2O3 heterojunction, making it promising for applications in high-power and military fields.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and mainly relates to the structure and fabrication method of a novel gallium oxide field-effect transistor. Specifically, it is a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor and its fabrication method, which can be used to fabricate high-voltage, low-on-resistance enhancement-mode gallium oxide devices. Background Technology

[0002] Gallium oxide exists in five crystal forms: α, β, γ, δ, and ε. Among them, monoclinic β-Ga₂O₃ exhibits the best thermal stability and is easy to produce, thus attracting extensive research. β-Ga₂O₃ has a band gap of 4.6 eV–4.9 eV, a critical breakdown field of approximately 8 MV / cm, which is more than 20 times that of Si and more than twice that of SiC and GaN. Its electron mobility at 300 K is 250–300 cm⁻¹. 2 / Vs, saturated electron velocity is 2×10 7 cm / s. Due to the aforementioned superior properties, β-Ga2O3 has a Baliga figure of merit exceeding 3000, which is more than 8 times that of third-generation semiconductor 4H-SiC and more than 4 times that of GaN; and at high frequencies, its Baliga figure of merit is approximately 150 times that of Si, approximately 3 times that of 4H-SiC, and 1.5 times that of GaN. The theoretical on-resistance of Ga2O3 material is very low, meaning that under the same conditions, the conduction loss of unipolar devices is at least an order of magnitude lower than that of SiC and GaN devices, which is beneficial for improving device efficiency. In summary, β-Ga2O3 is a promising power semiconductor material, and power semiconductor devices based on β-Ga2O3 have great potential in high-frequency, high-voltage, and high-power applications.

[0003] Currently fabricated vertical gallium oxide (GaO) field-effect transistors are based on effective n-type doping, typically using Sn as the n-type dopant, and the carriers in the n-type GaO crystal can be regulated over a wide range. However, in β-Ga₂O₃, p-type doping is difficult to achieve due to factors such as the self-compensation effect of Ga and O vacancies, the deeply dominant energy level formed by various impurities, and the low solubility of dopants. The current temporary solution is to use NiO and Cu₂O as substitutes for p-type β-Ga₂O₃. The band gap of NiO is 3.8-4.2 eV, much larger than the 2-2.4 eV band gap of Cu₂O, indicating that the critical breakdown electric field of NiO is much higher than that of Cu₂O. Although the hole mobility of NiO at room temperature is lower than that of Cu₂O, the main factor leading to device breakdown is the magnitude of the critical breakdown electric field. Therefore, to improve the breakdown voltage of β-Ga₂O₃, NiO is more suitable as a substitute for p-type β-Ga₂O₃. Furthermore, existing gallium oxide-based devices face several developmental bottlenecks: The ultra-wide bandgap and excellent thermal stability of β-Ga₂O₃ indicate its promising future in high-power applications, but increased power inevitably leads to higher temperatures. β-Ga₂O₃ has a thermal conductivity of only 0.2 W / cm·K, 8 times lower than GaN and 30 times lower than SiC, making low thermal conductivity a serious potential weakness of Ga₂O₃ materials. Currently available gallium oxide wafers are relatively small, with the largest being only 100 mm. For commercialization, wafer sizes should be at least 150 mm, with 200 mm being the next step. Larger wafer sizes not only reduce product costs but also allow for processing on more advanced production lines, resulting in better process control and lower defect density. Therefore, gallium oxide-based devices are still some distance from commercialization.

[0004] Currently, the processing of p-type β-Ga2O3 is quite difficult under existing technology, and the hole concentration is too low, making it difficult to generate homogeneous gallium oxide pn junctions. Due to the different device structures, heterojunctions made with other materials as p-type substitutes have high forward conduction resistance and the breakdown voltage has not yet reached the theoretical limit of Ga2O3. Summary of the Invention

[0005] The purpose of this invention is to address the problems and shortcomings of the existing technology by proposing a new approach: a high-voltage, low-on-resistance p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor and its fabrication method.

[0006] This invention relates to a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor, comprising, from bottom to top: a drain electrode, a substrate, an epitaxial layer with a circular boss structure, an Al2O3 isolation layer covering the upper surface of the epitaxial layer steps and the sidewalls of the boss, a gate metal layer covering the outside of the Al2O3 isolation layer and depositing a gate pad G on one side, a SiO2 isolation layer covering the outside of the gate metal layer, and a source electrode covering the upper surface of the device and having a window formed on the gate pad G portion. The center of the protruding part of the boss structure is located at the exact center of the device. The key feature is that the epitaxial layer is an n-Ga2O3 gallium oxide epitaxial layer, and a p-type NiO thin film layer is disposed between the upper surface of the top of the epitaxial layer boss and the source electrode. The p-type NiO thin film layer and the n-Ga2O3 epitaxial layer form a heterojunction pn junction, thus constituting a high-voltage, low-on-resistance, and low-power p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor.

[0007] This invention also discloses a method for fabricating a p-NiO / n-Ga2O3 hole-injection low-resistance vertical field-effect transistor, enabling the fabrication of any of the p-NiO / n-Ga2O3 hole-injection low-resistance vertical field-effect transistors described in claims 1-4. The method is characterized in that a p-type NiO thin film with a thickness of 300nm-500nm is deposited at low temperature between the upper surface of the top protrusion of the n-Ga2O3 epitaxial layer and the source electrode, forming a heterojunction between the p-type NiO thin film and the n-Ga2O3 epitaxial layer. The method includes the following steps:

[0008] 1) Substrate selection and pretreatment: Select a doping concentration of 1e18cm. -3 -3e18 cm -3 The n-type β-Ga2O3 single crystal substrate with a thickness ranging from 300nm to 500nm was ultrasonically cleaned for 5 minutes each in acetone solution, anhydrous ethanol, and deionized water, and then dried with nitrogen gas to obtain the pretreated substrate.

[0009] 2) Fabrication of the drain electrode: A Ti / Au layer with a thickness of 60nm / 120nm is deposited on the back side of the substrate using an electron beam evaporation E-Beam system to form the drain electrode metal layer;

[0010] 3) Cleaning the epitaxial wafer: Select a homogeneous gallium oxide epitaxial wafer with a thickness of 5μm-10μm and clean it. Specifically, immerse the gallium oxide epitaxial wafer in acetone solution and anhydrous ethanol solution for ultrasonic cleaning for 5min-10min each, then rinse it with a large amount of deionized water, and finally dry it with nitrogen gas to obtain the cleaned epitaxial wafer.

[0011] 4) Photolithography to form the area to be etched: Photolithography is performed on the cleaned epitaxial wafer. First, photoresist is coated on the surface of the n-Ga2O3 epitaxial wafer. Then, through pre-baking, alignment and exposure, post-baking, development, hardening and pattern inspection, a photoresist-protected area with a width of 0.3-1μm is obtained at the center of the surface of the epitaxial wafer.

[0012] 5) Etching areas not protected by photoresist: The photolithographically patterned epitaxial wafer is placed in a reactive ion etching (RIE) system to etch away areas not protected by photoresist. The sample is then placed in an annealing furnace under N2 conditions. The furnace annealing temperature is set to 800℃-1100℃, and the annealing time is 20-40 minutes to form good ohmic contacts. This yields an epitaxial layer with a boss structure; the width of the boss is 0.3-1 μm, and the height is 1-3 μm.

[0013] 6) Deposition of Al2O3 isolation layer and gate metal layer: Using atomic layer deposition (ALD) process, trimethylaluminum (TMA) and water (H2O) are used as precursors to deposit Al2O3 with a thickness of 50-100nm as a dielectric layer on the surface. Then, Cr with a thickness of 50nm is deposited on the surface of the Al2O3 layer by electron beam evaporation (E-Beam) system to form the gate metal layer. A gate pad with a thickness of 300nm-400nm is deposited on one side of the device to facilitate electrical measurement.

[0014] 7) Fabrication and formation of p-NiO / n-Ga2O3 heterojunction: On the surface of the deposited gate metal layer, the gate metal layer and Al2O3 isolation layer on the top of the epitaxial layer protrusion are etched away by reactive ion etching (RIE); then, a p-type NiO thin film with a thickness of 300nm-500nm is deposited on the top of the epitaxial layer protrusion by inductively coupled plasma chemical vapor deposition (ICP-CVD).

[0015] 8) Deposition of SiO2 isolation layer: A SiO2 isolation layer with a thickness of 200nm-300nm is first deposited on the entire sample surface using a plasma-enhanced chemical vapor deposition (PECVD) device, and then the SiO2 isolation layer covering the upper part of the p-type NiO thin film region is etched away by reactive ion etching (RIE).

[0016] 9) Fabrication of source electrode: A Ti / Au layer with a thickness of 60nm / 120nm is deposited on the top of the device using an electron beam evaporation E-Beam system to form a source metal layer. An ohmic contact is formed between the top of the epitaxial layer protrusion and the p-type NiO thin film, thus completing the fabrication of a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor.

[0017] This invention solves the problem in the prior art that the hole concentration of p-type Ga2O3 is too low and doping is difficult to achieve. This invention takes a different approach and uses p-type NiO material as a substitute for p-type gallium oxide material. It utilizes the hole super-injection effect generated in the heterojunction formed by p-NiO and n-Ga2O3 to significantly improve the reverse breakdown voltage and reduce the forward conduction resistance.

[0018] The present invention has the following advantages:

[0019] Effectively reducing forward conduction resistance and improving device breakdown voltage: This invention employs a vertically structured n-type gallium oxide MOSFET device and introduces a p-type NiO thin film, forming a heterojunction between the p-type NiO thin film and the n-Ga₂O₃ epitaxial layer. Due to NiO's large bandgap (approximately 3.8-4.2 eV) and high critical electric field strength (approximately 5 MV / cm), and its status as an oxide semiconductor, interface oxidation effects can be avoided. The heterojunction formed by the p-type NiO and n-type β-Ga₂O₃ contacts exhibits a conductivity modulation effect. As the forward voltage increases, the differential resistance continuously decreases, generating a hole super-injection effect, significantly reducing the forward conduction resistance and improving the device's breakdown voltage. This invention has significant development potential in high-power gallium oxide devices.

[0020] Reduced static losses and improved device reliability: By introducing a pn junction gate control structure into the MOSFET, this invention forms an enhanced gallium oxide device, which makes the device in the off state when the gate voltage is zero biased, thus reducing the static losses and improving the device reliability.

[0021] The prepared nickel oxide film has better uniformity and higher density: In the deposition of NiO film, the present invention uses inductively coupled plasma chemical vapor deposition (ICP-CVD) process, which can form a large area, high uniformity and high electron density plasma under low temperature and low pressure conditions, thereby rapidly depositing high-quality nickel oxide film with good uniformity and high density. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor structure of the present invention;

[0023] Figure 2 This is a schematic diagram of the fabrication process of the p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor of the present invention;

[0024] Figure 3 This is a flowchart illustrating the fabrication process of the p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor of the present invention. Detailed Implementation

[0025] Example 1

[0026] In the preparation of β-Ga2O3 materials, p-type doping of Ga2O3 is difficult to achieve due to factors such as the self-compensation effect of Ga and O vacancies, the deep principal energy level formed by various impurities, and the low solubility of dopants. It is necessary to find a matching heterogeneous p-type material based on the band gap, lattice matching degree, and various effects generated when different materials come into contact. Since NiO has a large band gap (approximately 3.8-4.2 eV) and a large critical electric field (approximately 5 MV / cm), and is also an oxide semiconductor, it can avoid interfacial oxidation effects. NiO itself has a high hole concentration. Therefore, this invention uses p-type NiO as a substitute for p-type Ga2O3.

[0027] This invention addresses the lack of p-type gallium oxide materials by using p-type NiO as a substitute for p-type Ga2O3 during the research process. NiO is combined with n-Ga2O3 to form a heterojunction, thus creating a novel gallium oxide field-effect transistor scheme.

[0028] This invention relates to a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor, comprising, from bottom to top: a drain electrode 1, a substrate 2, an epitaxial layer with a circular boss structure 3, an Al2O3 isolation layer covering the upper surface of the epitaxial layer steps and the sidewalls of the boss 4, a gate metal layer covering the outside of the Al2O3 isolation layer and having a gate pad G deposited on one side 5, a SiO2 isolation layer covering the outside of the gate metal layer 6, and a source electrode 8 covering the upper surface of the device and having a window formed in the gate pad G portion. The center of the protruding part of the boss structure is located at the exact center of the device. See [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of the p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor structure of the present invention. The epitaxial layer of the present invention is an n-Ga2O3 gallium oxide epitaxial layer. A p-type NiO thin film layer 7 is provided between the upper surface of the top of the epitaxial layer 3 boss and the source electrode 8. The p-type NiO thin film layer 7 and the n-Ga2O3 epitaxial layer 3 form a heterojunction. The drain electrode 1, the substrate 2, the epitaxial layer 3 with the circular boss structure, and the p-type NiO thin film layer 7 are all centrally symmetrical. The whole structure constitutes a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor with high withstand voltage, low on-resistance, and low power consumption.

[0029] This invention improves breakdown voltage and rated current by using a vertical field-effect transistor (FET) structure. It uses p-NiO as a substitute for p-type gallium oxide (GaO) material, forming a heterojunction with n-Ga2O3. Utilizing the conductivity modulation effect in the n-Ga2O3 / p-NiO heterojunction, the hole barrier decreases under forward bias, allowing holes in the p-region to jump across the PN heterojunction into the n-region. When the hole concentration exceeds the electron concentration, it induces an increase in electron concentration. As the forward voltage increases, the differential resistance continuously decreases, generating a hole over-injection effect, thereby significantly improving the breakdown voltage of the GaO device and reducing its on-resistance. Furthermore, by introducing a field-plate structure for the gate electrode, the static loss of the device is significantly reduced, achieving a high-performance and highly reliable enhancement-mode GaO device.

[0030] Example 2

[0031] The p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor structure is the same as in Example 1. In this invention, the total thickness of the n-Ga2O3 epitaxial layer 3 is 5μm-10μm. The center of the protruding portion of the boss structure is located at the exact center of the device. The width of the protruding portion is 0.3μm-1μm, and the height is 1μm-3μm. The thickness of the p-type NiO thin film layer 7 in this invention is 300-500nm.

[0032] This example illustrates three specific combinations of epitaxial layer thickness, boss size, and p-type NiO film thickness according to the present invention. The specific parameter combinations are as follows:

[0033] 1. An epitaxial layer with a thickness of 10 μm is selected, and the width of the protruding portion of the boss structure is set to 1 μm and the height to 3 μm. This allows sufficient drift space for charge carriers, resulting in better breakdown characteristics of the device. It also allows for a larger gate metal layer coverage area, stronger gate control, and lower static loss and higher reliability. In this example, a 500 nm thick NiO film is chosen to allow sufficient p-region holes to jump across the PN heterojunction into the n-region, thereby inducing a hole super-injection effect and reducing on-resistance.

[0034] 2. Select an epitaxial layer with a thickness of 5μm, set the width of the protruding part of the boss structure to 0.3μm and the height to 1μm, and set the NiO film thickness to 300nm. This will allow the device to have a smaller size, lower fabrication cost, higher integration of the fabricated circuit, and minimize the influence of parasitic capacitance.

[0035] 3. Select an epitaxial layer with a thickness of 7μm, set the width of the protruding part of the boss structure to 0.6μm and the height to 2μm, and set the NiO film thickness to 400nm. This can achieve a better balance between device size, cost, breakdown voltage and parasitic capacitance.

[0036] This example provides three specific combinations of epitaxial layer thickness, boss size, and p-type NiO film thickness of the present invention. In addition to the three combinations given in this embodiment, there can be more combinations within the range given in this example. It should not be assumed that the specific implementation of the present invention is limited to these three combinations.

[0037] Example 3

[0038] The structure of the p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor is the same as in Examples 1-2. In this invention, the drain electrode 1 is made of Ti / Au material with a thickness of 60nm / 200nm, the source electrode 8 is made of Ti / Au material with a thickness of 60nm / 120nm, and the gate metal layer 5 is made of Cr material with a thickness of 30nm-50nm.

[0039] Choosing Ti / Au metals as the source and drain materials of the device can form better ohmic contacts and reduce the DC power consumption of the device. Choosing Cr metal as the gate metal layer of the device allows for better chemical stability when the gate metal layer is sandwiched between Al2O3 and SiO2 isolation layers. A gate metal layer thickness of 30 nm optimizes the overall device size; a thickness of 50 nm improves the contact between the gate and the Al2O3 and SiO2 isolation layers; and a thickness of 40 nm strikes a good balance between device fabrication cost and performance. The gate metal layer thickness is not limited to the three thicknesses given above; a range of 30-50 nm can be considered a reasonable gate metal layer thickness.

[0040] Example 4

[0041] The p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor structure is the same as in Examples 1-3. In this invention, the substrate 2 is a Ga2O3 substrate with a thickness of 300-500nm.

[0042] In this invention, a Ga2O3 substrate is chosen to ensure the device has a high reverse breakdown voltage and low fabrication cost. A substrate thickness of 300-500 nm allows for a reasonable drift length for charge carriers, resulting in better current characteristics. A substrate thickness of 300 nm reduces device size and lowers forward on-resistance; a substrate thickness of 500 nm improves the overall breakdown voltage; and a substrate thickness of 400 nm provides both low forward on-resistance and high breakdown voltage. The substrate thickness is not limited to the three thicknesses mentioned above; any thickness between 300-500 nm can be considered reasonable.

[0043] This invention introduces a p-type NiO thin film to form a heterojunction with an n-type gallium oxide material, generating a significant hole super-injection effect, thereby improving the breakdown voltage of current Ga2O3 field-effect transistors and significantly reducing their on-resistance. From bottom to top, it comprises: a drain metal layer, a substrate, an epitaxial layer, an Al2O3 layer, a gate metal layer, a SiO2 isolation layer, a NiO thin film layer, and a source metal layer. An epitaxial layer is deposited above the substrate; a drain metal layer is deposited below the substrate, forming an ohmic contact with the substrate; the epitaxial layer has a circular boss structure; an Al2O3 isolation layer is deposited on the sidewalls of the protruding portion of the epitaxial layer boss and on the surfaces of both sides of the epitaxial layer; a gate metal layer is deposited on the surface of the Al2O3 isolation layer, and a gate pad is deposited on one side; a SiO2 isolation layer is deposited on the surface of the gate metal layer; a NiO thin film layer is deposited on the upper surface of the boss structure, forming a heterojunction with the upper surface of the protruding portion of the epitaxial layer boss, to form a normally-off gallium oxide device with high breakdown voltage, low on-resistance, and low power consumption; the source metal layer is deposited on the upper surface of the NiO thin film layer and the surface of the SiO2 isolation layer. This invention improves the performance and reliability of the device and can be used to fabricate gallium oxide vertical field-effect transistors with high breakdown voltage and low on-resistance.

[0044] Example 5

[0045] This invention also relates to a method for fabricating a p-NiO / n-Ga2O3 hole-injection low-resistance vertical field-effect transistor. For the fabrication of any of the aforementioned p-NiO / n-Ga2O3 hole-injection low-resistance vertical field-effect transistors, the structure of the p-NiO / n-Ga2O3 hole-injection low-resistance vertical field-effect transistor is the same as in Examples 1-4. (See also...) Figure 3 , Figure 3 This is a flowchart illustrating the fabrication process of the p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor of the present invention. A p-type NiO thin film with a thickness of 300nm-500nm is deposited at low temperature between the upper surface of the top protrusion of the n-Ga2O3 epitaxial layer 3 and the source electrode 8. The p-type NiO thin film layer 7 and the n-Ga2O3 epitaxial layer 3 form a heterojunction pn junction, including the following steps:

[0046] 1) Substrate selection and pretreatment: Select a doping concentration of 1e18cm. -3 -3e18 cm -3 The n-type β-Ga2O3 single crystal substrate, with a thickness ranging from 300nm to 500nm, was ultrasonically cleaned for 5 minutes each in acetone solution, anhydrous ethanol, and deionized water, and then dried with nitrogen gas to obtain the pretreated substrate.

[0047] 2) Fabrication of drain electrode: A 60nm / 120nm thick Ti / Au layer is deposited on the back of the substrate using an electron beam evaporation E-Beam system to form the drain electrode metal layer.

[0048] 3) Cleaning the epitaxial wafer: Select a homogeneous gallium oxide epitaxial wafer with a thickness of 5μm-10μm and clean it. Specifically, immerse the gallium oxide epitaxial wafer in acetone solution and anhydrous ethanol solution for ultrasonic cleaning for 5min-10min each, then rinse it with a large amount of deionized water, and finally dry it with nitrogen gas to obtain the cleaned epitaxial wafer.

[0049] 4) Photolithography to form the area to be etched: Photolithography is performed on the cleaned epitaxial wafer. First, photoresist is coated on the surface of the n-Ga2O3 epitaxial wafer. Then, through pre-baking, alignment and exposure, post-baking, development, hardening and pattern inspection, a region with a width of 0.3-1μm located at the center of the surface of the epitaxial wafer and protected by photoresist is obtained.

[0050] 5) Etching areas not protected by photoresist: The photolithographically patterned epitaxial wafer is placed in a reactive ion etching (RIE) system to etch away areas not protected by photoresist. The sample is then placed in an annealing furnace under N2 atmosphere, with the furnace temperature set to 800℃-1100℃ and the annealing time to 20-40 minutes to form good ohmic contacts. This yields an epitaxial layer with a raised structure, the width of which is 0.3-1 μm and the height of which is 1-3 μm.

[0051] 6) Deposition of Al2O3 isolation layer and gate metal layer: Using atomic layer deposition (ALD) process, trimethylaluminum (TMA) and water (H2O) are used as precursors to deposit Al2O3 with a thickness of 20-50 nm as a dielectric layer on the surface. Then, Cr with a thickness of 50 nm is deposited on the surface of Al2O3 isolation layer by electron beam evaporation (E-Beam) system to form gate metal layer. A gate pad with a thickness of 300 nm-400 nm is deposited on one side of the device to facilitate electrical measurement.

[0052] 7) Fabrication and formation of p-NiO / n-Ga2O3 heterojunction: On the surface of the deposited gate metal layer, the gate metal layer and Al2O3 isolation layer on the top of the epitaxial layer protrusion are etched away by reactive ion etching (RIE); then, a p-type NiO thin film with a thickness of 300nm-500nm is deposited on the top of the epitaxial layer protrusion by inductively coupled plasma chemical vapor deposition (ICP-CVD).

[0053] 8) Fabrication of SiO2 isolation layer: First, a SiO2 isolation layer with a thickness of 200nm-300nm is deposited on the entire sample surface using a plasma-enhanced chemical vapor deposition (PECVD) device. Then, the SiO2 isolation layer covering the upper part of the p-type NiO thin film region is etched away by reactive ion etching (RIE).

[0054] 9) Fabrication of source electrode: A Ti / Au layer with a thickness of 60nm / 120nm is deposited on the top of the device using an electron beam evaporation E-Beam system to form a source metal layer. An ohmic contact is formed between the top of the epitaxial layer protrusion and the p-type NiO thin film, thus completing the fabrication of a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor.

[0055] The nickel oxide thin film prepared by this invention has better uniformity and higher density: When depositing NiO thin film, this invention uses inductively coupled plasma chemical vapor deposition (ICP-CVD) to form a large-area plasma with high uniformity and high electron density under low temperature and low pressure conditions. This enables rapid deposition of high-quality nickel oxide thin films with good uniformity and high density, improving the performance and reliability of the device. It can be used to prepare gallium oxide vertical field-effect transistors with high breakdown voltage and low on-resistance.

[0056] Example 6

[0057] The p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor structure is the same as in Examples 1-5. In this invention, in steps 2) and 9), an electron beam evaporation (E-Beam) system is used to deposit metal Ti / Au in the drain and source electrode regions. The process conditions are as follows:

[0058] Evaporation rate: 0.1-20 A / s

[0059] Pre-evaporation power: 5-45

[0060] Evaporation power: 0-60

[0061] Working vacuum: 5e-4Pa

[0062] Operating temperature: 20℃-200℃.

[0063] This process yields Ti metal with a thickness of 60nm and Au metal with a thickness of 120nm-200nm, both with a smooth and uniform surface, forming a good ohmic electrode.

[0064] Example 7

[0065] The p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor structure is the same as in Examples 1-6. In steps 7) and 8) of this invention, reactive ion etching (RIE) is used to etch the Al2O3 isolation layer, the gate metal layer, and the SiO2 isolation layer. The process conditions are as follows:

[0066] Reaction chamber pressure: 20 mTorr

[0067] Reaction chamber gases: BCl3, Ar

[0068] Gas flow rate ratio in reaction chamber: BCl3:Ar = 20 sccm: 10 sccm

[0069] Etching power: 300W.

[0070] This reactive gas can effectively etch Al2O3, SiO2 and Cr metal materials. It can etch Al2O3 material with a thickness of 50 nm, SiO2 material with a thickness of 200 nm, and Cr metal material with a thickness of 50 nm, and etch out a smooth surface.

[0071] Example 8

[0072] The p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor structure is the same as in Examples 1-7. In step 7) of this invention, a low-temperature deposition equipment, ICP-CVD, is used to deposit a p-type NiO thin film, and the process conditions are as follows:

[0073] Reaction chamber pressure: 10 mTorr

[0074] Ionization voltage: 1.8-4.5KV

[0075] Plasma ionization electrode: Ni

[0076] Gases in the reaction chamber: O2, N2, Ar.

[0077] Under the gaseous conditions of this reaction chamber, a NiO film with low impurity content can be generated, and under this ionization voltage, a NiO film with a thickness of 300 nm and a smooth surface can be generated.

[0078] Example 9

[0079] The p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor structure is the same as in Examples 1-8. In step 7) of this invention, a SiO2 isolation layer is deposited on the device surface using plasma-enhanced chemical vapor deposition (PECVD). The process conditions are as follows:

[0080] Deposition temperature: 330℃

[0081] RF power: 100-200W

[0082] Working air pressure: 200Pa

[0083] Selecting process parameters of 330℃ deposition temperature, 200W RF power, and 200Pa operating pressure can generate a 300nm thick SiO2 isolation layer with a smooth surface.

[0084] Example 10

[0085] The p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor structure is the same as in Examples 1-9. In step 9) of this invention, the Al2O3 isolation layer is deposited using atomic layer deposition (ALD) technology, and the process conditions are as follows:

[0086] Reaction chamber pressure: 880 Pa

[0087] Reaction chamber gas: High-purity nitrogen

[0088] Gas flow rate in reaction chamber: 300 sccm

[0089] Al2O3 growth rate: 0.5 nm / min

[0090] Al2O3 growth time: 40min-100min.

[0091] The above process conditions enable the present invention to deposit Al2O3 material with low impurity concentration in a high-purity nitrogen environment. At a gas flow rate of 300 sccm, an Al2O3 isolation layer with a smooth surface and a thickness of 20 nm can be deposited in 40 minutes.

[0092] Example 11

[0093] The structure of the p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor is the same as that in Examples 1-10. The p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor and its fabrication process are described in further detail below with reference to the accompanying drawings.

[0094] Because NiO films exhibit significant p-type conductivity even without artificial doping, and have a relatively high hole concentration of approximately 1 × 10⁻⁶. 19 cm -3 Therefore, this invention selects NiO as the p-type material to construct a pn junction with n-Ga2O3 to improve the performance and reliability of the device.

[0095] Reference Figure 1The p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor of the present invention includes: a drain electrode 1, a substrate 2, an n-Ga2O3 epitaxial layer 3, an Al2O3 isolation layer 4, a gate metal layer 5, a SiO2 isolation layer 6, a p-type NiO thin film layer 7, and a source electrode 8. In this structure, the epitaxial layer 3 is deposited above the substrate 2; the drain electrode 1 is deposited below the substrate 2 and forms an ohmic contact with the substrate 1; the areas on both sides above the epitaxial layer 3 are etched to form a circular boss structure; the Al2O3 isolation layer 4 is deposited on the sidewalls of the raised portion of the boss structure and on the upper surface of the epitaxial layer 3; the gate metal layer 5 is deposited on the surface of the Al2O3 isolation layer 4 and a gate pad is deposited on one side; the SiO2 isolation layer 6 is deposited on the outside of the gate metal layer 5; the p-type NiO thin film layer 7 is deposited on the upper surface of the raised portion of the boss structure and forms a pn junction with the top of the raised portion to form a normally off gallium oxide device with high voltage resistance, low on-resistance, and low power consumption; the source electrode 8 is deposited on the entire device surface and a window is opened on one side of the source electrode to leave space for the gate pad.

[0096] p-NiO has a band gap of 3.9 eV and a high hole concentration (10). 18 -10 19 cm -3 This makes it suitable as a replacement for p-type gallium oxide materials. In the heterojunction formed by n-Ga₂O₃ and p-NiO, a conductivity modulation effect exists. Under forward bias, the hole barrier decreases, allowing holes in the p-region to jump across the PN heterojunction into the n-region. When the hole concentration exceeds the electron concentration, it induces an increase in electron concentration, thereby significantly reducing the device's on-resistance. As the forward voltage increases, the differential resistance continues to decrease, resulting in a hole over-injection effect, which significantly improves the breakdown voltage of gallium oxide devices and reduces on-resistance.

[0097] Reference Figure 2 This invention provides two specific examples for fabricating p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistors:

[0098] 1. On a gallium oxide substrate with a thickness of 300 nm and an n-type gallium oxide homoepitaxial wafer with a thickness of 5 μm, an epitaxial layer protrusion with a width of 0.3 μm and a height of 1 μm is fabricated, and a gallium oxide transistor with a p-type NiO film thickness of 300 nm-500 nm is formed.

[0099] Step 1, clean the epitaxial wafer, such as... Figure 2 (a).

[0100] Select homoepitaxial gallium oxide epitaxial wafers and clean them by sequentially immersing them in acetone solution and anhydrous ethanol solution for ultrasonic cleaning for 5 minutes each, then rinsing them with a large amount of deionized water, and finally drying them with nitrogen gas.

[0101] Step 2, fabricate the drain electrode, such as Figure 2 (b)

[0102] The drain electrode was deposited on the back side of the substrate by depositing Ti / Au with a thickness of 60nm / 200nm on the substrate using an electron beam evaporation E-Beam system. The sample was then placed in an annealing furnace in an N2 environment, with the furnace annealing temperature set at 500℃ and the annealing time at 1min to form a drain electrode with good ohmic contact.

[0103] Step 3: Photolithography forms the area to be etched, such as... Figure 2 (c)

[0104] Photolithography is performed on the cleaned n-Ga2O3 epitaxial layer surface. First, photoresist is coated on the n-Ga2O3 epitaxial layer to be etched, and then the area to be etched without photoresist protection is obtained through a series of processes including pre-baking, alignment and exposure, post-baking, development, hardening and pattern inspection.

[0105] Step 4, etch the areas not protected by photoresist, such as... Figure 2 (d)

[0106] The sample was placed in a reactive ion etching (RIE) system to etch the area to be etched after photolithography, forming an epitaxial layer protrusion with a width of 0.3 μm and a height of 1 μm. The etched sample was then sequentially ultrasonically cleaned in acetone, anhydrous ethanol, and deionized water for 5-10 minutes each, and dried with nitrogen. Afterward, it underwent annealing in an oxygen environment at 900℃ for 1 hour to improve interface contact performance.

[0107] Step 5, deposit an Al2O3 isolation layer, such as Figure 2 (e).

[0108] Using atomic layer deposition (ALD) with trimethylaluminum (TMA) and water (H2O) as precursors, Al2O3 with a thickness of 30 nm is deposited as an isolation layer on the top and sides of the protruding part of the epitaxial layer and on the upper surface of the epitaxial wafer.

[0109] Step 6, fabricate the gate electrode, such as Figure 2 (f).

[0110] Cr with a thickness of 50 nm was deposited on the surface of the deposited Al2O3 isolation layer using an electron beam evaporation E-Beam system. The deposited metal sheet was then placed in a stripping solution and stripped to form a gate electrode. The sample was then placed in an annealing furnace in a N2 environment, with the furnace annealing temperature set at 480 °C and the annealing time at 1 min to form a gate electrode with good ohmic contact.

[0111] Step 7: Etch the gate metal layer and Al2O3 isolation layer on the upper surface of the protrusion, as shown below. Figure 2 (g)

[0112] The gate metal layer and Al2O3 isolation layer covering the top of the epitaxial layer protrusion are etched away by reactive ion etching (RIE) to allow for the next step of p-type NiO thin film deposition.

[0113] Step 8, deposit p-type NiO thin film, such as Figure 2 (h).

[0114] Photolithography is performed on the upper surface of the raised portion of the epitaxial layer, which involves a series of processes including photoresist coating, pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection to form the p-NiO region to be deposited; then, inductively coupled plasma chemical vapor deposition (ICP-CVD) is applied to deposit a NiO thin film with a thickness of 300 nm on the upper surface of the raised portion of the raised structure.

[0115] Step 9: Deposit SiO2.

[0116] A 200 nm thick SiO2 isolation layer was deposited on the device surface using plasma-enhanced chemical vapor deposition (PECVD). Figure 2 (i).

[0117] Step 10: Etch the SiO2 isolation layer on the upper surface of the NiO film, such as... Figure 2 (j)

[0118] The SiO2 isolation layer covering the top of the epitaxial layer protrusion is etched away by reactive ion etching (RIE) to facilitate ohmic contact between the source metal and the p-type NiO thin film.

[0119] Step 11, fabricate the source electrode, such as Figure 2 (k).

[0120] Source regions were formed by photolithography on the surface of the p-type NiO thin film and on both sides of the protrusion. Ti / Au with a thickness of 60nm / 120nm was deposited in the source electrode region and the drain region by electron beam evaporation E-Beam system. The wafer after metal deposition was placed in the stripping solution and stripped to form the source electrode. The sample was then placed in an annealing furnace in a N2 environment, and the furnace annealing temperature was set to 480℃ for 1min to form a source electrode with good ohmic contact, thus completing the device fabrication.

[0121] 2. A gallium oxide transistor with a width of 0.8 μm and a height of 2 μm is fabricated on an n-type gallium oxide homoepitaxial wafer with a thickness of 10 μm and a thickness of 300 nm on a gallium oxide substrate and a p-type NiO thin film.

[0122] Step 1: Clean the sample, such as... Figure 2 (a).

[0123] 1.1) Transfer a 10 nm thick n-Ga2O3 epitaxial wafer onto a 300 nm thick n-Ga2O3 n-substrate;

[0124] 1.2) After the transfer was completed, the sample was placed in acetone solution and anhydrous ethanol solution for ultrasonic cleaning for 8 minutes each, then rinsed with a large amount of deionized water, and then dried with nitrogen gas.

[0125] Step two, fabricate the drain electrode, such as Figure 2 (b)

[0126] 2.1) Drain deposition was performed on the back side of the substrate by depositing Ti / Au with a thickness of 60nm / 200nm on the substrate using an electron beam evaporation E-Beam system;

[0127] 2.2) Place the sample in an annealing furnace in an N2 environment, set the furnace annealing temperature to 500℃ and the annealing time to 1 min, in order to form a drain electrode with good ohmic contact.

[0128] Step 3: Photolithography forms the area to be etched, such as... Figure 2 (c)

[0129] Photolithography is performed on the cleaned n-Ga2O3 epitaxial layer surface. First, photoresist is coated on the n-Ga2O3 epitaxial layer to be etched, and then the area to be etched without photoresist protection is obtained through a series of processes including pre-baking, alignment and exposure, post-baking, development, hardening and pattern inspection.

[0130] Step four: Etch the raised portion of the boss structure, such as... Figure 2 (d)

[0131] 4.1) Place it into a reactive ion etching (RIE) system to etch the area to be etched after photolithography, forming a raised portion with a width of 0.8 μm and a height of 2 μm;

[0132] 4.2) After etching, the sample was placed in acetone solution, anhydrous ethanol solution and deionized water in sequence for ultrasonic cleaning for 5 min-10 min each, and then dried with nitrogen gas.

[0133] 4.3) Annealing is performed in an oxygen environment at a temperature of 900°C for 1 hour to improve the interface contact performance.

[0134] Step 5: Deposit an Al2O3 isolation layer, such as... Figure 2 (e).

[0135] Using atomic layer deposition (ALD) with trimethylaluminum (TMA) and water (H2O) as precursors, Al2O3 with a thickness of 30 nm is deposited as an isolation layer on the upper surface and both sides of the protruding part of the epitaxial layer and on the upper surface of the epitaxial wafer.

[0136] Step six, fabricate the gate electrode, such as Figure 2 (f).

[0137] 6.1) Cr with a thickness of 50 nm is deposited on the surface of the deposited Al2O3 isolation layer by electron beam evaporation E-Beam system. The wafer after metal deposition is then placed in a stripping solution and stripped to form a gate electrode.

[0138] 6.2) Place the sample in an annealing furnace in an N2 environment, set the furnace annealing temperature to 480℃ and the annealing time to 1 min, in order to form a gate electrode with good ohmic contact.

[0139] Step 7: Etch the gate metal layer and Al2O3 isolation layer on the upper surface of the protrusion, as shown below. Figure 2 (g)

[0140] The gate metal layer and Al2O3 layer covering the top of the epitaxial layer protrusion are etched away by reactive ion etching (RIE) to allow for the next step of p-type NiO thin film deposition.

[0141] Step 8: Deposit p-type NiO thin film, such as... Figure 2 (h).

[0142] 8.1) Photolithography is performed on the upper surface of the protruding part of the epitaxial layer, that is, the p-NiO region to be deposited is formed by a series of processes including photoresist coating, pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection.

[0143] 8.2) Then, inductively coupled plasma chemical vapor deposition (ICP-CVD) was applied to deposit a NiO film with a thickness of 300 nm on the p-type NiO region to be deposited on the i-Ga2O3 film.

[0144] Step 9: Deposit a SiO2 isolation layer.

[0145] A 200 nm thick SiO2 isolation layer was deposited on the device surface using plasma-enhanced chemical vapor deposition (PECVD). Figure 2 (i).

[0146] Step 10: Etch the SiO2 isolation layer on the surface of the NiO film, such as... Figure 2 (j)

[0147] The SiO2 isolation layer covering the upper surface of the NiO film is etched away by reactive ion etching (RIE) to facilitate ohmic contact between the source metal and the p-type NiO film.

[0148] Step 11, fabricate the source electrode, such as Figure 2 (k).

[0149] 11.1) Photolithography is performed on the surface of the p-type NiO thin film and the upper surface of the protrusion to form the source region. Ti / Au with a thickness of 60nm / 120nm is deposited in the source electrode region and the drain region by electron beam evaporation E-Beam system. The wafer after metal deposition is placed in the stripping solution and stripped to form the source electrode.

[0150] 11.2) The sample was then placed in an annealing furnace in a N2 environment. The furnace annealing temperature was set to 480℃ and the annealing time was 1 min to form a source electrode with good ohmic contact, thus completing the fabrication of a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor device.

[0151] In summary, this invention provides a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor and its fabrication method. It solves the problem in existing technologies where the hole concentration of p-type Ga2O3 is too low and doping is difficult to achieve (by using p-type NiO material as a substitute for p-type gallium oxide material). From bottom to top, it includes: a drain electrode, a substrate, an epitaxial layer with a circular boss structure, an Al2O3 isolation layer covering the upper surface of the epitaxial layer steps and the sidewalls of the boss, a gate metal layer covering the outside of the Al2O3 isolation layer and depositing a gate pad G on one side, a SiO2 isolation layer covering the outside of the gate metal layer, a source electrode covering the upper surface of the device and forming a window at the gate pad G, and the epitaxial layer boss... A p-type NiO thin film layer is disposed between the top surface of the output portion and the source electrode. The p-type NiO thin film layer and the n-Ga2O3 epitaxial layer form a heterojunction pn junction. The specific fabrication steps include: selecting and pre-treating the substrate, fabricating the drain electrode, cleaning the epitaxial wafer, photolithographically etching the epitaxial layer with a circular boss structure, depositing an Al2O3 isolation layer and a gate metal layer, fabricating and forming the p-NiO / n-Ga2O3 heterojunction, depositing a SiO2 isolation layer, and fabricating the source electrode. This invention significantly improves the reverse breakdown voltage of gallium oxide devices and greatly reduces the forward conduction resistance through the hole super-injection effect generated by the heterojunction formed by the contact between p-NiO and n-Ga2O3, showing broad application prospects in high-power, military, and other fields.

[0152] The above are merely some embodiments of the present invention, and it should not be considered that the specific implementation of the present invention is limited to these descriptions. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and structure of the present invention. However, these modifications and changes based on the concept of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor, comprising, from bottom to top: a drain electrode, a substrate, an epitaxial layer with a circular boss structure, an Al2O3 isolation layer covering the upper surface of the epitaxial layer steps and the sidewalls of the boss, a gate metal layer covering the outside of the Al2O3 isolation layer and having a gate pad G deposited on one side, a SiO2 isolation layer covering the outside of the gate metal layer, and a source electrode covering the upper surface of the device and having a window formed in the gate pad G portion, wherein the center of the protruding portion of the boss structure is located at the exact center of the device, characterized in that: The epitaxial layer is an n-Ga2O3 gallium oxide epitaxial layer. A p-type NiO thin film layer is provided between the upper surface of the top of the epitaxial layer boss and the source electrode. The p-type NiO thin film layer and the n-Ga2O3 epitaxial layer form a heterojunction. The drain electrode, substrate, epitaxial layer with circular boss structure, and p-type NiO thin film layer are all centrally symmetrical. Together, they constitute a high-voltage, low-on-resistance, and low-power p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor.

2. The p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor according to claim 1, characterized in that, The n-Ga2O3 epitaxial layer has a thickness of 5μm-10μm, the center of the protruding part of the boss structure is located at the center of the device, the diameter of the protruding part of the boss structure is 0.3μm-1μm, and the height of the protruding part is 1μm-3μm; the thickness of the p-type NiO thin film layer is 300-500nm.

3. The p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor according to claim 1, characterized in that, The drain electrode is made of Ti / Au material with a thickness of 60nm / 200nm, the source electrode is made of Ti / Au material with a thickness of 60nm / 120nm, and the gate metal layer is made of Cr material with a thickness of 30nm-50nm.

4. The p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor according to claim 1, characterized in that, The substrate is a Ga2O3 substrate with a thickness of 300-500 nm.

5. A method for fabricating a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor, characterized in that, The upper surface of the top protrusion of the n-Ga2O3 epitaxial layer is connected to the source electrode by low-temperature deposition of a p-type NiO film with a thickness of 300nm-500nm. The p-type NiO film layer and the n-Ga2O3 epitaxial layer form a heterojunction, which includes the following steps: 1) Substrate selection and pretreatment: Select a doping concentration of 1e18cm. -3 -3e18 cm -3 The n-type β-Ga2O3 single crystal substrate with a thickness ranging from 300nm to 500nm was ultrasonically cleaned for 5 minutes each in acetone solution, anhydrous ethanol, and deionized water, and then dried with nitrogen gas to obtain the pretreated substrate. 2) Fabrication of the drain electrode: A Ti / Au layer with a thickness of 60nm / 120nm is deposited on the back side of the substrate using an electron beam evaporation E-Beam system to form the drain electrode metal layer; 3) Cleaning the epitaxial wafer: Select a homogeneous gallium oxide epitaxial wafer with a thickness of 5μm-10μm and clean it. Specifically, immerse the gallium oxide epitaxial wafer in acetone solution and anhydrous ethanol solution for ultrasonic cleaning for 5min-10min each, then rinse it with a large amount of deionized water, and finally dry it with nitrogen gas to obtain the cleaned epitaxial wafer. 4) Photolithography to form the area to be etched: Photolithography is performed on the cleaned epitaxial wafer. First, photoresist is coated on the surface of the n-Ga2O3 epitaxial wafer. Then, through pre-baking, alignment and exposure, post-baking, development, hardening and pattern inspection, a photoresist-protected area with a width of 0.3-1μm is obtained at the center of the surface of the epitaxial wafer. 5) Etching areas not protected by photoresist: Place the photolithographically patterned epitaxial wafer into a reactive ion etching (RIE) system to etch away areas not protected by photoresist. Then place the sample in an annealing furnace in a N2 environment. Set the furnace annealing temperature to 800℃-1100℃ and the annealing time to 20-40 minutes to form good ohmic contacts and obtain an epitaxial layer with a boss structure. The width of the boss is 0.3-1μm and the height is 1-3μm. 6) Deposition of Al2O3 isolation layer and gate metal layer: Using atomic layer deposition (ALD) process, trimethylaluminum (TMA) and water (H2O) are used as precursors to deposit Al2O3 with a thickness of 50-100nm as a dielectric layer on the surface. Then, Cr with a thickness of 50nm is deposited on the surface of the Al2O3 layer by electron beam evaporation (E-Beam) system to form the gate metal layer. A gate pad with a thickness of 300nm-400nm is deposited on one side of the device to facilitate electrical measurement. 7) Fabrication and formation of p-NiO / n-Ga2O3 heterojunction: The gate metal layer and Al2O3 isolation layer on the top of the protruding part of the boss are etched away by reactive ion etching (RIE) on the surface of the deposited gate metal layer; then, a p-type NiO thin film with a thickness of 300nm-500nm is deposited on the top of the protruding part of the boss by inductively coupled plasma chemical vapor deposition (ICP-CVD). 8) Fabrication of SiO2 isolation layer: First, a SiO2 isolation layer with a thickness of 200nm-300nm is deposited on the entire sample surface using a plasma-enhanced chemical vapor deposition (PECVD) device. Then, the SiO2 isolation layer covering the upper part of the p-type NiO thin film region is etched away at specific points using a reactive ion etching (RIE) process. 9) Fabrication of source electrode: A Ti / Au layer with a thickness of 60nm / 120nm is deposited on the top of the device using an electron beam evaporation E-Beam system to form a source metal layer. An ohmic contact is formed between the top of the protruding part of the boss and the p-type NiO thin film, thus completing the fabrication of the p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor.

6. The method for fabricating a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor according to claim 5, characterized in that, In steps 2) and 9), the electron beam evaporation (E-Beam) system is used to deposit metallic Ti / Au in the drain and source electrode regions. The process conditions are as follows: Evaporation rate: 0.1-20 A / s Pre-evaporation power: 5-45 Evaporation power: 0-60 Working vacuum: 5e-4Pa Operating temperature: 20℃-200℃.

7. The method for fabricating a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor according to claim 5, characterized in that, In steps 7) and 8), reactive ion etching (RIE) is used to etch the Al2O3 isolation layer, the gate metal layer, and the SiO2 isolation layer at specific points. The process conditions are as follows: Reaction chamber pressure: 20 mTorr Reaction chamber gases: BCl3, Ar Gas flow rate ratio in reaction chamber: BCl3:Ar = 20 sccm: 10 sccm Etching power: 300W.

8. The method for fabricating a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor according to claim 5, characterized in that, In step 7), a low-temperature deposition equipment, ICP-CVD, is used to deposit p-type NiO thin films. The process conditions are as follows: Reaction chamber pressure: 10 mTorr Ionization voltage: 1.8-4.5KV Plasma ionization electrode: Ni Gases in the reaction chamber: O2, N2, Ar.

9. The method for fabricating a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor according to claim 5, characterized in that, In step 7), a SiO2 isolation layer is deposited on the device surface using plasma-enhanced chemical vapor deposition (PECVD). The process conditions are as follows: Deposition temperature: 330℃ RF power: 100-200W Working air pressure: 200Pa.

10. The method for fabricating a p-NiO / n-Ga2O3 hole super-injection low-resistance vertical field-effect transistor according to claim 5, characterized in that, In step 9), an Al2O3 isolation layer is deposited using atomic layer deposition (ALD) technology, and the process conditions are as follows: Reaction chamber pressure: 880 Pa Reaction chamber gas: High-purity nitrogen Gas flow rate in reaction chamber: 300 sccm Al2O3 growth rate: 0.5 nm / min Al2O3 growth time: 40min-100min.

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