Time-to-digital converter, time-to-digital conversion method, and chip

Abstract

This invention discloses a time-to-digital conversion device, a time-to-digital conversion method, and a chip. In the time conversion device, a signal conversion module converts a timing start signal and a timing stop signal into measurement pulse signals. A delay chain module delays the measurement pulse signals and a register module temporarily stores the signal state. An edge detection module detects the rising and falling edges of the measurement pulse signals and determines the number of rising delay unit stages corresponding to the rising edge and the number of falling delay unit stages corresponding to the falling edge. A calculation module calculates the time interval between the rising and falling edges based on the number of clock signal cycles used between the detected rising and falling edges, the first delay time corresponding to the number of rising delay unit stages, and the second delay time corresponding to the number of falling delay unit stages. This invention features a simple circuit structure, saves significant resources and costs, and effectively solves problems such as measurement failure due to excessively large delay intervals between two signals.

Description

Technical Field

[0001] This invention belongs to the field of digital measurement of time, and in particular relates to a time-to-digital conversion device, a time-to-digital conversion method, and a chip. Background Technology

[0002] A time-to-digital converter (TDC) is an instrument that uses circuitry to measure the time interval between two pulses and converts the time signal representing that time interval into a digital signal. It can solve the problem of measuring ultra-short time intervals. Therefore, TDCs are widely used in medical imaging instruments, laser rangefinders, ultrasonic flow meters, ultrasonic density meters, ultrasonic thickness gauges, hysteresis positioning, particle collision time, quantum optics, and sensor applications, where physical quantities (such as capacitance, resistance, weight, density, and pressure) are converted into frequency and phase differences for measurement. Among these applications, the accuracy achievable in time measurement is crucial in TDCs.

[0003] In existing technologies, the most commonly used time measurement circuit for TDC (Time Controlled Counting) is the dual-chain TDC circuit. A typical dual-chain TDC circuit comprises two single-chain TDC circuits. The first single-chain TDC circuit includes a first delay chain module and a first register module. The first delay chain module receives the timing start signal (which can be labeled "start"), and the first register module receives the delayed timing start signal and the clock signal. The first register module also collects and temporarily stores the level state corresponding to the timing start signal passed through the first delay chain module for each clock signal. The second single-chain TDC circuit includes a second delay chain module and a second register module. The second delay chain module receives the timing stop signal (which can be labeled "stop"), and the second register module receives the delayed timing stop signal and the clock signal. The second register module also collects and temporarily stores the level state corresponding to the timing end signal passed through the first delay chain module for each clock signal.

[0004] In a dual-chain TDC circuit, the first single-chain TDC circuit is used to test the start time T1 of the timing start signal, and the second single-chain TDC circuit is used to test the start time T2 of the timing stop signal. The time difference between the timing start signal and the timing stop signal is obtained by subtracting the start time T2 from the start time T1. The dual-chain TDC circuit requires two TDC chains and related measurement circuits, making it complex and resource-intensive.

[0005] In addition, the industry has also improved the aforementioned dual-chain TDC circuit and proposed a single-chain TDC circuit technology.

[0006] The single-chain TDC circuit includes a delay chain module and a register module. The delay chain module is used to receive the timing start signal (which can be identified as start), the register module is used to receive the timing start signal and timing stop signal after the delay (which can be identified as stop), and the register module collects and temporarily stores the level state of the timing start signal after the delay according to each timing stop signal.

[0007] In a single-chain TDC circuit, the timing start signal is connected to a delay module, and the start of the timing start signal is locked by the start of the timing stop signal, thus measuring the time interval between the start time of the timing start signal and the start time of the timing stop signal. However, in a single-chain TDC circuit, due to the limited number of delay units in the delay chain module, in some cases, if the time interval between the start time of the timing start signal and the start time of the timing stop signal is too large, then when the timing start signal has already left the delay chain module but the timing stop signal has not yet arrived, it will result in the inability to measure. Summary of the Invention

[0008] The purpose of this invention is to disclose a time-to-digital conversion device, a time-to-digital conversion method, and a chip to solve problems such as resource consumption or measurement failure in existing timekeeping methods.

[0009] In a first aspect, the present invention discloses a time-to-digital conversion device, comprising: a signal conversion module, a delay chain module, a register module, an edge detection module, and a calculation module; The timing start signal and timing stop signal are converted into a measurement pulse signal by the signal conversion module. The time interval between the occurrence of the timing start signal and the occurrence of the timing stop signal is consistent with the pulse width of the measurement pulse signal. The delay chain module is electrically connected to the signal conversion module, and the delay chain module includes multiple electrically connected delay units; the multiple electrically connected delay units are used to sequentially delay the received measurement pulse signal; The register module is electrically connected to the delay chain module, and the register module includes multiple electrically connected registers. Each register corresponds to a delay unit. The registers collect and temporarily store the signal state of the corresponding delay unit according to each clock signal. The signal state represents the delay state of the measured pulse signal under the current clock signal after passing through the delay unit. The edge detection module, electrically connected to the register module, detects the rising and falling edges of the measurement pulse signal based on the temporarily stored signal state obtained from the register module. Based on the detection results of the rising and falling edges of the measurement pulse signal, it determines the number of rising delay unit stages corresponding to the rising edge and the number of falling delay unit stages corresponding to the falling edge. The calculation module is electrically connected to the edge detection module. The calculation module calculates the time interval between the rising edge and the falling edge of the measurement pulse signal based on the number of clock signal cycles between the rising edge and the falling edge of the measurement pulse signal detected by the edge detection module, and queries the first delay time corresponding to the determined rising delay unit level and the second delay time corresponding to the falling delay unit level.

[0010] In one possible embodiment, the signal conversion module includes a latch unit; the latch unit includes an RS latch circuit.

[0011] In one possible embodiment, the signal conversion module includes a latch unit, which includes an OR gate, an inverter, and a transmission gate circuit. The inverter includes a first inverter, a second inverter, and a third inverter. The transmission gate includes a first transmission gate and a second transmission gate. The first input of the OR gate receives a timing start signal, the second input of the OR gate receives a timing stop signal, the output of the OR gate is connected to the input of the first inverter, and the output of the OR gate is connected to the first control terminal of the first transmission gate and the second control terminal of the second transmission gate. The output of the first inverter is connected to the second control terminal of the first transmission gate and the first control terminal of the second transmission gate. The timing stop signal is input to the input of the first transmission gate. The output of the first transmission gate is connected to the input of the second transmission gate and the input of the second inverter. The output of the second inverter is connected to the input of the third inverter. The output of the second transmission gate is connected to the output of the third inverter.

[0012] In one possible embodiment, the edge detection module includes a rising edge detection unit and a falling edge detection unit; the rising edge detection unit detects whether the temporarily stored signal state obtained from the register module has a first transition state. When there is a first transition state, the signal state includes a rising edge, and a first mark is used to mark the signal position corresponding to the rising edge of the signal state; the falling edge detection unit detects whether the temporarily stored signal state obtained from the register module has a second transition state. When there is a second transition state, the signal state includes a falling edge, and a second mark is used to mark the signal position corresponding to the falling edge of the signal state, wherein the first transition state and the second transition state respectively represent different signal change states.

[0013] In one possible embodiment, the edge detection module further includes a decoding unit. The calculation module is electrically connected to the decoding unit. The decoding unit queries the number of delay units corresponding to the first mark as the number of rising delay units corresponding to the rising edge in the measurement pulse signal, and queries the number of delay units corresponding to the second mark as the number of falling delay units corresponding to the falling edge in the measurement pulse signal.

[0014] In one possible embodiment, the time-to-digital conversion device further includes: a calibration module and a delay time storage module; the calibration module is electrically connected to the edge detection module, and the calibration module measures the delay time of each delay unit in the delay chain module; the delay time storage module is electrically connected to the calibration module and the calculation module, and the delay time storage module stores the measurement results of the delay time of each delay unit in the delay chain module by the calibration module, and the calculation module queries the delay time storage module for the first delay time corresponding to the determined rising delay unit level and the second delay time corresponding to the falling delay unit level.

[0015] In one possible embodiment, the storage address of the delay time storage module corresponds to the level of the delay unit. The Nth storage address in the delay time storage module stores the delay time corresponding to the Nth delay unit level. The delay time corresponding to the Nth delay unit level is the sum of the delay times of the 1st to the Nth delay unit, where N is a positive integer greater than or equal to 1.

[0016] In one possible embodiment, the calculation module includes a clock counting unit. When the edge detection module detects the rising edge of the measurement pulse signal, the clock counting unit starts and records the period of the clock signal. When the edge detection module detects the falling edge of the measurement pulse signal, the clock counting unit stops. The period of the clock signal recorded by the clock counting unit is used as the number of periods n of the clock signal. The time interval between the rising and falling edges of the measurement pulse signal is calculated using the following formula: T = n T clk +ΔT1 -ΔT2 Where T represents the time interval between the rising and falling edges of the measurement pulse signal, T clk Let T represent the period of each clock signal, and let T be the period of the clock signal. clk The delay time is less than the sum of the delay chain modules, where n represents the number of clock signal cycles used between the detection of the rising edge of the measurement pulse signal and the detection of the falling edge of the measurement pulse signal by the edge detection module, and n≥0, ΔT1 represents the first delay time corresponding to the rising delay unit stage, and ΔT2 represents the second delay time corresponding to the falling delay unit stage.

[0017] Secondly, the present invention discloses a time-to-digital conversion method, comprising the following steps: The signal conversion module converts the timing start signal and timing stop signal into a measurement pulse signal. The time interval between the occurrence of the timing start signal and the occurrence of the timing stop signal is consistent with the pulse width of the measurement pulse signal. Multiple delay units electrically connected in the delay chain module sequentially delay the received measurement pulse signal, and multiple registers electrically connected in the register module collect and temporarily store the signal state of the corresponding delay unit according to each clock signal. The signal state represents the delay state of the measurement pulse signal after passing through the delay unit under the current clock signal. The edge detection module detects the rising and falling edges of the measurement pulse signal based on the temporarily stored signal state obtained from the register module; and based on the detection results of the rising and falling edges of the measurement pulse signal, it determines the number of rising delay unit stages corresponding to the rising edge and the number of falling delay unit stages corresponding to the falling edge in the measurement pulse signal; and The calculation module calculates the time interval between the rising and falling edges of the measurement pulse signal based on the clock signal cycle number between the rising and falling edges detected by the edge detection module, the first delay time corresponding to the determined rising delay unit stage, and the second delay time corresponding to the falling delay unit stage.

[0018] Thirdly, the present invention discloses a chip including the time-to-digital conversion device as described above.

[0019] This invention discloses a time-to-digital conversion device, a time-to-digital conversion method, and a chip. The time conversion device includes a signal conversion module, a delay chain module, a register module, an edge detection module, and a calculation module. The signal conversion module converts a timing start signal and a timing stop signal into a measurement pulse signal. The delay chain module delays the measurement pulse signal. The register module collects and temporarily stores the signal states of the corresponding delay units. The edge detection module detects the rising and falling edges of the measurement pulse signal and determines the rising delay unit level and the falling delay unit level corresponding to the falling edge based on the detection results. The calculation module calculates the time interval between the rising and falling edges of the measurement pulse signal based on the number of clock cycles detected by the edge detection module between the rising and falling edges, querying the first delay time corresponding to the rising delay unit level and the second delay time corresponding to the falling delay unit level. Thus, the technical solution of this application has a simpler circuit structure compared to conventional dual-delay chain time-to-digital converter circuits, eliminating the need to build complex dual-delay chain circuit structures and saving a lot of resources or costs; and compared to the original single-delay chain time-to-digital converter circuits, it can not only measure measurement pulse signals with small pulse widths, but also solve the problem of measurement failure due to excessive delay interval between two signals. Attached Figure Description

[0020] The preferred embodiments will now be described in a clear and easy-to-understand manner, in conjunction with the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of the present invention.

[0021] Figure 1 The diagram shown is a structural schematic of one embodiment of the time-to-digital conversion device of the present invention.

[0022] Figure 2 Displayed as Figure 1 A circuit diagram of the signal conversion module in one embodiment.

[0023] Figure 3 Displayed as Figure 1 A circuit diagram of the signal conversion module in another embodiment.

[0024] Figure 4 Displayed as Figure 3 The timing diagram of each signal in the signal conversion module is shown.

[0025] Figure 5 The diagram shown is a circuit schematic of a delay chain module in one embodiment.

[0026] Figure 6 The diagram shown is a structural schematic of the time-to-digital conversion device of the present invention in another embodiment.

[0027] Figure 7 The diagram shown is a structural schematic of an edge detection module in one embodiment.

[0028] Figure 8 The diagram shown is a structural schematic of the edge detection module in another embodiment.

[0029] Figures 9 to 12 This is a schematic diagram showing the status of different measurement stages during the measurement process.

[0030] Figure 13 The diagram shown is a flowchart of one embodiment of the time-to-digital conversion method of the present invention. Detailed Implementation

[0031] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The word "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] In existing technologies, dual-chain TDC circuits are often used. However, dual-chain TDC circuits require two TDC chains and related measurement circuits, which are complex in structure and resource-intensive. In contrast, existing single-chain TDC circuits cannot be measured when the time interval between the timing start signal and the timing stop signal is too large because the timing start signal and timing stop signal are directly connected to the single-chain TDC circuit.

[0033] In view of the various shortcomings of the existing solutions mentioned above, the inventors of this invention have proposed an improvement to the prior art.

[0034] The present invention discloses a time-to-digital conversion device, comprising: a signal conversion module, a delay chain module, a register module, an edge detection module, and a calculation module.

[0035] The timing start signal and timing stop signal are converted into a measurement pulse signal by the signal conversion module. The time interval between the occurrence of the timing start signal and the occurrence of the timing stop signal is consistent with the pulse width of the measurement pulse signal.

[0036] The delay chain module is electrically connected to the signal conversion module. The delay chain module includes multiple electrically connected delay units, which are used to delay the received measurement pulse signal in sequence.

[0037] The register module is electrically connected to the delay chain module. The register module includes multiple electrically connected registers, which correspond to delay units. The registers collect and temporarily store the signal state of the corresponding delay unit according to each clock signal. The signal state represents the delay state of the measured pulse signal passing through the delay unit under the current clock signal.

[0038] The edge detection module is electrically connected to the register module. The edge detection module detects the rising and falling edges of the measurement pulse signal based on the temporary signal state obtained from the register module. Based on the detection results of the rising and falling edges of the measurement pulse signal, the edge detection module determines the number of rising delay unit stages corresponding to the rising edge and the number of falling delay unit stages corresponding to the falling edge in the measurement pulse signal.

[0039] The calculation module, electrically connected to the edge detection module, calculates the time interval between the rising and falling edges of the measurement pulse signal based on the number of clock cycles between the rising and falling edges detected by the edge detection module. It then queries the first delay time corresponding to the determined rising delay unit stage and the second delay time corresponding to the falling delay unit stage. Based on the clock signal cycle, the number of cycles, the first delay time, and the second delay time, the calculation module calculates the time interval between the rising and falling edges of the measurement pulse signal. The time-to-digital conversion device disclosed in this application has a simple circuit structure, eliminating the need for a complex double-chain delay chain circuit structure, thus saving significant resources and costs. The timing start signal and timing stop signal are converted into measurement pulse signals by a signal conversion module. Then, through the cooperation of a delay chain module, a register module, an edge detection module, and a calculation module, the time interval between the rising and falling edges of the measurement pulse signal is measured. Therefore, measurement can be performed even with a small pulse width. For larger pulse widths, the timing start signal is not received by the delay module. Instead, the register module collects the level state of the timing start signal according to the timing stop signal. Therefore, even if the delay level is limited, an invalid timing start signal will not be collected by the timing stop signal, which has the advantages of accurate measurement.

[0040] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0041] Please see Figure 1 The diagram shown is a structural schematic of the time-to-digital conversion device of the present invention in one embodiment.

[0042] like Figure 1 As shown, the time-to-digital converter includes: a signal conversion module 11, a delay chain module 12, a register module 13, an edge detection module 14, and a calculation module 15.

[0043] The signal conversion module 11 is used to convert the timing start signal and the timing stop signal into a measurement pulse signal. Specifically, the input terminal of the signal conversion module 11 receives the timing start signal (which can be identified as start) and the timing stop signal (which can be identified as stop), converts the received timing start signal and timing stop signal into a measurement pulse signal, and outputs it.

[0044] The time interval between the timing start signal and the timing stop signal is consistent with the pulse width of the measurement pulse signal.

[0045] Specifically, the timing start signal and the timing stop signal are electrical signals with rising and falling edges, respectively. In some embodiments, the signal conversion module 11 converts the rising edges of the timing start signal and the timing stop signal into a measurement pulse signal, and the pulse width of the measurement pulse signal is consistent with the time interval between the occurrence of the timing start signal and the occurrence of the timing stop signal. Alternatively, the time interval between the occurrence of the edge of the timing start signal and the occurrence of the edge of the timing stop signal may be consistent with the pulse width of the measurement pulse signal. For example, the signal conversion module 11 records the rising edges of the timing start signal and the timing stop signal, and converts them into a measurement pulse signal accordingly. The rising edge of the measurement pulse signal corresponds to the rising edge of the timing start signal, and the falling edge of the measurement pulse signal corresponds to the rising edge of the timing stop signal, thereby ensuring that the time interval between the occurrence of the edge of the timing start signal and the occurrence of the edge of the timing stop signal is consistent with the pulse width of the measurement pulse signal.

[0046] Of course, the measurement pulse signal converted by the signal conversion module 11 is not limited to this. For example, in some embodiments, the pulse width of the measurement pulse signal converted by the signal conversion module 11 is consistent with the time interval between the time when the timing start signal appears at a preset position and the time when the timing stop signal appears at a preset position.

[0047] In other embodiments, the measurement pulse signal converted by the signal conversion module 11 is not limited to a measurement pulse signal whose rising edge corresponds to the rising edge of the timing start signal and whose falling edge corresponds to the rising edge of the timing end signal. Alternatively, the signal conversion module may record the rising edge of the timing start signal and the falling edge of the timing stop signal, and convert them into a measurement pulse signal, where the rising edge of the measurement pulse signal corresponds to the rising edge of the timing start signal and the falling edge of the measurement pulse signal corresponds to the falling edge of the timing stop signal. That is, the time interval between the occurrence of the rising edge of the timing start signal and the occurrence of the falling edge of the timing stop signal is consistent with the pulse width of the measurement pulse signal. Or, in some embodiments, the signal conversion module records the falling edge of the timing start signal and the rising edge of the timing stop signal, and converts them into a measurement pulse signal, where the rising edge of the measurement pulse signal corresponds to the falling edge of the timing start signal and the falling edge of the measurement pulse signal corresponds to the rising edge of the timing stop signal. That is, the time interval between the occurrence of the falling edge of the timing start signal and the occurrence of the rising edge of the timing stop signal is consistent with the pulse width of the measurement pulse signal. Alternatively, in some embodiments, the signal conversion module records the falling edge of the timing start signal and the falling edge of the timing stop signal, and converts them into a measurement pulse signal. The rising edge of the measurement pulse signal corresponds to the falling edge of the timing start signal, and the falling edge of the measurement pulse signal corresponds to the falling edge of the timing stop signal. That is, the time interval between the occurrence of the falling edge of the timing start signal and the occurrence of the falling edge of the timing stop signal is consistent with the pulse width of the measurement pulse signal.

[0048] Please see Figure 2 Displayed as Figure 1 A circuit diagram of the signal conversion module in one embodiment. (See diagram below.) Figure 2 As shown, the signal conversion module 11 may include a latching unit. In some embodiments, the latching unit may be, for example, an RS latching circuit. The RS latching circuit includes an R input terminal, an S input terminal, a first NOR gate G1, a second NOR gate G2, a Q output terminal, and a QN output terminal. The first input terminal of the first NOR gate G1 is connected to the R input terminal, the first input terminal of the second NOR gate G2 is connected to the S input terminal, the output terminal of the first NOR gate G1 is connected to the Q output terminal, the output terminal of the first NOR gate G1 is connected to the second input terminal of the second NOR gate G2, the output terminal of the second NOR gate G2 is connected to the QN output terminal, and the output terminal of the second NOR gate G2 is connected to the second input terminal of the first NOR gate G1.

[0049] As mentioned earlier, in some embodiments, the signal conversion module converts the rising edge of the timing start signal and the rising edge of the timing stop signal into a measurement pulse signal. The pulse width of the measurement pulse signal is consistent with the time interval between the rising edge time of the timing start signal and the rising edge time of the timing stop signal. Therefore, correspondingly, in one embodiment of the signal conversion module, the RS latch circuit has its S input terminal receiving the timing start signal, its R input terminal receiving the timing stop signal, and its Q output terminal outputting the converted measurement pulse signal. In application, when the timing start signal is high and the timing stop signal is low, the measurement pulse signal output by the Q output terminal of the RS latch circuit is high; when the timing start signal is low and the timing stop signal is high, the measurement pulse signal output by the Q output terminal of the RS latch circuit is low. It is evident that the latch unit using the RS latch circuit has a simple circuit structure and offers advantages such as high speed, stability, and reliability.

[0050] Of course, similarly, if the signal conversion module converts the measurement pulse signal based on the changes in other signal states of the timing start signal and timing stop signal, the input signals of the S input terminal, D input terminal, and Q output terminal in the RS latch unit can be changed in other ways, which will not be elaborated here.

[0051] Furthermore, in other embodiments, the structure of the RS latch circuit can also be changed. For example, in the RS latch circuit, the first NOR gate and the second NOR gate can be replaced with the first NAND gate and the second NAND gate, which should have similar functions.

[0052] Please see Figure 3 Displayed as Figure 1 A circuit diagram of the signal conversion module in another embodiment. (See diagram below.) Figure 3 As shown, the signal conversion module 11 may also include a latch unit, a latch unit OR gate, an inverter, and a transmission gate circuit. The inverter includes a first inverter N1, a second inverter N2, and a third inverter N3. The transmission gate circuit includes a first transmission gate T1 and a second transmission gate T2.

[0053] The first input of the OR gate is used to receive the timing start signal (which can be labeled as start), and the second input of the OR gate is used to receive the timing stop signal (which can be labeled as stop). The output of the OR gate is connected to the input of the first inverter N1. Thus, the output signal S of the OR gate is inversely related to the output signal SN after passing through the first inverter N1.

[0054] The transmission gate circuit includes a first transmission gate T1 and a second transmission gate T2. The output of the OR gate is connected to the first control terminal of the first transmission gate T1 and the second control terminal of the second transmission gate T2, so that the first control terminal of the first transmission gate T1 and the second control terminal of the second transmission gate T2 receive the signal S. The output of the first inverter N1 is connected to the second control terminal of the first transmission gate T1 and the first control terminal of the second transmission gate T2, so that the output of the first inverter N1 and the second control terminal of the first transmission gate T1 receive the signal SN. The input of the first transmission gate T1 is used to receive the timing stop signal (which can be labeled as stop). The output of the first transmission gate T1 is connected to the input of the second transmission gate T2 and the input of the second inverter N2. The output of the second inverter N2 is connected to the input of the third inverter N3. The output of the second inverter N2 is used to output the signal Q, that is, the signal Q is the converted measurement pulse signal.

[0055] Please see Figure 4 Displayed as Figure 3 The timing diagram of each signal in the signal conversion module is shown.

[0056] Combination Figure 3 and Figure 4 For an OR gate, the timing start signal (which can be labeled as start) and the timing stop signal (which can be labeled as stop) are the two input signals of the OR gate. When either the timing start signal or the timing stop signal is high, the output signal S of the OR gate is high, and the signal SN output through the first inverter N1 is low. When both the timing start signal and the timing stop signal are low, the output signal S of the OR gate is low, and the signal SN output through the first inverter N1 is high.

[0057] For the first transmission gate T1 and the second transmission gate T2, signals S and SN serve as the gate control signals for the first transmission gate T1 and the second transmission gate T2.

[0058] When the timing start signal is high, the signal S output by the OR gate is high, and the signal SN output by the first inverter N1 is low. The first transmission gate T1 is turned on, and the second transmission gate T2 is turned off. The timing stop signal is input to the first transmission gate T1. The timing stop signal is output by the second inverter N2 as signal Q. Signal Q is inverted with the timing stop signal. At this time, the timing stop signal is low, so signal Q is high.

[0059] When both the timing start signal and the timing stop signal are low, the signal S output by the OR gate is low, and the signal SN output by the first inverter N1 is high. The first transmission gate T1 is turned off, and the second transmission gate T2 is turned on. The signal Q passes through the third inverter N3 and the second transmission gate T2, reaches the input of the second inverter N2, and then passes through the second inverter N2 to reach the output. This keeps the signal Q in the state before the first transmission gate T1 was turned off, that is, the signal Q is kept at a high level.

[0060] When the timing stop signal is high, the signal S output by the OR gate is high, and the signal SN output by the first inverter N1 is low. The first transmission gate T1 is turned on, and the second transmission gate T2 is turned off. The timing stop signal passes through the second inverter N2 to obtain the signal Q. The signal Q is inverted with the timing stop signal. At this time, the timing stop signal is high, so the signal Q is low.

[0061] Thus, the timing start signal and timing stop signal are converted into a measurement pulse signal (i.e., signal Q) after passing through an OR gate, an inverter, and a transmission gate circuit.

[0062] Furthermore, the structure of the signal conversion module may also be varied in other embodiments.

[0063] Therefore, it can be seen that the signal conversion module can convert the timing start signal and the timing stop signal into a measurement pulse signal. In practical applications, the signal conversion module has multiple implementation methods.

[0064] The delay chain module is electrically connected to the signal conversion module and is used to delay the measurement pulse signal output by the signal conversion module. The register module is electrically connected to the delay chain module.

[0065] Please see Figure 5 The diagram shows a circuit diagram of a delay chain module and a register module in one embodiment.

[0066] Combination Figure 1 and Figure 5 The delay chain module 12 is electrically connected to the signal conversion module 11. The delay chain module 12 includes multiple electrically connected delay units, which are used to sequentially delay the received measurement pulse signal Q. The delay units in the delay chain module can be set according to the clock signal and the working requirements of the time-to-digital converter itself, wherein the period of the clock signal is less than the sum of the delay times of the delay chain module.

[0067] Register module 13 is electrically connected to delay chain module 12. Register module 13 includes multiple electrically connected registers, wherein each register corresponds to a delay unit; for example, there is a one-to-one correspondence between registers and delay units, i.e., one register corresponds to one delay unit. The registers in register module 13 acquire and temporarily store the signal state of the corresponding delay unit according to each clock signal. The signal state represents the delay state of the measured pulse signal passing through the delay unit under the current clock signal.

[0068] In some embodiments, for the register module 13, the signal data of the delay unit in the delay module is collected and temporarily stored when the rising edge of each clock cycle of the clock signal arrives. For example, the signal data on the delay unit at that instant is collected when the rising edge of each clock cycle arrives.

[0069] In some embodiments, please refer to Figure 6 The diagram shown is a structural schematic of the time-to-digital conversion device of the present invention in another embodiment. The time-to-digital conversion device of the present invention also includes a calibration module 16 and a delay time storage module 17.

[0070] The calibration module 16 is electrically connected to the edge detection module 14. The calibration module 16 is used to measure the delay time of each delay unit in the delay chain module 12.

[0071] For example, the delay chain module 12 includes N electrically connected delay units, where N is a positive integer greater than or equal to 1. The delay time of each delay unit in the delay chain module 12 can be measured using the calibration module 16, namely, the delay time of the first delay unit, the delay time of the second delay unit, the delay time of the third delay unit, ..., the delay time of the (N-1)th delay unit, and the delay time of the Nth delay unit.

[0072] The delay time storage module 17 is electrically connected to the calibration module 16 and the calculation module 15. The delay time storage module 17 stores the measurement results of the delay time of each delay unit in the delay chain module 12 by the calibration module 16.

[0073] In some embodiments, the storage address of the delay time storage module 17 corresponds to the level of the delay unit in the delay chain module 12. The Nth storage address in the delay time storage module 17 stores the delay time corresponding to the Nth delay unit level, where the delay time corresponding to the Nth delay unit level is the sum of the delay times of the first to the Nth delay units, and N is a positive integer greater than or equal to 1. For example, the first storage address of the delay time storage module 17 stores the delay time of the first delay unit; the second storage address stores the sum of the delay time of the first and second delay units; the third storage address stores the sum of the delay times of the first, second, and third delay units; and so on. The Nth storage address of the delay time storage module 17 stores the sum of the delay times of the first to the Nth delay units. In other embodiments, the delay time storage module 17 may correspond to a single level of delay time with the storage address. Thus, when the delay time in the measured pulse signal needs to be obtained, the required delay unit level can be directly queried through the calculation module 15. The calculation is performed based on the required delay unit level and the corresponding delay time, including the number of delay unit levels and the corresponding delay time before the required delay unit.

[0074] In practical applications, the delay time storage module 17 may include random access memory (RAM), flash memory, hard disk drive (HDD) or solid-state drive (SSD).

[0075] The edge detection module 14 is electrically connected to the register module 13. The edge detection module 14 detects the rising edge and falling edge of the measurement pulse signal based on the temporarily stored signal state obtained from the register module 13, and determines the number of rising delay unit stages corresponding to the rising edge and the number of falling delay unit stages corresponding to the falling edge in the measurement pulse signal based on the detection results of the rising edge and falling edge of the measurement pulse signal.

[0076] In some embodiments, the edge detection module 14 acquires the signal state registered in the register module 13 when the rising edge of each clock cycle arrives.

[0077] As mentioned above, the timing start signal and timing stop signal are converted into a measurement pulse signal by the signal conversion module 11. The measurement pulse signal has a rising edge and a falling edge. Therefore, in some embodiments, the edge detection module 14 may further include a rising edge detection unit and a falling edge detection unit. Please refer to... Figure 7The diagram shows a structural schematic of an edge detection module in one embodiment. Figure 7 As shown, the edge detection module 14 includes a rising edge detection unit 141 and a falling edge detection unit 143.

[0078] Combination Figure 1 and Figure 7 The rising edge detection unit 141 detects whether the temporarily stored signal state obtained from the register module 13 has a first transition state. The first transition state can be, for example, a transition from a low level to a high level, or a transition from signal data representing a low level to signal data representing a high level in the temporarily stored signal data obtained from the register module 13. When there is a first transition state, the signal state includes a rising edge, and a first mark is used to mark the signal position corresponding to the rising edge of the signal state. For example, in some embodiments, the rising edge detection unit 141 detects the signal states of the corresponding delay units temporarily stored in each register in the register module 13. When it is detected that the signal state temporarily stored in the current register is low and the signal state temporarily stored in the next register is high, it indicates that the rising edge of the corresponding measurement pulse signal has been detected. At this time, the position corresponding to the data signal of the register that first appears high in the temporarily stored signal data obtained from the register module 13 is marked. For example, the data signal of the register that first appears high in the temporarily stored signal data obtained from the register module can be represented by a first encoding, and the signal data corresponding to the remaining registers can be represented by a second encoding different from the first encoding, thereby marking the position corresponding to the rising edge. At this time, the first encoding is the first mark.

[0079] The falling edge detection unit 143 detects whether the temporarily stored signal state obtained from the register module 13 has a second transition state. The second transition state can be, for example, a transition from a high level to a low level, or a transition from signal data representing a high level to signal data representing a low level in the temporarily stored signal data obtained from the register module 13. When a second transition state exists, the signal state includes a falling edge, and a second marker is used to mark the signal position corresponding to the falling edge of the signal state. The first transition state and the second transition state represent different signal change states. For example, in some embodiments, the falling edge detection unit 143 detects the signal states of the corresponding delay units temporarily stored in each register in the register module 13. When it is detected that the signal state temporarily stored in the current register is high and the signal state temporarily stored in the next register is low, it indicates that the falling edge of the corresponding measurement pulse signal has been detected. At this time, the position corresponding to the signal data of the register that first appears low in the temporarily stored signal data obtained from the register module 13 is marked. For example, the signal data corresponding to the register that first appears low in the temporarily stored signal data obtained from the register module can be represented by a third code, and the signal data corresponding to the remaining registers can be represented by a fourth code different from the third code, thereby marking the position corresponding to the falling edge in the register module. At this time, the third code is recorded as the second mark. The first code and the third code can be the same or different, and the second code and the fourth code can be the same or different.

[0080] The edge detection module includes a rising edge detection unit and a falling edge detection unit. These two units can operate independently and simultaneously without interference. Even for measurement pulse signals with small pulse widths, such as those less than one clock cycle, the independently operating rising and falling edge detection units can still accurately detect the rising and falling edges of the measurement pulse signal.

[0081] The following explanation uses a high level of 1 and a low level of 0 as an example.

[0082] If the signal state acquired and temporarily stored by the register module is 0000000011111111, then the rising edge detection unit in the edge detection module detects that the signal state has a first transition state from low level to high level, and marks the signal position that generates the first transition state. For example, if 1 is used as the first type of encoding, then 1 is also used as the first mark. If 0 is used as the second type of encoding, then the signal position of the first transition state can be marked as 0000000010000000.

[0083] If the signal state acquired and temporarily stored by the register module is 1111111100000000, then the falling edge detection unit in the edge detection module detects that the signal state has a second transition state from high level to low level, and marks the signal position that generates the second transition state. For example, if 1 is used as the third type of encoding, then 1 is also used as the second mark. If 0 is used as the fourth type of encoding, then the signal position of the second transition state can be marked as 0000000010000000.

[0084] If the signal state acquired and temporarily stored by the register module is 0000000000000000 or 1111111111111111, then the rising edge detection unit in the edge detection module cannot detect the first transition state of the signal state from low level to high level, and the falling edge detection unit in the edge detection module cannot detect the second transition state of the signal state from high level to low level, and there is no edge.

[0085] In some embodiments, the edge detection module further includes a decoding unit. See also... Figure 8 The diagram shows a structural schematic of the edge detection module in another embodiment. Figure 8 As shown, the edge detection module 14 includes a rising edge detection unit 141, a falling edge detection unit 143, and a decoding unit 145.

[0086] The structure and function of the rising edge detection unit 141 and the falling edge detection unit 143 can be found in the foregoing. Figure 7 The description will not be repeated here.

[0087] Combination Figure 1 and Figure 8 The decoding unit 145 is electrically connected to the computing module 15. Combined with... Figure 6 and Figure 8 The decoding unit 145 is electrically connected to the calculation module 15 and the calibration module 16. The decoding unit 145 queries the number of delay units corresponding to the first mark as the number of rising delay units corresponding to the rising edge in the measurement pulse signal, and queries the number of delay units corresponding to the second mark as the number of falling delay units corresponding to the falling edge in the measurement pulse signal.

[0088] The calculation module 15 is electrically connected to the edge detection module 14. The calculation module 15 calculates the time interval between the rising edge and the falling edge of the measurement pulse signal detected by the edge detection module 14 based on the number of clock signal cycles between the rising edge and the falling edge of the measurement pulse signal detected by the edge detection module 14, and queries the first delay time corresponding to the determined rising delay unit stage and the second delay time corresponding to the falling delay unit stage. Thus, based on the clock signal cycle, the number of cycles, the first delay time, and the second delay time, the calculation module 15 calculates the time interval between the rising edge and the falling edge of the measurement pulse signal.

[0089] In some embodiments, the edge detection module 14 performs detection at the rising edge of each clock cycle. The calculation module 15 includes a clock counting unit. When the edge detection module 14 detects the temporarily stored signal state obtained from the register module 13 and detects the rising edge of the measurement pulse signal, the clock counting unit starts and begins recording the period of the clock signal. That is, when the rising edge detection unit 141 detects the rising edge of the measurement pulse signal, the clock counting unit starts and begins recording the period of the clock signal. Thereafter, every clock cycle, the edge detection module 14 detects the temporarily stored signal state in the register module 13 at the rising edge of each clock cycle, and at the same time, the clock counting unit accumulates the period of the clock signal. Until the edge detection module 14 detects the falling edge of the measurement pulse signal, that is, when the falling edge detection unit 143 detects the falling edge of the measurement pulse signal, the clock counting unit stops counting, and the period of the clock signal recorded by the clock counting unit is taken as the period number n of the clock signal.

[0090] Furthermore, the decoding unit 145 in the edge detection module 14 determines the number of rising delay unit stages corresponding to the rising edge and the number of falling delay unit stages corresponding to the falling edge in the measurement pulse signal based on the detection results of the rising and falling edges of the measurement pulse signal. Thus, the calculation module 15 can query and obtain the first delay time corresponding to the rising delay unit stage determined by the decoding unit 145 in the measurement pulse signal. Additionally, the calculation module 15 can query and obtain the second delay time corresponding to the falling delay unit stage determined by the decoding unit 145 in the measurement pulse signal. In some embodiments, the calculation module 15 can obtain the first delay time corresponding to the rising delay unit stage and the second delay time corresponding to the falling delay unit stage from the delay time storage module 17.

[0091] Subsequently, the calculation module 15 calculates the time interval between the rising and falling edges of the measurement pulse signal based on the following formula: T = n T clk +ΔT1-ΔT2 Where T represents the time interval between the rising and falling edges of the measurement pulse signal, T clk This represents the period of each clock signal, T. clkThe delay time is less than the total delay time of the delay chain module. n represents the number of clock signal cycles used between the detection of the rising edge of the measurement pulse signal and the detection of the falling edge of the measurement pulse signal by the edge detection module, and n≥0. ΔT1 represents the first delay time corresponding to the rising delay unit stage, and ΔT2 represents the second delay time corresponding to the falling delay unit stage.

[0092] The following examples provide a detailed description of the different measurement stages in the measurement process.

[0093] During measurement, the edge detection module detects the signal state of the delay unit registered in the register when the rising edge of each clock cycle arrives, and determines whether the signal state has changed.

[0094] When the edge detection module detects a first transition state (i.e., rising edge) in the delay unit registered in the register when the rising edge of a certain clock cycle arrives, it indicates that the measurement pulse signal has entered the delay chain module. The clock counter in the calculation module begins recording, the cycle number n is cleared to 0, and the edge detection module determines the number of rising delay unit stages corresponding to the rising edge of the measurement pulse signal based on the detection result. For example, n = 1 rising delay unit stages. The calculation module then queries the first delay time ΔT1 corresponding to the determined number of rising delay unit stages. The above measurement phase can be found in [reference needed]. Figure 9 .

[0095] The detection continues when the rising edge of the next clock cycle arrives. If the signal state of the delay unit registered in the edge detection module's detection register remains unchanged and remains high (i.e., the measurement pulse signal is high), then the number of cycles n recorded by the clock counter unit in the calculation module is incremented by 1 after each clock cycle. The above measurement phase can be found in [reference needed]. Figure 10 .

[0096] When the edge detection module continues detection in the next clock cycle, if it detects a second transition state (i.e., a falling edge) in the delay unit registered in the register, indicating that the tail of the measurement pulse signal has entered the delay chain module, the timing ends, and the number of cycles n recorded by the clock counter unit in the calculation module is incremented by 1. Furthermore, based on the detection result of the falling edge of the measurement pulse signal, the edge detection module determines the number of falling delay unit stages corresponding to the falling edge in the measurement pulse signal, for example, n² stages of delay units. The calculation module then queries the second delay time ΔT2 corresponding to the determined number of falling delay unit stages. The above measurement phase can be found in [reference needed]. Figure 11 .

[0097] Thus, the calculation module can calculate the time interval between the rising and falling edges of the measurement pulse signal based on the period of the time signal, the number of periods n, the first delay time ΔT1, and the second delay time ΔT2, i.e.: T = n T clk +ΔT1-ΔT2.

[0098] Of course, if at the arrival of the rising edge of a certain clock cycle, the signal state of the delay unit registered in the register simultaneously detects a first transition state (i.e., rising edge) from low level to high level and a second transition state (i.e., falling edge) from high level to low level, it indicates that the pulse width of the measurement pulse signal is within one clock cycle and the number of cycles n is 0. Furthermore, the edge detection module determines the number of rising delay unit stages corresponding to the rising edge in the measurement pulse signal based on the detection result of the rising edge of the measurement pulse signal, for example, n1 stages of delay units. The calculation module queries the first delay time ΔT1 corresponding to the determined number of rising delay unit stages. And, the edge detection module determines the number of falling delay unit stages corresponding to the falling edge in the measurement pulse signal based on the detection result of the falling edge of the measurement pulse signal, for example, n2 stages of delay units. The calculation module queries the second delay time ΔT2 corresponding to the determined number of falling delay unit stages. Thus, the calculation module calculates the time interval between the rising and falling edges of the measurement pulse signal based on the number of clock cycles n between the rising and falling edges of the measurement pulse signal, the first delay time ΔT1 corresponding to the number of rising delay unit stages, and the second delay time ΔT2 corresponding to the number of falling delay unit stages, i.e., T = n. T clk +ΔT1-ΔT2=0 T clk +ΔT1-ΔT2=ΔT1-ΔT2. The results of the above measurements can be found in [reference needed]. Figure 12 It is evident that even for measurement pulse signals with small pulse widths, it is still possible to detect the rising and falling edges of the measurement pulse signal, and then calculate the time interval between the rising and falling edges of the measurement pulse signal.

[0099] If the pulse width of the measurement pulse signal is very wide, even if the number of delay units electrically connected in the delay chain module is finite, the edge detection module in this invention can still detect the rising edge of each clock cycle and eventually detect the falling edge of the measurement pulse signal.

[0100] The time conversion device disclosed in this invention includes a signal conversion module, a delay chain module, a register module, an edge detection module, and a calculation module. The signal conversion module converts a timing start signal and a timing stop signal into a measurement pulse signal. The delay chain module delays the measurement pulse signal. The register module collects and temporarily stores the signal states of the corresponding delay units. The edge detection module detects the rising and falling edges of the measurement pulse signal and determines the number of rising delay unit stages corresponding to the rising edge and the number of falling delay unit stages corresponding to the falling edge based on the detection results. The calculation module obtains the number of clock cycles between the rising and falling edges of the measurement pulse signal based on the detection results of the edge detection module, and queries the first delay time corresponding to the determined number of rising delay unit stages and the second delay time corresponding to the determined number of falling delay unit stages, thereby calculating the time interval between the rising and falling edges of the measurement pulse signal. Thus, the time-to-digital conversion device disclosed in this application has a simple circuit structure, eliminating the need for a complex double-chain delay chain circuit structure, which can save a lot of resources or costs. Furthermore, it first converts the timing start signal and timing stop signal into measurement pulse signals through a signal conversion module. Then, through the cooperation of the delay chain module, register module, edge detection module, and calculation module, the time interval between the rising and falling edges of the measurement pulse signal is measured. Therefore, for measurement pulse signals with small pulse widths, measurement can be performed. For pulse widths with large pulse widths, instead of using the delay module to receive the timing start signal, the register module collects the level state of the timing start signal according to the timing stop signal. Therefore, even if the delay level is limited, an invalid timing start signal will not be collected using the timing stop signal, resulting in advantages such as accurate measurement.

[0101] The present invention also discloses a time-to-digital conversion method, which can be applied to the aforementioned time-to-digital conversion device.

[0102] Please see Figure 13 The diagram shown is a flowchart of the time-to-digital conversion method of the present invention in one embodiment.

[0103] like Figure 13 As shown, the time-to-digital conversion method of the present invention includes the following steps: In step S201, the signal conversion module converts the timing start signal and timing stop signal into a measurement pulse signal.

[0104] The time interval between the timing start signal and the timing stop signal is consistent with the pulse width of the measurement pulse signal.

[0105] The timing start signal can use either a rising edge or a falling edge, and the timing stop signal can also use either a rising edge or a falling edge, thus allowing for different implementation methods.

[0106] Taking the rising edge of both the timing start signal and the timing stop signal as an example, the signal conversion module converts the rising edges of the timing start signal and the timing stop signal into a measurement pulse signal. The pulse width of the measurement pulse signal is consistent with the time interval between the occurrence of the timing start signal and the occurrence of the timing stop signal. In other words, the pulse width of the measurement pulse signal is consistent with the time interval between the occurrence of the rising edge of the timing start signal and the occurrence of the rising edge of the timing stop signal.

[0107] In step S203, multiple delay units electrically connected in the delay chain module sequentially delay the received measurement pulse signal, and multiple registers electrically connected in the register module collect and temporarily store the signal state of the corresponding delay unit according to each clock signal.

[0108] The signal state characterizes the delay state of the measurement pulse signal after passing through the delay unit under the current clock signal.

[0109] In step S205, the edge detection module detects the rising and falling edges of the measurement pulse signal based on the temporarily stored signal state obtained from the register module, and determines the number of rising delay unit stages corresponding to the rising edge and the number of falling delay unit stages corresponding to the falling edge in the measurement pulse signal based on the detection results of the rising and falling edges of the measurement pulse signal.

[0110] In some embodiments, the edge detection module detects whether the temporarily stored signal state obtained from the register module has a first transition state, which may be, for example, a transition from low to high. When the first transition state exists, the signal state includes a rising edge, and a first flag is used to mark the delay unit corresponding to the register corresponding to the rising edge of the signal state. Similarly, the edge detection module detects whether the temporarily stored signal state obtained from the register module has a second transition state, which may be, for example, a transition from high to low. When the second transition state exists, the signal state includes a falling edge, and a second flag is used to mark the delay unit corresponding to the register corresponding to the falling edge of the signal state.

[0111] Furthermore, the edge detection module determines the number of rising delay unit stages corresponding to the rising edge and the number of falling delay unit stages corresponding to the falling edge in the measurement pulse signal based on the detection results of the rising and falling edges. Specifically, the number of rising delay unit stages corresponding to the rising edge in the measurement pulse signal is the number of delay unit stages corresponding to the first mark, and the number of falling delay unit stages corresponding to the falling edge in the measurement pulse signal is the number of delay unit stages corresponding to the second mark.

[0112] In some embodiments, the number of each delay unit is stored in a delay time storage module. The storage address of the delay time storage module corresponds to the number of delay units in the delay chain module. The Nth storage address in the delay time storage module stores the delay time corresponding to the Nth delay unit number, and the delay time corresponding to the Nth delay unit number is the sum of the delay times of the 1st to the Nth delay units, where N is a positive integer greater than or equal to 1.

[0113] In step S207, the calculation module calculates the time interval between the rising edge and the falling edge of the measurement pulse signal based on the number of clock signal cycles between the rising edge and the falling edge of the measurement pulse signal detected by the edge detection module, and queries the first delay time corresponding to the determined rising delay unit stage and the second delay time corresponding to the falling delay unit stage.

[0114] Based on the above embodiments, the present invention also discloses a chip, which includes the aforementioned time-to-digital conversion device.

[0115] In some embodiments, the chip may be, for example, a field-programmable gate array (FPGA) chip or other similar chip.

[0116] It should be noted that the time-to-digital conversion method disclosed in the above embodiments and the time-to-digital conversion device disclosed in the above embodiments belong to the same concept. The specific ways in which the relevant modules and units perform operations in each step have been described in detail in the device embodiments, and will not be repeated here.

[0117] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A time-to-digital conversion device, characterized in that, include: Signal conversion module, delay chain module, register module, edge detection module, and calculation module; The signal conversion module converts the timing start signal and timing stop signal into a measurement pulse signal. The time interval between the occurrence of the timing start signal and the occurrence of the timing stop signal is consistent with the pulse width of the measurement pulse signal. The delay chain module is electrically connected to the signal conversion module, and the delay chain module includes multiple delay units that are electrically connected; the multiple delay units that are electrically connected are used to sequentially delay the received measurement pulse signal; The register module is electrically connected to the delay chain module, and the register module includes multiple electrically connected registers. The registers correspond to the delay units. The registers collect and temporarily store the signal state of the corresponding delay unit according to each clock signal. The signal state represents the delay state of the measurement pulse signal passing through the delay unit under the current clock signal. The edge detection module is electrically connected to the register module. The edge detection module detects the rising edge and falling edge of the measurement pulse signal based on the temporarily stored signal state obtained from the register module, and determines the number of rising delay unit stages corresponding to the rising edge and the number of falling delay unit stages corresponding to the falling edge in the measurement pulse signal based on the detection results of the rising edge and falling edge of the measurement pulse signal. as well as The calculation module is electrically connected to the edge detection module. The calculation module calculates the time interval between the rising edge and the falling edge of the measurement pulse signal based on the number of clock signal cycles between the rising edge and the falling edge of the measurement pulse signal detected by the edge detection module, and queries the first delay time corresponding to the determined rising delay unit stage and the second delay time corresponding to the falling delay unit stage.

2. The time-to-digital conversion device according to claim 1, characterized in that, The signal conversion module includes a latch unit; the latch unit includes an RS latch circuit.

3. The time-to-digital conversion device according to claim 1, characterized in that, The signal conversion module includes a latch unit, which includes an OR gate, an inverter, and a transmission gate circuit. The inverter includes a first inverter, a second inverter, and a third inverter, and the transmission gate includes a first transmission gate and a second transmission gate; The first input of the OR gate receives the timing start signal, the second input of the OR gate receives the timing stop signal, the output of the OR gate is connected to the input of the first inverter, and the output of the OR gate is connected to the first control terminal of the first transmission gate and the second control terminal of the second transmission gate. The output of the first inverter is connected to the second control terminal of the first transmission gate and the first control terminal of the second transmission gate. The timing stop signal is input to the input of the first transmission gate. The output of the first transmission gate is connected to the input of the second transmission gate and the input of the second inverter. The output of the second inverter is connected to the input of the third inverter. The output of the second transmission gate is connected to the output of the third inverter.

4. The time-to-digital conversion device according to claim 1, characterized in that, The edge detection module includes a rising edge detection unit and a falling edge detection unit; The rising edge detection unit detects whether the temporarily stored signal state obtained from the register module has a first transition state. When the first transition state exists, the signal state includes a rising edge, and a first mark is used to mark the signal position corresponding to the rising edge of the signal state. The falling edge detection unit detects whether the temporarily stored signal state obtained from the register module has a second transition state. When the second transition state exists, the signal state includes a falling edge, and a second mark is used to mark the signal position corresponding to the falling edge of the signal state. The first transition state and the second transition state respectively represent different signal change states.

5. The time-to-digital conversion device according to claim 4, characterized in that, The edge detection module further includes a decoding unit. The calculation module is electrically connected to the decoding unit. The decoding unit queries the number of delay units corresponding to the first mark as the number of rising delay units corresponding to the rising edge in the measurement pulse signal, and queries the number of delay units corresponding to the second mark as the number of falling delay units corresponding to the falling edge in the measurement pulse signal.

6. The time-to-digital conversion device according to claim 1, characterized in that, Also includes: Calibration module and delay time storage module; The calibration module is electrically connected to the edge detection module, and the calibration module measures the delay time of each delay unit in the delay chain module; The delay time storage module is electrically connected to the calibration module and the calculation module. The delay time storage module stores the measurement results of the delay time of each delay unit in the delay chain module by the calibration module. The calculation module queries the delay time corresponding to the determined first delay time of the rising delay unit level and the second delay time corresponding to the falling delay unit level from the delay time storage module.

7. The time-to-digital conversion device according to claim 6, characterized in that, The storage address of the delay time storage module corresponds to the level of the delay unit. The Nth storage address in the delay time storage module stores the delay time corresponding to the Nth delay unit level. The delay time corresponding to the Nth delay unit level is the sum of the delay times of the 1st delay unit to the Nth delay unit, where N is a positive integer greater than or equal to 1.

8. The time-to-digital conversion device according to claim 1 or 7, characterized in that, The calculation module includes a clock counting unit. When the edge detection module detects the rising edge of the measurement pulse signal, the clock counting unit starts and records the period of the clock signal. When the edge detection module detects the falling edge of the measurement pulse signal, the clock counting unit stops. The period of the clock signal recorded by the clock counting unit is taken as the period number n of the clock signal. The time interval between the rising and falling edges of the measurement pulse signal is calculated using the following formula: T = n T clk +ΔT1 -ΔT2 Where T represents the time interval between the rising and falling edges of the measurement pulse signal, T clk Let T represent the period of each clock signal, and let T be the period of the clock signal. clk The delay time is less than the sum of the delay time of the delay chain modules, where n represents the number of clock signal cycles used between the detection of the rising edge of the measurement pulse signal and the detection of the falling edge of the measurement pulse signal by the edge detection module, and n≥0, ΔT1 represents the first delay time corresponding to the rising delay unit stage, and ΔT2 represents the second delay time corresponding to the falling delay unit stage.

9. A time-to-digital conversion method, characterized in that, Includes the following steps: The signal conversion module converts the timing start signal and the timing stop signal into a measurement pulse signal. The time interval between the occurrence of the timing start signal and the occurrence of the timing stop signal is consistent with the pulse width of the measurement pulse signal. Multiple delay units electrically connected in the delay chain module sequentially delay the received measurement pulse signal, and multiple registers electrically connected in the register module collect and temporarily store the signal state of the corresponding delay unit according to each clock signal. The signal state represents the delay state of the measurement pulse signal after passing through the delay unit under the current clock signal. The edge detection module detects the rising edge and falling edge of the measurement pulse signal based on the temporarily stored signal state obtained from the register module, and determines the number of rising delay unit stages corresponding to the rising edge and the number of falling delay unit stages corresponding to the falling edge in the measurement pulse signal based on the detection results of the rising edge and falling edge of the measurement pulse signal. as well as The calculation module calculates the time interval between the rising and falling edges of the measurement pulse signal based on the number of clock signal cycles between the rising edge and the falling edge of the measurement pulse signal detected by the edge detection module, and queries the first delay time corresponding to the determined rising delay unit stage and the second delay time corresponding to the falling delay unit stage.

10. A chip, characterized in that, Includes the time-to-digital conversion device as described in any one of claims 1 to 8.

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