A simulation circuit for a Turing machine

Abstract

This invention discloses a Turing machine simulation circuit, belonging to the field of computer science. It includes: multiple Turing machine simulation circuit units; each Turing machine simulation circuit unit includes: an input terminal for receiving input data; a first register for storing data from the input terminal or a second register; a state transition circuit for obtaining the state data of the Turing machine at the next moment based on data from the first register of its own or adjacent Turing machine simulation circuit unit; a second register for storing data from the state transition circuit; and an output terminal for connecting to a display device to display data from the second register; wherein the first register, the state transition circuit, and the second register are connected in series between the input terminal and the output terminal; the output terminal of the second register is coupled to the input terminal of the first register. This invention achieves Turing machine simulation at a relatively low cost.

Description

Technical Field

[0001] This invention belongs to the field of computer science and relates to a simulation circuit for a Turing machine. Background Technology

[0002] Turing machines are among the simplest computable models. Their concept first appeared in a paper published by mathematician A. Turing in 1936-1937. They can implement any given algorithm through the design of their state transition mechanisms. Turing machines are the standard computational model in university courses related to computability theory, so the computational process of Turing machines is frequently demonstrated in teaching. However, manufacturing a complete Turing machine containing all its components would be extremely costly and bulky, making it impractical for classroom teaching. Therefore, a device that can easily be demonstrated in the classroom and simulate a Turing machine is urgently needed. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a simulation circuit for a Turing machine, which realizes the simulation of a Turing machine at low cost.

[0004] To achieve the above objectives, the present invention is implemented using the following technical solution:

[0005] This invention provides a Turing machine simulation circuit, comprising: multiple Turing machine simulation circuit units; each Turing machine simulation circuit unit includes:

[0006] The input terminal is used to receive input data;

[0007] The first register is used to store data from the input terminal or the second register;

[0008] The state transition circuit is used to obtain the state data of the Turing machine at the next moment based on the data from the first register of the Turing machine simulation circuit unit where it is located or adjacent.

[0009] The second register is used to store data from the state transition circuit;

[0010] The output terminal is used to connect to a display device to display data from the second register;

[0011] The first register, the state transition circuit, and the second register are connected in series between the input and output terminals; the output terminal of the second register is coupled to the input terminal of the first register; and the state transition circuit is coupled to the output terminal of the first register of the adjacent Turing machine simulation circuit unit.

[0012] Furthermore, it also includes a clock module, which provides clock signals to the first and second registers of the plurality of Turing machine simulation circuit units.

[0013] Furthermore, the clock signal input terminal of the first register is equipped with an NOT gate.

[0014] Furthermore, the number of Turing machine simulation circuit units is greater than or equal to 3.

[0015] Furthermore, both the first register and the second register are composed of flip-flops.

[0016] Furthermore, the trigger includes a D trigger.

[0017] Furthermore, the Turing machine simulation circuit unit also includes a multiplexer, which is disposed between the input terminal and the first register; the output terminal of the second register is coupled to the input terminal of the first register through the multiplexer.

[0018] Furthermore, it also includes a selection circuit, which is sequentially coupled to the multiplexer input terminals of the plurality of Turing machine simulation circuit units to transmit a selection signal to the multiplexer;

[0019] When the selection signal is 1, the multiplexer transmits the input data from the input terminal to the first register; when the selection signal is 0, the multiplexer transmits the output data from the second register to the first register.

[0020] Furthermore, the state transition circuit includes a programmable gate array (FPGA).

[0021] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0022] The Turing machine simulation circuit provided by this invention uses multiple parallel Turing machine simulation circuit units to simulate the writing, erasing, or modification of data on the read / write tape by the Turing machine's read / write head. A clock module provides a synchronous clock signal to the first and second registers, ensuring the stability and continuity of data input and output. The read / write head position and Turing machine state are encoded into the first and second registers, eliminating the need for an additional storage module. This invention's Turing machine simulation circuit has a simple structure, small size, and low cost, making it suitable for classroom teaching and other similar applications. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a Turing machine model;

[0024] Figure 2 This is a schematic diagram of the simulation circuit of the Turing machine provided in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the area affected by the Turing machine's read / write head.

[0026] Figure 4 This is a schematic diagram of Turing machine encoding;

[0027] Figure 5 This is a schematic diagram of the operation flow of the simulation circuit of the Turing machine provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The same reference numerals in the drawings indicate the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. The embodiments and specific features within the embodiments of this application are detailed descriptions of the technical solution of this application, and not limitations thereof. Where there is no conflict, the embodiments and technical features within the embodiments of this application can be combined with each other.

[0029] The term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. The terms "center," "longitudinal," "lateral," "up," "down," "front," "back," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only used to explain the relative positional relationship and movement between components in a specific orientation. If the specific orientation changes, the directional indication will also change accordingly. This is only for the convenience of describing this application and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure / application.

[0030] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0031] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0032] The device structure of a Turing machine is as follows: Figure 1 As shown, it includes a read / write tape, a read / write head, a read / write head moving device, a controller, and a support. The read / write tape, composed of linear cells, is used to display the written data and its length must be sufficient for program execution. The read / write head is used to write, erase, or modify data on the read / write tape. The read / write head control device is used to move the read / write head left or right. The controller is used to control the read / write operations of the read / write head, move the read / write head, and convert and record the current state of the Turing machine.

[0033] The Turing machine operates as follows: It starts from a certain position on the paper tape (initial position), reads the symbol in the current cell, and performs calculations using the state transition function based on the current state and the read symbol. According to the state transition function, the Turing machine may change its current state, write a new symbol, or move its head one cell to the left or right. The above steps are repeated.

[0034] like Figure 2 As shown, this embodiment of the invention provides a simulation circuit for a Turing machine, including multiple Turing machine simulation circuit units.

[0035] The Turing machine simulation circuit unit includes an input terminal, a first register, a state transition circuit, a second register, and an output terminal that are connected in series. The state transition circuit is coupled to the output terminal of the first register of the adjacent Turing machine simulation circuit unit, and the output terminal of the second register is coupled to the input terminal of the first register.

[0036] The input terminal is used to connect to the data input device to receive input data. The input terminal is used to simulate the cells of the Turing machine's read / write tape. The input data received by the input terminal is equivalent to the initial data on the cells of the Turing machine's read / write tape.

[0037] The output is used to connect to a display device to show the Turing machine's computation, including displaying the data on the cells of the read / write tape.

[0038] The first register is used to store data from the input terminal or data from the second register.

[0039] The Turing machine simulation circuit unit of the present invention further includes a multiplexer disposed between the input terminal and the first register, and the output terminal of the second register is coupled to the input terminal of the first register through the multiplexer.

[0040] The Turing machine simulation circuit of the present invention also includes a selection circuit, which is sequentially coupled to the input terminals of the multiplexers of all the Turing machine simulation circuit units in the present invention to transmit a selection signal to the multiplexers. The selection signal output is 0 or 1. When the selection signal is 1, the multiplexer transmits the input data of the input terminal to the first register coupled to it; when the selection signal is 0, the multiplexer ignores the input terminal signal and transmits the output data of the second register to the first register coupled to it.

[0041] The state transition circuit is used to obtain the state data of the Turing machine at the next moment based on the data from the first register of the Turing machine simulation circuit unit in which it is located or adjacent.

[0042] In this embodiment of the invention, the state transition circuit element is composed of a Field Programmable Gate Array (FPGA) with erasable and rewritable capabilities, which facilitates modification of the simulated Turing machine algorithm. The function of the state transition circuit is to obtain the data on the Turing machine's read / write band at the current moment from the first register, convert it into the data on the Turing machine's read / write band at the next moment, and store it in the second register.

[0043] The data at the input and output terminals can be encoded according to specific needs. Whenever an encoding method is determined, the state transition circuit needs to be updated to adapt to this encoding method.

[0044] The Turing machine's computation process exhibits locality of reference; in each step of the computation, the Turing machine can only modify the data in the cell where its read / write head is located and move to neighboring cells. For example... Figure 3 The diagram illustrates the layout of a Turing machine during a specific computation. The black cells represent the locations of the read / write heads. Therefore, after completing this computation, the Turing machine can only influence a limited number of cells. Figure 3 The gray cells are not affected by changes in data, nor do they become the location of the read / write head. Therefore, the state transition circuit of this invention only needs to be coupled to the first register of itself and the Turing machine simulation circuit units on both sides to complete the calculation of the corresponding cell data.

[0045] In other embodiments of the invention, if it is necessary to manufacture a simulation circuit for a Turing machine read / write band length greater than 3 cells, it is only necessary to repeat... Figure 2 The component layout pattern allows for the setting of more Turing machine simulation circuit units.

[0046] The second register is used to store data from the state transition circuit.

[0047] The location of the Turing machine's read / write head and its current state can be encoded into the cell containing the read / write head's location. For example... Figure 4The diagram illustrates the layout of a Turing machine during a computation. The black cells represent the location of the read / write head, and the Turing machine is currently in state A. Therefore, the read / write head position and the Turing machine state can be encoded into the black cells as "#A,1". This invention encodes the read / write head position and the Turing machine state into the first and second registers, thus eliminating the need for an additional storage module to store these parameters.

[0048] The Turing machine simulation circuit unit of the present invention also includes a clock module, which is used to provide a synchronous clock signal for the first register and the second register of all Turing machine simulation circuit units in the present invention, so as to control the data output of the first register and the second register and ensure the accuracy, stability and continuity of data transmission.

[0049] In this embodiment of the invention, both the first register and the second register are composed of D flip-flops (DFFs), which are triggered on the rising edge of the clock. The clock signal input of the first register is equipped with an NOT gate. The second register receives the CLK signal, and the first register receives the inverted ^CLK signal. The first register and the second register update data at different times.

[0050] Figure 5 This is a schematic diagram of the operation flow of the Turing machine simulation circuit in this embodiment of the invention. After data is input through the input terminal, a cyclical calculation process of "first register - state transition circuit - second register" begins. Since the second register is connected to the clock signal CLK, and the first register is connected to the clock signal ^CLK, this cycle can be completed within one clock cycle. The output terminal continuously outputs the data in the second register, and the connected external device can monitor and display the calculation process accordingly.

[0051] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of this disclosure / application.

Claims

1. A simulation circuit for a Turing machine, characterized in that, include: Multiple Turing machine simulation circuit units; the Turing machine simulation circuit units include: The input terminal is used to receive input data; The first register is used to store data from the input terminal or the second register; The state transition circuit is used to obtain the state data of the Turing machine at the next moment based on the data from the first register of the Turing machine simulation circuit unit where it is located or adjacent. The second register is used to store data from the state transition circuit; The output terminal is used to connect to a display device to display data from the second register; The first register, the state transition circuit, and the second register are connected in series between the input and output terminals; the output terminal of the second register is coupled to the input terminal of the first register; and the state transition circuit is coupled to the output terminal of the first register of the adjacent Turing machine simulation circuit unit.

2. The simulation circuit for the Turing machine according to claim 1, characterized in that, It also includes a clock module, which provides clock signals to the first and second registers of the plurality of Turing machine simulation circuit units.

3. The simulation circuit for the Turing machine according to claim 2, characterized in that, The clock signal input terminal of the first register is equipped with an NOT gate.

4. The simulation circuit for the Turing machine according to claim 1, characterized in that, The number of Turing machine simulation circuit units is greater than or equal to 3.

5. The simulation circuit for the Turing machine according to claim 1, characterized in that, Both the first register and the second register are composed of flip-flops.

6. The simulation circuit for the Turing machine according to claim 5, characterized in that, The trigger includes a D trigger.

7. The simulation circuit for the Turing machine according to claim 1, characterized in that, The Turing machine simulation circuit unit also includes a multiplexer, which is disposed between the input terminal and the first register; the output terminal of the second register is coupled to the input terminal of the first register through the multiplexer.

8. The simulation circuit for the Turing machine according to claim 7, characterized in that, It also includes a selection circuit, which is sequentially coupled to the multiplexer input of the plurality of Turing machine simulation circuit units to transmit a selection signal to the multiplexer; When the selection signal is 1, the multiplexer transmits the input data from the input terminal to the first register; When the selection signal is 0, the multiplexer passes the output data of the second register to the first register.

9. The simulation circuit for the Turing machine according to claim 1, characterized in that, The state transition circuit includes a programmable gate array (FPGA).

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