Display device and driving method

Abstract

A display device and driving method are provided, including: a display panel (100); a driving circuit (200) electrically connected to the display panel (100); the driving circuit (200) is configured to control each photosensitive element in the photosensitive area of ​​the display panel (100) to collect incident light intensity signals when each sub-pixel in the photosensitive area of ​​the display panel (100) is in a non-light-emitting state during the light-emitting phase of a set display frame.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to display devices and driving methods. Background Technology

[0002] In displays such as Organic Light-Emitting Diode (OLED), there are typically multiple pixel units. Each pixel unit can include multiple subpixels of different colors. By controlling the brightness of each subpixel, the desired colors are mixed to display a color image. Summary of the Invention

[0003] The display device provided in this disclosure includes:

[0004] Display panel;

[0005] A driving circuit, which is electrically connected to the display panel;

[0006] The driving circuit is configured to control each photosensitive element in the photosensitive area of ​​the display panel to collect the incident light intensity signal when each sub-pixel in the photosensitive area is in a non-light-emitting state during the light-emitting phase of a set display frame.

[0007] In some possible implementations, the display panel includes a first region and a second region arranged sequentially along the column direction of the sub-pixels, the first region including the photosensitive region;

[0008] The driving circuit is further configured to control each photosensitive element in the photosensitive area to collect the incident light intensity signal when each sub-pixel in the first region is in a non-light-emitting state during the light-emitting phase of the set display frame.

[0009] In some possible implementations, the driving circuit is further configured to control the light emission control signal corresponding to each sub-pixel in the first region to have an invalid pulse of a first duration during the light emission phase, so that each sub-pixel in the first region is in a non-light emission state during the light emission phase.

[0010] The level of the invalid pulse of the light emission control signal is used to control the light emission control transistor in the display panel to turn off, and the first duration is longer than the duration of the non-light emission phase of one of the sub-pixels, the non-light emission phase occurring before the light emission phase.

[0011] In some possible implementations, during the light emission phase, the light emission control signal has at least one invalid pulse.

[0012] One of the at least one invalid pulses is an invalid pulse having the first duration.

[0013] In some possible implementations, when the light emission control signal has multiple invalid pulses during the light emission phase, the invalid pulse with the longest duration among the multiple invalid pulses is the invalid pulse with the first duration.

[0014] In some possible implementations, the driving circuit is further configured to stop outputting light emission control signals to each sub-pixel in the second region during the set display frame.

[0015] In some possible implementations, the driving circuit is further configured to control the light emission control signal corresponding to each sub-pixel in the second region to have an invalid pulse of a second duration during the light emission phase in the set display frame, so that each sub-pixel in the second region is in a non-light emission state during the light emission phase.

[0016] Wherein, the invalid pulses with the first duration and the invalid pulses with the second duration are invalid pulses that appear in the same order in the light emission control signal, and the first duration is longer than the second duration.

[0017] In some possible implementations, the driving circuit is further configured to control the same light emission control signal for each sub-pixel in the first region and the second region in all display frames other than the set display frame.

[0018] In some possible implementations, the display panel further includes: a first light-emitting control circuit and a second light-emitting control circuit; wherein the first light-emitting control circuit is electrically connected to a sub-pixel in the first region, and the second light-emitting control circuit is electrically connected to a sub-pixel in the second region;

[0019] The driving circuit is further configured to control the first light-emitting control circuit to output a corresponding light-emitting control signal to the sub-pixels in the first region, and to control the second light-emitting control circuit to output a corresponding light-emitting control signal to the sub-pixels in the second region.

[0020] In some possible implementations, each of a plurality of adjacent display frames is the designated display frame;

[0021] And / or, at least two of the adjacent display frames are the set display frames, and at least one other display frame other than the set display frame is spaced between two adjacent set display frames.

[0022] In some possible implementations, when at least two of the adjacent display frames are the designated display frames, the driving circuit is further configured to control the input of zero grayscale data voltage to each sub-pixel in the photosensitive area in the designated display frames.

[0023] In some possible implementations, when at least two of the adjacent display frames are the designated display frames, the driving circuit is further configured to control each sub-pixel in the remaining area of ​​the display panel to be in a data voltage holding state during the designated display frames.

[0024] In some possible implementations, the driving circuit is further configured to control the input of corresponding grayscale data voltages to each sub-pixel in the display panel in the remaining display frames other than the set display frame.

[0025] In some possible implementations, the driving circuit is further configured to control the input of corresponding grayscale data voltages to each sub-pixel of the display panel in each of the plurality of display frames.

[0026] This disclosure also provides a driving method, including:

[0027] When each sub-pixel in the photosensitive area of ​​the display panel is in a non-light-emitting state during the light-emitting phase of a set display frame, each photosensitive element in the photosensitive area is controlled to collect the incident light intensity signal.

[0028] In some possible implementations, the display panel includes a first region and a second region arranged sequentially along the column direction of the sub-pixels, the first region including the photosensitive region;

[0029] The control of each sub-pixel in the photosensitive area of ​​the display panel to be in a non-light-emitting state during the light-emitting phase of a set display frame includes:

[0030] The light emission control signal corresponding to each sub-pixel in the first region is controlled to have an invalid pulse of a first duration during the light emission phase, so that each sub-pixel in the first region is in a non-light emission state during the light emission phase;

[0031] The level of the invalid pulse of the light emission control signal is used to control the light emission control transistor in the display panel to turn off, and the first duration is longer than the duration of the non-light emission phase of one of the sub-pixels, the non-light emission phase occurring before the light emission phase.

[0032] In some possible implementations, the light emission control signal has at least one invalid pulse during the light emission phase;

[0033] One of the at least one invalid pulses is an invalid pulse having the first duration.

[0034] In some possible implementations, when the light emission control signal has multiple invalid pulses during the light emission phase, the invalid pulse with the longest duration among the multiple invalid pulses is the invalid pulse with the first duration.

[0035] In some possible implementations, it further includes: during the set display frame, controlling the light emission control signal corresponding to each sub-pixel in the second region to have an invalid pulse of a second duration during the light emission phase, so that each sub-pixel in the second region is in a non-light emission state during the light emission phase;

[0036] Wherein, the invalid pulses with the first duration and the invalid pulses with the second duration are invalid pulses that appear in the same order in the light emission control signal, and the first duration is longer than the second duration.

[0037] In some possible implementations, the method further includes: in display frames other than the set display frame, the control signals for controlling the light emission of each sub-pixel in the first region and the second region are the same.

[0038] In some possible implementations, each of a plurality of adjacent display frames is the designated display frame;

[0039] And / or, at least two of the adjacent display frames are the set display frames, and at least one other display frame other than the set display frame is spaced between two adjacent set display frames.

[0040] In some possible implementations, when at least two of the adjacent display frames are the set display frames, the driving method further includes: controlling each sub-pixel in the photosensitive area to input a zero-grayscale data voltage in the set display frame.

[0041] In some possible implementations, when at least two of the adjacent display frames are the set display frames, the driving method further includes: in the set display frames, controlling each sub-pixel in the remaining area of ​​the display panel to be in a data voltage holding state.

[0042] In some possible implementations, the method further includes controlling each sub-pixel in the display panel to input a corresponding grayscale data voltage in the remaining display frames other than the set display frame.

[0043] In some possible implementations, the method further includes: in each of the plurality of display frames, controlling each sub-pixel of the display panel to input a corresponding grayscale data voltage. Attached Figure Description

[0044] Figure 1 Schematic diagrams of some display devices provided in embodiments of this disclosure;

[0045] Figure 2a These are schematic diagrams of the structure of some display panels provided in embodiments of this disclosure;

[0046] Figure 2b Schematic cross-sectional view of some display panels provided in embodiments of this disclosure;

[0047] Figure 3 This is a schematic diagram of the structure of some pixel circuits provided in the embodiments of this disclosure;

[0048] Figure 4 Some signal timing diagrams provided for embodiments of this disclosure;

[0049] Figure 5 Further signal timing diagrams provided for embodiments of this disclosure;

[0050] Figure 6a A schematic diagram of some display frames provided for embodiments of this disclosure;

[0051] Figure 6b A schematic diagram of some further display frames provided in embodiments of this disclosure;

[0052] Figure 7 A cross-sectional structural schematic diagram of some other display panels provided in embodiments of this disclosure;

[0053] Figure 8 A cross-sectional structural schematic diagram of some other display panels provided in embodiments of this disclosure;

[0054] Figure 9 A cross-sectional structural schematic diagram of some other display panels provided in embodiments of this disclosure;

[0055] Figure 10 A cross-sectional structural schematic diagram of some other display panels provided in embodiments of this disclosure;

[0056] Figure 11 A cross-sectional structural schematic diagram of some other display panels provided in embodiments of this disclosure;

[0057] Figure 12 Further signal timing diagrams provided for embodiments of this disclosure;

[0058] Figure 13 Further signal timing diagrams provided for embodiments of this disclosure;

[0059] Figure 14 This is a schematic diagram of some further display frames provided for embodiments of this disclosure. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0061] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0062] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0063] In some embodiments, such as Figure 1 As shown, the display device may include a display panel 100 and a driving circuit 200. The driving circuit 200 is electrically connected to the display panel 100 and can drive the display panel to operate. Exemplarily, the driving circuit 200 may take the form of an embodiment combining software and hardware aspects. For example, the driving circuit 200 may be an integrated circuit (IC).

[0064] For example, such as Figure 2a and Figure 2bAs shown, a display device typically includes multiple layers of different structures. For example, it may include a top cover layer 110 composed of a glass cover plate, a display layer composed of a display panel 100, a transparent protective layer 120 composed of a protective film, and a shielding layer 130 composed of adhesive and foam, etc. In this embodiment, an aperture ALSK may be provided in the shielding layer 130, and a photosensitive element array formed by multiple photosensitive elements may be provided in the aperture ALSK. Furthermore, the area of ​​the display panel 100 corresponding to the aperture ALSK can be a photosensitive area ALSB.

[0065] For example, when adjusting the brightness of the display panel based on the photosensitive element array, the photosensitive element array can be an ambient light sensor (ALS) array.

[0066] For example, when implementing photo taking and video recording functions based on the photosensitive element array, the photosensitive element array can be a photodetector array in a camera.

[0067] For example, when implementing fingerprint recognition functionality based on the photosensitive element array, the photosensitive element array can be a fingerprint recognition detector array.

[0068] For example, the display panel 100 may include a display area and a non-display area surrounding the display area, the display area including a plurality of pixel units arranged in an array. Optionally, each pixel unit includes multiple sub-pixels of different colors. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, so that red, green, and blue can be mixed to achieve color display. Alternatively, a pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, so that red, green, blue, and white can be mixed to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0069] For example, if the photosensitive area is located in the display area, then pixel units are also provided in the photosensitive area, and pixel units are also provided in the remaining areas of the display area other than the photosensitive area. Optionally, in order to improve transmittance, the density of pixel units in the photosensitive area can be made lower than the density of pixel units in the remaining areas.

[0070] Electroluminescent diodes, such as Organic Light Emitting Diodes (OLEDs), Quantum Dot Light Emitting Diodes (QLEDs), Micro Light Emitting Diodes (Micro LEDs), and Mini LEDs, have advantages such as self-illumination and low energy consumption. In specific implementations, the display panel in this disclosure embodiment can be an electroluminescent display panel. In this disclosure embodiment, each sub-pixel may include an electroluminescent diode and pixel circuitry for driving the electroluminescent diode to emit light. Exemplarily, the electroluminescent diode may include at least one of OLED, QLED, Micro LED, and Mini LED. Furthermore, the pixel circuitry generally includes transistors and capacitors.

[0071] For example, such as Figure 3 As shown, the pixel circuit 10 may include: a driving transistor M0, a data writing transistor M1, a first reset transistor M2, a second reset transistor M3, a threshold compensation transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, and a storage capacitor CST. The cathode of the electroluminescent diode L is electrically connected to the second power supply terminal ELVSS.

[0072] For example, the gate of driving transistor M0 is electrically connected to node N1, the first terminal of driving transistor M0 is electrically connected to node N2, and the third terminal of driving transistor M0 is electrically connected to node N3. For example, as Figure 3 As shown, the driving transistor M0 can be configured as a P-type transistor; its first terminal can be its source, and its second terminal can be its drain. Of course, the driving transistor M0 can also be configured as an N-type transistor; this is not a limitation here.

[0073] Exemplarily, the gate of the data writing transistor M1 is electrically connected to the first scan signal terminal GA_P, the first terminal of the data writing transistor M1 is electrically connected to the data signal terminal, and the second terminal of the data writing transistor M1 is electrically connected to node N2. Exemplarily, the data writing transistor M1 is turned on under the control of the level of the valid pulse of the first scan signal at the first scan signal terminal GA_P, and turned off under the control of the invalid level of the first scan signal. Optionally, as... Figure 3 As shown, the data writing transistor M1 can be configured as a P-type transistor, in which case the level of the valid pulse of the first scan signal is low and the level of the invalid pulse is high. Alternatively, the data writing transistor can be configured as an N-type transistor, in which case the level of the valid pulse of the first scan signal is high and the level of the invalid pulse is low.

[0074] Exemplarily, the gate of the first reset transistor M2 is electrically connected to the first reset signal terminal RE_N, the first terminal of the first reset transistor M2 is electrically connected to the first initialization signal terminal VINIT1, and the second terminal of the first reset transistor M2 is electrically connected to node N1. Exemplarily, the first reset transistor M2 is turned on under the control of the level of the valid pulse of the first reset signal at the first reset signal terminal RE_N, and turned off under the control of the invalid level of the first reset signal. Optionally, as... Figure 3 As shown, the first reset transistor M2 can be configured as an N-type transistor, in which case the effective pulse level of the first reset signal is high and the invalid pulse level is low. Alternatively, the first reset transistor can be configured as a P-type transistor, in which case the effective pulse level of the first reset signal is low and the invalid pulse level is high.

[0075] Exemplarily, the gate of the second reset transistor M3 is electrically connected to the second reset signal terminal RE_P, the first terminal of the second reset transistor M3 is electrically connected to the second initialization signal terminal VINIT2, and the second terminal of the second reset transistor M3 is electrically connected to the anode of the electroluminescent diode L. Exemplarily, the second reset transistor M3 is turned on under the control of the effective pulse level of the second reset signal at the second reset signal terminal RE_P, and turned off under the control of the ineffective level of the second reset signal. Optionally, as... Figure 3 As shown, the second reset transistor M3 can be configured as a P-type transistor, in which case the effective pulse level of the second reset signal is low, and the invalid pulse level is high. Alternatively, the second reset transistor can be configured as an N-type transistor, in which case the effective pulse level of the second reset signal is high, and the invalid pulse level is low.

[0076] Exemplarily, the gate of the threshold compensation transistor M4 is electrically connected to the second scan signal terminal GA_N, the first terminal of the threshold compensation transistor M4 is electrically connected to node N1, and the second terminal of the threshold compensation transistor M4 is electrically connected to node N3. Exemplarily, the threshold compensation transistor M4 is turned on under the control of the level of the effective pulse of the second scan signal at the second scan signal terminal GA_N, and turned off under the control of the ineffective level of the second scan signal. Optionally, as... Figure 3 As shown, the threshold compensation transistor M4 can be set as an N-type transistor, in which case the level of the valid pulse of the second scan signal is high and the level of the invalid pulse is low. Alternatively, the threshold compensation transistor can be set as a P-type transistor, in which case the level of the valid pulse of the second scan signal is low and the level of the invalid pulse is high.

[0077] Exemplarily, the gate of the first light-emitting control transistor M5 is electrically connected to the light-emitting control signal terminal EM, the first terminal of the first light-emitting control transistor M5 is electrically connected to the first power supply terminal ELVDD, and the second terminal of the first light-emitting control transistor M5 is electrically connected to node N2. Exemplarily, the first light-emitting control transistor M5 is turned on under the control of the effective pulse level of the light-emitting control signal at the light-emitting control signal terminal EM, and turned off under the control of the ineffective pulse level of the light-emitting control signal. Optionally, as... Figure 3 As shown, the first light-emitting control transistor M5 can be configured as a P-type transistor, in which case the effective pulse level of the light-emitting control signal is low, and the invalid level is high. Alternatively, the first light-emitting control transistor can be configured as an N-type transistor, in which case the effective pulse level of the light-emitting control signal is high, and the invalid level is low.

[0078] Exemplarily, the gate of the second light-emitting control transistor M6 is electrically connected to the light-emitting control signal terminal EM, the first terminal of the second light-emitting control transistor M6 is electrically connected to node N3, and the second terminal of the second light-emitting control transistor M6 is electrically connected to the anode of the electroluminescent diode L. Exemplarily, the second light-emitting control transistor M6 is turned on under the control of an effective pulse level of the light-emitting control signal at the light-emitting control signal terminal EM, and turned off under the control of an ineffective pulse level of the light-emitting control signal. Optionally, as... Figure 3 As shown, the second light-emitting control transistor M6 can be configured as a P-type transistor, in which case the effective pulse level of the light-emitting control signal is low, and the ineffective level is high. Alternatively, the second light-emitting control transistor can be configured as an N-type transistor, in which case the effective pulse level of the light-emitting control signal is high, and the ineffective level is low.

[0079] The first electrode plate of the storage capacitor CST is electrically connected to node N1, and the second electrode plate of the storage capacitor CST is electrically connected to the first power supply terminal ELVDD.

[0080] In some embodiments of this disclosure, the first power supply terminal ELVDD can be configured to apply a constant first power supply voltage, which is generally positive. Similarly, the second power supply terminal ELVSS can apply a constant second power supply voltage, which is generally ground voltage or negative. In practical applications, the specific values ​​of the first and second power supply voltages can be designed and determined according to the actual application environment, and are not limited herein.

[0081] In some embodiments of this disclosure, the first terminal of the transistor can be used as its source and the second terminal as its drain, depending on the type of transistor and the signal of its gate; or, conversely, the first terminal of the transistor can be used as its drain and the second terminal as its source. This can be designed and determined according to the actual application environment, and no specific distinction is made here.

[0082] The above are merely examples illustrating the specific structure of the pixel circuit provided in the embodiments of this disclosure. In specific implementations, the pixel circuit is not limited to the structure provided in the embodiments of this disclosure, but may also be other structures known to those skilled in the art. These are all within the protection scope of this disclosure and are not specifically limited here.

[0083] In some examples, the following are... Figure 3 Taking the pixel circuit structure shown as an example, combined with Figure 4 The signal timing diagram shown describes the operation of the pixel circuit provided in this embodiment within a display frame. The diagram primarily selects... Figure 4 The signal timing diagram shown illustrates the non-light-emitting phase T0 and the light-emitting phase T4 within a display frame.

[0084] Where T4 represents the light-emitting stage, and the non-light-emitting stage T0 includes the reset stage T1, the data writing stage T2, and the initialization stage T3. Here, re_n represents the first reset signal loaded onto the first reset signal terminal RE_N, ga_n represents the second scan signal loaded onto the second scan signal terminal GA_N, ga_p represents the first scan signal loaded onto the first scan signal terminal GA_P, re_p represents the second reset signal loaded onto the second reset signal terminal RE_P, and em represents the light-emitting control signal loaded onto the light-emitting control signal terminal EM.

[0085] During the reset phase T1, the first reset transistor M2 is turned on, and the first initialization voltage of the first initialization signal terminal VINIT1 is input to node N1 to reset node N1. During this phase, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned off, and the electroluminescent diode L does not emit light.

[0086] During the data writing phase T2, data writing transistor M1 and threshold compensation transistor M4 are turned on. The data voltage Vda applied to the data signal terminal DA is input to node N2 and charges node N1 through the driving transistor M0, which forms a diode connection, causing the voltage of node N1 to change to Vda + Vth. Here, Vth represents the threshold voltage of driving transistor M0. During this phase, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned off, and the electroluminescent diode L does not emit light.

[0087] During the initialization phase T3, the second reset transistor M3 is turned on, and the second initialization voltage of the second initialization signal terminal VINIT2 is input to the anode of the electroluminescent diode L to initialize the anode of the electroluminescent diode L. During this phase, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned off, and the electroluminescent diode L does not emit light.

[0088] During the light-emitting stage T4, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are turned on. The voltage at node N2 becomes the first power supply voltage Velvdd, while the voltage at node N1 remains Vda + Vth, driving transistor M0 to generate a current IL. Furthermore, IL = k(Vda - Velvdd). 2 Where k is a structural parameter. Current IL is input to the electroluminescent diode L, driving the electroluminescent diode L to emit light.

[0089] Combination Figure 4 As shown, based on the operation of this pixel circuit in a display frame, it can be seen that the sub-pixel first enters a non-light-emitting phase T0, followed by a light-emitting phase T4 within the time of a display frame. In other words, the time of a display frame includes the non-light-emitting phase T0 and the light-emitting phase T4.

[0090] In practical applications, the driving circuit typically controls the photosensitive element to acquire light intensity signals during the non-light-emitting phase (i.e., the phase from the start of reset phase T1 to the end of initialization phase T3) when the first invalid pulse (such as the pulse corresponding to a high level) of the light-emitting control signal appears. For example, Figure 4 As shown, als0 represents the acquisition control signal that controls the photosensitive element. When the emission control signal EM is high, the acquisition control signal als0 is also high, controlling the photosensitive element to acquire light intensity signals. However, the rising and falling edges of the first invalid pulse of the emission control signal EM are delayed, resulting in a short period of time for the acquisition control signal als0 to be high. This fails to provide the photosensitive element with sufficient time to acquire light intensity signals, reducing the accuracy of the acquired light intensity signals.

[0091] To improve the accuracy of the light intensity signal collected by the photosensitive element, embodiments of this disclosure use a driving circuit to control each sub-pixel in the photosensitive area to be in a non-light-emitting state during the light-emitting phase of a set display frame. While each sub-pixel in the photosensitive area is in a non-light-emitting state during the light-emitting phase of the set display frame, each photosensitive element in the photosensitive area is controlled to collect the incident light intensity signal. By controlling each sub-pixel in the photosensitive area to be in a non-light-emitting state during the light-emitting phase of the set display frame, the duration of the non-light-emitting state of each sub-pixel in the photosensitive area can be adjusted. For example, by extending the duration of the non-light-emitting state of each sub-pixel in the photosensitive area, each photosensitive element can be controlled to collect the incident light intensity signal during this duration, enabling the photosensitive element to effectively collect the light intensity signal and improving the accuracy of the collected light intensity signal. For example, as... Figure 5 As shown, als1 represents the acquisition control signal that controls the photosensitive device. When each sub-pixel in the photosensitive area is in a non-light-emitting state during the light-emitting stage T4 of the set display frame, the acquisition control signal als1 is set to a high level, thereby controlling each photosensitive element to acquire light intensity signals.

[0092] For example, when the photosensitive element array is an ambient light sensor (ALS) array, the incident light intensity signal collected by the photosensitive elements can be an ambient light signal. This allows the display panel's brightness to be adjusted based on the collected ambient light signal. In this embodiment, because the accuracy of the collected light intensity signal can be improved, the accuracy of the collected ambient light signal can be improved, thereby improving the accuracy of adjusting the display panel's brightness and achieving automatic adjustment of the display panel's brightness.

[0093] For example, when the photosensitive element array can be a photodetector array in a camera, the functions of taking pictures and recording videos can be realized based on the collected light intensity signal. In this embodiment of the disclosure, the clarity of pictures and videos can be improved because the accuracy of the collected light intensity signal can be increased.

[0094] For example, when the photosensitive element array can be a fingerprint recognition detector array, the incident light intensity signal collected by the photosensitive element can be the light intensity signal reflected by the finger. This allows for fingerprint recognition based on the collected light intensity signal reflected by the finger. In this embodiment, because the accuracy of the collected light intensity signal can be improved, the accuracy of the collected light intensity signal reflected by the finger can be improved, thereby increasing the overall accuracy.

[0095] In this embodiment of the disclosure, a sub-pixel being in a non-light-emitting state means that the sub-pixel does not emit light, and the electroluminescent diode in the sub-pixel does not emit light.

[0096] In some embodiments of this disclosure, such as Figure 2a As shown, the display panel may include a first region aa1 and a second region aa2 arranged sequentially along the column direction of sub-pixels. The first region aa1 includes a photosensitive region ALSB. The driving circuit is further configured to control each photosensitive element in the photosensitive region to collect the incident light intensity signal when each sub-pixel in the first region aa1 is in a non-light-emitting state during the light-emitting phase of a set display frame. This allows adjustment of the duration during which each sub-pixel in the first region aa1 is in a non-light-emitting state. For example, by extending the duration during which each sub-pixel in the first region aa1 is in a non-light-emitting state, the photosensitive element can be controlled to collect the incident light intensity signal during this duration, enabling the photosensitive element to effectively collect the light intensity signal and improving the accuracy of the collected light intensity signal.

[0097] For example, the light emission control signal can have an invalid pulse during the light emission phase to control the sub-pixels not to emit light. In a specific implementation, the driving circuit is further configured to control the light emission control signal corresponding to each sub-pixel in the first region aa1 to have an invalid pulse of a first duration during the light emission phase, so that each sub-pixel in the first region aa1 is in a non-light emission state during the light emission phase. The level of the invalid pulse of the light emission control signal is used to control the light emission control transistor in the display panel to turn off, and the first duration is longer than the duration of the non-light emission phase of a sub-pixel, with the non-light emission phase occurring before the light emission phase. This prolongs the duration during which each sub-pixel in the first region aa1 is in a non-light emission state, thereby controlling each photosensitive element to collect the incident light intensity signal during this duration, enabling the photosensitive element to effectively collect the light intensity signal and improving the accuracy of the collected light intensity signal.

[0098] For example, combining Figure 5 As shown, em1 represents the light emission control signal corresponding to the sub-pixel in the first region aa1. The invalid pulse level (e.g., high level) of the light emission control signal em1 is used to control the light emission control transistors (e.g., the first light emission control transistor M5 and the second light emission control transistor M6) in the first region aa1 to turn off. The invalid pulse (e.g., the pulse corresponding to the high level) in the light emission stage T4 is used to control the light emission control transistors (e.g., the first light emission control transistor M5 and the second light emission control transistor M6) in the first region aa1 to turn off, so that the sub-pixels in the first region aa1 are in a non-light emission state during the light emission stage T4. Furthermore, the first maintenance duration WT1 is greater than the maintenance duration WT0 of the non-light emission stage of a sub-pixel. This can prolong the duration during which each sub-pixel in the first region aa1 is in a non-light emission state, thereby controlling each photosensitive element to collect the incident light intensity signal during this duration, enabling the photosensitive element to effectively collect the light intensity signal and improving the accuracy of the collected light intensity signal.

[0099] For example, such as Figure 5 As shown, in the set display frame, the light emission control signal em1 corresponding to the sub-pixel in the first region aa1 can have an invalid pulse (e.g., a high-level invalid pulse) in the light emission stage T4. This invalid pulse is an invalid pulse with a first duration.

[0100] In some embodiments of this disclosure, each of a plurality of adjacent display frames can be a designated display frame. For example, as Figure 6a As shown, taking 11 adjacent display frames FA1 to FA11 as an example, each of these 11 display frames FA1 to FA11 is set as a set display frame FAS.

[0101] In some embodiments of this disclosure, at least two of a plurality of adjacent display frames may be designated display frames, and at least one other display frame may be spaced between two adjacent designated display frames. For example, one other display frame may be spaced between two adjacent designated display frames. Figure 6b As shown, taking 11 adjacent display frames FA1 to FA11 as an example, display frames FA2, FA4, FA6, FA8 and FA10 are the set display frames FAS, and display frames FA1, FA3, FA5, FA7, FA9 and FA11 are the remaining display frames other than the set display frames.

[0102] In some embodiments of this disclosure, the driving circuit is further configured to control each sub-pixel in the display panel to input corresponding grayscale data voltages in the remaining display frames (excluding the designated display frame), thereby controlling the display panel to perform the image display function. Exemplarily, for these remaining display frames (such as display frames FA1, FA3, FA5, FA7, FA9, and FA11), the driving circuit can be based on... Figure 4 The signal timing diagram shown includes a first reset signal re_n, a second reset signal re_p, a first scan signal ga_p, a second scan signal ga_n, and a light emission control signal em. These signals drive each sub-pixel in the display panel to complete one display frame, thereby displaying the image. In a specific implementation, the driving circuit is further configured to control the light emission control signals corresponding to each sub-pixel in the first region aa1 and the second region aa2 to be the same in all display frames except the set display frame.

[0103] In some embodiments of this disclosure, the driving circuit is further configured to control the input of corresponding grayscale data voltages to each sub-pixel in the first and second regions of the display panel during a set display frame. Exemplarily, during a set display frame, the driving circuit may be based on... Figure 5 The signal timing diagram shown illustrates how the data voltage of each sub-pixel in the first area aa1 of the display panel is input to the corresponding grayscale level to complete one display frame. Furthermore, the driving circuit can be based on... Figure 4 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em in the signal timing diagram shown drive each sub-pixel in the second area aa2 of the display panel to input the corresponding grayscale data voltage, thus performing the working process of one display frame.

[0104] Since Vda in the gate voltage Vda+Vth of the driving transistor M0 is a zero-grayscale data voltage, the current IL generated by the driving transistor M0 is minimized. This current IL is insufficient to drive the electroluminescent diode L to emit light, thus allowing the sub-pixels in the photosensitive area to be in a non-emitting state directly during the light-emitting stage. In some embodiments of this disclosure, when there are at least two set display frames among adjacent display frames, the driving circuit is further configured to control the input of a zero-grayscale data voltage to each sub-pixel in the photosensitive area during the set display frames.

[0105] In some embodiments of this disclosure, when there are at least two set display frames among a plurality of adjacent display frames, the driving circuit is further configured to control each sub-pixel in the photosensitive area to input a zero-grayscale data voltage in the set display frame. Alternatively, the driving circuit is further configured to control each sub-pixel in the photosensitive area to input a corresponding grayscale data voltage in the set display frame. Furthermore, the driving circuit is further configured to control each sub-pixel in the areas other than the photosensitive area to input a corresponding grayscale data voltage in the set display frame, or to control each sub-pixel in the areas other than the photosensitive area to maintain a data voltage.

[0106] Furthermore, when there are at least two designated display frames among a plurality of adjacent display frames, the driving circuit is further configured to control each sub-pixel in the first region to input a zero-grayscale data voltage in the designated display frame. Alternatively, the driving circuit is further configured to control each sub-pixel in the first region to input a corresponding grayscale data voltage in the designated display frame. And, the driving circuit is further configured to control each sub-pixel in the second region to input a corresponding grayscale data voltage in the designated display frame, or to control each sub-pixel in the second region to maintain a data voltage.

[0107] For example, in setting the display frame, the driving circuit can be based on Figure 5 The signal timing diagram shown includes a first reset signal re_n, a second reset signal re_p, a first scan signal ga_p, a second scan signal ga_n, and an emissive control signal em1. These signals drive each sub-pixel of the first area aa1 of the display panel to input the corresponding grayscale data voltage or zero grayscale data voltage, thus completing the operation of one display frame. Furthermore, the driving circuit can be based on... Figure 4 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em in the signal timing diagram shown drive each sub-pixel of the second area aa2 of the display panel to input the corresponding grayscale data voltage, thus performing the working process of one display frame.

[0108] For example, in the display frames other than the set display frame, the driving circuit can be based on Figure 4The signal timing diagram shown includes a first reset signal re_n, a second reset signal re_p, a first scan signal ga_p, a second scan signal ga_n, and an emissive control signal em. These signals drive the data voltage of the corresponding grayscale level input to each sub-pixel of the first area aa1 of the display panel, performing the operation of one display frame. Furthermore, the driving circuit can be based on... Figure 4 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em in the signal timing diagram shown drive each sub-pixel of the second area aa2 of the display panel to input the corresponding grayscale data voltage, thus performing the working process of one display frame.

[0109] For example, during the setting of a display frame, the driving circuit controls each sub-pixel in the second region of the display panel to maintain a data voltage state. Optionally, the corresponding data voltage may not be input to the sub-pixels in the second region, thereby keeping each sub-pixel in the second region in a data voltage-maintaining state and reducing power consumption. For example, during the setting of a display frame, the driving circuit may be based on... Figure 5 The signal timing diagram shown illustrates the process of driving each sub-pixel in the first area aa1 of the display panel to complete one display frame. Additionally, the driving circuit stops outputting light-emitting control signals to each sub-pixel in the second area aa2. This reduces power consumption. Furthermore, the driving circuit also stops outputting the first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, and the second scan signal ga_n to each sub-pixel in the second area aa2. This controls the sub-pixels in the remaining areas of the display panel to maintain data voltage, further reducing power consumption.

[0110] In some embodiments of this disclosure, such as Figure 7 As shown, the display area of ​​the display panel 100 also includes multiple light emission control signal lines EMS. The light emission control signal terminal EM of the pixel circuit in a row of sub-pixels is electrically connected to a light emission control signal line EMS so as to input the corresponding light emission control signal to the electrically connected light emission control signal terminal EM through the light emission control signal line EMS.

[0111] In some embodiments of this disclosure, such as Figure 7 As shown, the non-display area of ​​the display panel also includes a first light-emitting control circuit 310 and a second light-emitting control circuit 320. The first light-emitting control circuit 310 is electrically connected to the light-emitting control signal line EMS in the first region aa1, thereby electrically connecting the first light-emitting control circuit 310 to the sub-pixels in the first region aa1. Furthermore, the second light-emitting control circuit 320 is electrically connected to the light-emitting control signal line EMS in the second region aa2, thereby electrically connecting the second light-emitting control circuit 320 to the sub-pixels in the second region aa2.

[0112] In some embodiments of this disclosure, the driving circuit is further configured to control the first light-emitting control circuit 310 to output a corresponding light-emitting control signal to the sub-pixels in the first region aa1, and to control the second light-emitting control circuit 320 to output a corresponding light-emitting control signal to the sub-pixels in the second region aa2.

[0113] In some embodiments of this disclosure, such as Figure 8 As shown, the display area of ​​the display panel 100 also includes multiple first reset signal lines RES_N. The first reset signal terminal RE_N of the pixel circuit in a row of sub-pixels is electrically connected to a first reset signal line RES_N so as to input a corresponding first reset signal to the electrically connected first reset signal terminal through the first reset signal line RES_N.

[0114] In some embodiments of this disclosure, such as Figure 8 As shown, the non-display area of ​​the display panel also includes a first reset control circuit 410 and a second reset control circuit 420. The first reset control circuit 410 is electrically connected to the first reset signal line RES_N in the first region aa1, thereby electrically connecting the first reset control circuit 410 to the sub-pixels in the first region aa1. Furthermore, the second reset control circuit 420 is electrically connected to the first reset signal line RES_N in the second region aa2, thereby electrically connecting the second reset control circuit 420 to the sub-pixels in the second region aa2.

[0115] In some embodiments of this disclosure, the driving circuit is further configured to control the first reset control circuit 410 to output a corresponding first reset signal to the sub-pixels in the first region aa1, and to control the second reset control circuit 420 to output a corresponding first reset signal to the sub-pixels in the second region aa2.

[0116] In some embodiments of this disclosure, such as Figure 9 As shown, the display area of ​​the display panel 100 also includes multiple second reset signal lines RES_P. The second reset signal terminal RE_P of the pixel circuit in a row of sub-pixels is electrically connected to a second reset signal line RES_P so as to input the corresponding second reset signal to the electrically connected second reset signal terminal through the second reset signal line RES_P.

[0117] In some embodiments of this disclosure, such as Figure 9As shown, the non-display area of ​​the display panel also includes a third reset control circuit 510 and a fourth reset control circuit 520. The third reset control circuit 510 is electrically connected to the second reset signal line RES_P in the first area aa1, thereby electrically connecting the third reset control circuit 510 to the sub-pixels in the first area aa1. Furthermore, the fourth reset control circuit 520 is electrically connected to the second reset signal line RES_P in the second area aa2, thereby electrically connecting the fourth reset control circuit 520 to the sub-pixels in the second area aa2.

[0118] In some embodiments of this disclosure, the driving circuit is further configured to control the third reset control circuit 510 to output a corresponding second reset signal to the sub-pixels in the first region aa1, and to control the fourth reset control circuit 520 to output a corresponding second reset signal to the sub-pixels in the second region aa2.

[0119] In some embodiments of this disclosure, such as Figure 10 As shown, the display area of ​​the display panel 100 also includes multiple first scan signal lines GA_P. The first scan signal terminal GA_P of the pixel circuit in a row of sub-pixels is electrically connected to a first scan signal line GA_P so as to input the corresponding first scan signal to the electrically connected first scan signal terminal GA_P through the first scan signal line GA_P.

[0120] In some embodiments of this disclosure, such as Figure 10 As shown, the non-display area of ​​the display panel also includes a first scan control circuit 610 and a second scan control circuit 620. The first scan control circuit 610 is electrically connected to the first scan signal line GA_P in the first region aa1, thereby electrically connecting the first scan control circuit 610 to the sub-pixels in the first region aa1. Furthermore, the second scan control circuit 620 is electrically connected to the first scan signal line GA_P in the second region aa2, thereby electrically connecting the second scan control circuit 620 to the sub-pixels in the second region aa2.

[0121] In some embodiments of this disclosure, the driving circuit is further configured to control the first scanning control circuit 610 to output a corresponding first scanning signal to the sub-pixels in the first region aa1, and to control the second scanning control circuit 620 to output a corresponding first scanning signal to the sub-pixels in the second region aa2.

[0122] In some embodiments of this disclosure, such as Figure 11 As shown, the display area of ​​the display panel 100 also includes multiple second scan signal lines GA_N. The second scan signal terminal GA_N of the pixel circuit in a row of sub-pixels is electrically connected to a second scan signal line GA_N so as to input the corresponding second scan signal to the electrically connected second scan signal terminal GA_N through the second scan signal line GA_N.

[0123] In some embodiments of this disclosure, such as Figure 11 As shown, the non-display area of ​​the display panel also includes a third scan control circuit 710 and a fourth scan control circuit 720. The third scan control circuit 710 is electrically connected to the second scan signal line GA_N in the first region aa1, thereby electrically connecting the third scan control circuit 710 to the sub-pixels in the first region aa1. Furthermore, the fourth scan control circuit 720 is electrically connected to the second scan signal line GA_N in the second region aa2, thereby electrically connecting the fourth scan control circuit 720 to the sub-pixels in the second region aa2.

[0124] In some embodiments of this disclosure, the driving circuit is further configured to control the third scan control circuit 710 to output a corresponding second scan signal to the sub-pixels in the first region aa1, and to control the fourth scan control circuit 720 to output a corresponding second scan signal to the sub-pixels in the second region aa2.

[0125] In some embodiments of this disclosure, the display area also includes multiple data lines, which can electrically connect the data signal terminals of the pixel circuits in one column of sub-pixels to one data line. Of course, the data signal terminals of the pixel circuits in two columns of sub-pixels can also be electrically connected to one data line, and this is not limited thereto.

[0126] For example, in setting the display frame, the driving circuit can be based on Figure 5 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em1 shown drive the corresponding transistors in the sub-pixels of the first region aa1 in the display panel. Furthermore, the driving circuit also controls the input of zero-grayscale data voltage to the data lines connected to the sub-pixels in the photosensitive area, and does not input data voltage to the other data lines. For example, the driving circuit can control the first reset control circuit 410 to output a signal such as... Figure 5 The first reset signal re_n shown controls the third reset control circuit 510 to output the following to the sub-pixels in the first region aa1: Figure 5 The second reset signal re_p shown controls the first scan control circuit 610 to output the following to the sub-pixels in the first region aa1: Figure 5 The first scan signal ga_p shown controls the third scan control circuit 710 to output the following to the sub-pixels in the first region aa1: Figure 5 The second reset signal re_n shown, and the control circuit 310 to output to the sub-pixels in the first region aa1, as shown Figure 5 The light emission control signal em1 is shown.

[0127] For example, during the set display frame, the driving circuit can control the second reset control circuit 420 to stop outputting the first reset signal, control the fourth reset control circuit 520 to stop outputting the second reset signal, control the second scan control circuit 620 to stop outputting the first scan signal, control the fourth scan control circuit 720 to stop outputting the second scan signal, and control the second light emission control circuit 320 to stop outputting the light emission control signal. Furthermore, the driving circuit also controls the input of data voltage to all data lines. This allows the second area aa2 to maintain its original data voltage during the set display frame, thereby maintaining the original display image and reducing the power consumption of the display panel.

[0128] For example, in setting the display frame, the driving circuit can also be based on Figure 4 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em shown drive the corresponding transistors in the sub-pixels of the second region aa2 in the display panel. Furthermore, the driving circuit also controls the input of data voltage to all data lines, so that the second region aa2 maintains its original data voltage in the set display frame, thereby maintaining the original display image. Alternatively, it can control the input of corresponding grayscale data voltage to all data lines, thereby displaying a new image. For example, the driving circuit can control the second reset control circuit 420 to output as shown in the image to the sub-pixels of the second region aa2. Figure 4 The first reset signal re_n shown controls the fourth reset control circuit 520 to output the following to the sub-pixels in the second region aa2: Figure 4 The second reset signal re_p shown controls the second scan control circuit 620 to output the following to the sub-pixels in the second region aa2: Figure 4 The first scan signal ga_p shown controls the fourth scan control circuit 720 to output the following to the sub-pixels in the second region aa2: Figure 4 The second reset signal re_n shown, and the control circuit 320 for the second light emission control circuit to output to the sub-pixels in the second region aa2, as shown Figure 4 The light emission control signal em is shown.

[0129] For example, in the display frames other than the set display frame, the driving circuit can also be based on Figure 4 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em shown drive the transistors in the sub-pixels of the first region aa1 and the second region aa2 in the display panel. Furthermore, the driving circuit also controls the input of corresponding grayscale data voltages to all data lines for image display. For example, the driving circuit can control the first reset control circuit 410 to output a signal such as... Figure 4The first reset signal re_n shown controls the third reset control circuit 510 to output the following to the sub-pixels in the first region aa1: Figure 4 The second reset signal re_p shown controls the first scan control circuit 610 to output the following to the sub-pixels in the first region aa1: Figure 4 The first scan signal ga_p shown controls the third scan control circuit 710 to output the following to the sub-pixels in the first region aa1: Figure 4 The second reset signal re_n shown, and the control circuit 310 to output to the sub-pixels in the first region aa1, as shown Figure 4 The light emission control signal em is shown. Furthermore, the driving circuit can control the second reset control circuit 420 to output the following signal to the sub-pixels in the second region aa2: Figure 4 The first reset signal re_n shown controls the fourth reset control circuit 520 to output the following to the sub-pixels in the second region aa2: Figure 4 The second reset signal re_p shown controls the second scan control circuit 620 to output the following to the sub-pixels in the second region aa2: Figure 4 The first scan signal ga_p shown controls the fourth scan control circuit 720 to output the following to the sub-pixels in the second region aa2: Figure 4 The second reset signal re_n shown, and the control circuit 320 for the second light emission control circuit to output to the sub-pixels in the second region aa2, as shown Figure 4 The light emission control signal em is shown.

[0130] Of course, all first reset signal lines can also be electrically connected to a reset control circuit, all second reset signal lines can also be electrically connected to another reset control circuit, all first scan signal lines can also be electrically connected to a scan control circuit, and all second scan signal lines can also be electrically connected to another scan control circuit; this is not limited here.

[0131] This disclosure provides further signal timing diagrams, such as... Figure 12 and Figure 13 As shown, this embodiment is a variation of the implementation described in the above embodiments. The following only describes the differences between this embodiment and the above embodiments; the similarities will not be repeated here.

[0132] In this embodiment of the disclosure, the light emission control signal has multiple invalid pulses during the light emission phase. For example, Figure 12 and Figure 13As shown, the light emission control signal has two invalid pulses during the light emission phase. Of course, the light emission control signal can have three, four, or more invalid pulses during the light emission phase; this is not limited here. This allows the light emission control signal to be set as a pulse width modulation (PWM) signal, which controls the brightness of the electroluminescent diode L, improving the display effect of the display panel. In other words, when the light emission control signal is set as a PWM signal, invalid pulses in the light emission phase can be multiplexed and extended to control the photosensitive element to collect light intensity signals during these invalid pulses.

[0133] In this embodiment of the disclosure, one of the plurality of invalid pulses in the light emission control signal during the light emission phase is an invalid pulse with a first duration. Further, the invalid pulse with the longest duration among the plurality of invalid pulses is the invalid pulse with the first duration. For example, as... Figure 13 As shown, the light emission control signal em1 has two invalid pulses during the light emission stage T4. The invalid pulse with the longest duration among the two invalid pulses is the invalid pulse with a first duration WT1.

[0134] In some embodiments of this disclosure, the driving circuit is further configured to control the input of corresponding grayscale data voltages to each sub-pixel in the display panel in display frames other than the set display frame. For example, in display frames other than the set display frame, the driving circuit can, for these other display frames (such as display frames FA1, FA3, FA5, FA7, FA9, and FA11), base its control on... Figure 12 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em in the signal timing diagram shown drive each sub-pixel in the display panel to perform a display frame operation to achieve image display. That is, the driving circuit is further configured to control the light emission control signals corresponding to each sub-pixel in the first region aa1 and the second region aa2 to be the same in all display frames except the set display frame.

[0135] In some embodiments of this disclosure, the driving circuit is further configured to control each sub-pixel of the display panel to input a corresponding grayscale data voltage in each of the remaining display frames, so as to achieve image display. That is, in each of the remaining display frames, the driving circuit controls each sub-pixel of the display panel to input a corresponding grayscale data voltage. Exemplarily, in a set display frame, the driving circuit can be based on... Figure 13The signal timing diagram shown includes a first reset signal re_n, a second reset signal re_p, a first scan signal ga_p, a second scan signal ga_n, and a light emission control signal em1, which drive each sub-pixel of the first area aa1 of the display panel to perform one display frame operation. Furthermore, the driving circuit can be based on... Figure 12 The signal timing diagram shown includes a first reset signal re_n, a second reset signal re_p, a first scan signal ga_p, a second scan signal ga_n, and an emissive control signal em, which drive each sub-pixel of the second area aa2 of the display panel to perform one display frame. In the remaining display frames, the driving circuit can be based on... Figure 13 The signal timing diagram shown includes a first reset signal re_n, a second reset signal re_p, a first scan signal ga_p, a second scan signal ga_n, and a light emission control signal em1, which drive each sub-pixel of the first area aa1 of the display panel to perform one display frame operation. Furthermore, the driving circuit can be based on... Figure 12 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em in the signal timing diagram shown drive each sub-pixel of the second area aa2 of the display panel to perform the operation of one display frame.

[0136] For example, combined Figure 12 and Figure 13 As shown, the driving circuit is further configured to control the light emission control signal em corresponding to each sub-pixel in the second region aa2 to have an invalid pulse with a second duration WT2 during the light emission phase in a set display frame, so that each sub-pixel in the second region aa2 is in a non-light emission state during the light emission phase. The invalid pulses with the first duration WT1 and the second duration WT2 are invalid pulses that appear in the same order in the light emission control signal (for example, the invalid pulses with the first duration WT1 and the invalid pulses with the second duration WT2 are both invalid pulses that appear for the first time during the light emission phase), and the first duration WT1 is greater than the second duration WT2.

[0137] In some embodiments of this disclosure, when there are at least two set display frames in a plurality of adjacent display frames, the driving circuit is further configured to control each sub-pixel in the photosensitive area to input a zero-grayscale data voltage in the set display frame. Since Vda in the gate voltage Vda+Vth of the driving transistor M0 is a zero-grayscale data voltage, the current IL generated by the driving transistor M0 is minimized. This current IL is insufficient to drive the electroluminescent diode L to emit light, thus allowing the sub-pixels in the photosensitive area to be in a non-emitting state directly during the light-emitting stage. Further, when there are at least two set display frames in a plurality of adjacent display frames, the driving circuit is further configured to control each sub-pixel in the remaining areas of the display panel to be in a data-holding voltage state in the set display frame. Exemplarily, the corresponding data voltage may not be input to the sub-pixels in the remaining areas, so that the sub-pixels in the remaining areas are in a data-holding voltage state, reducing power consumption. For example, in the set display frame, the driving circuit may be based on Figure 13 The signal timing diagram shown illustrates the process of driving each sub-pixel in the first area aa1 of the display panel to complete one display frame. Additionally, the driving circuit stops outputting light-emitting control signals to each sub-pixel in the second area aa2. This reduces power consumption. Furthermore, the driving circuit also stops outputting the first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, and the second scan signal ga_n to each sub-pixel in the second area aa2. This controls the sub-pixels in the remaining areas of the display panel to maintain data voltage, further reducing power consumption.

[0138] For example, in setting the display frame, the driving circuit can be based on Figure 13 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em1 shown drive the transistors in the sub-pixels of the first region aa1 in the display panel. Furthermore, the driving circuit also controls the input of zero-grayscale data voltage to the data lines connected to the sub-pixels in the photosensitive area, and does not input data voltage to the other data lines. For example, the driving circuit can control the first reset control circuit 410 to output a signal such as... Figure 13 The first reset signal re_n shown controls the third reset control circuit 510 to output the following to the sub-pixels in the first region aa1: Figure 13 The second reset signal re_p shown controls the first scan control circuit 610 to output the following to the sub-pixels in the first region aa1: Figure 13 The first scan signal ga_p shown controls the third scan control circuit 710 to output the following to the sub-pixels in the first region aa1: Figure 13 The second reset signal re_n shown, and the control circuit 310 to output to the sub-pixels in the first region aa1, as shown Figure 13 The light emission control signal em1 is shown.

[0139] For example, during the setting of the display frame, the driving circuit can control the second reset control circuit 420 to stop outputting the first reset signal, control the fourth reset control circuit 520 to stop outputting the second reset signal, control the second scan control circuit 620 to stop outputting the first scan signal, control the fourth scan control circuit 720 to stop outputting the first and second scan signals, and control the second light-emitting control circuit 320 to stop outputting the light-emitting control signal. Furthermore, the driving circuit also controls the input of data voltage to all data lines. This reduces the power consumption of the display panel.

[0140] For example, in setting the display frame, the driving circuit can also be based on Figure 12 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em shown drive the transistors in the sub-pixels of the second region aa2 in the display panel. Furthermore, the driving circuit also controls whether to input data voltage to all data lines or to input corresponding grayscale data voltage to all data lines. For example, the driving circuit can control the second reset control circuit 420 to output, for example, data voltage of the corresponding grayscale level to the sub-pixels of the second region aa2. Figure 12 The first reset signal re_n shown controls the fourth reset control circuit 520 to output the following to the sub-pixels in the second region aa2: Figure 12 The second reset signal re_p shown controls the second scan control circuit 620 to output the following to the sub-pixels in the second region aa2: Figure 12 The first scan signal ga_p shown controls the fourth scan control circuit 720 to output the following to the sub-pixels in the second region aa2: Figure 12 The second reset signal re_n shown, and the control circuit 320 for the second light emission control circuit to output to the sub-pixels in the second region aa2, as shown Figure 12 The light emission control signal em is shown.

[0141] For example, in the display frames other than the set display frame, the driving circuit can also be based on Figure 12 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em shown drive the transistors in the sub-pixels of the first region aa1 and the second region aa2 in the display panel. Furthermore, the driving circuit also controls the input of corresponding grayscale data voltages to all data lines. For example, the driving circuit can control the first reset control circuit 410 to output, for example, data voltages to the sub-pixels in the first region aa1. Figure 12 The first reset signal re_n shown controls the third reset control circuit 510 to output the following to the sub-pixels in the first region aa1: Figure 12The second reset signal re_p shown controls the first scan control circuit 610 to output the following to the sub-pixels in the first region aa1: Figure 12 The first scan signal ga_p shown controls the third scan control circuit 710 to output the following to the sub-pixels in the first region aa1: Figure 12 The second reset signal re_n shown, and the control circuit 310 to output to the sub-pixels in the first region aa1, as shown Figure 12 The light emission control signal em is shown. Furthermore, the driving circuit can control the second reset control circuit 420 to output the following signal to the sub-pixels in the second region aa2: Figure 12 The first reset signal re_n shown controls the fourth reset control circuit 520 to output the following to the sub-pixels in the second region aa2: Figure 12 The second reset signal re_p shown controls the second scan control circuit 620 to output the following to the sub-pixels in the second region aa2: Figure 12 The first scan signal ga_p shown controls the fourth scan control circuit 720 to output the following to the sub-pixels in the second region aa2: Figure 12 The second reset signal re_n shown, and the control circuit 320 for the second light emission control circuit to output to the sub-pixels in the second region aa2, as shown Figure 12 The light emission control signal em is shown.

[0142] In some embodiments of this disclosure, the driving circuit can control the light emission control signal corresponding to each sub-pixel in the first region aa1 to have an invalid pulse with a first duration WT1 during the light emission phase, so that each sub-pixel in the first region aa1 is in a non-light emission state during the light emission phase, and control each photosensitive element in the photosensitive area to collect the incident light intensity signal. Taking the photosensitive element array as an ambient light sensor (ALS) array as an example, the ambient light brightness can be determined according to the light intensity signal collected by each photosensitive element, and the display brightness of the display panel can be adjusted according to the determined ambient light brightness.

[0143] For example, such as Figure 13 As shown, als1 represents the acquisition control signal that controls the photosensitive device. When each sub-pixel in the photosensitive area is in a non-light-emitting state during the light-emitting stage T4 of the set display frame, the acquisition control signal als1 is set to a high level, thereby controlling each photosensitive element to acquire light intensity signals.

[0144] In some embodiments of this disclosure, the driving circuit can further control each sub-pixel in the photosensitive area to first collect the incident light intensity signal when it is in the non-light-emitting stage of a set display frame. The driving circuit can control the light-emitting control signal corresponding to each sub-pixel in the first region aa1 to have an invalid pulse of a first duration WT1 during the light-emitting stage, so that each sub-pixel in the first region aa1 is in a non-light-emitting state during the light-emitting stage, and control each photosensitive element in the photosensitive area to collect the incident light intensity signal a second time. Taking an ambient light sensor (ALS) array as an example, the first collected light intensity signal can be corrected based on the second collected light intensity signal of each photosensitive element to determine the ambient light brightness. That is, the ambient light brightness can be determined based on the first and second collected light intensity signals of each photosensitive element, and the display brightness of the display panel can be adjusted based on the determined ambient light brightness.

[0145] For example, such as Figure 13 As shown, als2 represents the acquisition control signal that controls the photosensitive device. When each sub-pixel in the photosensitive area is in a non-light-emitting state during the non-light-emitting stage (i.e., stages T1 to T3) and the light-emitting stage T4 of the set display frame, the acquisition control signal als2 is set to a high level, thereby controlling each photosensitive element to acquire light intensity signals.

[0146] This disclosure provides further signal timing diagrams, such as... Figure 14 As shown, this embodiment is a variation of the implementation described in the above embodiments. The following only describes the differences between this embodiment and the above embodiments; the similarities will not be repeated here.

[0147] In some embodiments of this disclosure, the driving circuit may also insert an intermediate display frame displaying a black image between two adjacent display frames, so as to control each photosensitive element in the photosensitive area to collect the incident light intensity signal in the intermediate display frame. This allows the photosensitive element to collect the light intensity signal for the duration of a display frame, improving the accuracy of the collected light intensity signal.

[0148] For example, an intermediate display frame is inserted between every two adjacent display frames in a plurality of adjacent display frames. For instance, taking display frames FA1 to FA6 as examples, an intermediate display frame FAM can be inserted between display frames FA1 and FA2, and between display frames FA2 and FA3. The rest are similar and will not be described in detail here.

[0149] Alternatively, an intermediate display frame can be inserted between every three adjacent display frames. Of course, an intermediate display frame can also be inserted between every four, five, or more adjacent display frames; this is not limited to this.

[0150] For example, in an intermediate display frame, the driving circuit can control each sub-pixel in the photosensitive area to display a black image. Optionally, in an intermediate display frame, the driving circuit can control each sub-pixel in the photosensitive area to input a zero-grayscale data voltage, so that each sub-pixel in the photosensitive area displays a black image.

[0151] For example, in the intermediate display frame, the driving circuit can be based on Figure 5 or Figure 13 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em1 shown drive the corresponding transistors in the sub-pixels of the first region aa1 in the display panel. Furthermore, the driving circuit also controls the input of zero-grayscale data voltage to the data lines connected to the sub-pixels in the photosensitive area, and does not input data voltage to the other data lines. For example, the driving circuit can control the first reset control circuit 410 to output a signal such as... Figure 5 or Figure 13 The first reset signal re_n shown controls the third reset control circuit 510 to output the following to the sub-pixels in the first region aa1: Figure 5 or Figure 13 The second reset signal re_p shown controls the first scan control circuit 610 to output the following to the sub-pixels in the first region aa1: Figure 5 or Figure 13 The first scan signal ga_p shown controls the third scan control circuit 710 to output the following to the sub-pixels in the first region aa1: Figure 5 or Figure 13 The second reset signal re_n shown, and the control circuit 310 to output to the sub-pixels in the first region aa1, as shown Figure 5 or Figure 13 The light emission control signal em1 is shown.

[0152] For example, in an intermediate display frame, the driving circuit can control each sub-pixel in the areas other than the photosensitive area to maintain the display of the previous display frame. Optionally, in an intermediate display frame, the driving circuit can control each sub-pixel in the areas other than the photosensitive area to maintain the data voltage of the previous display frame, so that each sub-pixel in the remaining areas maintains the display of the previous display frame, thereby reducing the power consumption of the display panel.

[0153] For example, in the intermediate display frame, the driving circuit can control the second reset control circuit 420 to stop outputting the first reset signal, control the fourth reset control circuit 520 to stop outputting the second reset signal, control the second scan control circuit 620 to stop outputting the first scan signal, control the fourth scan control circuit 720 to stop outputting the second scan signal, and control the second light-emitting control circuit 320 to stop outputting the light-emitting control signal. Furthermore, the driving circuit also controls the input of data voltage to all data lines. This allows the second area aa2 to maintain its original data voltage in the set display frame, thereby maintaining the original display image and reducing the power consumption of the display panel.

[0154] For example, the driving circuit can control the display panel to display a normal image in each display frame. For instance, the driving circuit can be based on... Figure 4 or Figure 12 The first reset signal re_n, the second reset signal re_p, the first scan signal ga_p, the second scan signal ga_n, and the light emission control signal em shown drive the transistors in the sub-pixels of the first region aa1 and the second region aa2 in the display panel. Furthermore, the driving circuit also controls the input of corresponding grayscale data voltages to all data lines for image display. For example, the driving circuit can control the first reset control circuit 410 to output a signal such as... Figure 4 or Figure 12 The first reset signal re_n shown controls the third reset control circuit 510 to output the following to the sub-pixels in the first region aa1: Figure 4 or Figure 12 The second reset signal re_p shown controls the first scan control circuit 610 to output the following to the sub-pixels in the first region aa1: Figure 4 or Figure 12 The first scan signal ga_p shown controls the third scan control circuit 710 to output the following to the sub-pixels in the first region aa1: Figure 4 or Figure 12 The second reset signal re_n shown, and the control circuit 310 to output to the sub-pixels in the first region aa1, as shown Figure 4 or Figure 12 The light emission control signal em is shown. Furthermore, the driving circuit can control the second reset control circuit 420 to output the following signal to the sub-pixels in the second region aa2: Figure 4 or Figure 12 The first reset signal re_n shown controls the fourth reset control circuit 520 to output the following to the sub-pixels in the second region aa2: Figure 4 or Figure 12 The second reset signal re_p shown controls the second scan control circuit 620 to output the following to the sub-pixels in the second region aa2: Figure 4 or Figure 12The first scan signal ga_p shown controls the fourth scan control circuit 720 to output the following to the sub-pixels in the second region aa2: Figure 4 or Figure 12 The second reset signal re_n shown, and the control circuit 320 for the second light emission control circuit to output to the sub-pixels in the second region aa2, as shown Figure 4 or Figure 12 The light emission control signal em is shown.

[0155] This disclosure also provides a driving method, including: controlling each sub-pixel in the photosensitive area of ​​the display panel to collect incident light intensity signals when each sub-pixel is in a non-light-emitting state during the light-emitting phase of a set display frame. The working principle and specific implementation of this driving method are the same as those of the driving circuit in the above embodiments. Therefore, this driving method can be implemented by referring to the specific implementation of the driving circuit in the above embodiments, and will not be repeated here.

[0156] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0157] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0158] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0159] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0160] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0161] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display device, comprising: Display panel; A driving circuit, which is electrically connected to the display panel; The driving circuit is configured to control each photosensitive element in the photosensitive area of ​​the display panel to collect the incident light intensity signal when each sub-pixel in the photosensitive area of ​​the display panel is in a non-light-emitting state during the light-emitting phase of a set display frame. The display panel includes a first region and a second region arranged sequentially along the column direction of the sub-pixels, wherein the first region includes the photosensitive region; The driving circuit is further configured to control each sub-pixel in the first region to be in a non-light-emitting state during the light-emitting phase of the set display frame, and to control each photosensitive element in the photosensitive region to collect the incident light intensity signal. The driving circuit is further configured to control the light emission control signal corresponding to each sub-pixel in the first region to have an invalid pulse of a first duration during the light emission phase, so that each sub-pixel in the first region is in a non-light emission state during the light emission phase. The level of the invalid pulse of the light emission control signal is used to control the light emission control transistor in the display panel to turn off, and the first duration is longer than the duration of the non-light emission phase of one of the sub-pixels, the non-light emission phase occurring before the light emission phase.

2. The display device as claimed in claim 1, wherein, During the light-emitting stage, the light-emitting control signal has at least one invalid pulse. One of the at least one invalid pulses is an invalid pulse having the first duration.

3. The display device as claimed in claim 2, wherein, When the light emission control signal has multiple invalid pulses during the light emission stage, the invalid pulse with the longest duration among the multiple invalid pulses is the invalid pulse with the first duration.

4. The display device as claimed in claim 3, wherein, The driving circuit is further configured to stop outputting light emission control signals to each sub-pixel in the second region during the set display frame.

5. The display device as claimed in claim 3, wherein, The driving circuit is further configured to control the light emission control signal corresponding to each sub-pixel in the second region to have an invalid pulse of a second duration during the light emission phase in the set display frame, so that each sub-pixel in the second region is in a non-light emission state during the light emission phase. Wherein, the invalid pulses with the first duration and the invalid pulses with the second duration are invalid pulses that appear in the same order in the light emission control signal, and the first duration is longer than the second duration.

6. The display device as claimed in claim 4 or 5, wherein, The driving circuit is further configured to control the light emission control signals corresponding to each sub-pixel in the first region and the second region to be the same in all display frames other than the set display frame.

7. The display device as claimed in claim 6, wherein, The display panel further includes: a first light-emitting control circuit and a second light-emitting control circuit; wherein the first light-emitting control circuit is electrically connected to the sub-pixels in the first region, and the second light-emitting control circuit is electrically connected to the sub-pixels in the second region; The driving circuit is further configured to control the first light-emitting control circuit to output a corresponding light-emitting control signal to the sub-pixels in the first region, and to control the second light-emitting control circuit to output a corresponding light-emitting control signal to the sub-pixels in the second region.

8. The display device according to any one of claims 1-5, wherein, Each of a plurality of adjacent display frames is the designated display frame; And / or, at least two of the adjacent display frames are the set display frames, and at least one other display frame other than the set display frame is spaced between two adjacent set display frames.

9. The display device as claimed in claim 8, wherein, When at least two of the adjacent display frames are the set display frames, the driving circuit is further configured to control the input of zero grayscale data voltage to each sub-pixel in the photosensitive area in the set display frames.

10. The display device as claimed in claim 9, wherein, When at least two of the adjacent display frames are the set display frames, the driving circuit is further configured to control each sub-pixel in the remaining area of ​​the display panel to be in a data voltage holding state in the set display frames.

11. The display device as claimed in claim 10, wherein, The driving circuit is also configured to control each sub-pixel in the display panel to input corresponding grayscale data voltages in the remaining display frames, excluding the set display frame.

12. The display device as claimed in claim 8, wherein, The driving circuit is also configured to control the input of corresponding grayscale data voltages to each sub-pixel of the display panel in each of the plurality of display frames.

13. A driving method, comprising: When each sub-pixel in the photosensitive area of ​​the control display panel is in a non-light-emitting state during the light-emitting phase of a set display frame, control each photosensitive element in the photosensitive area to collect the incident light intensity signal. The display panel includes a first region and a second region arranged sequentially along the column direction of the sub-pixels, wherein the first region includes the photosensitive region; Controlling each sub-pixel in the photosensitive area of ​​the display panel to be in a non-light-emitting state during the light-emitting phase of the set display frame includes: The light emission control signal corresponding to each sub-pixel in the first region is controlled to have an invalid pulse of a first duration during the light emission phase, so that each sub-pixel in the first region is in a non-light emission state during the light emission phase; The level of the invalid pulse of the light emission control signal is used to control the light emission control transistor in the display panel to turn off, and the first duration is longer than the duration of the non-light emission phase of one of the sub-pixels, the non-light emission phase occurring before the light emission phase.

14. The driving method as described in claim 13, wherein, The light emission control signal has at least one invalid pulse during the light emission phase; One of the at least one invalid pulses is an invalid pulse having the first duration.

15. The driving method as described in claim 14, wherein, When the light emission control signal has multiple invalid pulses during the light emission stage, the invalid pulse with the longest duration among the multiple invalid pulses is the invalid pulse with the first duration.

16. The driving method as described in claim 15, wherein, Also includes: In the set display frame, the light emission control signal corresponding to each sub-pixel in the second region is controlled to have an invalid pulse with a second duration during the light emission phase, so that each sub-pixel in the second region is in a non-light emission state during the light emission phase; Wherein, the invalid pulses with the first duration and the invalid pulses with the second duration are invalid pulses that appear in the same order in the light emission control signal, and the first duration is longer than the second duration.

17. The driving method as described in claim 15, wherein, Also includes: In all display frames other than the set display frame, the light emission control signals corresponding to each sub-pixel in the first region and the second region are the same.

18. The driving method according to any one of claims 13-17, wherein, Each of a plurality of adjacent display frames is the designated display frame; And / or, at least two of the adjacent display frames are the set display frames, and at least one other display frame other than the set display frame is spaced between two adjacent set display frames.

19. The driving method as described in claim 18, wherein, When at least two of the adjacent display frames are the set display frames, the driving method further includes: in the set display frames, controlling each sub-pixel in the photosensitive area to input a zero grayscale data voltage.

20. The driving method as described in claim 18, wherein, When at least two of the adjacent display frames are the set display frames, the driving method further includes: in the set display frames, controlling each sub-pixel in the remaining area of ​​the display panel to be in a data voltage holding state.

21. The driving method as described in claim 20, wherein, Also includes: In the remaining display frames other than the set display frame, control each sub-pixel in the display panel to input the corresponding grayscale data voltage.

22. The driving method as described in claim 18, wherein, Also includes: In each of the plurality of display frames, the data voltage of the corresponding gray level is input to each sub-pixel of the display panel.

Images