System and method for memory representation and tracking

Abstract

Systems and methods for memory representation and tracking are disclosed. A storage system can identify a request to allocate memory in a first storage medium. In response to the request, the storage system can represent the memory via at least a first node of a first data structure. The first node can store first information for a first portion of the memory and a second portion of the memory. A criterion can be monitored for at least one of the first portion or the second portion. An ordering of the first node in the first data structure can be updated based on detecting the criterion.

Description

Technical Field

[0001] One or more aspects of embodiments of this disclosure relate to storage systems, and more particularly to systems and methods for memory representation and tracking. Background Technology

[0002] Applications can interact with storage systems to read and write data. Accessing a storage system typically involves latency. The type of latency involved can depend on the type of storage devices included in the storage system. Some storage devices have lower latency than others. Therefore, it may be desirable to store data in appropriate data storage devices for efficient data retrieval.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may contain information that does not form prior art. Summary of the Invention

[0004] One or more embodiments of this disclosure relate to a storage system including a first storage medium, a processor configured to communicate with the first storage medium, and a memory coupled to the processor. In some embodiments, the memory stores instructions that, when executed by the processor, cause the processor to: recognize a request to allocate memory in the first storage medium, wherein the first storage medium is associated with a first layer of a memory hierarchy; in response to the request, represent the memory via at least a first node of a first data structure, wherein the first data structure is associated with the first layer; track activity associated with the memory address represented by the first node; update the ordering of the first nodes in the first data structure based on the activity; and move the association of the first node from the first data structure to a second data structure, wherein the second data structure is associated with a second layer of the memory hierarchy.

[0005] According to some embodiments, the second data structure is associated with a second storage medium.

[0006] According to some embodiments, the instructions also cause the processor to send a command to move data stored in a memory address from a first storage medium to a second storage medium based on moving the association of the first node from a first data structure to a second data structure.

[0007] According to some embodiments, the instructions also cause the processor to select a first storage medium for memory allocation based on preferences associated with the requesting process.

[0008] According to some embodiments, the first node represents a first block of memory, wherein the first block is associated with a first page of memory and a second page of memory.

[0009] According to some embodiments, the first node stores the first bit of the first page, which is used to identify whether the first page is associated with the first layer or the second layer.

[0010] According to some embodiments, the instructions that cause the processor to track activity include instructions that cause the processor to perform the following operations: identify access to at least one of a first page or a second page of memory; and calculate the percentage of memory pages identified as accessed.

[0011] According to some embodiments, the instructions executed by the processor are stored in the user space of the memory.

[0012] According to some embodiments, the processor is configured to move the association of the first node from the first data structure to a second data structure in response to detecting that the total number of pages represented by the first data structure exceeds a threshold number of pages.

[0013] According to some embodiments, the processor is configured to maintain bits in memory for memory addresses, wherein the bits indicate whether the memory address has been accessed.

[0014] One or more embodiments of this disclosure also relate to a method comprising identifying a request to allocate memory in a first storage medium. The first storage medium may be associated with a first layer of a memory hierarchy. The method includes, in response to the request, representing memory via at least a first node of a first data structure. The first data structure may be associated with the first layer. Activity associated with a memory address represented by the first node can be tracked, and the ordering of the first node in the first data structure can be updated based on the activity. The association of the first node may be moved from the first data structure to a second data structure. The second data structure may be associated with a second layer of the memory hierarchy.

[0015] These and other features, aspects, and advantages of embodiments of the present disclosure will be more fully understood when considered in conjunction with the following detailed description, the appended claims, and the accompanying drawings. Of course, the actual scope of the invention is defined by the appended claims. Attached Figure Description

[0016] The following figures illustrate a non-limiting and non-exhaustive embodiment of this invention, wherein, unless otherwise specified, the same reference numerals refer to the same parts in various views.

[0017] Figure 1 A block diagram of a system for memory representation and management according to one or more embodiments is depicted;

[0018] Figure 2 A block diagram of a storage manager according to one or more embodiments is depicted;

[0019] Figure 3A conceptual layout diagram depicts the components involved in memory allocation and allocation representation according to one or more embodiments;

[0020] Figure 4 A conceptual layout diagram depicting the migration of one or more pages represented by nodes according to one or more embodiments is provided.

[0021] Figure 5 A conceptual layout diagram of nodes in different states according to one or more embodiments of a data structure is depicted;

[0022] Figure 6 A conceptual layout diagram of a translation table maintained by a memory management unit according to one or more embodiments is depicted;

[0023] Figure 7 A flowchart is depicted illustrating a process for performing a memory tiering operation according to one or more embodiments;

[0024] Figure 8 A flowchart is depicted according to one or more embodiments for identifying a storage medium for allocating memory for an application;

[0025] Figure 9 A screen for displaying preference information for selecting a storage medium, according to one or more embodiments, is depicted;

[0026] Figure 10 A screen is depicted according to one or more embodiments, showing an exemplary memory allocation request intercepted by a memory allocation and list builder module;

[0027] Figure 11 A flowchart depicts a process for page activity tracking and data structure reordering according to one or more embodiments;

[0028] Figure 12 A screen depicting a list of page numbers whose display has been accessed (e.g., touched) and whose access bits have been set according to one or more embodiments;

[0029] Figure 13 A flowchart is depicted illustrating a process for making page migration decisions according to one or more embodiments;

[0030] Figure 14 A screen is depicted, according to one or more embodiments, displaying information about a page to be promoted from a lower-level data structure to a top-level data structure;

[0031] Figure 15A screen is depicted, according to one or more embodiments, displaying information about a page to be demoted from a top-level data structure to a lower-level data structure;

[0032] Figure 16 A screen is depicted, according to one or more embodiments, displaying information about pages that are downgraded and locked or unlocked;

[0033] Figure 17 A conceptual layout diagram of a first data structure (referred to as "top layer") and a second data structure (referred to as "lower layer") according to one or more embodiments is depicted;

[0034] Figure 18 Metadata stored in chunks according to one or more embodiments is described;

[0035] Figure 19 A conceptual layout diagram depicts activity data detected for each page represented by a block, according to one or more embodiments;

[0036] Figure 20 A conceptual layout diagram depicting the block activity values ​​of blocks in the top and lower layers according to one or more embodiments is provided.

[0037] Figure 21 A screen depicting information of example blocks generated in response to a memory allocation request, according to one or more embodiments;

[0038] Figure 22 A screen is depicted that displays exemplary information about blocks in the top and lower layers prior to a degradation decision, according to one or more embodiments;

[0039] Figure 23 Depicting a method based on one or more embodiments Figure 22 The example screen displays exemplary information about the blocks in the top and bottom layers after a degradation decision is made;

[0040] Figure 24 A screen depicts exemplary information about blocks in the top and bottom layers prior to an upgrade decision, according to one or more embodiments;

[0041] Figure 25 Depicting a method based on one or more embodiments Figure 24 The example screen displays exemplary information about the blocks in the top and bottom layers after an upgrade decision is made;

[0042] Figure 26 This is a flowchart of a process for performing a memory tiering operation according to one or more embodiments;

[0043] Figure 27This is a flowchart of a process for generating blocks in response to a memory allocation request, according to one or more embodiments;

[0044] Figure 28 A flowchart depicts a process for tracking the activity of a block according to one or more embodiments; and

[0045] Figure 29 A flowchart is depicted for a process of migrating a page from one layer to another, according to one or more embodiments. Detailed Implementation

[0046] In the following description, exemplary embodiments will be illustrated in more detail with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. However, this disclosure may be embodied in various different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided by way of example to make this disclosure more exhaustive and complete, and to fully convey aspects and features of this disclosure to those skilled in the art. Accordingly, processes, elements, and techniques unnecessary for those skilled in the art to fully understand aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements in the drawings and written description, and therefore, their description may not be repeated. Furthermore, in the drawings, the relative sizes of elements, layers, and regions may be enlarged and / or simplified for clarity.

[0047] Embodiments of this disclosure are described below with reference to block diagrams and flowcharts. Therefore, it should be understood that each block of the block diagrams and flowcharts can be implemented as a computer program product, a complete hardware embodiment, a combination of hardware and computer program products, and / or an apparatus, system, computing device, or computing device that executes instructions, operations, steps, and interchangeable similar terms (e.g., executable instructions, instructions for execution, program code, etc.) on a computer-readable storage medium for execution. For example, the retrieval, loading, and execution of code can be performed sequentially, such that one instruction is retrieved, loaded, and executed at a time. In some example embodiments, the retrieval, loading, and / or execution can be performed in parallel, such that multiple instructions are retrieved, loaded, and / or executed together. Thus, such embodiments can produce machines specifically configured to perform the steps or operations specified in the block diagrams and flowcharts. Accordingly, the block diagrams and flowcharts support various combinations of embodiments for performing the specified instructions, operations, or steps.

[0048] Generally, applications running on host computing devices may need to write data to and read data from storage media. Accessing storage media typically involves latency. The latency involved can vary depending on the type of storage media being accessed. For example, storage media attached to the central computing unit (CPU) of a computing device (e.g., Dynamic Random Access Memory (DRAM)) may have lower latency than storage media attached via a data communication link (e.g., Compute Express Link (CXL) memory). While storage media like DRAM can offer lower latency, they can also be expensive and offer limited capacity.

[0049] A storage system may be desirable that has different types of memory (e.g., a combination of DRAM and CXL memory) arranged in a memory hierarchy or tier, where the tiers assigned to the storage medium can be based on the characteristics of the storage medium (e.g., latency). For example, with latency, the number of tiers assigned to the storage medium can increase as the latency associated with the medium decreases. A tiered storage system allows data to be distributed in such a way that blocks, groups, or pages of data that are accessed more frequently than other memory pages (collectively referred to as “pages” or “memory pages”) are stored (or promoted to) higher memory tiers (e.g., DRAM), while less frequently accessed memory pages are stored (or demoted to) lower memory tiers (e.g., CXL memory).

[0050] Embodiments of this disclosure relate to systems and methods for representing application memory space and managing the storage of data for the application via memory tiering operations. Memory tiering operations may include memory allocation based on hardware topology or user configuration preferences for the application, generating representations of memory allocations, tracking memory accesses, reordering memory allocations based on the tracking representations, and / or making memory migration decisions. In some embodiments, memory tiering operations are performed on a per-application (or per-process) basis.

[0051] In some embodiments, memory tiers and associated memory tiering operations are implemented in user space (as opposed to kernel space) in a way that is transparent to the application in terms of performance and application code. Some benefits of configuring and managing memory tiers in user space include, but are not limited to: 1) applying memory tiers to selected processes or virtual machines (VMs), thereby allowing memory tiers to be customized based on process or VM requirements; 2) better user space control; 3) configuring memory tiers on a per-process basis after kernel boot; and 4) making changes (e.g., changes to memory tiers) in user space is relatively easier (e.g., no permission is required) compared to kernel space.

[0052] In some embodiments, instructions for memory tiering operations are included in a programming library (such as a memory tiering library that may be loaded prior to a memory allocation library). The memory tiering library may be configured to intercept memory allocation requests for an application and store memory allocation information in one or more data structures. The storage medium selected for memory allocation may depend on requirements and / or preferences identified for the application (collectively, preferences). In some embodiments, a first data structure may represent (or map) memory allocated in a first storage medium within a first memory tier, and a second data structure may represent memory allocated in a second storage medium within a second memory tier. The first memory tier may be higher than the second memory tier.

[0053] In some embodiments, nodes in the first and second data structures can represent one or more memory pages in the corresponding storage medium. Nodes can be used to track application access to one or more pages. In this regard, a page tracking process or thread can track page activity (or activity) information, including when a page is accessed and / or the number of accesses, and reorder the corresponding nodes based on the tracked information. For example, nodes corresponding to one or more active or hot pages can be moved to the top or head of the data structure, and nodes corresponding to one or more inactive or cold pages can be moved to the bottom or tail of the data structure.

[0054] In some embodiments, hot pages at the head of the second data structure can be further upgraded to the first data structure, and / or cold pages at the tail of the first data structure can be downgraded to the second data structure. Physical memory pages corresponding to the migrated node can also be upgraded or downgraded based on the upgrade or downgrade of the corresponding node.

[0055] Figure 1 A block diagram of a system for memory representation and management according to one or more embodiments is depicted. The system includes a host computing device (referred to as a “host”) 100 coupled to one or more endpoints, such as, for example, one or more storage devices or memory devices 102a-102c (collectively referred to as “storage device” 102).

[0056] Host 100 includes processor 105, main memory 104, memory management unit (MMU) 108, and root complex (RC) interface 112. Processor 105 may include one or more central processing unit (CPU) cores 116 configured to execute computer program instructions and process data stored in cache memory 118 (also simply referred to as "memory" or "cache"). Cache 118 may be dedicated to one of the CPU cores 116 or shared by the CPU cores 116.

[0057] Cache 118 may be coupled to memory controller 120, which in turn is coupled to main memory 104. Main memory 104 may include, for example, dynamic random access memory (DRAM) storing computer program instructions and / or data (collectively, data) used by processes executed by core 116. Data may be loaded into cache memory 118, and processes may consume data directly from cache memory. If the data to be consumed is not already in the cache, the process may need to query other memory devices in the memory hierarchy to find the data. For example, if the data being sought is not in cache 118, the process may query main memory 104, and if the data is not in main memory 104, it may query storage device 102.

[0058] In some embodiments, cache 118, main memory 104, and / or storage device 102 may be included in a storage system that allows for memory tiering to provide an appropriate cost or performance profile. In this regard, different types of storage media may be organized into memory tiers or levels based on the characteristics of the storage media. A characteristic may be access latency. In some embodiments, the number of tiers or levels of storage media increases as access latency decreases.

[0059] In some embodiments, one or more of the storage devices 102 are storage devices of the same or different types aggregated into a storage pool. For example, a storage pool may include one or more CXL memory devices and one or more SSDs. The layer of one type of storage device (e.g., a CXL memory device) in the pool may be higher than the layer of another type of storage device (e.g., an SSD) in the pool.

[0060] In some embodiments, host 100 may support one or more virtual machines (VMs), each having its own instance of processor 105, MMU 108, and / or machine memory 104. One of the one or more VMs may execute a process or application, such as, for example, a big data analytics application, an e-commerce application, a database application, a machine learning application, etc. In some embodiments, the first VM executes the first process concurrently with a second process executed by a second VM.

[0061] In some embodiments, host 100 includes a memory manager or memory manager 124 for implementing memory allocation and tiering operations for one or more applications. The memory manager 124 may be implemented via hardware, firmware (e.g., via an application-specific integrated circuit (ASIC)), software, or any combination of software, firmware, and / or hardware. For example, the memory (or storage) manager 124 may be implemented as a memory tiering library loaded by an application (e.g., at runtime). In some embodiments, the memory tiering library is loaded before other libraries (such as a memory allocation library) are loaded.

[0062] In some embodiments, the storage manager 124 is configured to recognize a memory allocation request from an application and store the memory allocation request in a queue. The memory allocation request can also proceed to execution. In this regard, in response to the allocation request, memory can be allocated in main memory 104 or in one of the storage devices 102. The selection of the storage medium for which memory is to be allocated can be based on preferences identified for the application.

[0063] In some embodiments, the storage manager 124 dequeues queued memory allocation requests and generates one or more nodes representing memory allocations. The generated nodes may be stored in one or more data structures, such as, for example, one or more linked lists. For example, a node in a first data structure may represent (and is also commonly referred to as containing) a memory page stored in a first storage medium (e.g., main memory 104) assigned to a first (e.g., top or fast) memory tier. A node in a second data structure may represent a memory page stored in a second storage medium (e.g., storage device 102) assigned to a second (e.g., low or slow) memory tier.

[0064] In some embodiments, storage manager 124 is configured to check the activity of pages represented by nodes. Page activity information can indicate whether a page has been accessed (e.g., is a "hot" page) or has not been accessed (e.g., is a "cold" page). In some embodiments, page activity information indicates the number of accesses to that page. The number of accesses can be maintained by a counter used by the storage medium (e.g., storage device 102) and in response to a host command provided to storage manager 124, as described in further detail in U.S. application entitled "Systems and Methods for Monitoring Memory Accesses," filed on the same date as this application, the contents of which are incorporated herein by reference.

[0065] In some embodiments, the storage manager 124 rearranges nodes in a data structure in response to page activity information. For example, a node with one or more hot pages may be moved to the head of the data structure, and a node with one or more cold pages may be moved to the tail of the data structure. Page migration (e.g., promotion or demotion) decisions may also be made on a periodic (regular or irregular) basis. For example, a node representing the first page at the tail of a first (top-level) data structure may be moved (e.g., demotion) to the tail of a second (lower-level) data structure, and / or a node representing the second page at the head of a second (lower-level) data structure may be moved (e.g., promotion) to the head of a first (top-level) data structure. Promotion and / or demotion decisions may be based on a comparison of the current number of pages in a tier with a threshold number of allowed pages.

[0066] In some embodiments, processor 105 (e.g., an application executed by a VM) generates a request to storage device 102. The request may include requests to read / load data, write / store data, erase / flush data, etc. One or more of the requests may be associated with a virtual memory address. In some embodiments, the processor may invoke MMU 108 to translate the virtual address into a physical address. MMU 108 may include a translation table 110 that maps virtual addresses to physical addresses. The request sent to storage device 102 may include a physical address corresponding to the virtual address.

[0067] In some embodiments, processor 105 sends a request to storage device 102 via RC interface 112 and interface connections 106a-106c (collectively referred to as 106). The request may include a data access request, a memory count information request, etc. Messages from storage device 102 to processor 105 (such as, for example, a response to a request from processor 105) are delivered to RC interface 112 via interface connection 106, and RC interface 112 then delivers the response to processor 105.

[0068] In some embodiments, interface connection 106 (e.g., connector and its protocol) includes various general-purpose interfaces, such as, for example, Ethernet, Universal Serial Bus (USB), etc. In some embodiments, interface connection 106 (e.g., connector and its protocol) may include (or may conform to) Compute Fast Link (CXL), Cache Coherent Interconnect for Accelerators (CCIX), Dual In-line Memory Module (DIMM) interface, Small Computer System Interface (SCSI), Fast Non-Volatile Memory (NVMe), Fast Peripheral Component Interconnect (PCIe), Remote Direct Memory Access over Ethernet (RDMA), Serial Advanced Technology Attachment (SATA), Fibre Channel, Serial Attached SCSI (SAS), NVMe over Fabric (NVMe-oF), iWARP protocol, InfiniBand protocol, 5G wireless protocol, Wi-Fi protocol, Bluetooth protocol, etc.

[0069] RC interface 112 may be, for example, a PCIe interface configured to implement a root complex for connecting processor 105 and host main memory 104 to storage device 102. RC interface 112 may include one or more ports 114a-114c to connect one or more storage devices 102 to the RC. In some embodiments, MMU 108 and / or translation table 110 may be integrated into RC interface 112 to allow address translation to be performed by RC interface 112.

[0070] Storage device 102 may include one or more of volatile computer-readable storage media and / or non-volatile computer-readable storage media. In some embodiments, one or more of storage devices 102 include any type of memory attached to a CPU or GPU, such as, for example, a CXL-attached memory device (including volatile and persistent memory devices), an RDMA-attached memory device, etc., but embodiments are not limited thereto. A CXL-attached memory device (referred to simply as CXL memory) may conform to the CXL.mem protocol, wherein host 100 may access the device using commands such as load and store commands. In this respect, host 100 may act as the requester, and CXL memory may act as the slave.

[0071] In some embodiments, one or more of the storage devices 102 may further include volatile computer-readable storage media, such as random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), fast page mode dynamic random access memory (FPM DRAM), extended data output dynamic random access memory (EDO DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), double data rate type 2 synchronous dynamic random access memory (DDR2 SDRAM), double data rate type 3 synchronous dynamic random access memory (DDR3 SDRAM), Rambus dynamic random access memory (RDRAM), dual transistor RAM (TTRAM), thyristor RAM (T-RAM), zero capacitor (Z-RAM), Rambus through-hole memory module (RIMM), dual in-line memory module (DIMM), single in-line memory module (SIMM), video random access memory (VRAM), cache memory (including various levels), flash memory, register memory, etc.

[0072] One or more storage devices 102 may include non-volatile computer-readable storage media, such as floppy disks, flexible disks, hard disks, solid-state storage (SSS) (e.g., solid-state drives (SSDs)), solid-state cards (SSCs), solid-state components (SSMs), enterprise flash drives, magnetic tape, or any other non-transitory magnetic media. Non-volatile computer-readable storage media may also include punched cards, paper tape, optical marking sheets (or any other physical media having perforated patterns or other optically identifiable markings), compact disc read-only memory (CD-ROM), rewritable compact disc (CD-RW), digital versatile disc (DVD), Blu-ray disc (BD), or any other non-transitory optical media. Such non-volatile computer-readable storage media may also include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory (e.g., serial, NAND, NOR, etc.), multimedia memory cards (MMC), secure digital storage (SD) cards, SmartMedia cards, CompactFlash (CF) cards, Memory Sticks, etc. In addition, non-volatile computer-readable storage media may also include conductive bridged random access memory (CBRAM), phase change random access memory (PRAM), ferroelectric random access memory (FeRAM), non-volatile random access memory (NVRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), silicon-oxide-nitride-oxide-silicon memory (SONOS), floating junction gate random access memory (FJG RAM), Millipede memory, racetrack memory, etc.

[0073] Figure 2 A block diagram of a storage manager 124 according to one or more embodiments is depicted. In some embodiments, the storage manager 124 is configured to execute in the user space of main memory 104. Execution in user space allows memory allocation and tiering operations to be customized on a per-process basis. In some embodiments, the storage manager 124 is invoked for memory allocation and tiering for a first application, while the storage manager 124 is not invoked for a second application. Therefore, the second application may not receive the same benefits of memory tiering as the first application.

[0074] In some embodiments, the storage manager 124 includes a storage identifier module 200, a memory allocation and list builder module 202, a page tracking and list management module 204, and a page migration module 206. One or more modules 200-206 can be executed concurrently via one or more processing threads. Furthermore, although one or more modules 200-206 can be implemented as separate functional units, those skilled in the art will recognize that the functionality of the modules can be combined or integrated into a single module, or further subdivided into further sub-modules, without departing from the spirit and scope of the inventive concept.

[0075] In some embodiments, the storage identifier module 200 is configured to identify the storage medium based on the preferences and / or requirements (collectively, preferences) of the application for which storage is to be allocated. Application preferences may be stored, for example, in a profile associated with the application. The profile may identify preferred storage parameters among one or more storage parameters, including bandwidth, latency, capacity, etc.

[0076] In some embodiments, the storage identifier module 200 collects information about one or more storage media (e.g., main memory 104 and / or storage device 102) that can be used by the application. The collected information may correspond to storage parameters in a configuration file. For example, the storage identifier module 200 may collect the capacity, bandwidth, and latency attributes of the identified storage media. The storage identifier module 200 may select one of the identified storage media based on preference information in the configuration file and the storage parameters of the identified storage media.

[0077] For example, if a first application identifies a bandwidth preference, the storage identifier module 200 identifies the storage medium among the identified storage media that provides the best bandwidth. In another example, a second application may identify a storage capacity preference, and the storage identifier module 200 may identify the storage medium among the identified storage media that provides the best storage capacity. In some embodiments, if no configuration file is provided for the application, the storage identifier module 200 may select a default storage medium, such as the one closest to the processor 105.

[0078] The memory allocation and list builder module 202 is configured to intercept memory allocation requests from applications and store the requests in a queue. Memory allocation can proceed according to the application's requests. When a request is executed, memory corresponding to the requested size can be allocated in a storage medium identified by the storage identifier module 200.

[0079] In some embodiments, the memory allocation and list builder module 202 retrieves memory requests from a queue and generates one or more nodes representing the allocated memory. In some embodiments, a node corresponds to one page of the allocated memory. In some embodiments, a node corresponds to two or more pages. The generated nodes may be stored in a data structure, such as, for example, a linked list. The data structure may identify or be associated with the memory layer selected for allocation.

[0080] Page tracking and list manager module 204 may be invoked from time to time to track page activity data and manage the data structure based on page activity. For example, module 204 may traverse the nodes of the data structure to retrieve activity information for one or more pages represented by the nodes. In this regard, module 204 may search for the virtual address of a page in translation table 110 and retrieve the access bit of that page. In some embodiments, if the access bit has been set, the page is considered a hot page. If the access bit has not been set, the page may be considered a cold page.

[0081] Page access information can be used to rearrange nodes in a data structure. In some embodiments, nodes are arranged from active to inactive, such that nodes identified as active are placed at the head of the data structure and nodes identified as inactive are placed at the tail of the data structure. In some embodiments, nodes are arranged based on the activity (e.g., number of accesses) of one or more pages represented by the nodes.

[0082] Page migration module 206 can be configured to make memory migration decisions based on the activity of pages represented by data structures and further based on a set threshold. In some embodiments, the page migration decision is triggered by a comparison of the current number of pages represented by nodes of the data structure with a threshold. For example, page migration module 206 may determine that the number of pages mapped to a first (top) data structure exceeds a maximum threshold number and downgrade one or more pages represented by one or more nodes at the tail of the first data structure to a second (lower) data structure so as not to exceed the maximum threshold number. In another example, page migration module 206 may determine that the number of pages mapped to a top data structure is below a minimum threshold number and promote one or more pages represented by one or more nodes at the head of the lower data structure to the top data structure to meet the minimum threshold number.

[0083] In some embodiments, the page migration module 206 supports page locking functionality for one or more applications. For example, an application may (e.g., in a configuration file) indicate that a certain percentage (e.g., 50%) of pages will remain locked in the fast tier memory and will not be degraded to low-tier memory. The page migration module 206 can identify the activity of pages in the fast tier memory and lock the pages with the highest activity of the indicated percentage. The remaining pages in the fast tier can be considered unlocked and eligible to be degraded to low-tier memory.

[0084] In some embodiments, in response to the migration of a page (which should be understood as the page's representation in a node) from one data structure or layer to another, the page migration module 206 sends a signal to the corresponding storage medium to physically move the corresponding page from one storage medium to another. The physical movement of the page can be performed via one or more read / load and write / store commands to the storage medium from the page migration module 206.

[0085] Figure 3 A conceptual layout diagram depicts the components involved in memory allocation and allocation representation according to one or more embodiments. An application 314 executed by processor 105 (or a VM hosted by processor 105) may make one or more memory allocation requests 304. The memory allocation request may include, for example, the size of the requested memory.

[0086] In some embodiments, the storage manager 124 (e.g., via the memory allocation and list builder module 202) intercepts (or identifies) memory allocation request 304 316 and stores the request in queue 306. In some embodiments, the memory allocation and list builder module 202 represents memory allocation via a top-level data structure 300 and / or a lower-level data structure 302. In this regard, the memory allocation and list builder module 202 dequeues queue entry 308 from queue 306 and generates at least a first node 310a in the top-level data structure 300 and / or at least a second node 310c in the lower-level data structure 302. The choice of layer may depend on preferences identified for the application. Although Figure 3 The embodiments include two data structures 300 and 302, but as those skilled in the art will understand, additional data structures corresponding to other types of storage media can also be generated.

[0087] In one embodiment, a node 310a-310d (collectively referred to as 310) of data structures 300, 302 represents a memory page. In this embodiment, node 310 stores information associated with the corresponding memory page. This information may include, for example, the virtual address and size of the memory page. In embodiments where data structures 300, 302 are linked lists, a node (e.g., node 310a) may also include a pointer to the next (adjacent) node (e.g., node 310b).

[0088] In some embodiments, processor 105 executes a memory allocation request and allocates the requested memory in a first storage medium 318 and / or a second storage medium 320. The selection of the storage medium may be based on preferences identified for application 314 (e.g., by storage identifier module 200).

[0089] In some embodiments, memory page accesses are tracked, and nodes 310 of data structures 300, 302 can be reorganized based on accesses. In this regard, data structures 300, 302 can be implemented as Least Recently Used (LRU) lists. For example, a node (e.g., node 310b) in one of the data structures (e.g., the top-level data structure 300) can be moved from its current position to the head 322 of the same data structure based on the activity of the memory page represented by node 310b. In another example, a node (e.g., node 310d) in one of the data structures (e.g., the lower-level data structure 302) can be moved from its current position toward the tail 324 of the same data structure based on the lack of activity of the memory page represented by node 310d.

[0090] In some embodiments, a node (which should be understood as a page represented by a node) can be upgraded from a lower-level data structure 302 to a top-level data structure 300, or downgraded from a top-level data structure 300 to a lower-level data structure 302. Upgrades and downgrades can be based on a maximum and / or minimum threshold number of pages set for a layer (e.g., the top level). In response to the upgrade and / or downgrade of node 310 between data structures 300 and 302, the physical memory page corresponding to the migrated page is also upgraded 328 and / or downgraded 330 between the first storage medium 318 and the second storage medium 320.

[0091] Figure 4 A conceptual layout diagram depicting the migration of one or more pages, represented by nodes 400a, 400b, according to one or more embodiments is provided. Figure 4 In the examples, the terms node and memory page can be used interchangeably, since one node corresponds to one memory page. Promotion and demotion decisions can be based on the activity (e.g., hot or cold) tracked for the corresponding memory page.

[0092] In some embodiments, upgrading or downgrading a node includes, for example (by removing pointers or links from neighboring nodes) removing the node from one layer and, for example (by reconnecting pointers or links to neighboring nodes) inserting the node into another layer. In some embodiments, the number of nodes (which should be understood as pages represented by nodes) selected for downgrading from the top-level data structure 300 to the lower-level data structure 302 may depend on, for example, a threshold 402. The threshold 402 may be the maximum number of pages that will be stored in the top-level structure. Figure 4 In the example, promoting a hot page (e.g., node 400a) to the top-level data structure 300 may cause the total number of nodes / pages to exceed the threshold 402. In this case, one or more cold pages at the tail of the top-level data structure 300 (e.g., node 400b) may be selected to be demoted to a lower-level data structure 302.

[0093] When node 400a is upgraded to the top-level data structure 300, the pointer to the next node 400c maintained in node 400a can be changed to identify node 400d. When node 400b is downgraded from the top-level data structure 300 to the lower-level data structure 302, the pointer to node 400b maintained in node 400e can be removed, and the pointer to node 400b in node 400f can be added.

[0094] Figure 5 A conceptual layout diagram of nodes 500 in different states 502a-502d according to one or more embodiments of a data structure (e.g., data structures 300, 302) is depicted. In some embodiments (e.g., in MMU 108), access bits are maintained for the address of a memory page represented by a node. Page tracking and list manager module 204 may periodically retrieve the access bits to determine whether a page is a hot page (access bit "1") or a cold page (access bit "0").

[0095] In state 502a, the access bit of the page, represented by the data structure, is set to "1". After a period of time, in state 502b, the page access bit is reset to "0".

[0096] In state 502c, an application can request access to one or more memory pages. MMU 108 can be invoked to retrieve the access bit for the requested memory page. A page fault can be triggered in response to the access bit being "0", and the access bit can be set to "1" in response to a page fault. Figure 5 In the example, nodes 500a and 500b represent pages where the access bit is set to "1", and nodes 500c, 500d, and 500e represent pages where the access bit is set to "0".

[0097] In state 502d, the page tracking and list manager module 204 can reorganize nodes based on the activity of the represented page. For example, nodes associated with a hot page (e.g., nodes 500a, 500b) can be moved to the head of the data structure, and nodes 500c-500e can be moved (or kept) at the tail of the data structure.

[0098] Figure 6 A conceptual layout diagram of a translation table 110 maintained by an MMU 108 is depicted according to one or more embodiments. Translation table 110 stores translations from virtual address 600 to physical memory address 602. In some embodiments, translation table 110 stores access bits 604 associated with virtual and physical memory addresses. A read / load or write / store request from an application to a page whose access bit is set to the value "0" can trigger a page fault. The access bit 604 of the requested memory address can be set to "1" in response to the triggering of a page fault. Processor 105 can periodically reset access bit 604 to "0".

[0099] In some embodiments, the page tracking and list manager module 204 periodically reads access bits 604 to determine the activity of memory pages associated with memory addresses 600, 602. Module 204 may mark a page as a hot page in response to its access bits having a value of "1". The module may mark a page as a cold page in response to its access bits having a value of "0".

[0100] Figure 7 A flowchart illustrating a process for performing memory tiering operations according to one or more embodiments is provided. In action 700, memory manager 124 (e.g., via memory allocation and list builder module 202) identifies a first memory allocation. For example, memory manager 124 may intercept a memory allocation request from an application and store the request in a queue (e.g., queue 306).

[0101] In action 702, the memory manager 124 may represent memory allocation via a first node of a first data structure (e.g., top-level data structure 300) associated with a first layer of the memory hierarchy. The selection of the data structure (and the associated memory layer) may be based on preferences set for the application.

[0102] In action 704, storage manager 124 (e.g., page tracking and list manager module 204) may track the activity of allocated memory addresses. Activity tracking may be for memory pages identified by memory addresses. In some embodiments, storage manager 124 retrieves access bits associated with memory addresses to determine page activity. In some embodiments, a page is identified as a "hot" page in response to an access bit being set to "1", and as a "cold" page in response to an access bit being set to "0". In some embodiments, page activity information is provided by storage device 102. In this regard, storage device 102 maintains a counter that increments for a memory address in response to the detection of an access to that memory address. The counter value may be provided to storage manager 124 upon request and used to determine page activity.

[0103] In action 706, storage manager 124 updates the order of first nodes in the first data structure based on retrieved activity information. For example, nodes representing hot pages can be moved to the head of the first data structure, and nodes representing cold pages can be moved to the tail of the first data structure. In embodiments where the activity information includes access counts, nodes can be organized in descending order based on access counts, wherein the node representing the page with the most access counts is placed at the head of the first data structure, and the node representing the page with the fewest access counts is placed at the tail of the first data structure.

[0104] In action 708, the storage manager 124 may (e.g., via the page migration module 206) determine that a page migration trigger has been satisfied and move the association of the first node from the first data structure to a second data structure. The second data structure may be associated with a second level of the memory hierarchy. For example, the page migration trigger may be satisfied in response to detecting that the total number of pages represented by the first data structure exceeds a threshold maximum number of pages.

[0105] Figure 8 A flowchart illustrating a process for identifying a storage medium for allocating memory for an application, according to one or more embodiments, is depicted. The process begins, and in action 800, the storage manager 124 (e.g., via storage identifier module 200) detects and parses a configuration file associated with the application.

[0106] In action 802, storage manager 124 retrieves preference information set for the application. This preference information can identify which of one or more storage parameters is preferred for the application. Storage parameters may include, but are not limited to, bandwidth, latency, capacity, and capacity thresholds. In one example, bandwidth may be selected as the preferred storage parameter for the application.

[0107] In some embodiments, during action 804, the storage manager 124 also obtains topology information of the available storage media. For example, the storage manager may identify a first storage medium (e.g., DRAM included in main memory 104) as having a first level and a second storage medium (e.g., CXL memory included in storage device 102) as having a second level.

[0108] In action 806, the storage manager 124 also identifies the attributes of the identified storage medium. For example, the storage manager 124 may identify the bandwidth, latency, and / or capacity of the identified storage medium.

[0109] In action 808, storage manager 124 compares the preferences identified by the application with the attributes of the identified storage media and selects at least one storage media that meets the identified preferences. For example, if the preference is for bandwidth, storage manager 124 selects the storage media that provides the highest bandwidth.

[0110] In action 810, the memory manager 124 (e.g., via the kernel) allocates memory of the requested size on the selected storage medium.

[0111] In some embodiments, the application may not have preference information set. In this case, the application can be assigned a default storage medium. The default storage medium can be the storage medium closest to the application.

[0112] Figure 9 A screen is depicted, according to one or more embodiments, displaying preference information for selecting a storage medium. The preference information may be associated with an application and is stored in a file 900 (such as, for example, a JSON file). The storage identifier module 200 can parse the file 900 and retrieve preference information 902 for the application. Preference information 902 may include preferences for, for example, bandwidth, latency, or capacity. Figure 9 In the example, file 900 indicates a preference for bandwidth.

[0113] The storage identifier module 200 can also retrieve and display storage media information 904 of the local storage media. The local storage media can be a Non-Unified Memory Access (NUMA) node. Storage media information may include, for example, the bandwidth, latency, and capacity of the identified storage media. The storage identifier module 200 can identify the appropriate storage media for memory allocation based on the storage media information and application-specific preference information. Figure 9 In the example, the screen displays information 906 about the storage medium that best matches a specific preference attribute (e.g., bandwidth, latency, or capacity).

[0114] Figure 10A screen is depicted displaying an exemplary memory allocation request intercepted by a memory allocation and list builder module 202, according to one or more embodiments. The intercepted memory request may include a memory allocation size of 1000 and an address of 1002 of the allocated page in the storage medium.

[0115] Figure 11 A flowchart depicts a process for page activity tracking and data structure reordering according to one or more embodiments. The process begins, and in action 1100, storage manager 124 (e.g., via page tracking and list manager module 202) determines whether a trigger for resetting access bits associated with a page has been detected. For example, the trigger could be after a certain amount of time.

[0116] If the answer is "yes", then in action 1102, the memory page access bit (e.g., Figure 6 The access bit (604) is reset (e.g., set to the value "0"). The access bit can be stored in a translation table 110, for example, in MMU 108.

[0117] In action 1103, storage manager 124 may perform bookkeeping actions, such as counting the number of pages mapped to top-level data structure 300 and the number of pages mapped to lower-level data structure 302, to determine whether a page migration decision should be made.

[0118] In action 1104, memory manager 124 tracks accesses to one or more memory pages. In this regard, memory manager 124 receives a request to access a memory address and determines whether the access bit for that memory address is set (e.g., set to the value "1"). If the answer is "no", a page fault is triggered, and in action 1106, processor 105 (e.g., kernel) sets the access bit for that memory address. In some embodiments, the accessed page is also included in an activity list maintained by memory manager 124.

[0119] In action 1108, the storage manager 124 periodically determines the activity of pages represented by nodes 310 of data structures 300 and 302. Nodes can be rearranged based on activity information. For example, a node representing a page with a set access bit can be moved toward the head of the data structure, and a node representing a page with a reset access bit can be moved toward the tail of the data structure.

[0120] Figure 12 A list of page numbers 1200a-1200d, depicting a display according to one or more embodiments, has been accessed (e.g., touched) and has had access bits set for it.

[0121] Figure 13 A flowchart illustrating a process for making page migration decisions according to one or more embodiments is provided. The process begins, and in action 1300, storage manager 124 (e.g., via page migration module 206) identifies the number of pages represented by nodes in top-level data structure 300 and the number of pages represented by nodes in low-level data structure 302.

[0122] In action 1302, storage manager 124 identifies one or more thresholds. Thresholds may include, for example, a maximum threshold number indicating the maximum number of pages to be mapped for the corresponding data structures 300, 302. Thresholds may also include, for example, a minimum threshold number indicating the minimum number of pages to be mapped for the corresponding data structures 300, 302.

[0123] In action 1304, one or more pages to be promoted or demoted are selected based on the current number of pages represented in one or more tiers and one or more thresholds. In some embodiments, storage manager 124 identifies the number of pages mapped to a tier that exceeds a maximum threshold number and selects pages to be migrated from the tier based on the identified number. For example, if the number of pages mapped to the top-level data structure 300 exceeds the maximum threshold of 5 pages, storage manager 124 selects 5 pages mapped to the tail of data structure 300 to migrate (e.g., demote) to the lower-level data structure 302.

[0124] In some embodiments, storage manager 124 determines that the number of pages represented in top-level data structure 300 is below a minimum threshold number. In this case, storage manager 124 identifies pages from lower-level data structure 302 that need to be migrated (e.g., upgraded) to top-level data structure 300.

[0125] In action 1306, the storage manager 124 upgrades or downgrades selected pages between the top-level data structure 300 and the lower-level data structure 302. In some embodiments, upgrading or downgrading includes removing pointers or links from adjacent nodes between the top-level data structure 300 and the lower-level data structure 302, and reconnecting pointers or links to adjacent nodes. In some embodiments, the physical page corresponding to the upgrade or downgrade decision is also moved from one storage medium to another.

[0126] Figure 14 A screen is depicted, according to one or more embodiments, displaying information about a page to be upgraded from a lower-level data structure 302 to a top-level data structure 300. Figure 14 In the example, count 1400 for the top-level data structure 300 indicates that 132 pages have been mapped to the top level, while count 1402 for the lower-level data structure 302 indicates that 21 pages have been mapped to the lower level. Figure 14In the example, the maximum threshold number 1404 is 1000. Because the number of pages mapped to the top layer is less than the maximum threshold number, the storage manager 124 selects the upgrade count 1406 corresponding to all 21 pages from the lower-level data structure for the upgrade to the top-level data structure. After the upgrade, the count 1408 for the top layer is updated to 153 pages.

[0127] Figure 15 A screen is depicted, according to one or more embodiments, displaying information about a page to be downgraded from a top-level data structure 300 to a lower-level data structure 302. Figure 15 In the example, count 1410 for the top-level data structure 300 indicates that 1266 pages have been mapped to the top level, while count 1412 for the lower-level data structure 302 indicates that 3523 pages have been mapped to the lower level. Figure 15 In the example, the maximum threshold number 1414 is 1000. Because the number of pages mapped to the top level exceeds the maximum threshold number, storage manager 124 selects 266 pages to be demoted to a lower level, as indicated by the demolition number 1416.

[0128] In some embodiments, storage manager 124 provides page locking functionality for one or more applications. Applications subscribing to the page locking option can (e.g., in a configuration file) indicate the amount of memory (or pages) to be held in the top-level data structure 300. For example, the configuration file might specify that 500 pages (or 2MB of memory, assuming each page is 4KB) will be held in the top level. In this case, storage manager 124 identifies the 500 hottest pages facing the head of the top-level data structure and identifies these pages as “locked.” In some embodiments, “locked” pages are prevented from being demoted to lower-level data structure 302, even under memory pressure. In some embodiments, the remaining pages mapped to the top-level data structure 300 are identified as “unlocked” and may be eligible to be demoted to lower-level data structure 302.

[0129] In some embodiments, the configuration file can specify the percentage of pages to be kept locked. For example, if the percentage is 50%, the storage manager 124 locks 50% of the pages in the top layer (e.g., the 50% most popular pages). The remaining 50% of the pages are unlocked and eligible for degradation.

[0130] Figure 16 A screen is depicted, according to one or more embodiments, displaying information about locked and unlocked pages for downgrading. Figure 16In the example, two pages (represented by their corresponding nodes) are in unlocked (U) states 1500a and 1502a. Assuming that 50% of the allocated pages are to be locked, the storage manager 124 places node 1, which has its access bit set, in the locked (L) state 1500b, while node 0, which does not have its access bit set, remains in the unlocked state 1502b.

[0131] exist Figure 16 In the example, four additional pages (nodes 5, 4, 3, and 2) 1504 are mapped to the top-level data structure 300. The storage manager 124 checks the activity 1506 of the mapped pages and identifies the active (hot) nodes (nodes 3, 2, 5, and 1). Assuming that only 50% of the pages are to be locked, the storage manager 124 identifies three 1508 of the active pages (represented by nodes 2, 3, and 1) facing the head of the data structure as locked, and the remaining pages 1510 (represented by nodes 0, 5, and 4) as unlocked.

[0132] Memory access tracking

[0133] In some embodiments, a node 310 of data structures (e.g., linked lists) 300, 302 represents a page of allocated memory, and memory access tracking granularity is at the page level. However, generating and maintaining nodes for individual pages can incur significant overhead. For example, processing a "release" pointer request might require knowing the size of the page associated with the allocation. A hash map might be needed to find the allocation size for the pointer. The allocation size could be divided by the page size to find the number of pages to be released. Subsequently, it might be necessary to traverse the nodes of the linked list data structure to find the nodes representing the pages to be released and remove those nodes. The links to the previous and next nodes of the removed nodes might also need to be reconnected.

[0134] Other problems with using nodes to represent individual memory pages in memory tiering solutions include: 1) Moving pages between memory tiers may require removing nodes from a linked list in one tier and inserting nodes into a linked list in another tier; 2) Pages represented by nodes can be identified as hot or cold pages without fine-grained distinction; 3) The position of a page in a linked list may not indicate access frequency because a page is either hot or cold based on whether the corresponding access bit has been set; 4) Determining the hotness of a page based on its access bits does not take advantage of the locality of access, which can also indicate the likelihood of access to surrounding pages; 5) Nodes are allocated for pages even if they are not physically allocated in the storage medium, which incurs high overhead and affects the tracking of allocated pages.

[0135] In some embodiments, the memory tiering operations described above can be efficiently handled by representing memory allocations via nodes of one or more chunk sizes (hereinafter referred to as chunks) in both the top-level and lower-level data structures. A chunk can represent one or more contiguous physical memory pages of a given page size. A chunk can have the starting address of the first memory page. The remaining memory pages can be accessed based on page size or offset.

[0136] In some embodiments, representing memory pages via blocks minimizes the space / capacity overhead required to track pages. In this respect, page activity can be tracked without physically allocating nodes to represent pages. In some embodiments, activity tracking is performed on a block-by-block basis, leveraging the locality of memory pages. Memory locality assumes that if a page is accessed by a process, then it is highly likely that adjacent pages can also be accessed. In some embodiments, blocks are reordered based on activity tracking of blocks, allowing reordering to occur on a set of pages rather than on individual pages.

[0137] In some embodiments, page migration from one layer to another occurs without physically adding or removing nodes from the data structure. In this regard, a first block generated in the first layer can be connected to a second block in the second layer. The second block in the second layer can represent the same page represented by the first block. First information (e.g., a first page mask) can be stored in the first block, and second information (e.g., a second page mask) can be stored in the second block. The first page mask can indicate whether one or more pages represented by the first and second blocks belong to the first layer. The second page mask can indicate whether one or more pages belong to the second layer.

[0138] In some embodiments, a page is migrated from one layer to another by modifying the values ​​in a first page mask and a second page mask. For example, a page can be demoted from layer one to layer two by setting the bit in the first page mask corresponding to the demoted page to "0" and the bit in the second page mask corresponding to the demoted page to "1". Similarly, a page can be promoted from layer two to layer one by setting the bit in the first page mask corresponding to the promoted page to "1" and the bit in the second page mask corresponding to the promoted page to "0".

[0139] Figure 17 A conceptual layout diagram of a first data structure (referred to as "top layer") 1600 and a second data structure (referred to as "lower layer") 1602 according to one or more embodiments is depicted. Apart from what is described herein, the top layer 1600 may be similar to... Figure 3 The top-level data structure is 300, and the lower-level structure 1602 can be similar to... Figure 3The low-level data structure 302.

[0140] In some embodiments, in response to a memory allocation request from an application, one or more blocks 1604a-1604g (collectively referred to as 1604) are generated in a top layer 1600 and a lower layer 1602. Block 1604 may represent a set of memory pages, wherein the memory pages have a set page size. In some embodiments, the block size is a multiple of the page size (e.g., 64KB, 128KB, etc.).

[0141] In some embodiments, blocks in the top layer 1600 are linked to blocks in the lower layer 1602. For example, block 1604a may be linked to block 1604b, and block 1604c may be linked to block 1604d. In some embodiments, the same group of memory pages represented by a block in the top layer (e.g., block 1604a) is also represented by a corresponding block in the lower layer (e.g., block 1604b). In some embodiments, a block (e.g., block 1604a) is also linked to the next group of blocks in the layer (e.g., block 1604c).

[0142] In some embodiments, block 1604 includes a page mask 1606. The size of the page mask corresponds to the number of pages represented by the block. For example, the page mask for a block representing 5 pages is 5 bits in length. In some embodiments, the bits of the page mask are set to "1" or "0" depending on whether the associated page is stored in the top layer 1600 or the lower layer 1602. For example, block 1604a sets the bits of page mask 1606a to "1" for pages stored in the top layer 1600 and sets the bits of page mask 1606a to "0" for pages stored in the lower layer 1602. The corresponding block 1604b sets the bits of page mask 1606b to "0" for pages stored in the top layer 1600 and sets the bits of page mask 1606b to "1" for pages stored in the lower layer 1606.

[0143] A page can be promoted or demoted from one layer to another by modifying corresponding bits in the page mask between two layers. For example, a page represented by mask bit 1608a in block 1604c in top layer 1600 can be "moved" (e.g., demoted) to a lower layer by changing the value of mask bit 1608a to "0" and changing the value of mask bit 1608b in the corresponding block 1604d in lower layer 1602 to "1". In another example, a page represented by mask bit 1610b in block 1604f in lower layer 1602 can be "moved" (e.g., promoted) to the top layer by changing the value of mask bit 1610b to "0" and changing the value of mask bit 1610a in the corresponding block 1604e in top layer 1600 to "1".

[0144] In some embodiments, the storage manager 124 determines the number of blocks required for allocation based on the allocation size and the block size. For example, if the block size is 64K and the allocation size is 128K, the allocation is divided into two 64K blocks in each layer 1600, 1602. In this respect, the storage manager 124 generates two blocks in the top layer 1600 and two blocks in the lower layer 1602. Furthermore, assuming the page size is 4K, each block includes 16 pages represented by a 16-bit page mask. Pages in a block can be accessed using the virtual address (chunk_ptr) of the first memory page and the page size or offset as follows:

[0145] Page 0 = chunk_ptr

[0146] Page 1=chunk_ptr+(PAGE_SIZE*1)

[0147] Page 2=chunk_ptr+(PAGE_SIZE*2) . . .

[0151] Assuming that for the initial allocation, memory is allocated in the storage medium associated with the top layer, the page mask stored in the two top-level blocks is set to "1", and the page mask stored in the two bottom-level blocks is set to "0".

[0152] Figure 18 Metadata 1700 stored in chunk 1604 according to one or more embodiments is depicted. In some embodiments, metadata 1700 includes the address (e.g., virtual address) 1702 (also referred to as chunk_ptr) of the first page of the allocated memory and the allocated size 1704. In some embodiments, the activity of the chunk is stored as activity percentage metadata 1706. Metadata 1700 may also store a page mask 1708 indicating the location of the page represented by chunk 1604 (e.g., top layer 1600 or lower layer 1602). In some embodiments, page count 1710 provides a count of the number of valid pages that have been touched or accessed. In some embodiments, metadata 1700 also includes a pointer 1712 to the next chunk in the same layer and a pointer 1714 to the corresponding chunk in a different layer.

[0153] In some embodiments, storage manager 124 is configured to track the activity of block 1604 to determine whether the block's position in the tier should be modified. In this regard, the storage manager (e.g., via page tracking and list manager module 202) determines the activity of individual pages mapped to the block and calculates a block activity value based on the activity of each individual page. For example, if four out of five pages in the block are detected as hot pages, the block's activity is calculated as 80%. The activity percentage can be stored in the block as percentage metadata 1706.

[0154] Figure 19 A conceptual layout diagram is depicted according to one or more embodiments for detecting activity data for individual pages represented by blocks. Because the same page is represented via corresponding blocks (e.g., blocks 1604a and 1604b) in the top layer 1600 and the lower layer 1602, the storage manager 124 traverses the blocks in either layer once to retrieve activity information for each page. The address of each page can be identified based on the address 1702 of the first page in the memory stored as block metadata 1700 and the page size 1704. For example, if block 1604 has 5 pages, the address of the page whose activity is to be checked can be calculated as follows:

[0155] Page 4=(chunk_ptr+(PAGE_SIZE)*4)

[0156] Page 3=(chunk_ptr+(PAGE_SIZE)*3)

[0157] Page 2=(chunk_ptr+(PAGE_SIZE)*2)

[0158] Page 1=(chunk_ptr+(PAGE_SIZE)*1)

[0159] Page 0=(chunk_ptr+(PAGE_SIZE)*0)

[0160] When checking the activity of a page, the storage manager 124 can do so in the translation table 110 ( Figure 6 The page address is searched in the array and the access bit 604 used for the page address is determined to be either marked as accessed (hot) or unaccessed (cold). The page mask 1606 can be used to determine whether the page is in the top layer 1600 or the lower layer 1602. The counter variable for the appropriate block 1604 in the top layer 1600 or the lower layer 1602 can be incremented in response to determining that the page being searched has the set access bit.

[0161] exist Figure 19In the example, the page represented by page mask bits 1800a and 1800b is identified as being in the top layer via the top page mask 1606a of block 1604a (e.g., the corresponding bits of the page mask are set). The page represented by mask bits 1800a and 1800b is identified as a hot page (e.g., the access bit is set in translation table 110) and is therefore added to the access count for block 1604a.

[0162] The page indicated by page mask bit 1800c is not set in the top page mask 1606a, thus indicating that the page is in the lower level 1602. These pages are represented by page mask bits 1802a and 1802b in block 1604b in the lower level. Storage manager 124 performs a lookup of the page indicated by page mask bit 1800c in translation table 110 and determines whether the page is a hot page or a cold page. Figure 19 In the example, the page represented by page mask 1802a is a hot page, while the page represented by page mask 1802b is a cold page.

[0163] In some embodiments, the storage manager 124 calculates the activity percentage of blocks 1604a and 1604b based on the corresponding access counts. For example, assuming based on... Figure 19 In the example, if all three pages represented by block 1604a have been accessed, then the activity value of block 1604a is 100%. If only one of the two pages represented by block 1604b has been accessed, then the activity value of block 1604b is 50%.

[0164] Figure 20 A conceptual layout diagram depicts the block activity values ​​of blocks 1604 in a top-level 1600 and a lower-level 1602 according to one or more embodiments. The block activity values ​​may be stored as percentage metadata 1706 in the respective blocks. The activity values ​​can be used to reorder blocks in the layers. In some embodiments, algorithms such as merge sort algorithms are used to rearrange the blocks based on the calculated activity values.

[0165] exist Figure 20 In the example, block 1604a has a 90% activity value and is placed at the head of the top-level data structure 1600, while block 1604g has a 2% activity value and is placed at the tail of the top-level data structure. Block 1604b in the lower layer 1602 has a 94% tracking activity value and is placed at the head of the lower-level data structure, while block 1604f has a 2% tracking activity value and is placed at the tail of the lower-level data structure.

[0166] Figure 21 A screen depicting information about example blocks generated in response to a memory allocation request, according to one or more embodiments, is described. For simplicity, for Figures 20-22 For example, suppose each block contains one page (e.g., block size = 4K, and page size = 4K). In response to a memory allocation request, four pages 2000 are allocated in the data storage medium at the top level. Four blocks 2002 are generated at the top level to represent the allocated pages. Each block includes the address 2004 of the page represented by the block. The page mask associated with block 2002 can also be set in response to identifying the memory allocation at the top level.

[0167] Block 2006, corresponding to block 2002 in the top layer, is also generated in the lower layer. Figure 21 In the example, assuming the page is assigned to the top level, no page is included in the chunks at the lower levels.

[0168] Figure 22 A screen depicting exemplary information of blocks 2102a, 2104a in the top and lower layers prior to a degradation decision, according to one or more embodiments, is shown. Figure 21 and Figure 22 In the example, the maximum threshold for storing pages in the top layer is 4. Figure 22 In the example, the top layer contains a total of six pages 2100, exceeding the maximum threshold of two. Therefore, the number of pages identified as needing to be downgraded is two.

[0169] Figure 23 Depicting a method based on one or more embodiments Figure 22 The example screen displays exemplary information about blocks 2102b and 2104b in the top and lower layers after a degradation decision. Figure 23 In the example, the pages represented by blocks 2106a and 2108a with the lowest activity percentage values ​​are selected to be demoted to a lower level. By changing the page mask bits associated with the demoted page to identify the lower level instead of the top level, the demoted page is "moved" to a lower level and associated with blocks 2106b and 2108b.

[0170] Figure 24 A screen depicts exemplary information of blocks 2200a, 2202a in the top and lower layers prior to a display upgrade decision, according to one or more embodiments. Figure 24 In the example, three pages are represented by block 2200a in the top layer. The lower layer contains one page represented by block 2204a. Assuming there is space in the top layer for an additional page, the page represented by block 2204a in the lower layer is selected to be promoted to the top layer.

[0171] Figure 25 Depicting a method based on one or more embodiments Figure 24The example screen displays exemplary information about blocks 2200b and 2202b in the top and lower layers after an upgrade decision is made. When upgrading a page represented by block 2204a, the page being upgraded is "moved" to the top layer and associated with block 2204b by changing the mask bits associated with the page to identify the top layer instead of the lower layer.

[0172] Figure 26 This is a flowchart of a process for performing memory tiering operations according to one or more embodiments. In action 2302, memory manager 124 (e.g., via memory allocation and list builder module 202) identifies a first memory allocation.

[0173] In action 2304, the memory manager 124 represents memory allocation via nodes (first nodes) of at least a first block size of a first data structure (e.g., top-level data structure 1600) associated with a first layer of the memory hierarchy. The selection of the data structure (and the associated memory layer) can be based on preferences set for the application.

[0174] In some embodiments, the first node stores first information for a first page (a first portion of the memory) and a second page (a second portion of the memory). The first information may include, for example: the virtual address of the first page (e.g., address 1702), the block activity percentage (e.g., activity percentage metadata 1706), the page location mask (e.g., page mask 1708), the number of validly touched pages in the block (e.g., page count 1710), a pointer to the next block in the same layer (e.g., pointer 1712), and a pointer to the corresponding block in a different layer (e.g., pointer 1714).

[0175] In some embodiments, in addition to allocating the first node in the first data structure, a second node is also allocated in a second data structure (e.g., lower-level data structure 1602) associated with a second layer of the memory hierarchy. The second node may store second information for the same first and second pages represented by the first node. The first node may be connected to the second node via pointer 1714.

[0176] In action 2306, storage manager 124 monitors a criterion for at least the first or second page. This criterion could be, for example, application access to the first and / or second page. In this regard, page tracking and list manager module 204 can be invoked to determine whether the first and / or second page has been accessed, and the block activity percentage can be calculated based on this determination. Although monitoring of the criterion is for making page migration decisions according to one or more embodiments, those skilled in the art will understand that monitoring can be for other purposes. For example, storage manager 124 can monitor activity to determine pages that should be cached or prefetched for faster access, monitor pages that should be locked to prevent them from being moved to the swap space, and / or monitor the number of times pages in a block have been accessed (access frequency count), and calculate a block percentage value based on other monitored activity.

[0177] In action 2308, storage manager 124 updates the sorting of first nodes in the first data structure based on chunk activity percentage. For example, chunks can be organized in descending order of chunk activity percentage, with the chunk with the highest activity percentage placed at the head of the first data structure and the chunk with the lowest activity percentage placed at the tail. Thus, chunk activity can be allowed to represent the degree or frequency of memory access (referred to as "warmth"), rather than simply representing activity as hot / accessed or cold / not accessed.

[0178] Figure 27 This is a flowchart of a process for generating a chunk in response to a memory allocation request, according to one or more embodiments. The process begins, and in action 2402, the memory manager 124 (e.g., via memory allocation and list builder module 202) intercepts the application's memory allocation request and stores the request in a queue (e.g., Figure 3 In queue 306).

[0179] In action 2404, storage manager 124 identifies the allocated size.

[0180] In action 2406, the storage manager generates one or more first blocks at the top level based on the allocation size, block size, and page size. For example, if the allocation size is 128K, the block size is 64K, and the page size is 4K, then two blocks are generated, each representing 16 memory pages.

[0181] In action 2408, one or more second blocks corresponding to the blocks generated in the top layer are generated in the lower layer. For example, if two blocks are generated in the top layer, then two corresponding blocks are generated in the lower layer.

[0182] In action 2410, the metadata of the represented page is stored in the generated first and second blocks. For example, the metadata may identify the address of the first page represented by the block, and also indicate whether the represented page is in the top-level or lower-level block. If the represented page is in the top-level block, the page mask in the top-level block is set to "1", and the page mask in the corresponding lower-level block is set to "0". If the represented page is in the lower-level block, the page mask in the lower-level block is set to "1", and the page mask in the corresponding top-level block is set to "0".

[0183] Metadata can also include pointers to the next set of blocks in the same layer and pointers to corresponding sets of blocks in different layers.

[0184] Figure 28 A flowchart illustrating a process for tracking the activity of block 1604 according to one or more embodiments is provided. The process begins, and in action 2500, storage manager 124 (e.g., via page tracking and list manager 204) determines if there are more blocks to examine to determine activity. In some embodiments, the process examines block 1604 in one of the layers (e.g., top layer 1600) without also examining blocks in another layer (e.g., bottom layer 1602).

[0185] If there are more blocks 1604 to examine, in action 2502, storage manager 124 identifies the page addresses of the pages associated with the blocks. The page addresses can be calculated based on the address of the starting page, the page offset, and the page number to which the lookup address is targeted, as follows:

[0186] The address for a page number = chunk_ptr + (PAGE_SIZE * page number)

[0187] In action 2504, the storage manager 124 checks the activity of a page using the calculated address. In some embodiments, the storage manager 124 performs a lookup of the address in the translation table 110 and determines the value of the corresponding access bit 604. In some embodiments, a page is identified as a hot page in response to the access bit being set to "1", and as a "cold" page in response to the access bit being set to "0".

[0188] In action 2506, storage manager 124 checks page mask 1606 used to identify the layer associated with the page. For example, if the page is associated with the top layer 1600, the corresponding bit in the page mask stored in the top layer block has a value of "1". If the page is associated with the bottom layer 1602, the corresponding bit in the page mask has a value of "0".

[0189] In action 2508, storage manager 124 increments the temporary activity variable of block 1604 in top-level 1600 in response to a page being identified as a hot page in top-level 1600, or increments the temporary activity variable of the corresponding block in lower-level 1602 in response to a page being identified as a hot page in lower-level 1602.

[0190] In action 2510, storage manager 124 determines whether there are additional pages in block 1604. If the answer is "yes", the process continues to action 2502 to determine the activity of the next page in block 1604.

[0191] If the answer is "no", then storage manager 124 calculates a chunk activity value in action 2512. The chunk activity value can be calculated for chunks 1604 in top-level 1600 and chunks in lower-level 1602 based on the counts of corresponding activity variables. In some embodiments, the chunk activity value is a percentage of hot pages in chunk 1604. This percentage can be calculated by dividing the value of the activity counter by the total number of pages in chunk 1604 (identified via page mask bit 1606). The activity value can be stored as activity percentage metadata 1706 for chunk 1604.

[0192] Referring again to action 2500, if there are no more blocks 1604 to check in the layer, then in action 2514, the storage manager 124 reorders blocks 1604 based on their activity values. For example, blocks 1604 could be sorted in descending order of activity, with the block having the highest activity value placed at the head of the data structure.

[0193] Figure 29 A flowchart illustrating a process for migrating pages from one layer to another, according to one or more embodiments, is provided. The migration process may be triggered, for example, by a determination made by storage manager 124 that the number of pages in top-level 1600 exceeds a maximum threshold number and therefore should be downgraded to a lower layer 1602. The migration process may also be triggered by a determination that the number of pages in top-level 1600 is below a minimum threshold number and one or more pages from lower layer 1602 should be promoted to top-level 1600.

[0194] The process begins, and in action 2600, storage manager 124 identifies pages to be promoted or demoted. For example, storage manager 124 may identify the number of pages to be migrated based on a comparison with a threshold number. Pages to be demoted may be, for example, pages from the tail of the top-level 1600 with the lowest chunk activity value. Pages to be promoted may be, for example, pages from the head of the lower-level 1602 with the highest chunk activity value.

[0195] In action 2602, storage manager 124 identifies the bits of page mask 1606 in the top-level and bottom-level blocks that represent the pages to be migrated.

[0196] In action 2604, storage manager 124 modifies the identified bits of page mask 1606 in the top-level and bottom-level blocks. Figure 17 For example, a page represented by mask bit 1608a in block 1604c in top-level 1600 can be "moved" (e.g., demoted) to a lower level by changing the value of mask bit 1608a to "0" and changing the value of mask bit 1608b in the corresponding block 1604d in lower-level 1602 to "1". In another example, a page represented by mask bit 1610b in block 1604f in lower-level 1602 can be "moved" (e.g., promoted) to the top level by changing the value of mask bit 1610b to "0" and changing the value of mask bit 1610a in the corresponding block 1604e in top-level 1600 to "1".

[0197] In some embodiments, the benefits of tracking blocks representing groups of memory pages rather than representing individual pages via individual nodes include: 1) nodes are allocated for blocks rather than physical nodes for each page, thereby reducing space overhead; 2) because corresponding blocks are allocated in top and low layers, moving pages between layers only changes bits in the page mask, where if a page is moved from a low layer to a top layer, the page mask bits in the low layer are cleared and the page mask bits in the top layer are set; 3) merge sort can be used to rearrange blocks based on a calculated block access percentage; 4) calculating the block access percentage (0-100%) allows warm... 5) The position of a block in the linked list indicates the access frequency, as the position is calculated based on the percentage of access rather than on hot or cold (one or zero) determination; 6) Corresponding blocks in the top and bottom layers are connected, allowing efficient page release on a block-by-block basis in both the top and bottom layers; 7) Memory locality can be used to efficiently group pages into blocks and make move decisions for a set of pages within a block; and 8) Block tracking does not require physical allocation for individual pages, as pages can be accessed using page offset values ​​using pointers to the starting memory address.

[0198] One or more embodiments of this disclosure can be implemented in one or more processors. The term processor can refer to one or more processors and / or one or more processing cores. One or more processors can be hosted in a single device or distributed across multiple devices (e.g., via a cloud system). Processors can include, for example, application-specific integrated circuits (ASICs), general-purpose or special-purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices such as field-programmable gate arrays (FPGAs). In a processor, as used herein, each function is executed by hardware configured (i.e., hardwired) to perform that function, or by more general-purpose hardware (such as a CPU) configured to execute instructions stored in a non-transitory storage medium (e.g., memory). Processors can be fabricated on a single printed circuit board (PCB) or distributed across several interconnected PCBs. Processors can include other processing circuitry; for example, processing circuitry can include two processing circuits, an FPGA, and a CPU interconnected on a PCB.

[0199] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, the first element, component, region, layer, or portion discussed herein may be referred to as the second element, component, region, layer, or portion without departing from the spirit and scope of the inventive concept.

[0200] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. Furthermore, unless expressly stated otherwise, the embodiments described herein are not mutually exclusive. Aspects of the embodiments described herein may be combined in certain implementations.

[0201] As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “including” are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any one and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire list of elements when preceding it, without modifying any individual element in the list. Furthermore, the use of “may” when describing embodiments of the inventive concept means “one or more embodiments of this disclosure.” Additionally, the term “exemplary” is intended to refer to an example or illustration. As used herein, the terms “use,” “in use,” and “being used” can be considered synonymous with the terms “utilize,” “in exploitation,” and “being exploited,” respectively.

[0202] While exemplary embodiments of systems and methods for on-demand data storage management have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Accordingly, it should be understood that systems and methods for on-demand data storage management constructed in accordance with the principles of this disclosure may be embodied in ways other than those specifically described herein. Furthermore, this disclosure is defined in the appended claims and their equivalents.

[0203] Systems and methods for handling storage transactions may include one or more combinations of the features set forth in the following statements.

[0204] Statement 1: A storage system includes: a first storage medium; a processor configured to communicate with the first storage medium; and a memory coupled to the processor, the memory storing instructions that, when executed by the processor, cause the processor to: recognize a request to allocate memory in the first storage medium; in response to the request, represent the memory via at least a first node of a first data structure, wherein the first node stores first information for a first portion of the memory and a second portion of the memory; monitor at least one of the first or second portions; and update the order of the first node in the first data structure based on the detected criteria.

[0205] Statement 2: According to the storage system of Statement 1, the first part includes a first page of the memory, and the second part includes a second page of the memory.

[0206] Statement 3: According to the storage system of Statement 1, wherein a first part of the memory is adjacent to a second part of the memory, wherein updating the order of the first node causes the first part of the memory and the second part of the memory to move as a group.

[0207] Statement 4: The storage system according to Statement 1, wherein the instructions for causing the processor to detect the criteria include instructions for causing the processor to detect access to at least one of the first or second portions of the memory.

[0208] Statement 5: According to the storage system of Statement 1, the instructions that cause the processor to update the sorting of the first node include instructions that cause the processor to perform the following operations: calculate the percentage of the standard detected; and determine the position of the first node in the first data structure based on the percentage.

[0209] Statement 6: According to the storage system of Statement 1, wherein a first data structure is associated with a first layer of a memory hierarchy, and the instructions further cause the processor to: in response to a request, represent memory via a second node of a second data structure, wherein the second node stores second information for a first portion of the memory and a second portion of the memory, wherein the second data structure is associated with a second layer of the memory hierarchy.

[0210] Statement 7: According to the storage system of Statement 6, the first information identifies whether the first part of the memory and the second part of the memory belong to the first layer, and the second information identifies whether the first part of the memory and the second part of the memory belong to the second layer.

[0211] Statement 8: According to the storage system of Statement 7, wherein the instructions further cause the processor to: identify the association between the first part and the first layer based on the first information or the second information; determine the conditions for changing the association of the first part; and modify the first information and the second information to change the association of the first part to the second layer.

[0212] Statement 9: According to the storage system of Statement 6, wherein the first node includes a link to the second node, wherein an update to the first information results in an update to the second information.

[0213] Statement 10: According to the storage system of Statement 1, wherein the instructions further cause the processor to: identify a first size for allocating memory; identify a second size of at least a first portion or a second portion; and determine the number of portions represented by a first node based on the first size and the second size, wherein the size of the first information is equal to the number of portions.

[0214] Statement 11: A method comprising: identifying a request to allocate memory in a first storage medium; representing the memory via at least a first node of a first data structure in response to the request, wherein the first node stores first information for a first portion of the memory and a second portion of the memory; for at least one monitoring criterion in the first portion or the second portion; and updating the order of the first node in the first data structure based on the detected criterion.

[0215] Statement 12: According to the method of Statement 11, the first part includes a first page of memory, and the second part includes a second page of memory.

[0216] Statement 13: According to the method of Statement 11, wherein the first part of the memory is adjacent to the second part of the memory, wherein updating the order of the first node causes the first part of the memory and the second part of the memory to move as a group.

[0217] Statement 14: According to the method of Statement 11, the detection criteria further include detecting access to at least one of the first or second portions of the memory.

[0218] Statement 15: According to the method of Statement 11, updating the sorting of the first node includes: calculating the percentage of the standard detected; and determining the position of the first node in the first data structure based on the percentage.

[0219] Statement 16: According to the method of Statement 11, wherein the first data structure is associated with a first layer of the memory hierarchy, and the method further includes: in response to a request, representing the memory via a second node of a second data structure, wherein the second node stores second information for a first portion of the memory and a second portion of the memory, wherein the second data structure is associated with a second layer of the memory hierarchy.

[0220] Statement 17: According to the method of Statement 16, the first information identifies whether the first part of the memory and the second part of the memory belong to the first layer, and the second information identifies whether the first part of the memory and the second part of the memory belong to the second layer.

[0221] Statement 18: The method according to Statement 17 further includes: identifying the association between the first part and the first layer based on the first information or the second information; determining the conditions for changing the association of the first part; and modifying the first information and the second information to change the association of the first part to the second layer.

[0222] Statement 19: According to the method of Statement 16, wherein the first node includes a link to the second node, wherein an update to the first information results in an update to the second information.

[0223] Statement 20: The method according to Statement 11 further includes: identifying a first size for allocating memory; identifying a second size of at least a first portion or a second portion; and determining the number of portions represented by the first node based on the first size and the second size, wherein the size of the first information is equal to the number of portions.

Claims

1. A storage system, comprising: First storage medium; The processor is configured to communicate with the first storage medium; as well as A memory, coupled to the processor, stores instructions that, when executed by the processor, cause the processor to: Identify a request to allocate memory in the first storage medium; In response to the request, the memory is represented by a first node of a first data structure and a second node of a second data structure, wherein the first node stores first information for a first portion of the memory and a second portion of the memory, and the second node stores second information for the first portion of the memory and the second portion of the memory; For at least one monitoring criterion in the first or second part; and Based on the detected standard, the order of the first nodes is updated in the first data structure, wherein the instruction that causes the processor to update the order includes an instruction that causes the processor to change the position of the first node in the first data structure relative to the position of the third node in the first data structure.

2. The storage system according to claim 1, wherein, The first portion includes a first page of memory, and the second portion includes a second page of memory.

3. The storage system according to claim 1, wherein, The first portion of the memory is adjacent to the second portion of the memory, wherein the order in which the first node is updated causes the first portion of the memory and the second portion of the memory to move as a group.

4. The storage system according to claim 1, wherein, The instructions that cause the processor to detect the standard include instructions that cause the processor to detect access to at least one of the first portion or the second portion of the memory.

5. The storage system according to claim 1, wherein, The instructions that cause the processor to update the order of the first nodes include instructions that cause the processor to perform the following operations: Calculate the percentage of tests performed according to the standard; and The position of the first node in the first data structure is determined based on the percentage.

6. The storage system according to claim 1, wherein, The first data structure is associated with the first layer of the memory hierarchy, and the second data structure is associated with the second layer of the memory hierarchy.

7. The storage system according to claim 6, wherein, The first information identifies whether the first part of the memory and the second part of the memory belong to the first layer, and the second information identifies whether the first part of the memory and the second part of the memory belong to the second layer.

8. The storage system according to claim 7, wherein, The instruction also causes the processor to: Identify the association between the first part and the first layer based on the first information or the second information; Determine the conditions for changing the association of the first part; as well as Modify the first information and the second information to change the association of the first part to the second layer.

9. The storage system according to claim 1, wherein, The first node includes a link to the second node, wherein an update to the first information results in an update to the second information.

10. The storage system according to claim 1, wherein, The instruction also causes the processor to: Identify a first size for allocating the memory; Identify a second size at least of the first portion or the second portion; and The number of parts represented by the first node is determined based on the first size and the second size, wherein the size of the first information is equal to the number of parts.

11. A method comprising: Identify requests to allocate memory in the first storage medium; In response to the request, the memory is represented by a first node of a first data structure and a second node of a second data structure, wherein the first node stores first information for a first portion of the memory and a second portion of the memory, and the second node stores second information for the first portion of the memory and the second portion of the memory; For at least one monitoring criterion in the first or second part; and Based on the detected standard, the order of the first node is updated in the first data structure, wherein updating the order includes changing the position of the first node in the first data structure relative to the position of the third node in the first data structure.

12. The method according to claim 11, wherein, The first portion includes a first page of memory, and the second portion includes a second page of memory.

13. The method according to claim 11, wherein, The first portion of the memory is adjacent to the second portion of the memory, wherein the order in which the first node is updated causes the first portion of the memory and the second portion of the memory to move as a group.

14. The method according to claim 11, wherein, The detection criteria also include detecting access to at least one of the first or second portions of the memory.

15. The method according to claim 11, wherein, The order in which the first node is updated includes: Calculate the percentage of tests performed according to the standard; and The position of the first node in the first data structure is determined based on the percentage.

16. The method according to claim 11, wherein, The first data structure is associated with the first layer of the memory hierarchy, and the second data structure is associated with the second layer of the memory hierarchy.

17. The method according to claim 16, wherein, The first information identifies whether the first part of the memory and the second part of the memory belong to the first layer, and the second information identifies whether the first part of the memory and the second part of the memory belong to the second layer.

18. The method of claim 17, further comprising: Identify the association between the first part and the first layer based on the first information or the second information; Determine the conditions for changing the association of the first part; as well as Modify the first information and the second information to change the association of the first part to the second layer.

19. The method according to claim 11, wherein, The first node includes a link to the second node, wherein an update to the first information results in an update to the second information.

20. The method of claim 11, further comprising: Identify a first size for allocating the memory; Identify a second size, at least of the first portion or the second portion; as well as The number of parts represented by the first node is determined based on the first size and the second size, wherein the size of the first information is equal to the number of parts.

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