Storage devices that use redundant memory to repair faulty main memory.

Abstract

In some aspects, a storage device includes: a memory cell array, input / output (I / O) circuitry, and I / O control logic coupled to the I / O circuitry. The memory cell array includes P groups of memory. P redundant memory cells are included in and shared by the P groups of memory. The I / O circuitry is coupled to the P groups of memory and configured to direct P×N data entries to or from P×N working memory cells. The I / O control logic is configured to determine the P×N working memory cells from the P groups of memory based on memory cell failure information indicating K failed primary memory cells from the P groups of memory. The P×N working memory cells include K redundant memory cells from the P redundant memory cells. The I / O control logic is configured to control the I / O circuitry to direct P×N data entries to or from the P×N working memory cells.

Description

[0001] This application is a divisional application of the invention patent application filed on June 30, 2021, entitled "Storage Device for Repairing Faulty Main Memory Using Redundant Memory", application number 202180002505.X.

[0002] Cross-reference to related applications

[0003] This application claims priority to international application No. PCT / CN2021 / 082696 entitled “MEMORY DEVICE WITH FAILED MAIN BANK REPAIR USING REDUNDANT BANK”, filed on March 24, 2021, and international application No. PCT / CN2021 / 082687 entitled “MEMORY DEVICE WITH FAILED MAIN BANK REPAIR USING REDUNDANT BANK”, both of which are incorporated herein by reference in their entirety. Technical Field

[0004] This disclosure relates to storage devices and methods of operation thereof. Background Technology

[0005] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory or NAND flash memory. As the number of storage cells in flash memory continues to increase, faulty (bad) storage cells may occur during the manufacturing process of storage devices.

[0006] For example, most NAND flash memory devices ship from foundries with some faulty cells. These cells are typically identified according to a specified faulty cell labeling policy. By allowing some bad cells, manufacturers can achieve higher yields than if all cells had to be verified as good. This significantly reduces the cost of NAND flash memory and only slightly reduces the storage capacity of the device. Summary of the Invention

[0007] In one aspect, a storage device includes: a memory cell array, input / output (I / O) circuitry, and I / O control logic coupled to the I / O circuitry. The memory cell array includes P groups of memory. Each group of memory includes redundant memory and N primary memory, such that the P redundant memory are included in and shared by the P groups of memory. Each of P and N is a positive integer. The I / O circuitry is coupled to the P groups of memory and configured to direct P×N data to or from the P×N working memory. The I / O control logic is configured to determine the P×N working memory from the P groups of memory based on memory failure information indicating K failed primary memory from the P groups of memory. The P×N working memory includes K redundant memory from the P redundant memory. K is a positive integer not greater than P. The I / O control logic is configured to control the I / O circuit to direct P×N data to or from the P×N working memory blocks respectively.

[0008] In another aspect, a system includes: a storage device configured to store data; and a storage controller coupled to the storage device and configured to control the storage device. The storage device includes: a memory cell array, I / O circuitry, and I / O control logic coupled to the I / O circuitry. The memory cell array includes P groups of memory. Each group of memory includes redundant memory and N primary memory, such that P redundant memory are included in and shared by the P groups of memory. Each of P and N is a positive integer. The I / O circuitry is coupled to the P groups of memory and configured to direct P×N data to or from the P×N working memory. The I / O control logic is configured to determine the P×N working memory from the P groups of memory based on memory failure information indicating K failed primary memory from the P groups of memory. The P×N working memory includes K redundant memory from the P redundant memory. K is a positive integer not greater than P. The I / O control logic is also configured to control the I / O circuit to direct P×N data to or from the P×N working memory blocks respectively.

[0009] In another aspect, a method for operating a storage device is provided. The storage device includes a memory cell array. The memory cell array includes P groups of memory. Each group of memory includes redundant memory and N main memory, such that P redundant memory are included in the P groups of memory. Each of P and N is a positive integer. Based on memory failure information indicating K faulty main memory from the P groups of memory, P×N working memory are determined from the P groups of memory. The P×N working memory includes K redundant memory from the P redundant memory. K is a positive integer not greater than P. P×N data entries are directed to or from the P×N working memory. Attached Figure Description

[0010] The accompanying drawings, which are incorporated herein and form part of this application, illustrate aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to implement and use it.

[0011] Figure 1 A block diagram of an exemplary system having storage devices according to some aspects of this disclosure is shown.

[0012] Figure 2A A diagram of an exemplary memory card having a storage device according to some aspects of this disclosure is shown.

[0013] Figure 2B A diagram of an exemplary solid-state drive (SSD) having a storage device according to some aspects of this disclosure is shown.

[0014] Figure 3 A schematic diagram of an exemplary storage device including peripheral circuitry according to some aspects of this disclosure is shown.

[0015] Figure 4 A block diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to some aspects of this disclosure is shown.

[0016] Figure 5 A block diagram of a storage device is shown that implements a faulty main memory repair scheme using redundant memory.

[0017] Figure 6A and 6B It shows the result of Figure 5 The storage devices implemented in the system utilize a faulty main memory repair scheme that uses redundant memory.

[0018] Figure 7 A block diagram of an exemplary storage device according to some aspects of this disclosure is shown, which uses redundant memory in the data input to implement a faulty main memory repair scheme.

[0019] Figure 8 A block diagram of an exemplary storage device according to some aspects of this disclosure is shown, which uses redundant memory in data output to implement a faulty main memory repair scheme.

[0020] Figure 9 A block diagram of exemplary I / O control logic in a storage device according to some aspects of this disclosure is shown.

[0021] Figures 10A-10C This disclosure illustrates some aspects of the present disclosure. Figure 7-9 An exemplary faulty main memory repair scheme using redundant memory is implemented in the storage devices.

[0022] Figure 11 A flowchart illustrating an exemplary method for operating a storage device having a faulty primary memory and redundant memory, according to some aspects of this disclosure, is shown.

[0023] Figure 12 A flowchart is shown as another exemplary method for operating a storage device having a faulty primary memory and redundant memory, according to some aspects of this disclosure.

[0024] Figure 13 A schematic diagram of an exemplary storage device including multiple surfaces is shown according to some aspects of this disclosure.

[0025] Figure 14A A schematic diagram of an exemplary surface in a storage device according to some aspects of this disclosure is shown.

[0026] Figure 14B Some aspects of this disclosure are shown. Figure 14A A schematic diagram of an exemplary data bus in the plane.

[0027] Figure 15A A block diagram of an exemplary memory device, including a first-level memory unit having a plurality of second-level memory elements and I / O circuitry, is shown according to some aspects of this disclosure.

[0028] Figure 15B A block diagram of an exemplary memory device including a die having multiple surfaces and I / O circuitry, according to some aspects of this disclosure, is shown.

[0029] Figure 15C A block diagram of another exemplary memory device, including a die having multiple surfaces and I / O circuitry, is shown according to some aspects of this disclosure.

[0030] Figure 15D Some aspects of this disclosure are shown. Figure 15CA schematic diagram of an exemplary data bus in a storage device.

[0031] Figures 16A-16D Schematic diagrams of exemplary memory devices according to some aspects of this disclosure are shown, each exemplary memory device including multiple surfaces and multiple I / O circuits.

[0032] Figure 17 A schematic diagram of an exemplary storage device is shown, illustrating an implementation of a faulty primary memory repair scheme in data input using a write multiplexer (MUX) array having multiple write subarrays, according to some aspects of this disclosure.

[0033] Figure 18A A schematic diagram of an exemplary storage device is shown, illustrating an implementation of a faulty primary memory repair scheme in data input using a write MUX array with two write subarrays, according to some aspects of this disclosure.

[0034] Figure 18B-18C This disclosure illustrates some aspects of the present disclosure. Figure 18A An exemplary faulty main memory repair scheme is implemented in the data input of the storage device.

[0035] Figure 18D A schematic diagram of another exemplary storage device is shown, illustrating the use of a write MUX array with two write subarrays to implement a faulty primary memory repair scheme in data input, according to some aspects of this disclosure.

[0036] Figure 19A A schematic diagram of an exemplary storage device is shown, illustrating an implementation of a faulty primary memory repair scheme in data input using a write MUX array with three write subarrays, according to some aspects of this disclosure.

[0037] Figure 19B-19C This disclosure illustrates some aspects of the present disclosure. Figure 19A An exemplary faulty main memory repair scheme is implemented in the data input of the storage device.

[0038] Figure 20 A schematic diagram of an exemplary storage device is shown, illustrating an implementation of a faulty primary memory repair scheme in data output using a read MUX array having multiple read subarrays, according to some aspects of this disclosure.

[0039] Figure 21A A schematic diagram of an exemplary storage device is shown, illustrating an implementation of a faulty primary memory repair scheme in data output using a read MUX array with two read subarrays, according to some aspects of this disclosure.

[0040] Figure 21B This disclosure illustrates some aspects of the present disclosure. Figure 21AAn exemplary faulty main memory repair scheme for data output implemented in the storage device.

[0041] Figure 21C A schematic diagram of another exemplary storage device is shown, illustrating the use of a read MUX array with two read subarrays to implement a faulty primary memory repair scheme in data output, according to some aspects of this disclosure.

[0042] Figure 22A A schematic diagram of an exemplary storage device is shown, illustrating an implementation of a faulty primary memory repair scheme in data output using a read MUX array with three read subarrays, according to some aspects of this disclosure.

[0043] Figure 22B-22C This disclosure illustrates some aspects of the present disclosure. Figure 21A An exemplary faulty main memory repair scheme for data output implemented in the storage device.

[0044] Figure 23 A flowchart is shown as an exemplary method for operating a storage device that implements a faulty primary memory repair scheme, according to some aspects of this disclosure.

[0045] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0046] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other, and such combinations, adjustments, and modifications are within the scope of this disclosure in a manner not specifically depicted in the accompanying drawings.

[0047] Generally, terms can be understood at least in part based on their usage in the context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "described" can still be understood, at least in part on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but may allow for the presence of additional factors that are not necessarily explicitly described, which still depends at least in part on the context.

[0048] As the number of storage cells increases to meet the growing demand for greater storage capacity, the likelihood of storage cell failures also increases during the manufacturing process of storage devices. One way to handle faulty storage cells is to add redundant storage cell regions (e.g., redundant banks, also known as redundant columns or redundant groups) in addition to the primary storage cell regions (e.g., primary banks, also known as primary columns or primary groups). For each storage device, if the number of faulty storage cell regions identified during post-manufacturing testing is below a limit (e.g., not greater than the number of redundant storage cell regions), a remediation scheme can be employed so that, when operating the storage device, the redundant storage cell regions can replace the faulty storage cell regions for reading and writing data.

[0049] Some known memory devices, such as NAND flash memory devices, can perform concurrent data input / output (I / O) operations to write or read eight data entries (e.g., eight bytes) to or from eight physically separate main memory cell regions (e.g., main banks). An equal number of eight redundant memory cell regions (e.g., redundant banks) are coupled to the main memory cell regions. According to known remediation schemes, once a main memory cell region is identified as a faulty main memory cell region, the corresponding redundant memory cell region replaces the faulty memory cell region in data input and output. However, such remediation schemes and redundant bank designs have various problems. For example, a large number of redundant banks can waste chip area because not all redundant banks are typically usable. A relatively large number of redundant banks can also affect the flexibility of the remediation scheme. Furthermore, the additional wiring length coupling each main bank and the corresponding redundant bank can increase data line skew.

[0050] To address one or more of the aforementioned problems, this disclosure introduces a solution in which a fewer number of redundant memory banks than the number of primary memory banks and a flexible repair scheme can be used to handle faulty primary memory banks in a storage device, such as a NAND flash memory device. Consistent with certain aspects of this disclosure, multiplexers can be used to couple adjacent memory banks, allowing input or output data to be shifted between adjacent memory banks (primary or redundant memory banks). Therefore, redundant memory banks are no longer dedicated to a specific primary memory bank but can replace any faulty primary memory bank without being coupled to each primary memory bank. Consequently, the total chip area of ​​redundant memory banks and the chance of wasting redundant memory bank area can be significantly reduced. Furthermore, due to the data shift-based repair scheme, each memory bank is coupled only to adjacent memory banks (single or multiple), thus reducing skew between data lines and shortening the wiring length of data lines. Compared to known methods, the redundant memory bank design and data shift-based repair scheme disclosed herein also increase repair flexibility, even with a smaller number of redundant memory banks.

[0051] Consistent with certain aspects of this disclosure, the data shift-based repair scheme disclosed herein can be implemented at the die level (or surface level) of the storage device. The I / O circuitry and I / O control logic used to implement the data shift-based repair scheme can be shared by multiple surfaces within the die (or by multiple surface sections within a surface). For example, instead of implementing the I / O circuitry and I / O control logic in each surface section of each surface, the I / O circuitry and I / O control logic can be implemented in the die and shared by different surfaces within the die. Alternatively, instances of I / O circuitry and I / O control logic can be implemented in each surface and shared by different surface sections within the corresponding surface. As a result, because the I / O circuitry and I / O control logic are shared across different surfaces (or different surface sections within the corresponding surface) of the die, circuit area overhead can be reduced, and timing control optimization of the data shift-based repair scheme can be more easily implemented.

[0052] Consistent with certain aspects of this disclosure, each set of memory banks in a memory device for concurrent data input / output may include redundant memory banks and multiple primary memory banks. The I / O circuitry disclosed herein may include write MUX arrays and read MUX arrays, each of which includes multiple subarrays (e.g., multi-stage data shift sub-circuit). In this case, the redundant memory banks in each set can be shared not only by multiple primary memory banks within the same set, but also by memory banks from one or more other sets to replace any faulty primary memory bank in one or more other sets. Therefore, the total chip area of ​​the redundant memory banks, and the opportunity to waste redundant memory bank area, can be further reduced.

[0053] Figure 1 A block diagram of an exemplary system 100 having storage devices according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a storage system 102 having a storage controller 106 and one or more storage devices 104. The host 108 may be a processor of an electronic device such as a central processing unit (CPU) or a system-on-a-chip (SoC) such as an application processor (AP). The host 108 may be configured to send or receive data to or from the storage device 104.

[0054] Storage device 104 can be any storage device disclosed herein. As detailed below, storage device 104, such as a NAND flash memory device, can include a smaller number of redundant memory banks than the main memory banks and implement flexible, data shift-based repair schemes in data input and output operations to handle faulty main memory banks identified during post-manufacturing testing of storage device 104.

[0055] According to some embodiments, storage controller 106 is coupled to storage device 104 and host 108 and configured to control storage device 104. Storage controller 106 can manage data stored in storage device 104 and communicate with host 108. In some embodiments, storage controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, storage controller 106 is designed for high duty cycle environments, such as SSDs, or as embedded multimedia cards (eMMC) used as data storage for mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. Storage controller 106 can be configured to control the operation of storage device 104, such as read, erase, and program operations. Storage controller 106 can also be configured to manage various functions regarding data stored or to be stored in storage device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, storage controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to storage device 104. Any other suitable functions may also be performed by storage controller 106, such as formatting storage device 104. Storage controller 106 may communicate with external devices (e.g., host 108) according to specific communication protocols. For example, storage controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0056] The storage controller 106 and one or more storage devices 104 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the storage system 102 can be implemented and packaged into different types of end electronic products. Figure 2A In one example shown, the storage controller 106 and a single storage device 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 2B In another example shown, storage controller 106 and multiple storage devices 104 can be integrated into SSD 206. SSD 206 may also include components for connecting SSD 206 to a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0057] Figure 3 A schematic circuit diagram of an exemplary storage device 300 including peripheral circuitry according to some aspects of this disclosure is shown. The storage device 300 may be... Figure 1 An example of memory device 104 is shown. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are arranged in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell (including a floating-gate transistor) or a charge-trapping type memory cell (including a charge-trapping transistor).

[0058] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, while a second storage state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in four or more storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erase state to present one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used in the erase state.

[0059] like Figure 3 As shown, each NAND flash memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The SSG 310 and DSG 312 may be configured to activate the selected NAND flash memory string 308 (column of the array) during read and program operations. In some embodiments, the SSG 310 of the NAND flash memory strings 308 in the same block 304 is coupled to ground via a common source line (SL) 314 (e.g., a common SL). According to some embodiments, the DSG 312 of each NAND flash memory string 308 is coupled to a corresponding bit line 316 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0060] like Figure 3As shown, NAND memory strings 308 can be organized into multiple blocks 304, each block potentially having a common source line 314. In some embodiments, each block 304 is a basic data element for erase operations, i.e., all memory cells 306 on the same block 304 are erased simultaneously. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic data element for program operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) and gate lines coupling the control gates at each memory cell 306 in the corresponding page 320.

[0061] Peripheral circuitry 302 can be coupled to memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 4 Examples of peripheral circuitry 302 are shown, including a page buffer / sensor amplifier 404, a column decoder / bit line driver 406, I / O circuitry 407, a row decoder / word line driver 408, a voltage generator 410, control logic 413, a register 414, an interface 416, and a data bus 418. Control logic 413 may include I / O control logic 412 configured to control the operation of I / O circuitry 407. It should be understood that in some examples, it may also include... Figure 4 Additional peripheral circuitry not shown.

[0062] Page buffer / sensor amplifier 404 can be configured to read and program (write) data to and from memory cell array 301 according to control signals from control logic 413. In one example, page buffer / sensor amplifier 404 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 404 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 404 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during a read operation.

[0063] The column decoder / bit line driver 406 can be configured to be controlled by control logic 413 and to select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 410. I / O circuitry 407 can be coupled to page buffer / sensor amplifier 404 and / or column decoder / bit line driver 406 and is configured to route data input from data bus 418 to desired memory cell regions (e.g., memory banks) of memory cell array 301, and to route data output from desired memory cell regions to data bus 418. As described in detail below, I / O circuitry 407 may include write multiplexer (MUX) arrays and read MUX arrays to implement the flexible, data shift-based repair schemes disclosed herein, such as those controlled by control logic 413 (including I / O control logic 412).

[0064] The row decoder / word line driver 408 can be configured to be controlled by control logic 413 and select block 304 of the memory cell array 301 and word line 318 of the selected block 304. The row decoder / word line driver 408 can be further configured to drive the selected word line 318 using a word line voltage generated from a voltage generator 410. The voltage generator 410 can be configured to be controlled by control logic 413 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and verification voltage) to be supplied to the memory cell array 301.

[0065] As part of peripheral circuitry 302, control logic 413 can be coupled to the other peripheral circuits described above and configured to control the operation of those circuits. Register 414 can be coupled to control logic 413 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses, for controlling the operation of each peripheral circuit. Interface 416 can be coupled to control logic 413 and acts as a control buffer to buffer and relay control commands received from the host (not shown) to control logic 413 and status information received from control logic 413 to the host. Interface 416 can also be coupled to I / O circuitry 407 via data bus 418 and acts as a data I / O interface and data buffer to buffer and relay write data received from the host (not shown) to I / O circuitry 407 and read data from I / O circuitry 407 to the host. For example, interface 416 may include data I / O 417 coupled to data bus 418.

[0066] Figure 5 A block diagram of a storage device 500 implementing a faulty main memory repair scheme using redundant memory is shown. The memory cell array 301 in the storage device 500 includes i arrays consisting of eight main memory cells 502 (…). <0> ...and <7> A group consisting of 8 redundant memory banks (504) and j units. <0> ...and <7> The main memory bank 502 is composed of a group of data lines (L1, L2, L3, L4, L5, L6, L7, L8, L9, L1, L1, L2, L9, L1, L2, L1, L2, L3, L4, L5, L6, L7, L8, L9, L1, L9, L1, L2 ... <0> ... or L <7> The primary memory bank 502 is coupled to a corresponding redundant memory bank 504. That is, in the event that a primary memory bank 502 is identified as a faulty primary memory bank during post-manufacturing testing, each primary memory bank 502 has its own dedicated redundant memory bank 504 as a backup. The storage device 500 is capable of concurrently inputting or outputting eight data entries (e.g., eight bytes) to each of the eight primary memory banks 502. The storage device 500 includes i groups consisting of eight primary memory banks 502 and j groups consisting of eight redundant memory banks 504.

[0067] The column decoder / bit line driver 406 of the memory device 500 includes i main decoders 510 coupled to i groups of eight main memory banks 502 and j redundant decoders 511 coupled to j groups of eight redundant memory banks 504. The column decoder / bit line driver 406 of the memory device 500 also includes a main pre-decoder 506 coupled to the i main decoders 510 and a redundant (RED) pre-decoder 508 coupled to the j redundant decoders 511. The I / O control logic 412 of the memory device 500 implements a faulty main memory repair scheme by controlling the main pre-decoder 506 and the redundant pre-decoder 508 with control signals such as a redundancy enable signal (RED_EN). Based on the control signals from the I / O control logic 412, the main pre-decoder 506 enables each of the i main decoders 510 to use a select / deselect signal (YSEL). <0> ...and YSEL This disables any faulty main memory in the corresponding group of eight main memory banks 502. On the other hand, based on control signals from I / O control logic 412, redundant pre-decoder 508 causes each of the j redundant decoders 511 to use a select / deselect signal (YREDSEL). <0> ...and YREDSEL <j>Enable any redundant memory bank 504 in the corresponding redundant memory bank group that is coupled to the corresponding failed primary memory bank via a corresponding bit line. The page buffer / sensor amplifier 404 of the storage device 500 is shared by the primary memory bank 502 and the redundant memory bank 504 for read and write operations.

[0068] Figure 6A and 6B It shows the result of Figure 5 The storage device 500 implements a faulty main memory repair scheme using redundant memory. Figure 6A and 6B The diagram illustrates a group consisting of eight main memory banks 502 and a group consisting of eight redundant memory banks 504. The eight main memory banks 502 include memory bank 0 low (B0_L), memory bank 0 high (B0_H), memory bank 1 low (B1_L), memory bank 1 high (B1_H), memory bank 2 low (B2_L), memory bank 2 high (B2_H), memory bank 3 low (B3_L), and memory bank 3 high (B3_H). The eight main memory banks 502 are isolated from each other, meaning that data routed to one main memory bank 502 cannot be routed to another main memory bank 502 because they are not coupled via data lines. Instead, each main memory bank 502 is connected via a data line (e.g., ...). Figure 5 L in <0> ... or L <7> ) coupled to the corresponding redundant memory bank 504 (e.g. Figure 6A and 6B (The adjacent storage bank on the right), the data line is located between the main storage bank 502 and the corresponding redundant storage bank 504.

[0069] Figure 6A The diagram illustrates a scenario where all eight main memory banks 502 are active, meaning no faulty main memory banks were identified through post-manufacturing testing. In this case, the first eight data entries (0..., and 7) are routed to or from each of the eight main memory banks 502, while all eight redundant memory banks 504 remain unused, i.e., without data (marked "x"). Similarly, the second eight data entries (8..., and 15) are again routed to or from each of the eight main memory banks 502, while all eight redundant memory banks 504 remain unused, i.e., without data (marked "x").

[0070] Figure 6B The example illustrates a scenario where one of the eight main memory banks 502 is a faulty main memory bank identified through post-manufacturing testing. In one example where B2_H is the faulty main memory bank, seven of the first eight data entries (0, 1, 2, 3, 4, 6, and 7) are booted to or from the seven working main memory banks 502 (excluding B2_H), while data is rebooted to or from B2_H (5). That is, the faulty main memory bank B2_H is replaced by its dedicated backup—a redundant memory bank 504 coupled to B2_H—for data input and output. In another example where B0_L is the faulty main memory bank, seven of the second eight data entries (9... and 15) are booted to or from the seven working main memory banks 502 (excluding B0_L), while data is rebooted to or from the redundant memory bank 504 coupled to B0_L (8). In other words, the faulty main memory bank B0_L is replaced by its dedicated backup—a redundant memory bank 504 coupled to B0_L—for data input and output.

[0071] As mentioned above, Figure 5 , 6A The redundant memory design and associated repair scheme shown in Figure 6B suffer from various problems. First, seven of the eight redundant memory banks 504 are wasted, and only one redundant memory bank 504 is used to repair the failed primary memory bank. Second, the repair scheme lacks flexibility because the failed primary memory bank can only be replaced by a pre-allocated dedicated redundant memory bank 504. Third, each primary memory bank 502 needs to be coupled to the corresponding redundant memory bank 504 via a data line, which increases the wiring length and skew of the data lines.

[0072] To overcome one or more of those problems, this disclosure provides an improved redundant memory design with a smaller number of redundant memory cells and associated flexible, data shift-based remediation schemes. Consistent with the scope of this disclosure, the storage device may include an array of memory cells (e.g., Figure 3 and 4 The memory cell array 301 in the memory cell array), I / O circuits (e.g., Figure 4 The I / O circuits 407 and control logic (e.g., Figure 4 The I / O control logic 412 in the diagram. The memory cell array may include N main memory banks and M redundant memory banks, where N and M are both positive integers, and N is greater than M. That is, compared to having only main memory banks, the memory cell array can have a smaller number of redundant memory banks. It is understood that, similar to... Figure 5 The storage device 500 in the document may include a group of N main storage banks and a group of M redundant storage banks. However, N is the number of data entries that can be concurrently input (written / programmed) and output (read) from the storage bank array. It should also be understood that the term "storage bank" as used herein (in the context of "main storage bank," "redundant storage bank," or "working storage bank") can refer to a storage cell region to which one of N concurrent data entries is directed or withdrawn. For example, a storage bank can be a portion of a page, block, or face in the storage bank array.

[0073] The I / O circuitry can be coupled to N main memory banks and M redundant memory banks, and is configured to direct N data items to or from the N working memory banks, respectively. In some implementations, the I / O circuitry is coupled to each pair of adjacent memory banks among the N main memory banks and M redundant memory banks, such that the I / O circuitry is configured to direct one of the N data items to or from any of the memory banks in that pair of adjacent memory banks (e.g., see below). Figure 7 and 8 ).

[0074] In some implementations, M equals 1. That is, a single redundant memory bank can be used to repair a group of N (2, 3, 4, 5, etc.) main memory banks, which can significantly reduce the chip area of ​​redundant memory banks and the waste of unused redundant memory banks. For example, Figure 7 and Figure 8 A block diagram of an exemplary storage device 700 is shown, which implements a faulty primary memory repair scheme by using redundant memory in data input and data output according to some aspects of this disclosure. Storage device 700 may be... Figure 3 and 4 An example of storage device 300 is provided. For ease of description, details of the components in storage device 300 may be omitted when describing storage device 700, and these details can be similarly applied to storage device 700. For example... Figure 7 and 8 As shown, the storage device 700 may include a memory cell array 301 having eight main memory banks 702 (B0_L, B0_H, B1_L, B1_H, B2_L, B2_H, B3_L, and B3_H) and one redundant memory bank 704 (RED). That is, in the storage device 700, N equals 8 and M equals 1. In other words, according to some embodiments, the memory cell array 301 includes nine memory banks, which include eight main memory banks 702 and one redundant memory bank 704.

[0075] I / O circuitry 407 can be coupled to eight main memory banks 702 and one redundant memory bank 704, for example, through a page buffer / sensor amplifier 404 and a column decoder / bit line driver 406. Figure 7 In some embodiments shown, during data input (e.g., write operations), the page buffer / sensor amplifier 404 and the column decoder / bit line driver 406 include nine drivers 706 coupled to eight main memory banks 702 and one redundant memory bank 704, respectively. Figure 8 In some of the embodiments shown, during data output (e.g., read operations), the page buffer / sensor amplifier 404 and the column decoder / bit line driver 406 include nine sense amplifiers 802 coupled to eight main memory banks 702 and one redundant memory bank 704, respectively.

[0076] I / O circuit 407 can be configured to direct eight data entries to or from eight working memory banks respectively. Figure 7 In some embodiments shown, during data input, I / O circuitry 407 is configured to direct eight input data entries (e.g., write data: gwd<7:0>, gwd<15:8>, gwd<23:16>, gwd<31:24>, gwd<39:32>, gwd<47:40>, gwd<55:48>, and gwd<63:56>) to eight working memory banks out of nine memory banks (i.e., eight main memory banks 702 and one redundant memory bank 704), for example, seven main memory banks 702 and one redundant memory bank 704. Figure 8 In some embodiments shown, in data output, I / O circuitry 407 is configured to drive eight output data entries (e.g., read data: grd<7:0>, grd<15:8>, grd<23:16>, grd<31:24>, grd<39:32>, grd<47:40>, grd<55:48>, and grd<63:56>) from eight working memory banks out of nine memory banks, such as seven main memory banks 702 and one redundant memory bank 704. Figure 7 and 8 As shown, in some embodiments, I / O circuitry 407 is coupled to each pair of adjacent memory banks such that I / O circuitry 407 is configured to direct a write data (gwd) to or from any of the adjacent memory banks in the pair of adjacent memory banks. The pair of adjacent memory banks may be two primary memory banks 702, or one primary memory bank 702 and a redundant memory bank 704. In some embodiments, redundant memory bank 704 is coupled to both primary memory banks 702 via I / O circuitry 407. It should be understood that although redundant memory bank 704 is as described... Figure 7 and 8 As shown, the eight main memory banks 702 are coupled to two main memory banks 702 (B1_H and B2_L) respectively via I / O circuit 407 in the middle. However, in some examples, the redundant memory bank 704 can be coupled to any two main memory banks 702 respectively via I / O circuit 407 or coupled to only one main memory bank 702 (e.g., B0_L or B3_H) at the end of the eight main memory banks 702.

[0077] The I / O circuit 407 can be implemented using one or more MUX arrays. In such... Figure 7 In some embodiments shown, the I / O circuitry 407 of the memory device 700 includes a write MUX array 707. The write MUX array 707 may include a group of nine write MUXs 708, each coupled to one of eight main memory banks 702 and one redundant memory bank 704 for data input. Each write MUX 708 may include an output (Out), two inputs (A and B), and a select port (S). The output of each write MUX 708 is coupled to a corresponding memory bank 702 or 704. The select port of the write MUX 708 may be configured to receive a write select signal (red_en_b0_l_wt, ..., red_en_b12_wt, ..., or red_en_b3_h_wt) indicating the selection of one of the inputs (A or B). For example, a positive bias write select signal, i.e., the write select signal is enabled, allows selection of input B.

[0078] In some implementations, in addition to the write MUX 708 coupled at its ends to two main memory banks 702 (B0_L and B3_H) (i.e., coupled to only one other main memory bank 702), each write MUX 708 coupled to the respective main memory bank 702 has two inputs configured to input two data lines, including one write data line intended for the respective main memory bank 702 and another write data line intended for the adjacent main memory bank 702. For example, the write MUX 708 coupled to B0_H may have an input A configured to input write data gwd<15:8> and an input B configured to input write data gwd<7:0>.

[0079] As for the write MUX 708 coupled to the redundant memory bank 704, it may have two inputs configured to input two pieces of data, including one piece of write data intended for one adjacent main memory bank 702 and another piece of write data intended for another adjacent main memory bank 702. For example, the write MUX 708 coupled to RED may have input A configured to input write data gwd<31:24> and input B configured to input write data gwd<39:32>.

[0080] For a write MUX 708 coupled to two main memory banks 702 (B0_L and B3_H) at its ends, one of its inputs can be configured to input a write data intended for the corresponding main memory bank 702, and its other input can be configured to input a signal indicating data inactivation due to a memory bank failure, such as the system voltage Vdd. As a result, each write data can be coupled to both inputs of the two adjacent memory banks and input to either input of the two adjacent memory banks.

[0081] In some implementations, such as Figure 8 As shown, the I / O circuitry 407 of the storage device 700 includes a read MUX array 807. The read MUX array 807 may include a group of eight read MUXs 804 coupled to eight main memory banks 702 and one redundant memory bank 704 for data output. Each read MUX 804 may include an output (Out), two inputs (A and B), and a select port (S). The select port of the read MUX 804 can be configured to receive a read select signal (red_en_b0_l_rd, ..., or red_en_b3_h_rd) indicating the selection of one input (A or B). For example, a positive bias read select signal, i.e., read select signal enabled, can select input B.

[0082] In some implementations, each read MUX 804 has two inputs coupled to two adjacent memory banks. For example, the leftmost read MUX 804 may have input A coupled to B0_L and input B coupled to B0_H; the middle read MUX 804 may have input A coupled to B1_H and input B coupled to RED. In other words, apart from the two end main memory banks 702 (B0_L and B3_H), each memory bank 702 or 704 may be coupled to the inputs of the two read MUX 804s respectively. The output of each read MUX 804 may be configured to output a piece of data from input A or B based on a corresponding read selection signal, i.e., any piece of data stored in the two adjacent memory banks. For example, the read data gwd<7:0> output from the leftmost read MUX 804 may come from B0_L or B0_H; the read data gwd<31:24> output from the middle read MUX 804 may come from B1_H or RED.

[0083] As mentioned above Figure 7 and 8 As described, I / O circuitry 407 can be coupled to each pair of adjacent memory banks and configured to direct a data link to or from any of the memory banks in each pair. It should be understood that while the above description of an exemplary design of the write MUX array 707 and read MUX array 807 in I / O circuitry 407 per memory bank 700 with eight main memory banks 702 and one redundant memory bank 704 is applicable to memory devices with N main memory banks and M redundant memory banks, where N and M are both positive integers and N is greater than M. Based on the design of redundant memory banks in the memory cell array and MUX arrays in the I / O circuitry, flexible, data shift-based repair schemes can be implemented. I / O control logic can be coupled to the I / O circuitry and configured to determine N working memory banks from the N main memory banks and M redundant memory banks based on memory bank fault information indicating K faulty main memory banks among the N main memory banks. The N working memory banks may include K redundant memory banks among the M redundant memory banks, where K is a positive integer not greater than M. I / O control logic 412 can also be configured to control I / O circuitry to direct K data items out of N data items to or from K redundant memory banks respectively.

[0084] For example, such as Figure 9 As shown, the I / O control logic 412 may include read redundancy enable logic 902, write redundancy enable logic 904, and working memory logic 906. Each logic 902, 904, or 906 may be implemented by a microprocessor, microcontroller (also known as a microcontroller unit (MCU)), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gating logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below. In some embodiments, one or more of the read redundancy enable logic 902, write redundancy enable logic 904, and working memory logic 906 are implemented using content-addressable memory (CAM).

[0085] In some embodiments, working memory logic 906 is coupled to register 414 and configured to obtain memory bank fault information indicating one or more faulty main memory cells in the main memory of a storage device (e.g., storage device 700), for example, K faulty main memory cells out of N main memory cells. During post-manufacturing testing, bad (inoperable) memory cells can be detected from the storage device, and each main memory cell containing at least one bad memory cell can be identified as a faulty main memory cell. In some embodiments, the memory bank fault information indicates each of the faulty main memory cells of the storage device and is stored in the storage device, for example, in register 414. Thus, each storage device can have its own memory bank fault information. Before operating the storage device, working memory logic 906 can obtain the memory bank fault information from register 414 and determine the N working memory cells of the storage device that can be used for data input and output. According to some embodiments, the number of working memory cells (N) is the same as the number of concurrent input / output data entries (N) (e.g., 8 in storage device 700). That is, the working memory logic 906 can replace K faulty main memory banks with the same number (K) of redundant memory banks, so that N working memory banks can include K redundant memory banks and NK main memory banks. In the storage device 700, one faulty main memory bank among the eight main memory banks 702 can be replaced by a redundant memory bank 704 to form eight working memory banks, as determined by the working memory logic 906 of the I / O control logic 412.

[0086] Based on the determined N working memory banks, read redundancy enable logic 902 and write redundancy enable logic 904 can be configured to control I / O circuitry 407 to direct K data entries out of N data entries to or from the K redundant memory banks, respectively. In some embodiments, for data input, write redundancy enable logic 904 is coupled to write MUX 708 in write MUX array 707 of I / O circuitry 407 and is configured to provide multiple write selection signals 905 to write MUX 708. For example, write redundancy enable logic 904 is coupled to nine write MUX 708 of I / O circuitry 407 and is configured to provide nine write selection signals (e.g., red_en_b0_l_wt, ..., red_en_b12_wt, ..., and red_en_b3_h_wt) to the nine write MUX 708 based on the determined eight working memory banks. In some implementations, for data output, read redundancy enable logic 902 is coupled to read MUX 804 in read MUX array 807 of I / O circuitry 407 and configured to provide multiple read select signals 903 to read MUX 804. For example, read redundancy enable logic 902 is coupled to eight read MUX 804 and configured to provide eight read select signals (e.g., red_en_b0_l_rd, ..., and red_en_b3_h_rd) to the eight read MUX 804 respectively based on eight determined working banks. In some implementations, read redundancy enable logic 902 and write redundancy enable logic 904 also provide synchronization signals to the strobe clocks of read MUX 804 and write MUX 708 respectively to align data and select signals.

[0087] Each selection signal can be enabled (e.g., positively biased) or disabled (e.g., negatively biased) based on the K faulty primary memory banks. In some implementations, if the first memory bank in a pair of adjacent memory banks is one of the K faulty primary memory banks, then read redundancy enable logic 902 and write redundancy enable logic 904 are configured to control I / O circuitry 407 to direct the data to or from the second memory bank in that pair of adjacent memory banks. That is, according to some implementations, I / O control logic 412 is configured to select one memory bank in each pair of adjacent memory banks based on memory bank fault information and control I / O circuitry 407 to direct the data to or from the selected memory bank in each pair of adjacent memory banks.

[0088] Now for reference Figure 7 In the data input, write redundancy enable logic 904 can be configured to control a first write MUX 708 coupled to a first memory bank (i.e., the failed primary memory bank) to prevent the data from being input from input A of the first write MUX 708 and to prevent the data from being output to the first memory bank. Conversely, write redundancy enable logic 904 can be configured to control a second write MUX 708 coupled to a second memory bank (e.g., a redundant memory bank 704 or a primary memory bank 702 adjacent to the first memory bank) to enable the data from being input from input B of the second write MUX 708 and to output the data to the second memory bank. That is, by using a write MUX 708 coupled to the failed primary memory bank as controlled by write redundancy enable logic 904, data intended for the failed primary memory bank can be redirected to its adjacent memory bank, primary memory bank 702 or redundant memory bank 704. The same operation can be applied to each pair of adjacent memory banks, causing the data input to be shifted between adjacent memory banks.

[0089] For example, assuming B0_L is a faulty primary memory, write redundancy enable logic 904 can enable red_en_b0_l_wt and red_en_b0_h_wt, causing Vdd to be input from input B to B0_L, and gwd<7:0> to be rebooted and input from input B to B0_H. To shift data input, write redundancy enable logic 904 can also enable red_en_b1_l_wt and red_en_b1_h_wt, causing gwd<15:8> to be rebooted and input from input B to B1_L, and gwd<23:16> to be rebooted and input from input B to B1_H. Write redundancy enable logic 904 can also disable red_en_b12_wt, causing gwd<31:24> to be rebooted and input from input A to RED. That is, input data can be shifted from the faulty primary memory B0_L to the redundant memory RED accordingly. For the other main memory banks B2_L, B2_H, B3_L, and B3_H, input data shifting may not be required, allowing write redundancy enable logic 904 to disable red_en_b2_l_wt, red_en_b2_h_wt, red_en_b3_l_wt, and red_en_b3_h_wt. As a result, each of B2_L, B2_H, B3_L, and B3_H can still receive data from input A without data shifting.

[0090] Now for reference Figure 8 In data output, read redundancy enable logic 902 can be configured to control read MUX 804 coupled to the first and second memory banks (i.e., the failed primary memory bank and the redundant memory bank 704 or primary memory bank 702 adjacent to the failed primary memory bank) to enable the output of the data from the second memory bank (e.g., the redundant memory bank 704 or primary memory bank 702 adjacent to the failed primary memory bank). That is, by means of read MUX 804 as controlled by read redundancy enable logic 902, the data intended for the failed primary memory bank can be redirected from its adjacent memory bank (primary memory bank 702 or redundant memory bank 704). The same operation can be applied to each pair of adjacent memory banks, causing the data output to shift between adjacent memory banks.

[0091] For example, assuming B0_L is a faulty primary memory, read redundancy enable logic 902 can enable red_en_b0_l_rd, causing grd<7:0> to be redirected and output from B0_H, which is coupled to input B. To shift data output, read redundancy enable logic 902 can also enable red_en_b0_h_rd, red_en_b1_l_rd, and red_en_b1_h_rd, causing grd<15:8> to be redirected and output from B1_L, grd<23:16> to be redirected and output from B1_H, and grd<31:24> to be redirected and output from RED. In other words, output data can be shifted accordingly from the faulty primary memory B0_L to the redundant memory RED. For the other main memory banks B2_L, B2_H, B3_L, and B3_H, output data shifting may not be required, allowing read redundancy enable logic 902 to disable red_en_b2_l_rd, red_en_b2_h_rd, red_en_b3_l_rd, and red_en_b3_h_rd. As a result, data can still be output from input A from B2_L, B2_H, B3_L, and B3_H without data shifting.

[0092] Figures 10A-10C Other examples of a faulty main memory repair scheme using redundant memory bank 704, implemented by storage device 700 according to some aspects of this disclosure, are shown. Figure 10A The diagram illustrates a scenario where all eight main memory banks 702 are active, meaning no faulty main memory bank was identified through post-manufacturing testing. In this case, the first eight data entries (0, ..., and 7) can be booted to or from the eight main memory banks 702, while the redundant memory bank 704 can remain unused, i.e., without data (marked "x"). Similarly, a second set of eight data entries (8, ..., and 15) can again be booted to or from the eight main memory banks 702, while the redundant memory bank 704 can remain unused, i.e., without data (marked "x").

[0093] Figure 10B and 10C This illustrates a scenario where one of the eight main memory banks 702 is a faulty main memory bank identified during post-manufacturing testing. (As shown...) Figure 10B As shown, in an example where B2_H is a faulty main memory, the first four data entries (1, 2, 3, and 4) of the first eight data entries can be bootsted to or from four corresponding working main memory entries B0_L, B0_H, B1_L, and B1_H, which are separated from B2_H by redundant memory 704. Data (5) intended for B2_H can be bootsted to the adjacent working main memory B2_L, and data (4) intended for B2_L can be bootsted to redundant memory 704 (data left shift). B2_H can become unused. That is, data shifting can occur between B2_H and redundant memory 704. The last two data entries (6 and 7) of the first eight data entries can be bootsted to or from two corresponding working main memory entries B3_L and B3_H, respectively, without data shifting. In another example where B0_L is the faulty primary memory, the first four data entries (8, 9, 10, and 11) of the second set of eight data entries can be rebooted to or from adjacent working primary memory entries B0_H, B1_L, and B1_H, as well as redundant memory entry 704 (data right shift). B0_L can become unused. That is, data shifting may occur between B0_L and redundant memory entry 704. The last four data entries (12, 13, 14, and 15) of the second set of eight data entries can be rebooted to or from the four corresponding working primary memory entries B2_L, B2_H, B3_L, and B3_H, without data shifting.

[0094] like Figure 10C As shown, in an example where B1_L is a faulty primary memory, the first two data entries (0 and 1) of the first eight data entries can be bootsted to or from the two corresponding working primary memory entries B0_L and B0_H, respectively. The next two data entries (2 and 3) of the first eight data entries can be bootsted to or from the adjacent working primary memory entry B1_H and the redundant memory entry 704 (data right shift). B1_L can become unused. That is, data shifting may occur between B1_L and the redundant memory entry 704. The last four data entries (4, 5, 6, and 7) of the second eight data entries can be bootsted to or from the four corresponding working primary memory entries B2_L, B2_H, B3_L, and B3_H, respectively, without data shifting. In another example where B2_L is the faulty primary memory, the first four data entries (8, 9, 10, and 11) of the second set of eight data entries can be bootsted to or from the corresponding working primary memory B0_L, B0_H, B1_L, and B1_H, which are separated from B2_L by redundant memory 704. Data (12) intended for B2_L can be bootsted to or from redundant memory 704 (data left shift), and B2_L can become unused. That is, data shifting may occur between B2_L and redundant memory 704. The last three data entries (13, 14, and 15) of the second set of eight data entries can be bootsted to or from the three corresponding working primary memory B2_H, B3_L, and B3_H, respectively, without data shifting.

[0095] Figure 11 A flowchart illustrating an exemplary method 1100 for operating a storage device having a faulty primary memory and redundant memory, according to some aspects of this disclosure, is shown. The storage device can be any suitable storage device disclosed herein. Method 1100 may be implemented by I / O control logic 412. It should be understood that the operations shown in method 1100 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 11 The different execution sequences are shown.

[0096] refer to Figure 11 Method 1100 begins with operation 1102, in which bank failure information indicating a faulty primary memory bank among a plurality of primary memory banks is obtained. Faulty primary memory banks can be identified through post-manufacturing testing of the storage device. For example, working bank logic 906 can obtain bank failure information from register 414 before operating the storage device.

[0097] Method 1100 proceeds to operation 1104, such as... Figure 11 As shown, multiple working memory banks are determined from multiple primary memory banks and redundant memory banks based on memory bank fault information. These multiple working memory banks may include redundant memory banks. For example, working memory bank logic 906 can determine working memory banks that include redundant memory banks and remaining primary memory banks.

[0098] Method 1100 proceeds to operation 1106, such as... Figure 11 As shown, one memory cell from each pair of adjacent memory cells is selected based on memory cell fault information. According to some implementations, the selected memory cell is the working memory cell. For example, the working memory cell logic 906 can select one working memory cell from each pair of adjacent memory cells based on memory cell fault information.

[0099] Method 1100 proceeds to operation 1108, such as... Figure 11 As shown, control directs a data item to or from a selected memory bank in each pair of adjacent memory banks. According to some implementations, to control the directing of this data item, a first memory bank in a pair of adjacent memory banks is identified as the faulty primary memory bank, and control directing the data item to or from a second memory bank in the pair of adjacent memory banks. In one example, write redundancy enable logic 904 can control a first write MUX 708 to prevent the data item from being output to the first memory bank, and control a second write MUX 708 to enable the data item to be output to the second memory bank. In another example, read redundancy enable logic 902 can control a read MUX 804 to enable the data item to be output from the second memory bank.

[0100] Figure 12 A flowchart is shown of another exemplary method 1200 for operating a storage device having a faulty primary memory and redundant memory, according to some aspects of this disclosure. The storage device can be any suitable storage device disclosed herein. Method 1200 can be implemented by I / O control logic 412. It should be understood that the operations shown in method 1200 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 12 The different execution sequences are shown.

[0101] refer to Figure 12 Method 1200 begins with operation 1202, in which memory bank fault information indicating K faulty main memory banks out of N main memory banks is obtained. K can be a positive integer not greater than N. These K faulty main memory banks can be identified through post-manufacturing testing of the storage device. For example, the working memory bank logic 906 can obtain the memory bank fault information from register 414 before operating the storage device.

[0102] Method 1200 proceeds to operation 1204, such as... Figure 12 As shown, N working memory banks are determined from N main memory banks and M redundant memory banks based on memory bank fault information. The N working memory banks may include K redundant memory banks from the M redundant memory banks. For example, working memory bank logic 906 may determine N working memory banks that include K redundant memory banks and the remaining main memory banks. In some embodiments, M equals 1, and a working memory bank is selected from each pair of adjacent memory banks among the N main memory banks and redundant memory banks based on the memory bank fault information.

[0103] Method 1200 proceeds to operation 1206, such as... Figure 12 As shown, K data items are directed to or from K redundant memory banks. In some implementations, M equals 1, and one data item is directed to or from the selected working memory bank in each pair of adjacent memory banks among the N main memory banks and redundant memory banks.

[0104] Figure 13 A schematic diagram of an exemplary memory device 1300 including multiple surfaces 1302 according to some aspects of the present disclosure is shown. Multiple surfaces 1302 may be included in a die 1301. In some embodiments, surfaces 1302 may be independent of each other when performing read, program, or erase operations. For example, each surface 1302 may be configured to independently perform a read operation in response to receiving a read control signal from control logic 413. In some embodiments, each surface 1302 covers a local buffer for reading and programming data and may process operations in parallel, thereby improving processing speed. To enable its independent operation, each surface 1302 may include a set of blocks 304 of a memory cell array 301 and a set of peripheral circuitry, such as a page buffer / sensor amplifier 404, a column decoder / bit line driver 406, and a row decoder / word line driver 408.

[0105] In some other embodiments, surface 1302 can be configured to perform read operations, program operations, or erase operations serially. For example, in response to receiving a corresponding control signal from control logic 413, read operations, program operations, or erase operations can be performed one after another on multiple surfaces 1302.

[0106] Figure 14A An exemplary layout of facet 1302 is shown according to some aspects of this disclosure. According to some aspects of this disclosure, Figure 14B It shows Figure 14A A schematic diagram of an exemplary data bus in face 1302. In some embodiments, the memory cells in face 1302 may be divided into multiple segments (referred to herein as face segments). Face 1302 may include a page buffer / sensor amplifier 404 divided into multiple portions 1406 (referred herein as page buffer / sensor amplifier portions 1406). Each page buffer / sensor amplifier portion 1406 may correspond to a face segment in face 1302 and may be configured to read and program (write) data from and to memory cells in the face segment according to control signals from control logic 413.

[0107] like Figure 14A As shown, the page buffer / sensor amplifier 404 includes four physically separate portions 1406a, 1406b, 1406c, and 1406d (e.g., four quarters). It should be understood that the number of portions is not limited to four and can be any integer greater than 1 (e.g., 2, 3, 4, 5, 6, etc.), such as two halves. The page buffer / sensor amplifier 404 may include multiple storage elements (e.g., latches, caches, or registers) for temporarily storing (buffering) one or more pages of data to be read from or written to the memory cells in face 1302. In some embodiments, each portion 1406a, 1406b, 1406c, or 1406d has the same size, i.e., one-quarter of the page buffer / sensor amplifier 404. For example, the page buffer / sensor amplifier 404 may store 16KB of data, and each portion 1406a, 1406b, 1406c, or 1406d may store 4KB of data.

[0108] In some implementations, the global data bus 1418 may be coupled to each page buffer / sensor amplifier section 1406a, 1406b, 1406c, or 1406d, respectively. (Refer to the reference...) Figure 14A and 14B The global data bus 1418 can branch at each node 1401, 1402, 1404a, or 1404b to form its branch data buses. For example, the global data bus 1418 can branch at node 1401 into two face branch data buses 1403a and 1403b. Face branch data bus 1403a can branch at node 1402 into two segment branch data buses 1405a and 1405b. Segment branch data bus 1405a can branch at node 1404a into two segment sub-branch data buses 1407a and 1407b. Similarly, segment branch data bus 1405b can branch at node 1404b into two segment sub-branch data buses 1407c and 1407d. As a result, the global data bus 1418 can be coupled to the corresponding page buffer / sensor amplifier sections 1406a, 1406b, 1406c, or 1407d via one or more of the branch data buses (e.g., 1403a, 1405a, 1405b, 1407a, 1407b, 1407c, and 1407d).

[0109] In some implementations, face 1302 may include a row decoder / word line driver 408, which may be divided into multiple row decoder / word line driver portions. Each row decoder / word line driver portion may correspond to a face segment in face 1302 and may be controlled by control logic 413 and configured to select a block 304 of the memory cell array 301 in the face segment and select the word line 318 of the selected block 304.

[0110] In some implementations, face 1302 may include a column decoder / bit line driver 406, which may be divided into multiple column decoder / bit line driver portions. Each column decoder / bit line driver portion may correspond to a face segment in face 1302 and may be controlled by control logic 413 and configured to select one or more NAND memory strings 308 in the face segment by applying a bit line voltage generated from voltage generator 410.

[0111] Figure 15A A block diagram of an exemplary storage device 1500 according to some aspects of this disclosure is shown. The exemplary storage device 1500 includes first-level storage elements having I / O circuitry and a plurality of second-level storage elements. For example, the storage device 1500 may include a storage cell array including first-level storage elements 1514. First-level storage elements 1514 may include second-level storage elements 1515a and 1515b. Each second-level storage element 1515a or 1515b may include one or more sets of storage banks, each set of storage banks including redundant storage banks for concurrent data input and / or data output and N main storage banks.

[0112] Each second-level memory element 1515a or 1515b can be coupled to a corresponding page buffer / sensor amplifier 404 (or a corresponding page buffer / sensor amplifier section 1406), a corresponding column decoder / bit line driver 406 (or a corresponding column decoder / bit line driver section 1506), and a corresponding row decoder / word line driver 408 (or a corresponding row decoder / word line driver section 1504).

[0113] like Figure 15A As shown, the first-level storage element 1514 may include I / O circuitry 407, I / O control logic 412, and registers 414. The I / O circuitry 407 and I / O control logic 412 may be shared by the second-level storage elements 1515a and 1515b. Each second-level storage element 1515a or 1515b may correspond to one or more corresponding registers 414, which are configured to store bank fault information of the corresponding second-level storage element 1515a or 1515b. In some embodiments, one or more of the I / O circuitry 407, I / O control logic 412, and registers 414 may be located outside the first-level storage element 1514 (e.g., in the peripheral region of the first-level storage element 1514).

[0114] In some implementations, I / O circuitry 407 may be coupled to a first-level data bus 1510. The first-level data bus 1510 may branch at node 1511 to form two branch data buses, including branch data buses 1512a and 1512b. Consequently, via the first-level data bus 1510 and branch data buses 1512a or 1512b, I / O circuitry 407 may be coupled to a page buffer / sensor amplifier 404 (or page buffer / sensor amplifier portion 1406) and a column decoder / bit line driver 406 (or column decoder / bit line driver portion 1506) in the second-level memory element 1515a or 1515b. I / O circuitry 407 may be configured to direct N data entries to or from N working banks in the second-level memory element 1515a or 1515b via the first-level data bus 1510 and branch data buses 1512a or 1512b, respectively.

[0115] I / O control logic 412 can be coupled to I / O circuitry 407 and configured to determine N working banks from the N main and redundant banks in secondary storage elements 1515a or 1515b based on bank failure information indicating a faulty main bank among the N main banks. I / O control logic 412 can control I / O circuitry 407 to direct N data entries to or from the N working banks respectively. (Refer to above) Figure 9 The I / O control logic 412 has been described, and similar descriptions will not be repeated here.

[0116] In some embodiments, the first-level memory element 1514 may be a die comprising multiple facets, and each second-level memory element 1515a or 1515b may be a corresponding facet within the die. The first-level data bus 1510 may be a global data bus within the die. I / O circuitry 407 may be coupled to the global data bus and configured to direct N data entries to or from N working banks in the corresponding facet via one or more branch data buses in the corresponding facet and the global data bus, respectively. (Refer to the following...) Figure 15B-15D As shown in the example, the first-level storage element 1514 is a die, the second-level storage element 1515a or 1515b is a surface, the first-level data bus 1510 is a global data bus, and the I / O circuit 407 is coupled to the global data bus.

[0117] In some embodiments, the first-level storage element 1514 may be a surface comprising multiple surface segments, and each second-level storage element 1515a or 1515b may be a corresponding surface segment within that surface. The first-level data bus 1510 may be a surface-branch data bus within the surface. I / O circuitry 407 may be coupled to the surface-branch data bus and configured to direct N data entries to or from N working banks in the corresponding surface segments via the surface-branch data bus and the segment-branch data bus, respectively. (Refer to the following...) Figure 16A As shown in the example, the first-level storage element 1514 is a surface, the second-level storage element 1515a or 1515b is a surface segment, the first-level data bus 1510 is a surface branch data bus, and the I / O circuit 407 is coupled to the surface branch data bus.

[0118] In some embodiments, the first-level storage element 1514 may be a surface comprising multiple surface segments, and each second-level storage element 1515a or 1515b may be a corresponding surface segment within that surface. The first-level data bus 1510 may be a segment branch data bus within the surface. I / O circuitry 407 may be coupled to the segment branch data bus and configured to direct N data entries to or from N working memory banks in the corresponding surface segments via the segment branch data bus and the segment sub-branch data bus, respectively. (Refer to the following...) Figure 16B and 16D As shown in the example, the first-level storage element 1514 is a surface, the second-level storage element 1515 is a surface segment, the first-level data bus 1510 is a segment branch data bus, and the I / O circuit 407 is coupled to the segment branch data bus.

[0119] Figure 15B A block diagram of an exemplary memory device 1530 according to some aspects of this disclosure is shown. The memory device 1530 includes a die having I / O circuitry (e.g., I / O circuitry 407) and multiple faces. The die (e.g., die 1301) may include multiple faces 1302a and 1302b. The memory device 1530 may include components similar to those of any suitable memory device disclosed herein, and similar descriptions will not be repeated here.

[0120] In some implementations, control logic 413 may include global I / O control logic configured to control data input and output through global data bus 1418. For example, control logic 413 may control buffering of data input / output to or from global data bus 1418 and may perform integrity checks on the input / output data. In some examples, register 414 may also be included within control logic 413.

[0121] I / O control logic 412 and I / O circuitry 407 can be shared by planes 1302a and 1302b. I / O circuitry 407 can be coupled to a global data bus 1418. Global data bus 1418 can branch at node 1401 to form plane branch data buses 1403a and 1403b. I / O circuitry 407 can be configured to direct N data entries to or from N working memory banks in planes 1302a or 1302b via global data bus 1418 and plane branch data buses 1403a or 1403b, respectively.

[0122] Figure 15C A block diagram of another exemplary storage device 1550 according to some aspects of the present disclosure is shown, the storage device 1550 including a die having I / O circuitry (e.g., I / O circuitry 407) and a plurality of faces. Figure 15D Some aspects of this disclosure are shown. Figure 15C A schematic diagram of an exemplary data bus in the storage device 1550. Figure 15C-15D The die (e.g., die 1301) may include multiple faces 1302a and 1302b, each face 1302a or 1302b including multiple face segments 1502a, 1502b, 1502c, and 1502d. I / O control logic 412 and I / O circuitry 407 may be shared by faces 1302a and 1302b (e.g., also by face segments 1502a, 1502b, 1502c, and 1502d of each face 1302a or 1302b). Storage device 1550 may include components similar to those of any suitable storage device disclosed herein, and similar descriptions will not be repeated here.

[0123] exist Figure 15C-15D In this configuration, I / O circuitry 407 can be coupled to global data bus 1418. Global data bus 1418 can branch at node 1401 to form plane branch data buses 1403a and 1403b. Regarding plane 1302a, plane branch data bus 1403a can branch at node 1402a to form segment branch data buses 1405a, 1405b, 1405c, and 1405d. As a result, I / O circuit 407 can be coupled to each face segment 1502a, 1502b, 1502c or 1502d of face 1301a, and is configured to guide N data to or from N working memory banks in each face segment 1502a, 1502b, 1502c or 1502d via global data bus 1418, face branch data bus 1403a, and segment branch data buses 1405a, 1405b, 1405c or 1405d.

[0124] Regarding face 1302b, face branch data bus 1403b can branch at node 1402b to form segment branch data buses 1405e, 1405f, and 1405g. Segment branch data bus 1405g can branch at node 1404 to form segment sub-branch data buses 1407a and 1407b. As a result, I / O circuit 407 can be coupled to face segment 1502a or 1502b of face 1302b and is configured to guide N data to or from N working memory banks in face segment 1502a or 1502b via global data bus 1418, face branch data bus 1403b, and segment branch data buses 1405e or 1405f, respectively. Furthermore, I / O circuit 407 can be coupled to surface segment 1502c or 1502d of surface 1302b, and is configured to guide N data to or from N working memory banks in surface segment 1502c or 1502d via global data bus 1418, surface branch data bus 1403b, segment branch data bus 1405g, and segment sub-branch data bus 1407a or 1407b, respectively.

[0125] Figures 16A-16D Schematic diagrams of exemplary storage devices 1610, 1620, 1630, and 1640 according to some aspects of this disclosure are shown, each including multiple surfaces and multiple I / O circuits. Reference Figure 16A Storage device 1610 may include components similar to those of any suitable storage device disclosed herein, and similar descriptions will not be repeated here. Figure 16A In this embodiment, each surface 1302a or 1302b may include a corresponding I / O circuit 407a or 407b. Although the storage device 1610 includes a single I / O control logic 412 shared by the multiple surfaces 1302a and 1302b, in some embodiments, each surface 1302a or 1302b may include: (1) a corresponding I / O control logic 412 coupled to its corresponding I / O circuit 407a or 407b; and (2) one or more corresponding registers 414 coupled to its corresponding I / O control logic 412.

[0126] Regarding face 1302a, I / O circuit 407a (and the corresponding I / O control logic 412 and corresponding register 414, if any corresponding I / O control logic 412 and corresponding register 414 are present in face 1302a) can be shared by face segments 1502a, 1502b, 1502c, and 1502d of face 1302a. I / O circuit 407a can be coupled to face branch data bus 1403a. I / O circuit 407a can be coupled to each face segment 1502a, 1502b, 1502c or 1502d of face 1302a, and is configured to guide N data to or from N working memory banks in each face segment 1502a, 1502b, 1502c or 1502d via face branch data bus 1403a and segment branch data buses 1405a, 1405b, 1405c or 1405d.

[0127] Regarding face 1302b, I / O circuit 407b (and corresponding I / O control logic 412 and corresponding register 414, if any corresponding I / O control logic 412 and corresponding register 414 are present in face 1302b) can be shared by face segments 1502a, 1502b, 1502c, and 1502d of face 1302b. I / O circuit 407b can be coupled to face branch data bus 1403b. I / O circuit 407b can be coupled to face segment 1502a or 1502b in face 1302b and configured to direct N data to or from N working memory banks in face segment 1502a or 1502b via face branch data bus 1403b and segment branch data bus 1405e or 1405f, respectively. Additionally, I / O circuit 407b can be coupled to surface segment 1502c or 1502d of surface 1302b, and is configured to guide N data to or from N working memory banks in surface segment 1502c or 1502d via surface branch data bus 1403b, segment branch data bus 1405g, and segment sub-branch data bus 1407a or 1407b, respectively.

[0128] refer to Figure 16B Storage device 1620 may include components similar to those of any suitable storage device disclosed herein, and similar descriptions will not be repeated here. Figure 16B In the middle, surface 1302a may include I / O circuit 407a shared by surface segments 1405a-1405d of surface 1302a. Surface 1302b may include I / O circuits 407b, 407c and 407d.

[0129] Regarding face 1302b, I / O circuit 407b (and corresponding I / O control logic 412 and corresponding register 414, if any corresponding I / O control logic 412 and corresponding register 414 are present in face 1302b) can be shared by face segments 1502c and 1502d of face 1302b. I / O circuit 407b can be coupled to segment branch data bus 1405g. I / O circuit 407b can be coupled to face segment 1502c or 1502d of face 1302b and configured to direct N data to or from N working memory banks in face segment 1502c or 1502d via segment branch data bus 1405g and segment sub-branch data bus 1407a or 1407b, respectively. I / O circuit 407c can be coupled to segment branch data bus 1405f. I / O circuit 407c can be coupled to surface segment 1502b of surface 1302b and is configured to guide N data entries to or from N working memory banks in surface segment 1502b via segment branch data bus 1405f. I / O circuit 407d can be coupled to segment branch data bus 1405e. I / O circuit 407d can be coupled to surface segment 1502a of surface 1302b and is configured to guide N data entries to or from N working memory banks in surface segment 1502a via segment branch data bus 1405e.

[0130] refer to Figure 16C The storage device 1630 may include components similar to those of any suitable storage device disclosed herein, and similar descriptions will not be repeated here. Face 1302a may include I / O circuits 407a, 407b, 407c, and 407d corresponding to face segments 1502a, 1502b, 1502c, and 1502d, respectively. I / O circuit 407a may be coupled to face segment 1502a of face 1302a and is configured to direct N data entries to or from N working memory banks in face segment 1502a via segment branch data bus 1405a. I / O circuit 407b may be coupled to face segment 1502b of face 1302a and is configured to direct N data entries to or from N working memory banks in face segment 1502b via segment branch data bus 1405b. I / O circuit 407c can be coupled to surface segment 1502c of surface 1302a and is configured to guide N data entries to or from N working memory banks in surface segment 1502c via segment branch data bus 1405c. I / O circuit 407d can be coupled to surface segment 1502d of surface 1302a and is configured to guide N data entries to or from N working memory banks in surface segment 1502d via segment branch data bus 1405d.

[0131] Surface 1302b may include I / O circuits 407e, 407f, 407g, and 407h corresponding to surface segments 1502a, 1502b, 1502c, and 1502d, respectively. I / O circuit 407e may be coupled to surface segment 1502a of surface 1302b and is configured to guide N data entries to or from N working memory banks in surface segment 1502a via segment branch data bus 1405e. I / O circuit 407f may be coupled to surface segment 1502b of surface 1302b and is configured to guide N data entries to or from N working memory banks in surface segment 1502b via segment branch data bus 1405f. I / O circuit 407g can be coupled to surface segment 1502c of surface 1302b and is configured to guide N data entries to or from N working memory banks in surface segment 1502c via segment sub-branch data bus 1407a. I / O circuit 407h can be coupled to surface segment 1502d of surface 1302b and is configured to guide N data entries to or from N working memory banks in surface segment 1502d via segment sub-branch data bus 1407b.

[0132] refer to Figure 16D Storage device 1640 may include components similar to those of any suitable storage device disclosed herein, and similar descriptions will not be repeated here. Figure 16D In the middle, surface 1302a may include I / O circuit 407a shared by surface segments 1502a, 1502b, 1502c and 1502d of surface 1302a. Surface 1302b may include I / O circuits 407b and 407c.

[0133] Regarding face 1302b, face branch data bus 1403b can branch at node 1402b to form segment branch data buses 1405e and 1405f. Segment branch data bus 1405e can branch at node 1404a to form segment sub-branch data buses 1407a and 1407b. Segment branch data bus 1405f can branch at node 1404b to form segment sub-branch data buses 1407c and 1407d. I / O circuit 407b (and the corresponding I / O control logic 412 and the corresponding register 414, if there are any corresponding I / O control logic 412 and the corresponding register 414 in face 1302b) can be shared by face segments 1502a and 1502b of face 1302b. I / O circuit 407b can be coupled to segment branch data bus 1405e. I / O circuit 407b can be coupled to surface segment 1502a or 1502b of surface 1302b, and is configured to guide N data to or from N working memory banks in surface segment 1502a or 1502b via segment branch data bus 1405e and segment sub-branch data bus 1407a or 1407b, respectively.

[0134] I / O circuit 407c (and corresponding I / O control logic 412 and corresponding register 414, if any corresponding I / O control logic 412 and corresponding register 414 are present in face 1302b) can be shared by face segments 1502c and 1502d of face 1302b. I / O circuit 407c can be coupled to segment branch data bus 1405f. I / O circuit 407d can be coupled to face segment 1502c or 1502d of face 1302b and is configured to direct N data to or from N working memory banks in face segment 1502c or 1502d via segment branch data bus 1405f and segment sub-branch bus 1407c or 1407d, respectively.

[0135] Figure 17 A schematic diagram of an exemplary storage device 1700 according to some aspects of this disclosure is shown, which implements a faulty primary memory repair scheme in data input using a write MUX array having multiple write subarrays. Storage device 1700 may include components similar to those of any suitable storage device described herein, and similar descriptions will not be repeated herein.

[0136] In some embodiments, the storage device 1700 may include a memory cell array comprising P groups of memory, where P may be a positive integer. Each group of memory may include redundant memory cells 704 for concurrent data input / output and N main memory cells 702 (e.g., N = 8), and thus, the P redundant memory cells are included in and shared by the P groups of memory. I / O circuitry 407 may, for example, be coupled to the P groups of memory in the storage device 1700 via a page buffer / sensor amplifier 404 and a column decoder / bit line driver 406 (or a page buffer / sensor amplifier portion 1406 and a column decoder / bit line driver portion 1506). Figure 17 In some embodiments shown, during data input (e.g., write operations), the page buffer / sensor amplifier 404 and the column decoder / bit line driver 406 (or the page buffer / sensor amplifier portion 1406 and the column decoder / bit line driver portion 1506) may include nine drivers 706 respectively coupled to eight main memory banks 702 and one redundant memory bank 704 in each memory bank.

[0137] I / O circuitry 407 may include N+1 outputs coupled to redundant memory banks 704 and N main memory banks 702 in each memory bank via a data bus 1701 and a set of wiring. This set of wiring may include wires 1702, 1704, 1706, 1708, 1710, 1712, 1714, 1716, and 1718. For example, the outputs of I / O circuitry 407 may be coupled to the corresponding memory banks via corresponding data lines of the data bus 1701 and corresponding wires in the wiring group.

[0138] In some implementations, the I / O circuit 407 may be located in the first-level storage element 1514 and shared by multiple second-level storage elements 1515a and 1515b, such as Figure 15A As shown. The data bus 1701 can be Figure 15A The first-level data bus 1510 in the system. This group of wiring may include branch data buses 1512a or 1512b, depending on which second-level storage element 1515a or 1515b the N main memory banks 702 and redundant memory banks 704 are located in.

[0139] In some implementations, the I / O circuit 407 may be located in the die and shared by multiple surfaces (e.g., as shown in the image). Figure 15B-15D (As shown). For example, data bus 1701 can be Figure 15B The global data bus 1418 is shown. This group of cabling may include... Figure 15B The shown face-branch data bus 1403a or 1403b depends on which face the N main memory banks 702 and redundant memory banks 704 are located on. In another example, data bus 1701 could be... Figure 15C Or the global data bus 1418 shown in 15D. This group of cabling may include Figure 15D The face branch data bus 1403a or 1403b, the segment branch data bus 1405a-1405g, and the segment sub-branch data bus 1407a or 1407b shown depend on which segment of face 1302a or face 1302b the N main memory banks 702 and redundant memory banks 704 are located in.

[0140] In some implementations, the I / O circuit 407 may be located in a plane and shared by multiple plane segments within the plane. For example, Figure 17 The I / O circuit 407 in the middle can be Figure 16A The I / O circuits are 407a or 407b, and the data bus 1701 can be... Figure 16A The shown is a branched data bus 1403a or 1403b. This group of cabling may include... Figure 16A The segment branch data buses 1405a-1405g and / or segment sub-branch data buses 1407a or 1407b shown depend on which segment of face 1302a or face 1302b the N main memory banks 702 and redundant memory banks 704 are located in. In another example, Figure 17 The I / O circuit 407 in the middle can be Figure 16D The I / O circuit 407b, and the data bus 1701 can be Figure 16D The segment branch data bus 1405e in face 1302b. This group of cabling may include Figure 16D The segment sub-branch data bus 1407a or 1407b shown depends on which face segment 1502a or 1502b of face 1302b the N main memory banks 702 and redundant memory banks 704 are located in. In yet another example, Figure 17 The I / O circuit 407 in the middle can be Figure 16D The I / O circuit 407c, and the data bus 1701 can be Figure 16D The segment branch data bus 1405f in face 1302b. This group of cabling may include Figure 16D The segment sub-branch data bus 1407c or 1407d shown depends on which face segment 1502c or 1502d of face 1302b the N main memory banks 702 and redundant memory banks 704 are located in.

[0141] I / O circuitry 407 may include a write MUX array 707. In some embodiments, the write MUX array 707 may include P serially applied write subarrays 1720 (e.g., a first write subarray, a second write subarray, ..., and a Pth write subarray). See below for reference. Figure 18A , 18D Various exemplary structures for each write subarray 1720 are described in more detail in 19A.

[0142] Figure 18A A schematic diagram of an exemplary storage device 1800 according to some aspects of this disclosure is shown, which implements a faulty primary memory repair scheme in data input using a write MUX array with two write subarrays. Storage device 1800 may include components similar to those of any suitable storage device described herein, and similar descriptions will not be repeated here. In some embodiments, storage device 1800 may include a memory cell array comprising P groups of memory (P=2), such as Group 0 and Group 1. Each group of memory may include one redundant memory cell 704 and N primary memory cells 702 for concurrent data input / output (e.g., N=8), and thus, the two redundant memory cells 704 are included in and shared by the two groups of memory.

[0143] exist Figure 18A In some embodiments shown, the write MUX array 707 of the I / O circuit 407 may include a first write subarray 1720a and a second write subarray 1720b. Each write subarray 1720a or 1720b may include a redundant write MUX 1881 and N primary write MUX 1880s (e.g., N = 8). The redundant write MUX 1881 may be located among the N primary write MUX 1880s in each write subarray 1720a or 1720b. Each primary write MUX 1880 and each redundant write MUX 1881 may each include a first input terminal A, a second input terminal B, a selection port S, and an output terminal Out. The redundant write MUX 1881 in the second write subarray 1720b may also include a first redundant input terminal C, while the redundant write MUX 1881 in the first write subarray 1720a does not include any redundant input terminals.

[0144] In some implementations, each of the first write subarray 1720a and the second write subarray 1720b may have the same characteristics as... Figure 7 The structure of the write MUX array 707 shown is similar. However, the redundant write MUX 1881 of the second write subarray 1720b can additionally include a first redundant input terminal C, and Figure 7 The write MUX in the write MUX array 707 does not include any redundant inputs. In some implementations, Figure 7 Two instances of the write MUX array 707 can be serially cascaded and modified to form Figure 18A The write MUX array 707 has two write subarrays, 1720a and 1720b. Generally speaking, Figure 7 P instances of the write MUX array 707 can be cascaded and modified to form a write MUX array with P write subarrays.

[0145] Regarding the first write subarray 1720a, the output of each master write MUX 1880 is coupled to the first input A of the corresponding master write MUX 1880 in the second write subarray 1720b via a corresponding signal line (e.g., 1811, 1812, 1813, 1814, 1816, 1817, 1818, or 1819). The output of the redundant write MUX 1881 in the first write subarray 1720a is coupled to the redundant input C of the redundant write MUX 1881 in the second write subarray 1720b via signal line 1815. The first input A of each master write MUX 1880 in the first write subarray 1720a is coupled to the corresponding I / O data line (e.g., 1801, 1802, 1803, 1804, 1806, 1807, 1808, or 1809) and is configured to receive data from the corresponding I / O data line.

[0146] Regarding the second write subarray 1720b, the outputs of the N main write MUX 1880 and the redundant write MUX 1881 are coupled to the N main memory banks 702 and redundant memory banks 704 in the corresponding group of memory banks through signal lines 1821, 1822, 1823, 1824, 1825, 1826, 1827, 1828 and 1829, respectively.

[0147] For each write subarray 1720a or 1720b, the first input A and second input B of the redundant write MUX 1881 are coupled to the first input A of two adjacent master write MUX 1880s in the same write subarray. The second input B of each master write MUX 1880 in each write subarray 1720a or 1720b is coupled to the Vdd signal line or the first input A of an adjacent master write MUX 1880 in the same write subarray. The Vdd signal line can be configured to receive the system voltage Vdd. For example, for each master write MUX 1880 located at the left or right end of each write subarray 1720a or 1720b, the second input B of the corresponding master write MUX 1880 is coupled to the Vdd signal line. For each primary write MUX 1880 to the left of the redundant write MUX 1881 (which is not a primary write MUX on the left end), the second input B of the corresponding primary write MUX 1880 is coupled to the first input A of the adjacent primary write MUX 1880 to its left. For each primary write MUX 1880 to the right of the redundant write MUX 1881 (which is not a primary write MUX on the right end), the second input B of the corresponding primary write MUX 1880 is coupled to the first input A of the adjacent primary write MUX 1880 to its right.

[0148] Each master write MUX 1880's selection port S can be configured to receive a write selection signal indicating the selection of an input (A or B). For example, a positive bias write selection signal for each master write MUX 1880, i.e., the write selection signal is enabled, selects the second input B. A negative bias write selection signal for each master write MUX 1880, i.e., the write selection signal is disabled, selects the first input A. In some embodiments, the write selection signal for the corresponding master write MUX 1880 in the first write subarray 1720a can be red1_en_b0_l_wt, red1_en_b0_h_wt, red1_en_b1_l_wt, red1_en_b1_h_wt, red1_en_b2_l_wt, red1_en_b2_h_wt, red1_en_b3_l_wt, or red1_en_b3_h_wt. The write selection signal for the corresponding master write MUX 1880 in the second write subarray 1720b can be red2_en_b0_l_wt, red2_en_b0_h_wt, red2_en_b1_l_wt, red2_en_b1_h_wt, red2_en_b2_l_wt, red2_en_b2_h_wt, red2_en_b3_l_wt, or red2_en_b3_h_wt.

[0149] Each redundant write MUX 1880's selection port S can be configured to receive a write selection signal indicating the selection of an input (A, B, C, or any other available redundant input). For example, a first level of the write selection signal (indicating that the write selection signal is disabled) can select the first input A, a second level can select the second input B, a third level can select the first redundant input C, and so on. In some embodiments, the write selection signal for the redundant write MUX 1881 in the first write subarray 1720a can be red1_en_b12_wt. The write selection signal for the redundant write MUX 1881 in the second write subarray 1720b can be red2_en_b12_wt.

[0150] In some implementations, each master write MUX 1880 or redundant write MUX 1881 can be configured as a holding element with storage functionality. A holding element can be configured to temporarily store its previous output signal and maintain the previous output signal for the current clock cycle regardless of the current input. For example, a write select signal can be configured to have a specific voltage or current level (referred to herein as a holding level) such that the master write MUX 1880 or redundant write MUX 1881 can become a holding element in response to receiving a write select signal with a holding level. References below... Figure 18B-18C Exemplary applications of holding elements are described in 19B-19C.

[0151] Figure 18B-18C This disclosure illustrates some aspects of the present disclosure. Figure 18A An exemplary faulty main memory repair scheme is implemented in the data input of the storage device 1800. (See reference...) Figure 18B Assume that Group 0 and Group 1 together comprise two failed main memory banks. As shown in Table 1856, these two failed main memory banks can be distributed within Group 0 (e.g., B0_L and B0_H in Group 0 are failed main memory banks). This document incorporates references... Figure 9 and 18A describe Figure 18B .

[0152] In some implementations, the working memory logic 906 of the I / O control logic 412 is coupled to register 414 and configured to obtain memory failure information indicating two failed primary memory units from Group 0. The working memory logic 906 can determine 2×N working memory units from Group 0 and Group 1 that can be used for data input and output. That is, the working memory logic 906 can replace the two failed primary memory units with the same number of redundant memory units, such that the 2×N working memory units can include two redundant memory units from Group 0 and Group 1 and 2×N-2 primary memory units.

[0153] Based on the determined 2×N working memory banks, write redundancy enable logic 904 can be configured to control I / O circuitry 407 to direct 2×N data entries to the 2×N working memory banks respectively. For example, write redundancy enable logic 904 is coupled to each primary write MUX 1880 and each redundant write MUX 1881 in each write subarray 1720a or 1720b. Write redundancy enable logic 904 is configured to provide multiple write select signals 903 to the primary write MUX 1880 and redundant write MUX 1881 in each write subarray 1720a or 1720b based on the determined 2×N working memory banks.

[0154] Suppose that the intention is to store the first N data entries, including (0,0), (0,1), ..., and (0,7) (where N = 8), in the N main storage blocks of Group 0, and the intention is to store the second N data entries, including (1,0), (1,1), ..., and (1,7), in the N main storage blocks of Group 1. Figure 18B The data is written in the order from Group 0 to Group 1. The first row of Table 1850 shows that the first N data entries are loaded onto I / O signal lines 1801-1804 and 1806-1809 at clock signal 0 (clk0). The second row of Table 1850 also shows that the second N data entries are loaded onto I / O signal lines 1801-1804 and 1806-1809 at clock signal 1 (clk1).

[0155] Initially, at clk0, the first N data lines (0,0), (0,1), ..., and (0,7) are input to the main write MUX 1880 of the first write subarray 1720a via I / O signal lines 1801-1804 and 1806-1809, as shown in the first row of Table 1850.

[0156] At clkl, since B0_L of Group 0 is a faulty primary memory bank, write redundancy enable logic 904 can enable red1_en_b0_l_wt, ..., and red1_en_b1_h_wt, allowing each primary write MUX 1880 to the left of the redundant write MUX 1881 in the first write subarray 1720a to input data from the second input terminal B to achieve a right data shift of one memory bank. That is, the data (0,0), (0,1), and (0,2) are shifted right by one memory bank by the first write subarray 1720a and output by signal lines 1812-1814, as shown in the first row of Table 1852. Write enable logic 904 can also disable red1_en_b12_wt, causing (0,3) to be redirected to the redundant write MUX 1881 of the first write subarray 1720a and output by signal line 1815, as shown in the first row of Table 1852. As a result, each data (0,0), (0,1), (0,2), or (0,3) is right-shifted one memory bank at clk1 by the first write subarray 1720a. For other data (0,4), (0,5), (0,6), and (0,7), input data shifting may not be necessary, allowing write redundancy enable logic 904 to disable red1_en_b2_l_wt, red1_en_b2_h_wt, red1_en_b3_l_wt, and red1_en_b3_h_wt. Then, each main write MUX 1880 to the right of the redundant write MUX 1881 can input data from the first input terminal A without data shifting, and the data (0,4), (0,5), (0,6), and (0,7) are output by the first write subarray 1720a via signal lines 1816-1819, as shown in the first row of Table 1852. As a result, at clk1, the first N data lines (0,0), (0,1), (0,2), (0,3), (0,4), (0,5), (0,6), and (0,7) are input to the second write subarray 1720b via signals 1812-1819, respectively. For example, at clk1, data (0,3) is input to the redundant input C of the redundant write MUX 1881 of the second write subarray 1720b via signal line 1815.

[0157] Furthermore, at clk1, the second N data (1,0), (1,1), ..., and (1,7) are input to the main write MUX1 1880 of the first write subarray 1720a through I / O signal lines 1801-1804 and 1806-1809, as shown in the second row of Table 1850.

[0158] At clock signal 2 (clk2), since B0_H of Group 0 is also a faulty primary memory bank, the write redundancy enable logic 904 can enable red2_en_b0_h_wt, red2_en_b1_l_wt, and red2_en_b1_h_wt. This allows the corresponding primary write MUX 1880 on the left side of the redundant write MUX 1881 of the second write subarray 1720b to input data (0,0) and (0,1) from the second input terminal B, thereby achieving a right data shift of one memory bank. That is, the data (0,0) and (0,1) are shifted right again by one memory bank and output by signal lines 1823 and 1824 respectively, as shown in the first row of Table 1854. The write redundancy enable logic 904 can also disable red2_en_b12_wt, causing the redundant write MUX 1881 that redirects data (0,2) from the first input A to the second write subarray 1720b and outputs it via signal line 1825, as shown in the first row of Table 1854. As a result, at clk2, each data (0,0), (0,1), or (0,2) is right-shifted one memory bank by the second write subarray 1720b, as shown in the first row of Table 1854. For the other data (0,4), (0,5), (0,6), and (0,7), no input data shift is required, and the data (0,4), (0,5), (0,6), and (0,7) are output by the second write subarray 1720b via signal lines 1826-1829 respectively, without data shifting, as shown in the first row of Table 1854. As a result, at clk2, the data (0,0), (0,1), (0,2), (0,4), (0,5), (0,6), and (0,7) from the first N data entries are output to the seven working memory banks in Group 0 via signal lines 1823-1829. That is, the data (0,0), (0,1), (0,2), (0,4), (0,5), (0,6), and (0,7) from the first N data entries are stored in the seven working memory banks of Group 0, as shown in the second row of Table 1856.

[0159] Furthermore, at clk2, the second N data lines (1,0), (1,1), ..., and (1,7) are output from the first write subarray 1720a via signal lines 1811-1814 and 1816-1819 respectively, without data shifting, as shown in the second row of Table 1852. Write redundancy enable logic 904 can generate a write select signal (e.g., red1_en_b12_wt with a hold level) with a hold level for the redundant write MUX 1881 of the first write subarray 1720a, such that the redundant write MUX 1881 of the first write subarray 1720a is configured as a hold element to maintain its previous output signal regardless of the current input. Therefore, the redundant write MUX 1881 of the first write subarray 1720a can still output data (0,3) at clk2 via signal line 1815 (e.g., the same as clk1), as shown in the second row of Table 1852. That is, the data (0,3) is still input to the redundant input C of the redundant write MUX 1881 of the second write subarray 1720b via signal line 1815 (e.g., the same as clk1). Therefore, at clk2, the second N data is combined with the data (0,3) from the first N data and input to the second write subarray 1720b respectively, as shown in the second row of Table 1852.

[0160] At clock signal 3 (clk3), the second N data lines (1,0), (1,1), ..., (1,7) are output by the second write subarray 1720b via signal lines 1821-1824 and 1826-1829 respectively, without data shifting, as shown in the second row of Table 1854. Write redundancy enable logic 904 can also enable red2_en_b12_wt to the third level, causing the redundant write MUX 1881 of the second write subarray 1720b to select its output from the redundant input C and output data (0,3) via signal line 1825, as shown in the second row of Table 1854. That is, at clk3, the second N data lines (1,0), (1,1), ..., (1,7) are output and stored in the N main memory banks of Group 1, and the data (0,3) from the first N data lines is output and stored in the redundant memory bank of Group 1, as shown in the first row of Table 1856.

[0161] refer to Figure 18C Assume that B0_L and B0_H in Group 0 are the faulty primary memory as shown in Table 1866 (and... Figure 18B (Same as Table 1856 in the table). Similar to... Figure 18B The intention is to store the first N data entries (where N = 8) including (0,0), (0,1), ..., and (0,7) in the N main storage blocks of Group 0, and to store the second N data entries including (1,0), (1,1), ..., and (1,7) in the N main storage blocks of Group 1. Figure 18B and 18C The differences between them include Figure 18B The data is written in the order from Group 0 to Group 1, and Figure 18C The data is written in the order from Group 1 to Group 0. This article references... Figure 9 and 18A describe Figure 18C .

[0162] Figure 18C The first row of Table 1860 shows the second N data points (1,0), (1,1), ..., (1,7) loaded at clk0 respectively. Figure 18A The I / O signal lines are 1801-1804 and 1806-1809. That is, at clk0, the second N data are input to the main write MUX1880 of the first write subarray 1720a through I / O signal lines 1801-1804 and 1806-1809 respectively.

[0163] At clk1, since there is no faulty primary memory in Group 1, the second N data (1,0), (1,1), ..., and (1,7) are output from the first write subarray 1720a through signal lines 1811-1814 and 1816-1819 respectively, without data shifting, as shown in the first row of Table 1862.

[0164] Similarly, at clk1, the first N data segments (0,0), (0,1), ..., (0,7) are loaded onto I / O signal lines 1801-1804 and 1806-1809, respectively. That is, at clk1, the first N data segments are input to the main write MUX 1880 of the first write subarray 1720a via I / O signal lines 1801-1804 and 1806-1809, respectively.

[0165] At clk2, the second N data entries (1,0), (1,1), ..., (1,7) that were input to the second write subarray 1720b at clk1 may not yet have been processed by the second write subarray 1720b. Since B0_L and B0_H of Group 0 are faulty primary memory, the second N data entries are continuously input to the second write subarray 1720b in order to wait for a data entry from the first N data entries. This allows the data entry from the first N data entries to be written to the redundant memory of Group 1 while the second N data entries are being written to the primary memory of Group 1.

[0166] Specifically, at clk2, the write redundancy enable logic 904 can generate a write select signal with a hold level for each master write MUX 1880 of the first write subarray 1720a, such that each master write MUX 1880 of the first write subarray 1720a is configured as a hold element to maintain the previous output signal of clk1, regardless of the current input. That is, at clk2, the second N data (1,0), (1,1), ..., and (1,7) are still output from the N master write MUX 1880s of the first write subarray 1720a via signal lines 1811-1814 and 1816-1819 respectively, without data shifting, as shown in the second row of Table 1862. Simultaneously, the write redundancy enable logic 904 can generate a write select signal with a first level for the redundant write MUX 1881 of the first write subarray 1720a (e.g., the write redundancy enable logic 904 can disable red1_en_b12_wt for the redundant write MUX 1881), causing the data (0,3) from the first N data lines to be redirected from input A of the redundant write MUX 1881 of the first write subarray 1720a to the redundant write MUX 1881 of the first write subarray 1720a and output by signal line 1815 (with a right data shift of one memory bank), as shown in the second row of Table 1862. In this case, at clk2, the second N data lines (1,0), (1,1), ..., and (1,7) and the data (0,3) from the first N data lines are combined and input to the second write subarray 1720b via signal lines 1811-1819 respectively.

[0167] Furthermore, at clk2, the first N data lines (0,0), (0,1), ..., and (0,7) are not processed by the primary write MUX 1880 of the first write subarray 1720a (except for data (0,3), which is processed by the redundant write MUX 1881 of the first write subarray 1720a, as described above). The first N data lines are still loaded onto I / O signal lines 1801-1804 and 1806-1809, respectively, as shown in the third row of Table 1860.

[0168] At clk3, the second N data entries (1,0), (1,1), ..., (1,7) and the data entry (0,3) from the first N data entries are output from the N main write MUX 1880 and redundant write MUX 1881 of the second write subarray 1720b via signal lines 1821-1829, respectively, without data shifting, as shown in the first row of Table 1864. That is, at clk3, the second N data entries (1,0), (1,1), ..., (1,7) are output and stored in the N main memory banks of Group 1, and the data entry (0,3) from the first N data entries is output and stored in the redundant memory bank of Group 1, as shown in the first row of Table 1866.

[0169] Furthermore, at clk3, because Group 0's B0_L is a faulty primary memory bank, the data (0,0), (0,1), and (0,2) are shifted one memory bank to the right by the first write subarray 1720a and output via signal lines 1812-1814, as shown in the third row of Table 1862. For the other data (0,4), (0,5), (0,6), and (0,7), no input data shifting may be required. The data (0,4), (0,5), (0,6), and (0,7) are output by the first write subarray 1720a via signal lines 1816-1819 without data shifting, as shown in the third row of Table 1862. As a result, at clk3, the first N data lines (0,0), (0,1), (0,2), (0,4), (0,5), (0,6) and (0,7) are input to the second write subarray 1720b via signal lines 1812-1814 and 1816-1819 respectively.

[0170] At clock signal 4 (clk4), because Group 0's B0_H is also a faulty primary memory bank, data (0,0) and (0,1) are again right-shifted one memory bank by the second write subarray 1720b and output via signal lines 1823 and 1824, respectively, as shown in the second row of Table 1864. Data (0,2) is redirected from input A of the redundant write MUX 1881 of the second write subarray 1720b to the redundant write MUX 1881 of the second write subarray 1720b and output via signal line 1825 with a right data shift of one memory bank, as shown in the second row of Table 1864. As a result, each data (0,0), (0,1), or (0,2) is right-shifted one memory bank by the second write subarray 1720b at clk4. For the other data (0,4), (0,5), (0,6), and (0,7), no input data shifting is required, and the data (0,4), (0,5), (0,6), and (0,7) are output from the second write subarray 1720b via signal lines 1826-1829 without data shifting, as shown in the second row of Table 1864. As a result, at clk4, the data (0,0), (0,1), (0,2), (0,4), (0,5), (0,6), and (0,7) from the first N data entries are output to the seven working memory banks in Group 0 via signal lines 1823-1829. That is, the data (0,0), (0,1), (0,2), (0,4), (0,5), (0,6), and (0,7) from the first N data entries are stored in the seven working memory banks of Group 0, as shown in the second row of Table 1866.

[0171] Figure 18D A schematic diagram of another exemplary storage device 1890 according to some aspects of this disclosure is shown, which uses a write MUX array with two write subarrays to implement a faulty primary memory repair scheme in the data input. Storage device 1890 may include any suitable storage device described herein (e.g., Figure 18A The components of the storage device 1800 are similar to those components, and similar descriptions will not be repeated here. For example, Figure 18D Each of Group 0 and Group 1 can include N main memory banks 702 and 1 redundant memory bank 704 for concurrent data input / output, where N = 4. The write MUX array 707 of the I / O circuit 407 can include a first write subarray 1720a and a second write subarray 1720b. Each write subarray 1720a or 1720b can include a redundant write MUX 1881 and N main write MUX 1880, where N = 4.

[0172] The redundant write MUX 1881 can be located to the left or right of the N primary write MUX 1880s in each write subarray 1720a or 1720b. One of the first and second inputs of the redundant write MUX 1881 in each write subarray 1320a or 1320b is coupled to the first input A of an adjacent primary write MUX 1880 in the same write subarray, and the other of the first and second inputs of the redundant write MUX 1881 is coupled to the Vdd signal line. For example, as... Figure 18D As shown, the redundant write MUX 1881 is located to the right of the N primary write MUX 1880s in each write subarray 1720a or 1720b. The first input terminal A of the redundant write MUX 1881 is coupled to the first input terminal A of the adjacent primary write MUX 1880 on the left. The second input terminal B of the redundant write MUX 1881 is coupled to the Vdd signal line.

[0173] Figure 19A A schematic diagram of an exemplary storage device 1900 according to some aspects of this disclosure is shown, which implements a faulty primary memory repair scheme in data input using a write MUX array with three write subarrays. Storage device 1900 may include components similar to those of any suitable storage device described herein, and similar descriptions will not be repeated here. In some embodiments, storage device 1900 may include a memory cell array comprising P groups of memory (P=3), such as Group 0, Group 1, and Group 2. Each group of memory may include N primary memory cells 702 (e.g., N=4) and one redundant memory cell 704 for concurrent data input / output; thus, the three redundant memory cells 704 are included in and shared by the three groups of memory.

[0174] Figure 19A The write MUX array 707 may include a first write subarray 1720a, a second write subarray 1720b, and a third write subarray 1720c. Each write subarray 1720a, 1720b, or 1720c may include a redundant write MUX 1881 and N primary write MUX 1880s (e.g., N = 4). The redundant write MUX 1881 in the second write subarray 1720b may include a redundant input C, and the redundant write MUX 1881 in the third write subarray 1720c may include redundant inputs C and D.

[0175] Regarding the first write subarray 1720a, the output of each master write MUX 1880 is coupled to the first input A of the corresponding master write MUX 1880 in the second write subarray 1720b via a corresponding signal line (e.g., 1913, 1914, 1916, or 1917). The output of the redundant write MUX 1881 in the first write subarray 1720a is coupled to the redundant input C of the redundant write MUX 1881 in the second write subarray 1720b via signal line 1915, and is also coupled to the redundant input D of the redundant write MUX 1881 in the third write subarray 1720c via signal line 1925b. Signal line 1915 is connected to signal line 1925b. The first input terminal A of each master write MUX 1880 in the first write subarray 1720a is coupled to the corresponding I / O data line (e.g., 1903, 1904, 1906, or 1907) and is configured to receive data from the corresponding I / O data line.

[0176] Regarding the second write subarray 1720b, the output of each primary write MUX 1880 is coupled to the first input A of the corresponding primary write MUX 1880 in the third write subarray 1720b via a corresponding signal line (e.g., 1923, 1924, 1926, or 1927). The output of the redundant write MUX 1881 in the second write subarray 1720b is coupled to the redundant input C of the redundant write MUX 1881 in the third write subarray 1720c via signal line 1925a.

[0177] Regarding the third write subarray 1720c, the outputs of the N main write MUX 1880 and the redundant write MUX 1881 are coupled to the N main memory banks 702 and redundant memory banks 704 in the corresponding group of memory banks through signal lines 1933, 1934, 1935, 1936 and 1937, respectively.

[0178] For each write subarray 1720a, 1720b, or 1720c, the first input A and second input B of the redundant write MUX 1881 are coupled to the first input A of two adjacent master write MUX 1880s in the same write subarray. The second input B of each master write MUX 1880 in each write subarray 1720a, 1720b, or 1720c is coupled to the Vdd signal line or to the first input A of an adjacent master write MUX 1880 in the same write subarray. For example, for each master write MUX 1880 located at a corresponding end of each write subarray 1720a, 1720b, or 1720c, the second input B of the corresponding master write MUX 1880 is coupled to the Vdd signal line. For each primary write MUX 1880 to the left of the redundant write MUX 1881 (excluding the primary write MUX 1880 at the left end), the second input B of the corresponding primary write MUX 1880 is coupled to the first input A of the adjacent primary write MUX 1880 on the left. For each primary write MUX 1880 to the right of the redundant write MUX 1881 (excluding the primary write MUX at the right end), the second input B of the corresponding primary write MUX 1880 is coupled to the first input A of the adjacent primary write MUX 1880 on the right.

[0179] Each master write MUX 1880's selection port S can be configured to receive a write selection signal indicating the selection of an input (A or B). In some implementations, the write selection signal for the corresponding master write MUX 1880 in the first write subarray 1720a can be red1_en_b0_l_wt, red1_en_b0_h_wt, red1_en_b1_l_wt, or red1_en_b1_h_wt. The write selection signal for the corresponding master write MUX 1880 in the second write subarray 1720b can be red2_en_b0_l_wt, red2_en_b0_h_wt, red2_en_b1_l_wt, or red2_en_b1_h_wt. The write selection signal for the corresponding master write MUX 1880 in the third write subarray 1720c can be red3_en_b0_l_wt, red3_en_b0_h_wt, red3_en_b1_l_wt, or red3_en_b1_h_wt.

[0180] Each redundant write MUX 1880's selection port S can be configured to receive a write selection signal indicating the selection of an input (A, B, C, D, or any other available input). For example, a first level of the write selection signal (indicating that the write selection signal is disabled) can select a first input A, a second level can select a second input B, a third level can select a redundant input C, and a fourth level can select a redundant input D. In some implementations, the write selection signals for the redundant write MUX 1881 in the first write subarray 1720a, the second write subarray 1720b, and the third write subarray 1720c can be red1_en_b01_wt, red2_en_b01_wt, and red3_en_b01_wt, respectively.

[0181] Figure 19B-19C This disclosure illustrates some aspects of the present disclosure. Figure 19A An exemplary faulty main memory repair scheme is implemented in the data input of the storage device 1900. (See reference...) Figure 19B Assume that Group 0, Group 1, and Group 2 comprise a total of three failed main memory units. As shown in Table 1956, these three failed main memory units can be distributed within Group 0 (for example, B0_L, B0_H, and B1_L in Group 0 are failed main memory units). This document incorporates references... Figure 9 and 19A To describe Figure 19B .

[0182] In some implementations, the working memory logic 906 of the I / O control logic 412 is coupled to register 414 and configured to obtain memory failure information indicating three failed primary memory units from Group 0. The working memory logic 906 can determine 3×N working memory units available for data input and output from Group 0, Group 1, and Group 3. That is, the working memory logic 906 can replace the three failed primary memory units with the same number of redundant memory units, such that the 3×N working memory units can include three redundant memory units from Group 0, Group 1, and Group 2, and 3×N-3 primary memory units.

[0183] Based on the determined 3×N working memory banks, the write redundancy enable logic 904 can be configured to control the I / O circuit 407 to direct 3×N data entries to the 3×N working memory banks respectively. For example, the write redundancy enable logic 904 is coupled to the primary write MUX 1880 and redundant write MUX 1881 in each write subarray 1720a, 1720b, or 1720c, and is configured to provide multiple write select signals 903 to the primary write MUX 1880 and redundant write MUX 1881 in each write subarray 1720a, 1720b, or 1720c based on the determined 3×N working memory banks.

[0184] Suppose that the intention is to store the first N data entries (where N=4) including (0,0), (0,1), (0,2), and (0,3) in the N main storage blocks of Group 0, the intention is to store the second N data entries including (1,0), (1,1), (1,2), and (1,3) in the N main storage blocks of Group 1, and the intention is to store the third N data entries including (2,0), (2,1), (2,2), and (2,3) in the N main storage blocks of Group 2. Figure 19B The data is written in the order from Group 0 to Group 1, and then to Group 2. Figure 19B Table 1950 shows the first N data entries loaded at clk0 to I / O signal lines 1903, 1904, 1906, and 1907 respectively. Table 1950 also includes a second N data entries loaded at clk1 to I / O signal lines 1903, 1904, 1906, and 1907 respectively. Table 1950 further includes a third N data entries loaded at clk2 to I / O signal lines 1903, 1904, 1906, and 1907 respectively.

[0185] Initially, at clk0, the first N data lines (0,0), (0,1), (0,2) and (0,3) are input to the main write MUX 1880 of the first write subarray 1720a through I / O signal lines 1903, 1904, 1906 and 1907, as shown in the first row of Table 1950.

[0186] At clk1, because Group 0's B0_L is the faulty primary memory, the data (0,0) and (0,1) from the first N data entries are shifted one memory cell to the right by the first write subarray 1720a and output via signal lines 1914-1915, as shown in the first row of Table 1952. For the other data (0,2) and (0,3), no input data shift is required, and the data (0,2) and (0,3) are output by the first write subarray 1720a via signal lines 1916 and 1917, respectively, without data shift, as shown in the first row of Table 1952. As a result, at clk1, the first N data entries (0,0), (0,1), (0,2), and (0,3) are input to the second write subarray 1720b via signals 1914-1917. For example, at clk1, data (0,1) is input to the redundant input C of the redundant write MUX 1881 in the second write subarray 1720b via signal line 1915, and is also input to the redundant input D of the redundant write MUX 1881 in the third write subarray 1720b via signal line 1925b.

[0187] Also at clk1, the second N data (1,0), (1,1), (1,2), and (1,3) are input to the main write MUX 1880 in the first write subarray 1720a through I / O signal lines 1903, 1904, 1906, and 1907, respectively, as shown in the second row of Table 1950.

[0188] At clk2, because Group 0's B0_H is also a faulty primary memory, the data (0,0) from N data entries is redirected from input A to the redundant write MUX 1881 of the second write subarray 1720b and output via signal line 1925a from the redundant write MUX 1881 of the second write subarray 1720b (with a right data shift of one memory cell), as shown in the first row of Table 1954. For other data (0,2) and (0,3), no input data shift may be required, and data (0,2) and (0,3) are output from the second write subarray 1720b via signal lines 1926 and 1927 respectively, without data shift, as shown in the first row of Table 1954. As a result, the data (0,0), (0,2) and (0,3) from the first N data are output by the second write subarray 1720b through signal lines 1925a, 1926 and 1927 respectively, as shown in the first row of Table 1954.

[0189] Write redundancy enable logic 904 can generate a write select signal (e.g., red1_en_b01_wt with a hold level) having a hold level for the redundant write MUX 1881 of the first write subarray 1720a. As a result, the redundant write MUX 1881 of the first write subarray 1720a is configured as a hold element to maintain its previous output signal at clk1, and still outputs data (0,1) at clk2 via signal line 1915. Therefore, at clk2, data (0,1) is still input via signal line 1915 to the redundant input C of the redundant write MUX 1881 of the second write subarray 1720b and via signal line 1925b to the redundant D of the redundant write MUX 1881 of the third write subarray 1720c. As a result, at clk2, the first N data (0,0), (0,1), (0,2) and (0,3) are input to the third write subarray 1720b through signal lines 1925a, 1925b, 1926 and 1927 respectively, as shown in the first row of Table 1954.

[0190] Furthermore, at clk2, the second N data lines (1,0), (1,1), (1,2), and (1,3) are output from the first write subarray 1720a via signal lines 1913, 1914, 1916, and 1917, respectively, without data shifting, as shown in the second row of Table 1952. As mentioned above, at clk2, the data (0,1) is still input to the redundant input C of the redundant write MUX 1881 of the second write subarray 1720b via signal line 1915. As a result, at clk2, the second N data lines and the data (0,1) from the first N data lines are input to the second write subarray 1720b via signal lines 1913-1917, respectively, as shown in the second row of Table 1952.

[0191] In addition, at clk2, the third N data (2,0), (2,1), (2,2), and (2,3) are input to the main write MUX 1880 of the first write subarray 1720a via I / O signal lines 1903, 1904, 1906, and 1907, as shown in the third row of Table 1950.

[0192] At clk3, because B1_L of Group 0 is also a faulty primary memory, the data (0,2) from the first N data entries is redirected from input B to the redundant write MUX 1881 of the third write subarray 1720c and output via signal line 1935 (with a left data shift of one memory bank), as shown in the first row of Table 1955. For data (0,3), no input data shift is required. Data (0,3) is output via signal line 1937 from the third write subarray 1720c without data shift, as shown in the first row of Table 1955. As a result, at clk3, the data (0,2) and (0,3) from the first N data entries are output to the two working memory banks in Group 0 via signal lines 1935 and 1937, respectively. That is, the data (0,2) and (0,3) from the first N data are stored in the two working storages of Group 0, as shown in the last row of Table 1956.

[0193] Also at clk3, the second N data lines (1,0), (1,1), (1,2), and (1,3) are output from the N master write MUX 1880s of the second write subarray 1720b via signal lines 1923, 1924, 1926, and 1927, respectively, without data shifting, as shown in the second row of Table 1954. Furthermore, the redundant write MUX 1881 of the first write subarray 1720a is still configured as a holding element to maintain the previous output signal of clk2, and still outputs the data (0,1) from the first N data lines via signal line 1915. Therefore, the data (0,1) is still input to the redundant input C of the redundant write MUX 1881 of the second write subarray 1720b via signal line 1915, and to the redundant D of the redundant write MUX 1881 of the third write subarray 1720c via signal line 1925b. Furthermore, the redundant write MUX 1881 of the second write subarray 1720b is configured as a holding element to maintain the previous output signal of clk2, and outputs data (0,0) from the first N data lines via signal line 1925a at clk3. Therefore, the data (0,0) is still input to the redundant input C of the redundant write MUX 1881 of the third write subarray 1720c via signal line 1925a. As a result, at clk3, the second N data lines and the data (0,0) and (0,1) from the first N data lines are input to the third write subarray 1720c via signal lines 1913, 1924, 1925a, 1925b, 1926, and 1927, respectively, as shown in the second row of Table 1954.

[0194] Also at clk3, the third N data lines (2,0), (2,1), (2,2), and (2,3) are output from the N main write MUX 1880s of the first write subarray 1720a via signal lines 1913, 1914, 1916, and 1917, respectively, without data shifting, as shown in the second row of Table 1952. As mentioned above, at clk3, the data (0,1) is still input to the redundant input terminal C of the redundant write MUX 1881 of the second write subarray 1720b via signal line 1915. As a result, at clk3, the data (2,0), (2,1), (0,1), (2,2), and (2,3) are input to the second write subarray 1720b via signal lines 1913-1917, respectively, as shown in the second row of Table 1952.

[0195] At clk4, the second N data lines (1,0), (1,1), (1,2), and (1,3) are output from the N main write MUX 1880s of the third write subarray 1720c via signal lines 1933, 1934, 1936, and 1937, respectively, without data shifting, as shown in the second row of Table 1955. Write redundancy enable logic 904 enables red3_en_b01_wt to the third level, causing the redundant write MUX 1881 of the write subarray 1720c to select data (0,0) from its redundant input C and output data (0,0) via signal line 1935, as shown in the second row of Table 1955. As a result, at clk4, the second N data lines are combined with data (0,0) from the first N data lines, causing the second N data lines and data (0,0) to be output to the five working memory banks of Group 1 via signal lines 1933-1937, respectively. That is, the second N data and the data (0,0) from the first N data are stored in the five working storages of Group 1, as shown in the second row of Table 1956.

[0196] Also at clk4, the third N data lines (2,0), (2,1), (2,2), and (2,3) are output from the N master write MUX 1880s of the second write subarray 1720b via signal lines 1923, 1924, 1926, and 1927, respectively, without data shifting, as shown in the third row of Table 1954. At clk4, the redundant write MUX 1881 of the first write subarray 1720a is also configured as a holding element to maintain its previous output signal from clk3, and still outputs data (0,1) from the first N data lines via signal lines 1915 and 1925b. That is, the data (0,1) is still input to the redundant D of the redundant write MUX 1881 of the third write subarray 1720c via signal line 1925b. As a result, at clk4, the third N data is combined with the data (0,1) from the first N data, so that the third N data and the data (0,1) are output to the third write subarray 1720c through signal lines 1923, 1924, 1925b, 1926 and 1927 respectively, as shown in the third row of Table 1954.

[0197] At clock signal 5 (clk5), the third N data lines (2,0), (2,1), (2,2), and (2,3) are output from the N main write MUX 1880s of the third write subarray 1720c via signal lines 1933, 1934, 1936, and 1937, respectively, without data shifting, as shown in the third row of Table 1955. Write redundancy enable logic 904 enables red3_en_b01_wt to the fourth level, causing the redundant write MUX 1881 of the third write subarray 1720c to select data (0,1) from its redundant input D and output data (0,1) via signal line 1935, as shown in the third row of Table 1955. As a result, at clk5, the third N data lines and the data (0,1) from the first N data lines are output to the five working memory banks in Group 2 via signal lines 1933-1937, respectively. That is, the third N data and the data (0,1) from the first N data are stored in the five working storages of Group 2, as shown in the first row of Table 1956.

[0198] refer to Figure 19C Suppose the intention is to store the first N data entries (0,0), (0,1), (0,2), and (0,3) in N main memory locations of Group 0 (where N=4), the intention is to store the second N data entries (1,0), (1,1), (1,2), and (1,3) in N main memory locations of Group 1, and the intention is to store the third N data entries (2,0), (2,1), (2,2), and (2,3) in N main memory locations of Group 2 (e.g., similar to...). Figure 19B That way). Figure 19B and 19C The differences between them include, Figure 19C In this context, Group 0 has two failed main memory banks (e.g., B0_L, B1_L), and Group 1 has one failed main memory bank (e.g., B1_L). Figure 19B In this context, Group 0 has 3 failed primary memory blocks.

[0199] Figure 19C Table 1960 shows the first N data entries loaded at clk0 to I / O signal lines 1903, 1904, 1906, and 1907 respectively. Table 1960 also includes a second N data entries loaded at clk1 to I / O signal lines 1903, 1904, 1906, and 1907 respectively. Table 1960 further includes a third N data entries loaded at clk2 to I / O signal lines 1903, 1904, 1906, and 1907 respectively.

[0200] Initially, at clk0, the first N data lines (0,0), (0,1), (0,2) and (0,3) are input to the main write MUX 1880 of the first write subarray 1720a through I / O signal lines 1903, 1904, 1906 and 1907, as shown in the first row of Table 1960.

[0201] At clk1, the first N data lines (0,0), (0,1), (0,2), and (0,3) are output from the N master write MUX 1880s of the first write subarray 1720a via signal lines 1913, 1914, 1916, and 1917, respectively, without data shifting, as shown in the first row of Table 1962.

[0202] At clk2, since B1_L of Group 0 is the faulty primary memory bank, the redundant write MUX 1881 of the second write subarray 1720b selects data (0,2) from its input B and outputs data (0,2) through signal line 1925a, as shown in the first row of Table 1964. As a result, at clk2, the data (0,2) is shifted left by one memory bank by the second write subarray 1720b. For other data (0,0), (0,1), and (0,3), no input data shift may be required. Then, the data (0,0), (0,1), and (0,3) are output by the second write subarray 1720b through signal lines 1923, 1924, and 1927 respectively, without data shift, as shown in the first row of Table 1964. As a result, at clk2, the first N data lines (0,0), (0,1), (0,2), and (0,3) are input to the third write subarray 1720c via signal lines 1923, 1924, 1925a, and 1927, respectively. For example, at clk2, data (0,2) is input to the redundant input C of the redundant write MUX 1881 in the third write subarray 1720c via signal line 1925a.

[0203] Also at clk2, the second N data lines (1,0), (1,1), (1,2), and (1,3) are output from the N main write MUX 1880s of the first write subarray 1720a via signal lines 1913, 1914, 1916, and 1917, respectively, without data shifting, as shown in the second row of Table 1962. Also at clk2, the third N data lines (2,0), (2,1), (2,2), and (2,3) are input to the main write MUX 1880s of the first write subarray 1720a via I / O signal lines 1903, 1904, 1906, and 1907, respectively, without data shifting, as shown in the third row of Table 1960.

[0204] At clk3, because Group 0's B0_L is also a faulty primary memory, the data (0,0) and (0,1) from the first N data entries are shifted one memory bank to the right by the third write subarray 1720c and output via signal lines 1924 and 1935 respectively, as shown in the first row of Table 1965. For the data (0,3), no input data shift is required. The data (0,3) is output via signal line 1937 by the third write subarray 1720c without data shifting, as shown in the first row of Table 1965. As a result, at clk3, the data (0,0), (0,1), and (0,3) from the first N data entries are output to the three working memory banks in Group 0 via signal lines 1934, 1935, and 1937 respectively. That is, the data (0,0), (0,1), and (0,3) from the first N data entries are stored in the three working memory banks of Group 0, as shown in the last row of Table 1966.

[0205] Also at clk3, the second N data lines (1,0), (1,1), (1,2), and (1,3) are output from the N master write MUX 1880s of the second write subarray 1720a via signal lines 1923, 1924, 1926, and 1927, respectively, without data shifting, as shown in the second row of Table 1964. The redundant write MUX 1881 of the second write subarray 1720b is configured as a holding element to maintain the previous output signal of clk2 and outputs data (0,2) at clk3 via signal line 1925a. Therefore, data (0,2) is still input via signal line 1925a to the redundant input terminal C of the redundant write MUX 1881 of the third write subarray 1720b. That is, at clk3, the data (1,0), (1,1), (0,2), (1,2) and (1,3) are input to the third write subarray 1720b through signal lines 1923, 1924, 1925a, 1926 and 1927 respectively, as shown in the second row of Table 1964.

[0206] Also at clk3, the third N data (2,0), (2,1), (2,2) and (2,3) are output from the N master write MUX 1880s of the first write subarray 1720a via signal lines 1913, 1914, 1916 and 1917 respectively, without data shifting, as shown in the third row of Table 1962.

[0207] At clk4, since B1_L of Group 1 is also a faulty primary memory bank, the data (1,2) can be shifted left by one memory bank by the redundant write MUX 1881 of the third write subarray 1720c and output via signal line 1935, as shown in the second row of Table 1965. For the data (1,0), (1,1), and (1,3), no input data shift may be required. The data (1,0), (1,1), and (1,3) are output by the third write subarray 1720c via signal lines 1933, 1934, and 1937 respectively, without data shifting, as shown in the second row of Table 1965. As a result, at clk4, the second N data lines (1,0), (1,1), (1,2), and (1,3) are output to the four working memory banks in Group 1 via signal lines 1933-1935 and 1937 respectively. In other words, the second N data entries (1,0), (1,1), (1,2), and (1,3) are stored in the four working memory blocks of Group 1, as shown in the second row of Table 1966.

[0208] Also at clk4, the third N data lines (2,0), (2,1), (2,2), and (2,3) are output from the N master write MUX 1880s of the second write subarray 1720a via signal lines 1923, 1924, 1926, and 1927, respectively, without data shifting, as shown in the third row of Table 1964. The redundant write MUX 1881 of the second write subarray 1720b is also configured as a holding element to maintain its previous output signal at clk3 and still outputs data (0,2) via signal line 1925a at clk4. Therefore, data (0,2) is still input to the redundant input C of the redundant write MUX 1881 of the third write subarray 1720b via signal line 1925a. That is, at clk4, the data (2,0), (2,1), (0,2), (2,2) and (2,3) are input to the third write subarray 1720c through signal lines 1923, 1924, 1925a, 1926 and 1927 respectively, as shown in the third row of Table 1964.

[0209] At clk5, the third N data lines (2,0), (2,1), (2,2), and (2,3) are output from the N main write MUX 1880s of the third write subarray 1720c via signal lines 1933, 1934, 1936, and 1937, respectively, without data shifting, as shown in the third row of Table 1965. The redundant write MUX 1881 of the third write subarray 1720c selects data (0,2) from its redundant input C and outputs data (0,2) via signal line 1935, as shown in the third row of Table 1965. As a result, at clk5, the third N data lines and the data (0,2) from the first N data lines are output to the five working memory banks in Group 3 via signal lines 1933-1937, respectively. That is, the third N data lines and the data (0,2) from the first N data lines are stored in the five working memory banks of Group 3, as shown in the first row of Table 1966.

[0210] Figure 20 A schematic diagram of an exemplary storage device 2000 according to some aspects of this disclosure is shown, which implements a faulty primary memory repair scheme in data output using a read MUX array having multiple read subarrays. Figure 20 In some embodiments shown, during data output (e.g., read operations), the page buffer / sensor amplifier 404 and the column decoder / bit line driver 406 (or the page buffer / sensor amplifier portion 1406 and the column decoder / bit line driver portion 1506) may include nine sense amplifiers 802 coupled to eight main memory banks 702 and one redundant memory bank 704, respectively. The memory device 2000 may include any suitable memory device described herein (e.g., Figure 17 The components of the storage device 1700 are similar to those of other components, and similar descriptions will not be repeated here.

[0211] I / O circuitry 407 may include N+1 inputs of N primary memory banks 702 and redundant memory banks 704 in each memory bank group, respectively, via a data bus 1701 and a set of wiring including wires 1702, 1704, 1706, 1708, 1710, 1712, 1714, 1716, and 1718. For example, the corresponding memory banks may be coupled to the inputs of I / O circuitry 407 via corresponding data lines of data bus 1701 and corresponding wires in the wiring group. I / O circuitry 407 may include a read MUX array 807. Under the control of I / O control logic 412, read MUX array 807 may be configured to drive P×N data from P×N working memory banks in P memory banks respectively. In some embodiments, read MUX array 807 may include P read subarrays 2020 applied serially (e.g., a first read subarray, a second read subarray, ..., and a Pth read subarray). Reference is made below. Figure 21A , 21C The exemplary structure of each read subarray 2020 is described in more detail in sections 22A and 22A.

[0212] Figure 21A A schematic diagram of an exemplary storage device 2100 according to some aspects of this disclosure is shown, which implements a faulty primary memory repair scheme in data output using a read MUX array with two read subarrays. Storage device 2100 may include components similar to those of any suitable storage device described herein, and similar descriptions will not be repeated here. In some embodiments, storage device 2100 may include a memory cell array comprising P groups of memory (P=2), such as Group 0 and Group 1. Each group of memory may include N primary memory cells 702 (e.g., N=8) and one redundant memory cell 704 for concurrent data input / output; thus, the two redundant memory cells 704 are included in and shared by the two groups of memory.

[0213] exist Figure 21A In some embodiments shown, the read MUX array 807 of the I / O circuit 407 may include a first read subarray 2020a and a second read output subarray 2020b applied serially. Each read subarray 2020a or 2020b may include N read MUX 2180s (e.g., read MUX 2180a, read MUX 2180b, etc.). Each read MUX 2180 may include a first input terminal A, a second input terminal B, a selection port S, and an output terminal Out.

[0214] In some implementations, each read subarray 2020a or 2020b may have the same characteristics as... Figure 8 The structure is similar to that of the MUX array 807. For example, Figure 8 Two instances of the MUX array 807 can be serially cascaded and modified to form Figure 21A Reading the MUX array 807. Generally speaking, Figure 8 P instances of the read MUX array 807 can be serially cascaded and modified to form a read MUX array with P read subarrays.

[0215] Regarding the first read subarray 2020a, the first input terminal A of each read MUX 2180 in the first read subarray 2020a is coupled to the corresponding main memory 702 via a corresponding signal line (e.g., 2101, 2102, 2103, 2104, 2106, 2107, 2108, or 2109). The output terminal of each read MUX 2180 in the first read subarray 2020a is coupled to the first input terminal A of the corresponding read MUX 2180 in the second read subarray 2020b via a corresponding signal line (e.g., 2111, 2112, 2113, 2114, 2116, 2117, 2118, or 2119).

[0216] Regarding the second read subarray 2020b, the output of each read MUX 2180 in the second read subarray 2020b is coupled to the corresponding I / O data line (e.g., 2121, 2122, 2123, 2124, 2126, 2127, 2128 or 2129) and is configured to output the data of the corresponding bar to the corresponding I / O data line.

[0217] For each read subarray 2020a or 2020b, the selection port S of each read MUX 2180 can be configured to receive a read selection signal indicating the selection of an input (A or B). For example, a positive bias read selection signal for each read MUX 2180, i.e., the read selection signal is enabled, can select the second input B. The second input B of each read MUX 2180 in read subarray 2020a or 2020b is coupled to the first input A of an adjacent read MUX 2180 in the same read subarray, or coupled to the redundant memory bank 704 via a corresponding signal line (e.g., 2105 or 2115). Signal line 2115 is connected to signal line 2105 and coupled to the redundant memory bank 704.

[0218] For example, in each group of memory banks, redundant memory banks 704 can be located among N main memory banks 702, and the N main memory banks 702 can be divided into two groups of main memory banks (e.g., left group main memory banks and right group main memory banks located to the left and right of redundant memory banks 704, respectively). The N read MUX 2180 in each read subarray 2020a or 2020b can be divided into left group read MUX 2180 and right group read MUX 2180, respectively corresponding to the left group main memory bank and the right group main memory bank. In each read subarray 2020a or 2020b, the second input B of the first read MUX (e.g., read MUX 2180b) in the left group of read MUX 2180 is coupled to the redundant memory bank 704 via signal line 2105 or 2115, and the second input B of each remaining read MUX 2180 in the left group of read MUX 2180 is coupled to the first input A of its adjacent read MUX 2180 to its right. Similarly, the second input B of the first read MUX (e.g., read MUX 2180a) in the right group of read MUX 2180 is coupled to the redundant memory bank 704 via signal line 2105 or 2115, and the second input B of each remaining read MUX 2180 in the right group of read MUX 2180 is coupled to the first input A of its adjacent read MUX 2180 to its left.

[0219] Figure 21B This disclosure illustrates some aspects of the present disclosure. Figure 21A This document describes an exemplary faulty primary memory repair scheme for data output implemented in storage device 2100. It assumes that Group 0 and Group 1 together comprise two faulty primary memories. As shown in Table 2156, these two faulty primary memories can be distributed within Group 0 (e.g., B0_L and B0_H in Group 0 are faulty primary memories). This document incorporates references... Figure 20 and 21A describe Figure 21B .

[0220] In some implementations, the working memory logic 906 of the I / O control logic 412 is coupled to register 414 and configured to acquire memory failure information indicating two failed primary memories from Group 0. The working memory logic 906 can determine 2×N working memories from Group 0 and Group 1 that can be used for data input and output. Based on the determined 2×N working memories, read redundancy enable logic 902 can be configured to control I / O circuitry 407 to boot 2×N data entries from each of the 2×N working memories. For example, the read redundancy enable logic 902 is coupled to each read MUX 2180 and configured to provide multiple read selection signals 905 to each read MUX 2180 in each read subarray 2020a or 2020b based on the determined 2×N working memories. For example, the plurality of read selection signals 905 may include red1_en_b0_l_rd, red1_en_b0_h_rd, red1_en_b1_l_rd, red1_en_b1_h_rd, red1_en_b2_l_rd, red1_en_b2_h_rd, red1_en_b3_l_rd, and red1_en_b3_h_rd for the read MUX 2180 in the first read subarray 2020a, and red2_en_b0_l_rd, red2_en_b0_h_rd, red2_en_b1_l_rd, red2_en_b1_h_rd, red2_en_b2_l_rd, red2_en_b2_h_rd, red2_en_b3_l_rd, and red2_en_b3_h_rd for the read MUX 2180 in the second read subarray 2020b.

[0221] Suppose that the 7 data points (0,0), (0,1), (0,2), (0,4), ..., and (0,7) (where N = 8) from the first N data points are stored in the 7 working memory blocks of Group 0, and the second N data points (1,0), (1,1), ..., and (1,7) and the data point (0,3) from the first N data points are stored in the N+1 working memory blocks of Group 1, as shown in Table 2156. Figure 21B The data reading order is from Group 0 to Group 1. Table 2150 shows that at clk0, the seven data points (0,0), (0,1), (0,2), (0,4), ..., (0,7) from the first N data points are read from the seven working memory blocks of Group 0 and loaded onto signal lines 2103-2109, respectively. Table 2150 also shows that at clk1, the second N data points and the data (0,3) from the first N data points are read from the N+1 working memory blocks of Group 1 and loaded onto signal lines 2101-2109, respectively.

[0222] Initially, at clk0, the seven data points (0,0), (0,1), (0,2), (0,4), ..., and (0,7) from the first N data points are input to the read MUX 2180 in the first read subarray 2020a via signal lines 2103-2109, as shown in Table 2150.

[0223] In clk1, because B0_H of Group 0 is the faulty primary memory, the read redundancy enable logic 902 can enable red1_en_b0_l_rd, ..., and red1_en_b1_h_rd, so that each read MUX 2180 in the left group read MUX 2180 of the first read subarray 2020a can input data from its input terminal B while shifting the data left by one memory block. That is, the data (0,0), (0,1), and (0,2) are each shifted left by one memory block and output by signal lines 2112-2114, as shown in Table 2152. For the other data (0,4), (0,5), (0,6), and (0,7), input data shifting may not be required, allowing the read redundancy enable logic 902 to disable red1_en_b2_l_rd, ..., and red1_en_b3_h_rd. This allows each read MUX 2180 in the right-hand group of read MUX 2180 in the first read subarray 2020a to input data from its input terminal A without data shifting. The data (0,4), (0,5), (0,6), and (0,7) are then output via signal lines 2116-2119, as shown in Table 2152.

[0224] Also at clk1, the second N data lines and the data (0,3) from the first N data lines are input to the read MUX 2180 of the first read subarray 2020a via signal lines 2101-2109, as shown in Table 2150. For example, the data (0,3) from the first N data lines is input to the read MUX 2180a and 2180b of the first read subarray 2020a via signal line 2105. Since signal line 2115 is connected to signal line 2105, the data (0,3) is also input to the read MUX 2180a and 2180b of the second read subarray 2020b via signal line 2115. As a result, at clk1, the first N data (0,0), (0,1), (0,2), (0,3), (0,4), (0,5), (0,6), and (0,7) are input to the second read subarray 2020b via signals 2112-2119 respectively.

[0225] At clk2, since Group 0's B0_L is also a faulty primary memory bank, the read redundancy enable logic 902 can enable red1_en_b0_l_rd, ..., and red1_en_b1_h_rd, allowing each read MUX 2180 in the left-hand group read MUX 2180 of the second read subarray 2020b to input data from its input terminal B while shifting the data left by one memory bank. That is, the data (0,0), (0,1), (0,2), and (0,3) are each shifted left by one memory bank and output by I / O data lines 2121-2124, as shown in Table 2154. For other data (0,4), (0,5), (0,6), and (0,7), input data shifting may not be necessary. Then, the data (0,4), (0,5), (0,6), and (0,7) are output from the second read subarray 2020b via signal lines 2126-2129, respectively, without data shifting, as shown in Table 2154. As a result, the first N data lines are successfully output from the read MUX array 807.

[0226] Furthermore, at clk2, the second N data lines are output from the read MUX 2180 of the first subarray 2020a via signal lines 2111-2114 and 2116-2109 respectively, without data shifting, as shown in Table 2152. The second N data lines are input to the read MUX 2180 of the second read subarray 2020a via signal lines 2111-2114 and 2116-2119 respectively.

[0227] At clk3, the second N data lines are output from the read MUX 2180 of the second read subarray 2020b via signal lines 2121-2124 and 2126-2129 respectively, without data shifting, as shown in Table 2154. As a result, the second N data lines are successfully output from the read MUX array 807.

[0228] Figure 21C A schematic diagram of another exemplary storage device 2190 is shown, illustrating a faulty primary memory repair scheme implemented in data output using a read MUX array with two read subarrays, according to some aspects of this disclosure. Storage device 2190 may include any suitable storage device described herein (e.g., Figure 21A The components of the storage device 2100 are similar to those components, and similar descriptions will not be repeated here.

[0229] For example, Figure 21C Each of Group 0 and Group 1 can include N=4 main memory banks 702 and 1 redundant memory bank 704 for concurrent data input / output. The read MUX array 807 of the I / O circuit 407 can include a first read subarray 2020a and a second read subarray 2020b. Each read subarray 2020a or 2020b can include N=4 read MUX 2180.

[0230] exist Figure 21C In each group of memory shown, N primary memory banks 702 may be located to the left of redundant memory bank 704 and may be referred to as left-side primary memory banks. N read MUXs 2180 in each read subarray 2020a or 2020b may be referred to as left-side read MUXs 2180 corresponding to the left-side primary memory banks. In each read subarray 2020a or 2020b, the second input B of the first read MUX (e.g., read MUX 2180b) in the left-side read MUX 2180 is coupled to redundant memory bank 704 via signal line 2105 or 2115. The second input B of each remaining read MUX 2180 in the left-side read MUX 2180 is coupled to the first input A of its adjacent read MUX 2180 to its right.

[0231] In some other embodiments, the N main memory banks 702 may be located to the right of the redundant memory bank 704, and the N main memory banks 702 may be referred to as the right-side group main memory banks. The N read MUXs 2180 in each read subarray 2020a or 2020b may be referred to as the right-side group read MUXs 2180 corresponding to the right-side group main memory banks. In each read subarray 2020a or 2020b, the second input terminal B of the first read MUX (e.g., read MUX 2180a) in the right-side group read MUX 2180 is coupled to the redundant memory bank 704 via signal lines 2105 or 2115. The second input terminal B of each remaining read MUX 2180 in the right-side group read MUX 2180 is coupled to the first input terminal A of its adjacent read MUX 2180 to its left.

[0232] Figure 22A A schematic diagram of an exemplary storage device 2200 according to some aspects of this disclosure is shown, which implements a faulty primary memory repair scheme in data output using a read MUX array having three read subarrays. Storage device 2200 may include components similar to those of any suitable storage device described herein, and similar descriptions will not be repeated here. In some embodiments, storage device 2200 may include a memory cell array comprising P groups of memory (P=3), such as Group 0, Group 1, and Group 2. Each group of memory may include N primary memory cells 702 (e.g., N=4) and one redundant memory cell 704 for concurrent data input / output; thus, the three groups of memory include and share three redundant memory cells 704. The read MUX array 807 of I / O circuitry 407 may include a first read subarray 2020a, a second read subarray 2020b, and a third read subarray 2020c. Each read subarray 2020a, 2020b, or 2020c may include N read MUX 2180s (e.g., N = 4). Each read MUX 2180 may include a first input A, a second input B, a selection port S, and an output port Out.

[0233] Regarding the first read subarray 2020a, the first input terminal A of each read MUX 2180 in the first read subarray 2020a is coupled to the corresponding main memory 702 via a corresponding signal line (e.g., 2203, 2204, 2206, or 2207). The output terminal of each read MUX 2180 in the first read subarray 2020a is coupled to the first input terminal A of the corresponding read MUX 2180 in the second read subarray 2020b via a corresponding signal line (e.g., 2213, 2214, 2216, or 2217). Regarding the second read subarray 2020b, the output terminal of each read MUX 2180 in the second read subarray 2020b is coupled to the first input terminal A of the corresponding read MUX 2180 in the third read subarray 2020c via a corresponding signal line (e.g., 2223, 2224, 2226, or 2227). Regarding the third read subarray 2020c, the output of each read MUX2180 in the third read subarray 2020c is coupled to the corresponding I / O data line (e.g., 2233, 2234, 2236, or 2237) and is configured to output the data of the corresponding strip to the corresponding I / O data line.

[0234] For each read subarray 2020a, 2020b, or 2020c, the selection port S of each read MUX 2180 can be configured to receive a read selection signal indicating the selection of an input (A or B). The input B of each read MUX 2180 in read subarrays 2020a, 2020b, or 2020c is coupled to the first input A of an adjacent read MUX 2180 in the same read subarray, or coupled to redundant memory bank 704 via corresponding signal lines (e.g., 2205, 2215, or 2225). Signal lines 2215 and 2225 are connected to signal line 2205 and coupled to redundant memory bank 704.

[0235] For example, in each read subarray 2020a, 2020b, or 2020c, the second input B of the first read MUX (e.g., read MUX 2180b) in the left group of read MUX 2180 is coupled to the redundant memory bank 704 via signal lines 2205, 2215, or 2225. The second input B of each remaining read MUX 2180 in the left group of read MUX 2180 is coupled to the first input A of its adjacent read MUX 2180 to its right. The second input B of the first read MUX (e.g., read MUX 2180a) in the right group of read MUX 2180 is coupled to the redundant memory bank 704 via signal lines 2205, 2215, or 2225. The second input B of each remaining read MUX 2180 in the right group of read MUX 2180 is coupled to the first input A of its adjacent read MUX 2180 to its left.

[0236] Figure 22B-22C This disclosure illustrates some aspects of the present disclosure. Figure 21A An exemplary main memory failure repair scheme is implemented in the data output of the storage device. (Reference) Figure 22B Assume that Group 0, Group 1, and Group 2 comprise a total of three failed main memory units. As shown in Table 2256, these three failed main memory units can be distributed within Group 0 (for example, B0_L, B0_H, and B1_L in Group 0 are failed main memory units). This document incorporates references... Figure 9 , 20 And 22A to describe Figure 22B .

[0237] In some implementations, the working memory logic 906 of the I / O control logic 412 is coupled to register 414 and configured to acquire memory failure information indicating three failed primary memories from Group 0. The working memory logic 906 can determine 3×N working memories from Group 0, Group 1, and Group 2 that can be used for data input and output. Based on the determined 3×N working memories, read redundancy enable logic 902 can be configured to control I / O circuitry 407 to boot 3×N data entries from each of the 3×N working memories. For example, the read redundancy enable logic 902 is coupled to each read MUX 2180 and configured to provide multiple read selection signals 905 to each read MUX 2180 in each read subarray 2020a, 2020b, or 2020c based on the determined 3×N working memories. For example, the plurality of read selection signals 905 may include red1_en_b0_l_rd, red1_en_b0_h_rd, red1_en_b1_l_rd, and red1_en_b1_h_rd for reading MUX 2180 in the first read subarray 2020a, red2_en_b0_l_rd, red2_en_b0_h_rd, red2_en_b1_l_rd, and red2_en_b1_h_rd for reading MUX 2180 in the second read subarray 2020b, and red3_en_b0_l_rd, red3_en_b0_h_rd, red3_en_b1_l_rd, and red3_en_b1_h_rd for reading MUX 2180 in the third read subarray 2020c.

[0238] Suppose that the data (0,2) and (0,3) from the first N data (where N=4) are stored in the two working memory blocks of Group 0, the second N data including (1,0), (1,1), (1,2), and (1,3) and the data (0,0) from the first N data are stored in the N+1 working memory blocks of Group 1, and the third N data including (2,0), (2,1), (2,2), and (2,3) and the data (0,1) from the first N data are stored in the N+1 working memory blocks of Group 2, as shown in Table 2256. Figure 22B The data is read in the order from Group 0 to Group 1, and then to Group 2.

[0239] Table 2250 shows that at clk0, the data (0,2) and (0,3) from the first N data entries are read from the two working memory banks of Group 0 and loaded into signal lines 2205 and 2207, respectively. Table 2250 also shows that at clk1, the second N data entries and the data (0,0) from the first N data entries are read from the N+1 working memory banks of Group 1 and loaded into signal lines 2203-2107, respectively. Table 2250 further shows that at clk2, the third N data entries and the data (0,1) from the first N data entries are read from the N+1 working memory banks of Group 2 and loaded into signal lines 2203-2107, respectively.

[0240] Initially, at clk0, the data (0,2) and (0,3) from the first N data are input to the first read subarray 2020a to read the MUX 2180 via signal lines 2205 and 2207, as shown in Table 2250.

[0241] At clk1, because Group 0's B1_L is the faulty primary memory, the data (0,2) input to the read MUX 2180a in the first read subarray 2020a can be right-shifted by one memory bank and output by the read MUX 2180a via signal line 2216, as shown in Table 2252. For the data (0,3), no input data shift may be required, allowing the corresponding read MUX 2180 in the right group of read MUX 2180 in the first read subarray 2020a to select the data (0,3) from its input A without data shifting. Then, the data (0,2) and (0,3) are output via signal lines 2216 and 2217, respectively, as shown in Table 2252.

[0242] Also at clk1, the second N data lines and the data (0,0) from the first N data lines are input to the read MUX 2180 of the first read subarray 2020a via signal lines 2203 to 2207, as shown in Table 2250. For example, the data (0,0) from the first N data lines is input to the read MUXs 2180a and 2180b of the first read subarray 2020a via signal line 2205. Since signal line 2215 is connected to signal line 2205, the data (0,0) is also input to the read MUXs 2180a and 2180b of the second read subarray 2020b via signal line 2215. As a result, at clk1, the data (0,0), (0,2), and (0,3) from the first N data lines are input to the second read subarray 2020b via signals 2215-2217, respectively.

[0243] At clk2, because Group 0's B0_H is the faulty primary memory, the data (0,0) can be shifted left by one memory cell and output via signal line 2224 by the read MUX 2180b in the second read subarray 2020b, as shown in Table 2254. For the data (0,2) and (0,3), no input data shift may be required, allowing the corresponding read MUX 2180 in the right-hand group read MUX 2180 of the second read subarray 2020b to select the data (0,2) and (0,3) from input A without data shifting. Then, the data (0,0), (0,2), and (0,3) are output via signal lines 2224, 2226, and 2227, respectively, as shown in Table 2254.

[0244] Also at clk2, the second N data lines are output from the read MUX 2180 of the first read subarray 2202a via signal lines 2213, 2214, 2216, and 2217, respectively, without data shifting, as shown in Table 2252. The second N data lines are input to the read MUX 2180 of the second read subarray 2020b via signal lines 2213, 2214, 2216, and 2217, respectively.

[0245] Also at clk2, the third N data and the data (0,1) from the first N data are input to the read MUX 2180 of the first read subarray 2202a via signal lines 2203-2207, as shown in Table 2250. For example, the data (0,1) from the first N data is input to the read MUXs 2180a and 2180b of the first read subarray 2020a via signal line 2205. Since signal line 2225 is connected to signal line 2205, the data (0,1) is also input to the read MUXs 2180a and 2180b of the third read subarray 2020c via signal line 2225. As a result, at clk2, the data (0,0), (0,1), (0,2), and (0,3) from the first N data are input to the third read subarray 2020c via signal lines 2224-2227, as shown in Table 2254.

[0246] At clk3, since Group 0's B0_L is also a faulty primary memory bank, the data (0,0) and (0,1) can be shifted left by one memory bank and output via I / O data lines 2233 and 2234 by the corresponding read MUX 2180 in the third read subarray 2020c, as shown in Table 2255. For the data (0,2) and (0,3), no input data shift may be required, allowing the corresponding read MUX 2180 in the third read subarray 2020b to output the data (0,2) and (0,3) via I / O data lines 2236 and 2237 respectively without data shifting, as shown in Table 2255. As a result, the first N data entries are successfully output from the read MUX array 807.

[0247] Also at clk3, the second N data lines are output from the read MUX 2180 of the second read subarray 2020b via signal lines 2223, 2224, 2226, and 2227, respectively, without data shifting, as shown in Table 2254. The second N data lines are then input to the read MUX 2180 of the third read subarray 2020c via signal lines 2223, 2224, 2226, and 2227, respectively.

[0248] Also at clk3, the third N data lines are output from the read MUX 2180 of the first read subarray 2020a via signal lines 2213, 2214, 2216, and 2217, respectively, without data shifting, as shown in Table 2252. The third N data lines are input to the read MUX 2180 of the second read subarray 2020b via signal lines 2213, 2214, 2216, and 2217, respectively.

[0249] At clk4, the second N data lines are output from the read MUX 2180 of the third subarray 2020c via data lines 2233, 2234, 2236, and 2237 respectively, without data shifting, as shown in Table 2255. As a result, the second N data lines are successfully output from the read MUX array 807.

[0250] Also at clk4, the third N data lines are output from the read MUX 2180 of the second read subarray 2020b via signal lines 2223, 2224, 2226, and 2227 respectively, without data shifting, as shown in Table 2254. The third N data lines are input to the read MUX 2180 of the third read subarray 2020c via signal lines 2223, 2224, 2226, and 2227 respectively.

[0251] At clk5, the third N data lines are output from the read MUX 2180 of the third read subarray 2020c via data lines 2233, 2234, 2236, and 2237 respectively, without data shifting, as shown in Table 2255. As a result, the third N data lines are successfully output from the read MUX array 807.

[0252] refer to Figure 22C Assume that Group 0, Group 1, and Group 2 comprise a total of three failed primary memory units. As shown in Table 2266, these three failed primary memory units may include B0_L and B1_L of Group 0 and B1_L of Group 1. (Refer to...) Figure 22A To describe Figure 22C Table 2266 shows that the data (0,0), (0,1), and (0,3) from the first N data (where N=4) are stored in the three working memory blocks of Group 0, the second N data including (1,0), (1,1), (1,2), and (1,3) are stored in the N working memory blocks of Group 1, and the third N data including (2,0), (2,1), (2,2), and (2,3) and the data (0,2) from the first N data are stored in the N+1 working memory blocks of Group 2, as shown in Table 2266. Figure 22C The data is read in the following order: from Group 0 to Group 1, and then to Group 2.

[0253] Table 2260 shows that at clk0, the data (0,0), (0,1), and (0,3) from the first N data entries are read from the three working memory banks of Group 0 and loaded onto signal lines 2204, 2205, and 2207, respectively. Table 2260 also shows that at clk1, the second N data entries are read from the N working memory banks of Group 1 and loaded onto signal lines 2203-2105 and 2207, respectively. Table 2260 further shows that at clk2, the third N data entries and the data (0,2) from the first N data entries are read from the N+1 working memory banks of Group 2 and loaded onto signal lines 2203-2107, respectively.

[0254] Initially, at clk0, the data (0,0), (0,1) and (0,3) from the first N data are input to the read MUX 2180 of the first read subarray 2020a via signal lines 2204, 2205 and 2207, as shown in Table 2260.

[0255] At clk1, since Group 0's B0_L is the faulty primary memory, the data (0,0) and (0,1) can be shifted left by one memory cell by the first read subarray 2020a and output via signal lines 2213-2214, as shown in Table 2262. For the data (0,3), no input data shift may be required, allowing the first read subarray 2020a to output the data (0,3) via signal line 2217 without data shifting, as shown in Table 2262. As a result, at clk1, the data (0,0), (0,1), and (0,3) are output via signal lines 2213, 2214, and 2217, respectively, as shown in Table 2262.

[0256] In addition, at clk1, the second N data are input to the read MUX 2180 of the first read subarray 2020a via signal lines 2203-2205 and 2207, as shown in Table 2260.

[0257] At clk2, for the data (0,0), (0,1) and (0,3), it may not be necessary to shift the input data, so that the second read subarray 2020b can output the data (0,0), (0,1) and (0,3) through signal lines 2223, 2224 and 2227 respectively without data shifting, as shown in Table 2264.

[0258] Also at clk2, because B1_L of Group 1 is the faulty primary memory, the data (1,2) of the second N data entries can be shifted one memory cell to the right by the read MUX 2180a in the first read subarray 2202a and output via signal line 2216, as shown in Table 2262. For data (1,0), (1,1), and (1,3), input data shifting may not be necessary, allowing the first read subarray 2020a to output data (1,0), (1,1), and (1,3) via signal lines 2213-2214 and 2227 respectively, without data shifting. As a result, data (1,0), (1,1), (1,2), and (1,3) are output via signal lines 2213-2214 and 2216-227 respectively, as shown in Table 2262.

[0259] Also at clk2, the third N data and the data (0,2) from the first N data are input to the read MUX 2180 of the first read subarray 2020a via signal lines 2203-2207, as shown in Table 2260. For example, the data (0,2) from the first N data is input to the read MUXs 2180a and 2180b of the first read subarray 2020a via signal line 2205. Since signal line 2225 is connected to signal line 2205, the data (0,2) is also input to the read MUXs 2180a and 2180b of the third read subarray 2020c via signal line 2225. As a result, at clk2, the data (0,0), (0,1), (0,2), and (0,3) from the first N data are input to the third read subarray 2020c via signal lines 2224-2225 and 2227, as shown in Table 2264.

[0260] At clk3, since Group 0's B1_L is also a faulty primary memory bank, the data (0,2) from the first N data entries can be right-shifted one memory bank by the read MUX 2180a of the third read subarray 2020c and output via I / O data line 2236, as shown in Table 2265. For data (0,0), (0,1), and (0,3), input data shifting may not be necessary, allowing the third read subarray 2020c to select data (0,0), (0,1), and (0,3) from input A and output them via I / O data lines 2233-2234 and 2237 respectively, without data shifting, as shown in Table 2265. As a result, the first N data entries are successfully output from the read MUX array 807.

[0261] Also at clk3, the second N data lines are output from the read MUX 2180 of the second read subarray 2020b via signal lines 2223, 2224, 2226, and 2227, respectively, without data shifting, as shown in Table 2264. The second N data lines are then input to the read MUX 2180 of the third read subarray 2020c via signal lines 2223, 2224, 2226, and 2227, respectively.

[0262] Also at clk3, the third N data lines are output from the read MUX 2180 of the first read subarray 2020a via signal lines 2213, 2214, 2216, and 2217, respectively, without data shifting, as shown in Table 2262. The third N data lines are input to the read MUX 2180 of the second read subarray 2020b via signal lines 2213, 2214, 2216, and 2217, respectively.

[0263] At clk4, the second N data lines are output from the read MUX 2180 of the third read subarray 2020c via data lines 2233, 2234, 2236, and 2237 respectively, without data shifting, as shown in Table 2265. As a result, the second N data lines are successfully output from the read MUX array 807. Also at clk4, the third N data lines are output from the read MUX 2180 of the second read subarray 2020b via signal lines 2223, 2224, 2226, and 2227 respectively, without data shifting, as shown in Table 2264. The third N data lines are input to the read MUX 2180 of the third read subarray 2020c via signal lines 2223, 2224, 2226, and 2227 respectively.

[0264] At clk5, the third N data lines are output from the read MUX 2180 of the third read subarray 2020c via data lines 2233, 2234, 2236, and 2237 respectively, without data shifting, as shown in Table 2265. As a result, the third N data lines are successfully output from the read MUX array 807.

[0265] Based on the above Figure 17-22C This document discloses an exemplary general structure of I / O circuitry 407 in a storage device. The storage device may include a memory cell array comprising P groups of memory banks. Each group of memory banks may include N main memory banks 702 and redundant memory banks 704 for concurrent data input / output; therefore, the P groups of memory banks include and share P redundant memory banks.

[0266] In some embodiments, the memory cell array includes first - level memory elements, and the first - level memory elements include a plurality of second - level memory elements. One of the second - level memory elements includes P groups of memory banks. The I / O circuit 407 and the I / O control logic 412 are shared by the plurality of second - level memory elements. For example, the first - level memory element is a die including a plurality of faces. The second - level memory cell including P groups of memory banks is a face in the die, and the face includes P×N working memory banks from the P groups of memory banks. The I / O circuit 407 is coupled to the global data bus and is configured to direct P×N data to or from the P×N working memory banks in the face through the global data bus and one or more branch data buses within the face, respectively.

[0267] The I / O circuit 407 may include a write MUX array 707. In some embodiments, the write MUX array 707 may include P write sub - arrays applied serially. For example, the write sub - arrays in the write MUX array 707 may be denoted as the p - th write sub - array, where p is a positive integer and 1≤p≤P. Each write sub - array in the write MUX array 707 may include a redundant write MUX 1881 and N main write MUXes 1880. Each main write MUX 1880 and each redundant write MUX 1881 may respectively include a first input terminal A, a second input terminal B, a selection port S, and an output terminal.

[0268] For 2≤p≤P, the redundant write MUX 1881 in the p - th write sub - array may further include p - 1 redundant input terminals (S). For example, as Figure 19A shown, the redundant write MUX 1881 in the first write sub - array does not include any redundant input terminals, the redundant write MUX 1881 in the second write sub - array may include a first redundant input terminal C, the redundant write MUX 1881 in the third write sub - array may include a first redundant input terminal C and a second redundant input terminal D, and so on.

[0269] For 1≤p<P, the output terminal of each main write MUX 1880 in the p - th write sub - array is coupled to the first input terminal A of the corresponding main write MUX 1880 in the (p + 1) - th write sub - array. Also for 1≤p<P, the output terminal of the redundant write MUX 1881 in the p - th write sub - array is coupled to the q - th redundant input terminal of the corresponding redundant write MUX 1881 in each (p + q) - th write sub - array, where 1≤q≤P - p and q is a positive integer. For p = P, the output terminals of the N main write MUXes 1880 and the redundant write MUXes 1881 in the p - th write sub - array are respectively coupled to the N main memory banks 702 and the redundant memory banks 704 in the corresponding group of memory banks.

[0270] For p = 1, the first input terminal A of each main write MUX 1880 in the p-th write sub-array is coupled to the corresponding I / O data line and is configured to receive data of the corresponding stripe from the corresponding I / O data line. For 1 ≤ p ≤ P, the second input terminal B of each main write MUX 1880 in the p-th write sub-array is coupled to the signal line of Vdd or the first input terminal A of the corresponding adjacent main write MUX 1880 in the p-th write sub-array.

[0271] In some embodiments, the redundant write MUX 1881 in the p-th write sub-array 1720 is located between the N main write MUXes 1880 in the p-th write sub-array, as Figure 18A and 19A shown. For 1 ≤ p ≤ P, the first input terminal A and the second input terminal B of the redundant write MUX 1881 in the p-th write sub-array are respectively coupled to the first input terminals of two adjacent main write MUXes 1880 in the p-th write sub-array.

[0272] In some other embodiments, the redundant write MUX 1881 in the p-th write sub-array is located on one side of the N main write MUXes 1880 in the p-th write sub-array, as Figure 18D shown. For 1 ≤ p ≤ P, one of the first input terminal A and the second input terminal B of the redundant write MUX 1881 in the p-th write sub-array is coupled to the first input terminal A of the adjacent main write MUX 1880 in the p-th write sub-array. The other of the first input terminal A and the second input terminal B of the redundant write MUX 1881 in the p-th write sub-array is coupled to the Vdd signal line.

[0273] In addition, the I / O circuit 407 may include a read MUX array 807. The read MUX array 807 is coupled to each set of memory banks and is configured to respectively direct P×N data from P×N working memory banks. The read MUX array 807 may include P read sub-arrays applied serially, and each read sub-array may include N read MUXes 2180. Each read MUX 2180 respectively includes a first input terminal A, a second input terminal B, a selection port S, and an output terminal Out. For example, the read sub-array in the read MUX array 807 may be represented as the p-th read sub-array, where 1 ≤ p ≤ P.

[0274] For 1 ≤ p < P, the output terminal of each read MUX 2180 in the p-th read sub-array is coupled to the first input terminal A of the corresponding read MUX 2180 in the (p + 1)-th read sub-array. For p = P, the output terminal of each read MUX 2180 in the p-th read sub-array is coupled to the corresponding I / O data line and is configured to output data of the corresponding stripe to the corresponding I / O data line.

[0275] For p=1, the first input terminal A of each read MUX 2180 in the p-th read subarray is coupled to the corresponding main memory in the N main memory. For 1≤p≤P, the second input terminal B of each read MUX 2180 in the p-th read subarray is coupled to the first input terminal A of the corresponding adjacent read MUX 2180 in the p-th read subarray or a redundant memory.

[0276] In some implementations, it is assumed that the P groups of memory comprise K faulty primary memory, where K is a positive integer not greater than P (1 ≤ K ≤ P). The K faulty primary memory may be distributed across a single group of memory (or two or more groups of memory) from the P groups of memory. I / O control logic 412 may be configured to determine P×N working memory from the P groups of memory based on memory failure information indicating the K faulty primary memory from the P groups of memory. The P×N working memory may include K redundant memory from the P redundant memory. I / O control logic 412 may also be configured to control I / O circuitry 407 to direct P×N data to or from the P×N working memory respectively.

[0277] For example, suppose the first set of memory includes K faulty primary memory, while the other sets of memory do not include any faulty primary memory. I / O control logic 412 can be configured to: (1) direct K data from the first N data to or from the K redundant memory; (2) direct the remaining NK data from the first N data to or from the NK working primary memory in the first set of memory; and (3) direct other data intended to be stored in the other set of memory to or from the corresponding working primary memory in the other set of memory.

[0278] Figure 23 A flowchart is shown of an exemplary method 2300 for operating a storage device according to some aspects of this disclosure, which implements a failed main memory repair scheme during data input / output. The storage device can be any suitable storage device disclosed herein. Method 2300 may be implemented by I / O control logic 412. It should be understood that the operations shown in method 2300 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 23 The different execution sequences are shown.

[0279] refer to Figure 23 Method 2300 begins with operation 2302, in which memory bank fault information indicating K faulty primary memory banks from group P memory banks is obtained. These K faulty primary memory banks can be identified through post-manufacturing testing of the memory device. For example, working memory bank logic 906 can obtain the memory bank fault information from register 414 before operating the memory device.

[0280] Method 2300 continues to operation 2304, such as... Figure 23 As shown, the P×N working memory banks are determined from the P groups of memory banks based on memory bank failure information. For example, the working memory bank logic 906 can determine P×N working memory banks from the P groups of memory banks, including K redundant memory banks and the remaining main memory banks.

[0281] Method 2300 continues to operation 2306, such as... Figure 23 As shown, P×N data are directed to or from P×N working memory units respectively.

[0282] According to one aspect of this disclosure, a storage device includes: a memory cell array, I / O circuitry, and I / O control logic coupled to the I / O circuitry. The memory cell array includes P groups of memory. Each group of memory includes redundant memory and N primary memory, such that the P redundant memory are included in and shared by the P groups of memory. Each of P and N is a positive integer. The I / O circuitry is coupled to the P groups of memory and configured to direct P×N data to or from the P×N working memory. The I / O control logic is configured to determine the P×N working memory from the P groups of memory based on memory failure information indicating K failed primary memory from the P groups of memory. The P×N working memory includes K redundant memory from the P redundant memory. K is a positive integer not greater than P. The I / O control logic is configured to control the I / O circuit to direct P×N data to or from the P×N working memory blocks respectively.

[0283] In some implementations, the I / O circuitry includes a write MUX array coupled to each memory bank and configured to route the P×N data entries to the P×N working memory banks respectively.

[0284] In some implementations, the write MUX array comprises P write subarrays applied serially. Each write subarray includes a redundant write MUX and N primary write MUXs.

[0285] In some embodiments, each main write MUX and each redundant write MUX respectively include a first input terminal, a second input terminal, and an output terminal. For 2 ≤ p ≤ P, the redundant write MUX in the p-th write sub-array of the write MUX array further includes p - 1 redundant input terminals, where p is a positive integer.

[0286] In some embodiments, for 1 ≤ p < P, the output terminal of each main write MUX in the p-th write sub-array is coupled to the first input terminal of the corresponding main write MUX in the (p + 1)-th write sub-array. The output terminal of the redundant write MUX in the p-th write sub-array is coupled to the q-th redundant input terminal of the corresponding redundant write MUX in each (p + q)-th write sub-array, where 1 ≤ q ≤ P - p, and q is a positive integer. For p = P, the output terminals of the N main write MUXes and the redundant write MUX in the p-th write sub-array are respectively coupled to the N main memory banks and the redundant memory bank.

[0287] In some embodiments, for p = 1, the first input terminal of each main write MUX in the p-th write sub-array is coupled to the corresponding I / O data line and is configured to receive data of the corresponding stripe from the corresponding I / O data line. For 1 ≤ p ≤ P, the second input terminal of each main write MUX in the p-th write sub-array is coupled to the Vdd signal line or the first input terminal of the corresponding adjacent main write MUX in the p-th write sub-array.

[0288] In some embodiments, for 1 ≤ p ≤ P, the redundant write MUX in the p-th write sub-array is located between the N main write MUXes in the p-th write sub-array. The first input terminal and the second input terminal of the redundant write MUX in the p-th write sub-array are respectively coupled to the first input terminals of two adjacent main write MUXes in the p-th write sub-array.

[0289] In some embodiments, for 1 ≤ p ≤ P, the redundant write MUX in the p-th write sub-array is located on one side of the N main write MUXes in the p-th write sub-array. One of the first input terminal and the second input terminal of the redundant write MUX in the p-th write sub-array is coupled to the first input terminal of the adjacent main write MUX in the p-th write sub-array. The other of the first input terminal and the second input terminal of the redundant write MUX in the p-th write sub-array is coupled to the Vdd signal line.

[0290] In some embodiments, the I / O circuit includes a read MUX array, and the MUX array is coupled to each group of memory banks and is configured to respectively guide the P × N data from the P × N working memory banks.

[0291] In some embodiments, the read MUX array includes P read sub-arrays applied serially. Each read sub-array includes N read MUXs. Each read MUX includes a first input terminal, a second input terminal, and an output terminal, respectively.

[0292] In some embodiments, for 1 ≤ p < P, the output terminal of each read MUX in the p-th read sub-array is coupled to the first input terminal of the corresponding read MUX in the (p + 1)-th read sub-array, where p is a positive integer. For p = P, the output terminal of each read MUX in the p-th read sub-array is coupled to the corresponding I / O data line and is configured to output the data of the corresponding stripe to the corresponding I / O data line.

[0293] In some embodiments, for p = 1, the first input terminal of each read MUX in the p-th read sub-array is coupled to the corresponding main memory bank among the N main memory banks. For 1 ≤ p ≤ P, the second input terminal of each read MUX in the p-th read sub-array is coupled to the redundant memory bank or the first input terminal of the corresponding adjacent read MUX in the p-th read sub-array.

[0294] In some embodiments, the K failed main memory banks are distributed in one or more groups of memory banks from the P groups of memory banks.

[0295] In some embodiments, the memory cell array includes first-level memory elements. The first-level memory elements include a plurality of second-level memory elements, and one of the plurality of second-level memory elements includes the P groups of memory banks. The I / O circuit and the I / O control logic are shared by the plurality of second-level memory elements.

[0296] In some embodiments, the first-level memory element is a die including a plurality of faces. The second-level memory element including the P groups of memory banks is a face in the die, and the face includes the P × N working memory banks from the P groups of memory banks. The I / O circuit is coupled to a global data bus and is configured to direct the P × N data to or from the P × N working memory banks in the face through the global data bus and one or more branch data buses in the face.

[0297] In some embodiments, N = 4 or ⑧. The memory device includes a 3D NAND flash memory device.

[0298] According to another aspect of this disclosure, a system includes: a storage device configured to store data; and a storage controller coupled to the storage device and configured to control the storage device. The storage device includes: a memory cell array, I / O circuitry, and I / O control logic coupled to the I / O circuitry. The memory cell array includes P groups of memory. Each group of memory includes redundant memory and N primary memory, such that P redundant memory are included in and shared by the P groups of memory. Each of P and N is a positive integer. The I / O circuitry is coupled to the P groups of memory and configured to direct P×N data to or from the P×N working memory. The I / O control logic is configured to determine the P×N working memory from the P groups of memory based on memory failure information indicating K failed primary memory from the P groups of memory. The P×N working memory includes K redundant memory from the P redundant memory. K is a positive integer not greater than P. The I / O control logic is also configured to control the I / O circuit to direct P×N data to or from the P×N working memory blocks respectively.

[0299] In some implementations, the system further includes a host coupled to the storage controller and configured to send or receive the data.

[0300] In some implementations, the I / O circuitry includes a write MUX array coupled to each memory bank and configured to route the P×N data entries to the P×N working memory banks respectively.

[0301] In some implementations, the write MUX array comprises P write subarrays applied serially. Each write subarray includes a redundant write MUX and N primary write MUXs.

[0302] In some implementations, each primary write MUX and each redundant write MUX includes a first input terminal, a second input terminal, and an output terminal, respectively. For 2≤p≤P, the redundant write MUX in the p-th write subarray of the write MUX array further includes p-1 redundant input terminals, where p is a positive integer.

[0303] In some embodiments, for 1 ≤ p < P, the output terminal of each main write MUX in the p-th write sub-array is coupled to the first input terminal of the corresponding main write MUX in the (p + 1)-th write sub-array. The output terminal of the redundant write MUX in the p-th write sub-array is coupled to the q-th redundant input terminal of the corresponding redundant write MUX in each (p + q)-th write sub-array, where 1 ≤ q ≤ P - p and q is a positive integer. For p = P, the output terminals of the N main write MUXes and the redundant write MUX in the p-th write sub-array are respectively coupled to the N main memory banks and the redundant memory bank.

[0304] In some embodiments, for p = 1, the first input terminal of each main write MUX in the p-th write sub-array is coupled to the corresponding I / O data line and is configured to receive data of the corresponding strip from the corresponding I / O data line. For 1 ≤ p ≤ P, the second input terminal of each main write MUX in the p-th write sub-array is coupled to the Vdd signal line or the first input terminal of the corresponding adjacent main write MUX in the p-th write sub-array.

[0305] In some embodiments, for 1 ≤ p ≤ P, the redundant write MUX in the p-th write sub-array is located between the N main write MUXes in the p-th write sub-array. The first input terminal and the second input terminal of the redundant write MUX in the p-th write sub-array are respectively coupled to the first input terminals of two adjacent main write MUXes in the p-th write sub-array.

[0306] In some embodiments, for 1 ≤ p ≤ P, the redundant write MUX in the p-th write sub-array is located on one side of the N main write MUXes in the p-th write sub-array. One of the first input terminal and the second input terminal of the redundant write MUX in the p-th write sub-array is coupled to the first input terminal of the adjacent main write MUX in the p-th write sub-array. The other of the first input terminal and the second input terminal of the redundant write MUX in the p-th write sub-array is coupled to the Vdd signal line.

[0307] In some embodiments, the I / O circuit includes a read MUX array, the MUX array is coupled to each group of memory banks and is configured to respectively guide the P × N data from the P × N working memory banks.

[0308] [[ID=IS]]In some embodiments, the read MUX array includes P read sub-arrays applied serially. Each read sub-array includes N read MUXes. Each read MUX respectively includes a first input terminal, a second input terminal, and an output terminal.

[0309] In some embodiments, for 1 ≤ p < P, the output terminal of each read MUX in the p-th read sub-array is coupled to the first input terminal of the corresponding read MUX in the (p + 1)-th read sub-array, where p is a positive integer. For p = P, the output terminal of each read MUX in the p-th read sub-array is coupled to the corresponding I / O data line and is configured to output the data of the corresponding strip to the corresponding I / O data line.

[0310] In some embodiments, for p = 1, the first input terminal of each read MUX in the p-th read sub-array is coupled to the corresponding main memory bank among the N main memory banks. For 1 ≤ p ≤ P, the second input terminal of each read MUX in the p-th read sub-array is coupled to the redundant memory bank or the first input terminal of the corresponding adjacent read MUX in the p-th read sub-array.

[0311] In some embodiments, the K failed main memory banks are distributed in one or more groups of memory banks from the P groups of memory banks.

[0312] In some embodiments, the memory cell array includes first-level storage elements. The first-level storage elements include a plurality of second-level storage elements, and one of the plurality of second-level storage elements includes the P groups of memory banks. The I / O circuit and the I / O control logic are shared by the plurality of second-level storage elements.

[0313] In some embodiments, the first-level storage element is a die including a plurality of planes. The second-level storage element including the P groups of memory banks is a plane in the die, and the plane includes the P×N working memory banks from the P groups of memory banks. The I / O circuit is coupled to a global data bus and is configured to direct the P×N data lines to or from the P×N working memory banks in the plane through the global data bus and one or more branch data buses in the plane.

[0314] In some embodiments, N = 4 or 8. The memory device includes a 3D NAND flash memory device.

[0315] According to another aspect of this disclosure, a method for operating a storage device is provided. The storage device includes a memory cell array. The memory cell array includes P groups of memory. Each group of memory includes redundant memory and N main memory, such that P redundant memory are included in the P groups of memory. Each of P and N is a positive integer. Based on memory failure information indicating K faulty main memory from the P groups of memory, P×N working memory are determined from the P groups of memory. The P×N working memory includes K redundant memory from the P redundant memory. K is a positive integer not greater than P. P×N data entries are directed to or from the P×N working memory.

[0316] In some implementations, memory failure information indicating the K faulty primary memory units is obtained.

[0317] In some implementations, P is not less than 2.

[0318] In some implementations, the K faulty primary memory banks are distributed across one or more memory banks from the P memory banks.

[0319] In some implementations, each of the P redundant memory banks is shared by the P groups of memory banks.

[0320] In some embodiments, the storage device further includes I / O circuitry. The I / O circuitry includes a write MUX array and a read MUX array, each coupled to each set of memory banks. The write MUX array includes P serially applied write subarrays. The read MUX array includes P serially applied read subarrays. Guiding the P×N data entries includes: guiding the P×N data entries to the P×N working memory banks via the P write subarrays; and guiding the P×N data entries from the P×N working memory banks via the P read subarrays.

[0321] In some implementations, N = 4 or 8. The storage device includes a three-dimensional (3D) NAND flash memory device.

[0322] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, it is intended that such adaptations and modifications be within the meaning and scope of equivalents of the disclosed embodiments.

[0323] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.< / j>

Claims

1. A storage device, comprising: The array of storage cells includes P groups of storage cells, each group of storage cells including redundant storage cells and N main storage cells, where each of P and N is a positive integer; Input / output (I / O) circuitry, coupled to the P groups of memory and configured to respectively input to P... × N working memory units or from the P × N working memory units boot P × N data entries; wherein the redundant memory bank is coupled to at least two of the main memory banks via the I / O circuit; and I / O control logic, coupled to the I / O circuit and configured as follows: For each of the P groups of memory where K main memory cells fail, P × N working memory cells are determined from the P groups of memory cells. These P × N working memory cells include K redundant memory cells from the P redundant memory cells, where K is a positive integer not greater than P; and Control the I / O circuit to send to the P respectively × N working memory units or from the P × N working memory units boot P × N data entries, The I / O circuitry includes a write multiplexer (MUX) array, which is coupled to each memory bank and configured to transmit the P... × N data entries are respectively directed to P. × N working memory units, and The write MUX array comprises P serially applied write subarrays, each of which includes a redundant write MUX and N main write MUXs.

2. The storage device as claimed in claim 1, wherein, Each primary write MUX and each redundant write MUX includes a first input terminal, a second input terminal, and an output terminal, respectively; and For 2≤ p ≤P, the first one written to the MUX array p Redundant write MUX in write subarray also includes p -1 redundant input terminal, where, p is a positive integer.

3. The storage device as claimed in claim 2, wherein, For 1≤ p <P, The first p The output of each master write MUX in the write subarray is coupled to the ( p +1) Write to the first input of the corresponding master write MUX in the subarray; and The first p The output of the redundant write MUX in the write subarray is coupled to each ( ) p + q The corresponding redundant write MUX in the subarray is written to. q Redundant input terminals, where 1 ≤ q ≤P- p ,in, q It is a positive integer; and for p =P, The first p The outputs of the N main write MUXs and the redundant write MUXs in the write subarray are coupled to the N main memory banks and the redundant memory banks, respectively.

4. The storage device as claimed in claim 2 or 3, wherein, for p =1, The first p The first input terminal of each master write MUX in the write subarray is coupled to the corresponding I / O data line and is configured to receive data from the corresponding I / O data line. and For 1≤ p ≤P, The first p The second input of each master write MUX in the write subarray is coupled to the Vdd signal line or the second input of the master write MUX. p Write to the first input of the corresponding adjacent master write MUX in the subarray.

5. The storage device according to any one of claims 2-4, wherein, For 1≤ p ≤P, The first p The redundant write MUX in the write subarray is located in the first p Write between the N main write MUXs in the subarray; and The first p The first and second inputs of the redundant write MUX in the write subarray are respectively coupled to the first... p Write to the first input of two adjacent master writes in the subarray.

6. The storage device according to any one of claims 2-4, wherein, For 1≤ p ≤P, The first p The redundant write MUX in the write subarray is located in the first p Write to one side of the N main write MUXs in the subarray; The first p One of the first and second inputs of the redundant write MUX in the write subarray is coupled to the first... p Write to the first input of the adjacent master write MUX in the subarray; and The first p The other of the first and second inputs of the redundant write MUX in the subarray is coupled to the Vdd signal line.

7. The storage device according to any one of claims 1-6, wherein, The I / O circuitry includes a read multiplexer (MUX) array coupled to each memory bank and configured to read from the P memory bank respectively. × N working memory blocks guide the P × N data entries.

8. The storage device as claimed in claim 7, wherein, The read MUX array includes P read subarrays applied serially, each read subarray includes N read MUXs, and each read MUX includes a first input terminal, a second input terminal, and an output terminal.

9. The storage device of claim 8, wherein, For 1≤ p <P, No. p The output of each read MUX in the read subarray is coupled to the ( p +1) Read the first input terminal of the corresponding read MUX in the subarray, where, p It is a positive integer; and for p =P, The first p The output of each read MUX in the read subarray is coupled to the corresponding I / O data line and configured to output the data of the corresponding line to the corresponding I / O data line.

10. The storage device of claim 9, wherein, for p =1, The first p The first input terminal of each read MUX in the read subarray is coupled to the corresponding main memory in the N main memory banks; and For 1≤ p ≤P, The first p The second input of each read MUX in the read subarray is coupled to the redundant memory or the first p Read the first input terminal of the corresponding adjacent read MUX in the subarray.

11. The storage device according to any one of claims 1-10, wherein, The K faulty primary memory cells are distributed across one or more memory cells from the P memory cells.

12. The storage device according to any one of claims 1-11, wherein, The storage cell array includes a first-level storage element, and the first-level storage element includes a plurality of second-level storage elements, one of which includes the P-group storage; and The I / O circuitry and the I / O control logic are shared by the plurality of secondary storage elements.

13. The storage device of claim 12, wherein, The first-level storage element is a die comprising multiple surfaces; The second-level storage element, including the P-group of memory, is a surface in the die, and the surface includes the P-group of memory. × N working memory units; and The I / O circuitry is coupled to a global data bus and configured to transmit data to the P in the plane via the global data bus and one or more branch data buses in the plane. × N working memory units or from the P in the face. × N working memory blocks guide the P × N data entries.

14. The storage device according to any one of claims 1-13, wherein, The storage device includes a three-dimensional (3D) NAND flash memory device.

15. A storage device comprising: A storage cell array comprising P groups of storage cells, each group consisting of redundant storage cells and N main storage cells, where each of P and N is a positive integer; and Input / output (I / O) circuitry coupled to the P groups of memory; wherein the redundant memory is coupled to at least two of the main memory via the I / O circuitry; the I / O circuitry includes a write multiplexer (MUX) array coupled to each group of memory and configured to output P... × N data points are directed to P. × N working memory modules, The write MUX array comprises P serially applied write subarrays, each of which includes a redundant write MUX and N main write MUXs.

16. The storage device of claim 15, wherein, Each primary write MUX and each redundant write MUX includes a first input terminal, a second input terminal, and an output terminal, respectively; and For 2≤ p ≤P, the first one written to the MUX array p Redundant write MUX in write subarray also includes p -1 redundant input terminal, where, p is a positive integer.

17. The storage device of claim 16, wherein, For 1≤ p <P, The first p The output of each master write MUX in the write subarray is coupled to the ( p +1) Write to the first input of the corresponding master write MUX in the subarray; and The first p The output of the redundant write MUX in the write subarray is coupled to each ( ) p + q The corresponding redundant write MUX in the subarray is written to. q Redundant input terminals, where 1 ≤ q ≤P- p ,in, q It is a positive integer; and for p =P, The first p The outputs of the N main write MUXs and the redundant write MUXs in the write subarray are coupled to the N main memory banks and the redundant memory banks, respectively.

18. The storage device as claimed in claim 16 or 17, wherein, for p =1, The first p The first input terminal of each master write MUX in the write subarray is coupled to the corresponding I / O data line and is configured to receive data from the corresponding I / O data line. and For 1≤ p ≤P, The first p The second input of each master write MUX in the write subarray is coupled to the Vdd signal line or the second input of the master write MUX. p Write to the first input of the corresponding adjacent master write MUX in the subarray.

19. The storage device according to any one of claims 15-17, wherein, The storage device further includes: I / O control logic, coupled to the I / O circuit and configured to control the I / O circuit to send data to the P... × N working memory units or from the P × N working memory units boot P × N data entries.

20. A storage device comprising: A storage cell array comprising P groups of storage cells, each group consisting of redundant storage cells and N main storage cells, where each of P and N is a positive integer; and Input / output (I / O) circuitry is coupled to the P groups of memory; wherein the redundant memory is coupled to at least two of the main memory via the I / O circuitry; the I / O circuitry includes a read multiplexer (MUX) array, which is coupled to each group of memory and configured to read from P... × N working memory units boot P × N data entries, The read MUX array includes P read subarrays applied serially, each read subarray includes N read MUXs, and each read MUX includes a first input terminal, a second input terminal, and an output terminal.

21. The storage device of claim 20, wherein, For 1≤ p <P, No. p The output of each read MUX in the read subarray is coupled to the ( p +1) Read the first input terminal of the corresponding read MUX in the subarray, where, p It is a positive integer; and for p =P, The first p The output of each read MUX in the read subarray is coupled to the corresponding I / O data line and configured to output the data of the corresponding line to the corresponding I / O data line.

22. The storage device of claim 21, wherein, for p =1, The first p The first input terminal of each read MUX in the read subarray is coupled to the corresponding main memory in the N main memory banks; and For 1≤ p ≤P, The first p The second input of each read MUX in the read subarray is coupled to the redundant memory or the first p Read the first input terminal of the corresponding adjacent read MUX in the subarray.

23. The storage device according to any one of claims 20-22, wherein, The storage device further includes: I / O control logic, coupled to the I / O circuit and configured to control the I / O circuit to send data to the P... × N working memory units or from the P × N working memory units boot P × N data entries.

24. A storage system, comprising: One or more storage devices as described in any one of claims 1 to 23 and a memory controller coupled to and controlling the storage device.

25. A method for operating a storage device comprising an array of memory cells, the array of memory cells comprising P groups of memory cells, each group of memory cells comprising redundant memory cells and N main memory cells, wherein, Each of P and N is a positive integer, the redundant memory is coupled to at least two of the main memory, and the method includes: For each of the K primary memory banks in a set of P memory banks that fails, P×N working memory banks are determined from the P memory banks, wherein the P×N working memory banks include K redundant memory banks from the P redundant memory banks; and To the P respectively × N working memory units or from the P × N working memory units boot P × N data entries, in, The storage device also includes input / output I / O circuitry; The I / O circuitry includes a write multiplexer (MUX) array and a read MUX array, each coupled to a memory bank. The write MUX array comprises P write subarrays applied serially; The read MUX array comprises P read subarrays applied serially; and Guide the P × The N data entries include: Through the P write subarrays, respectively to the P × N working memory blocks guide the P × N data entries; and Through the P read subarrays, respectively from the P × N working memory blocks guide the P × N data entries.

26. The method of claim 25, further comprising obtaining memory failure information indicating the K faulty primary memory units.

27. The method of claim 25 or 26, wherein, P is not less than 2.

28. The method of claim 25, wherein, The K faulty primary memory cells are distributed across one or more memory cells from the P memory cells.

29. The method of claim 25, wherein, Each of the P redundant storage units is shared by the P groups of storage units.

30. The method of claim 25, wherein, N = 4 or 8, and the storage device includes a three-dimensional (3D) NAND flash memory device.

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