A method for manufacturing a fast recovery diode and a fast recovery diode

Abstract

The application provides a preparation method of a fast recovery diode and the fast recovery diode. The polycrystalline silicon structure is used in the active region, the concentration of the P type in the local region is reduced to reduce the emission efficiency, the minority carrier lifetime is controlled, the area of the PN junction is increased, the fast recovery capability of the fast recovery diode is improved, and a lower forward voltage drop is obtained.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to a method for preparing a fast recovery diode and the fast recovery diode itself. Background Technology

[0002] The main performance parameter of fast recovery diodes is reverse recovery time. Currently, the mainstream approach is to reduce minority carrier lifetime by controlling minority carrier lifetime and forming recombination centers in the drift region of the device through platinum diffusion, electron irradiation, or hydrogen (helium) injection. At present, not only is a short reverse recovery time required, but also a fast recovery characteristic.

[0003] Existing fast recovery diode fabrication methods produce fast recovery diodes with high emission efficiency but low fast recovery capability and high forward voltage drop. Summary of the Invention

[0004] The purpose of this application is to solve or alleviate the technical problems existing in the prior art. The present invention provides a method for preparing a fast recovery diode and a fast recovery diode to solve the technical problems of high emission efficiency, low fast recovery capability and high forward voltage drop of fast recovery diodes prepared in the prior art.

[0005] This application provides a method for fabricating a fast recovery diode, the method comprising:

[0006] A thick oxide layer is formed at intervals in the protective ring region on the front side of the substrate, wherein the substrate is of a first conductivity type;

[0007] A gate oxide layer and polysilicon are sequentially grown on the front side of the substrate, and polysilicon is formed at intervals on the upper surface of the gate oxide layer.

[0008] A well region with a second doping type is formed in the guard ring region and the active region of the substrate;

[0009] A first implantation region having a first doping type is formed in the protection ring region of the substrate;

[0010] A second implantation region having a second doping type is formed in the well region;

[0011] A dielectric layer spaced apart is formed on the front side of the substrate;

[0012] A third implantation region having a second doping type is formed in the second implantation region, wherein the junction depth of the third implantation region is greater than the junction depth of the second implantation region, and the implantation concentration of the third implantation region is less than the implantation concentration of the second implantation region;

[0013] A first metal layer is deposited between and above the dielectric layers, and the first metal layer in the protection ring region is photolithographically and etched to form a spaced first metal layer in the protection ring region;

[0014] A passivation layer is formed between and above the first metal layer in the protective ring region;

[0015] A second metal layer is deposited on the back side of the substrate.

[0016] In a preferred embodiment of this application, after forming a third injection region having a second conductivity type in the second injection region, the method includes:

[0017] Metal sputtering and diffusion are performed on the substrate.

[0018] In a preferred embodiment of this application, the thickness of the thick oxide layer is 10000 Å to 20000 Å.

[0019] In a preferred embodiment of this application, before sequentially growing a gate oxide layer and depositing polysilicon on the upper surface of the substrate, the method further includes,

[0020] A sacrificial oxide layer is grown on the surface of the substrate, and then the sacrificial oxide layer is removed.

[0021] In a preferred embodiment of this application, the thickness of the gate oxide layer is 500 Å to 2000 Å, and the thickness of the polysilicon is 2000 Å to 9000 Å.

[0022] In a preferred embodiment of this application, the element injected into the well region is boron, and the boron injection energy is 30 keV to 120 keV, the injection dose is 1E13 to 1E14, the propulsion time is 30 min to 180 min, the propulsion temperature is 1000℃ to 1200℃, and the junction depth of the well region is approximately 4 to 10 μm.

[0023] In a preferred embodiment of this application, the element injected into the second injection region is boron, the injection energy is 30 keV to 120 keV, and the injection dose is 1E15 to 1E16.

[0024] In a preferred embodiment of this application, the element injected into the third injection region is boron, the energy of the injected boron is 120 keV to 1 MeV, and the injection dose is 1E11 to 1E12.

[0025] In a preferred embodiment of this application, the first doping type is N-type and the second doping type is P-type.

[0026] Compared with the prior art, the present application provides a method for fabricating a fast recovery diode. The active region of the present invention adopts a polycrystalline silicon structure, which can reduce the concentration of P-type in the local area to reduce the emission efficiency and thus control the minority carrier lifetime, and can also increase the area of ​​the PN junction. This improves the fast recovery capability of the fast recovery diode while also achieving a lower forward voltage drop.

[0027] Secondly, embodiments of this application also provide a fast recovery diode, which is prepared by any of the preparation methods described in the first aspect.

[0028] Compared with the prior art, the embodiments of this application also provide a fast recovery diode with the same beneficial effects as the fast recovery diode preparation method described in the first aspect, which will not be repeated here. Attached Figure Description

[0029] Figure 1 A schematic flowchart illustrating a fast recovery diode fabrication method provided in this application embodiment;

[0030] Figures 2-12 The diagram shows the structural results obtained from each step of a fast recovery diode fabrication method provided in this application embodiment. Detailed Implementation

[0031] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0032] like Figure 1 and Figure 2 As shown in the figure, this application provides a method for fabricating a fast recovery diode, the method comprising:

[0033] Step S01: A thick oxide layer 102 is formed at intervals in the protective ring region on the front side of the substrate 101, wherein the substrate 101 is of the first doping type;

[0034] It should be noted that a thick oxide layer 102 of 10000Å to 20000Å is grown on the substrate 101 by a thermal oxidation process. The thick oxide layer 102 is subjected to photolithography and etching in sequence, and then the photoresist is removed. The substrate 101 is N-type doped. The thick oxide layer 102 is only disposed in the guard ring region, and the thick oxide layer 102 is disposed at intervals in the guard ring region. No thick oxide layer 102 is grown in the active region.

[0035] refer to Figure 1 and Figure 3 As shown, in step S02, a gate oxide layer 103 and a polysilicon 104 are sequentially grown on the front side of the substrate 101, and polysilicon 104 is deposited at intervals on the upper surface of the gate oxide layer 103.

[0036] Before step S02, the method further includes,

[0037] A sacrificial oxide layer is grown on the front side of the substrate 101, and then the sacrificial oxide layer is removed.

[0038] It should be noted that, in this embodiment, a gate oxide layer 103 is grown on the upper surface of the active region of the substrate 101, and a gate oxide layer 103 is also grown in the guard ring region of the substrate 101. The area in the guard ring region where the gate oxide layer 103 is grown is different from the area in the guard ring region where the thick oxide layer 102 is grown. The thickness of the gate oxide layer is 500 Å to 2000 Å, and the thickness of the polysilicon 104 is 2000 Å to 9000 Å. Subsequently, polysilicon 104 is deposited on the front side of the gate oxide layer 103. Finally, the polysilicon 104 is photolithographically etched and etched to form spaced polysilicon 104.

[0039] The depth of the well region 105 in different regions of the substrate 101 can be adjusted by the spacing of the polysilicon 104 in subsequent processes. In this embodiment, the concentration of the active region well region 105 is controlled by depositing polysilicon 104, thereby increasing the PN junction area, because the area of ​​the PN junction with the bottom of the well region 105 being curved is larger than the area of ​​the bottom of the well region 105 being straight.

[0040] refer to Figure 1 and Figure 4 As shown, in step S03, a well region 105 with a second doping type is formed in the guard ring region and the active region of the substrate 101;

[0041] It should be noted that in this embodiment, the second doping type is P-type. A P-type well region 105 is formed in the substrate 101 by ion implantation. The implanted element in the P-type well region 105 is boron, and the boron implantation energy is 30keV to 120keV, the implantation dose is 1E13 to 1E14, the drive time is 30min to 180min, and the drive temperature is 1000℃ to 1200℃. The junction depth of the P-type well region 105 is about 4 to 10μm. A PN junction is formed between the P-type well region 105 and the N-type substrate 101. Due to the obstruction of polysilicon 104, during the ion implantation process, the number of particles implanted in the region of the substrate 101 corresponding to the polysilicon 104 is less than that in the region of the substrate 101 without polysilicon 104 on the upper surface of the substrate 101. Therefore, by setting polysilicon 104 at intervals, the concentration of the well region 105 in the active region can be controlled by partitioning, thereby increasing the PN junction area.

[0042] refer to Figure 1 and Figure 5 As shown, in step S04, a first implantation region 106 having a first doping type is formed in the protection ring region of the substrate 101;

[0043] It should be noted that before forming the first implantation region 106, a portion of the thick oxide layer 102 on the front side of the substrate 101 needs to be etched to form the first implantation region 106. By forming the first implantation region 106 of the first doping type in the protection ring region of the substrate 101, the function of setting a stop ring in the protection ring region can be achieved. The first doping type is N-type. The first implantation region 106 is located in the edge region of the protection ring region. Before forming the first implantation region 106, the thick oxide layer 102 in the protection ring region needs to be photolithographically etched and etched so that the first implantation region 106 can be formed in the substrate 101 corresponding to the etching removal of the thick oxide layer 102.

[0044] refer to Figure 1 and Figure 6 As shown, in step S05, a second implantation region 112 having a second doping type is formed in the well region 105;

[0045] It should be noted that the second doping type is P-type, and a second implantation region 112 is set in the well region 105. The doping concentration of the second implantation region 112 is relatively high. The implanted element in the second implantation region 112 is boron, the implantation energy of boron is 30 keV to 120 keV, and the implantation dose is 1E15 to 1E16.

[0046] refer to Figure 1 and Figure 7 As shown, in step S06, a dielectric layer 107 is formed on the substrate 101 at intervals;

[0047] It should be noted that a dielectric layer 107 is grown on the upper surface of the gate oxide layer 103, the upper surface of the polysilicon 104, and the side surface. The dielectric layer 107 is an oxide layer, which mainly serves as an insulating layer. Subsequently, the dielectric layer 107 is photolithographically etched and etched, and the photoresist is removed. At the same time as etching the dielectric layer 107, the gate oxide layer 103 on the upper surface of the substrate 101 is also etched and removed. Therefore, the dielectric layer 107 is only disposed on the side surface of all polysilicon 104 and part of the front surface of polysilicon 104, while the gate oxide layer 103 is only disposed on the bottom of polysilicon 104.

[0048] refer to Figure 1 and Figure 8 As shown, in step S07, a third implantation region 108 with a second doping type is formed in the second implantation region 112, wherein the junction depth of the third implantation region 108 is greater than the junction depth of the second implantation region 112, and the implantation concentration of the third implantation region 108 is less than the implantation concentration of the second implantation region 112.

[0049] It should be noted that in this step, the junction depth of the third injection region 108 is greater than that of the second injection region 112, and the injection concentration of the third injection region 108 is less than that of the second injection region 112; the injected element in the third injection region 108 is boron, the injected boron energy is 120 keV to 1 MeV, and the injection dose is 1E11 to 1E12.

[0050] refer to Figure 1 and Figure 9 As shown, after forming a second implantation region 108 having a second doping type in the second implantation region 112, the method includes:

[0051] Metal 109 is sputtered and diffused on the substrate 101.

[0052] refer to Figure 1 and Figure 10 As shown, in step S08, a first metal layer 110 is deposited between and above the dielectric layer 107, and the first metal layer 110 in the protection ring region is photolithographically and etched to form a spaced first metal layer 110 in the protection ring region.

[0053] It should be noted that, in step S08, a first metal layer 110 is deposited in the contact holes between the dielectric layers 107 in order to bring out the electrode, and the first metal layer 110 is metallic copper.

[0054] refer to Figure 1 and Figure 11 As shown, in step S09, a passivation layer 111 is formed between and above the first metal layer 110 in the protection ring region;

[0055] refer to Figure 1 and Figure 12 As shown, in step S10, a second metal layer 113 is deposited on the back side of the substrate 101.

[0056] It should be noted that the second metal layer is made of copper.

[0057] Secondly, embodiments of this application also provide a fast recovery diode, which is prepared by any of the preparation methods described in the first aspect.

[0058] Compared with the prior art, the embodiments of this application also provide a fast recovery diode with the same beneficial effects as the fast recovery diode preparation method described in the first aspect, which will not be repeated here.

[0059] Although this application has been described in detail herein with general description and specific embodiments, modifications or improvements can be made to it, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of this application fall within the scope of protection claimed in this application.

Claims

1. A method for fabricating a fast recovery diode, characterized in that, The method includes: A thick oxide layer is formed at intervals in the protective ring region on the front side of the substrate, wherein the substrate is of the first doping type; A gate oxide layer and polysilicon are sequentially grown on the front side of the substrate, and polysilicon is formed at intervals on the upper surface of the gate oxide layer. A well region with a second doping type is formed in the guard ring region and the active region of the substrate; A first implantation region having a first doping type is formed in the protection ring region of the substrate; A second implantation region having a second doping type is formed in the well region; A dielectric layer spaced apart is formed on the front side of the substrate; A third implantation region having a second doping type is formed in the second implantation region, wherein the junction depth of the third implantation region is greater than the junction depth of the second implantation region, and the implantation concentration of the third implantation region is less than the implantation concentration of the second implantation region; A first metal layer is deposited between and above the dielectric layers, and the first metal layer in the protection ring region is photolithographically and etched to form a spaced first metal layer in the protection ring region; A passivation layer is formed between and above the first metal layer in the protective ring region; A second metal layer is deposited on the back side of the substrate.

2. The method for fabricating a fast recovery diode as described in claim 1, characterized in that, After forming a third implantation region having a second doping type in the second implantation region, the method includes: Metal sputtering and diffusion are performed on the substrate.

3. The method for fabricating a fast recovery diode as described in claim 1, characterized in that, The thickness of the thick oxide layer is 10000Å to 20000Å.

4. The method for fabricating a fast recovery diode as described in claim 1, characterized in that, Before sequentially growing a gate oxide layer and depositing polysilicon on the upper surface of the substrate, the method further includes, A sacrificial oxide layer is grown on the front side of the substrate, and then the sacrificial oxide layer is removed.

5. The method for fabricating a fast recovery diode as described in claim 1, characterized in that, The thickness of the gate oxide layer is 500 Å to 2000 Å, and the thickness of the polycrystalline silicon is 2000 Å to 9000 Å.

6. The method for fabricating a fast recovery diode as described in claim 1, characterized in that, The element injected into the well region is boron, and the boron injection energy is 30 keV to 120 keV, the injection dose is 1E13 to 1E14, the propulsion time is 30 min to 180 min, the propulsion temperature is 1000℃ to 1200℃, and the junction depth of the well region is 4 to 10 µm.

7. The method for fabricating a fast recovery diode as described in claim 1, characterized in that, The second injection zone is injected with boron at an energy of 30 keV to 120 keV and an injection dose of 1E15 to 1E16.

8. The method for fabricating a fast recovery diode as described in claim 1, characterized in that, The third injection zone is injected with boron at an energy of 120 keV to 1 MeV and a dose of 1E11 to 1E12.

9. The method for fabricating a fast recovery diode as described in claim 1, characterized in that, The first doping type is N-type, and the second doping type is P-type.

10. A fast recovery diode, characterized in that, Prepared by the preparation method according to any one of claims 1 to 9.

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