Semiconductor device and manufacturing method thereof, electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the semiconductor device comprising: at least one transistor, an insulating layer covering the transistor, and a bit line disposed on a side of the insulating layer away from the transistor; the transistor comprising: a semiconductor pillar extending along a third direction, the semiconductor pillar comprising a channel region and first and second regions respectively disposed on two sides of the channel region, the bit line being in contact with the second region, and a contact surface of the bit line with the second region being perpendicular to the third direction. The semiconductor device provided by the embodiment has the bit line prepared at the top end of the semiconductor pillar, the process difficulty is reduced, the bit line uniformity is improved, the void is not prone to being generated, and the bit line resistance is reduced.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] Traditional vertical-ring gate dynamic random access memory (DRAM) arrays are fabricated by first forming embedded bit lines, then word lines, and finally storage capacitors on top. This process is complex, difficult to control precisely, and results in poor device performance. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a semiconductor device and its manufacturing method, as well as an electronic device, which reduces process complexity and improves device performance.

[0005] This disclosure provides a semiconductor device, including: at least one transistor, an insulating layer covering the transistor, and a bit line disposed on the insulating layer on a side away from the transistor; the transistor includes: a semiconductor pillar extending along a third direction, the semiconductor pillar including a channel region and a first region and a second region respectively disposed on both sides of the channel region, the insulating layer having a groove exposing the second region, the bit line being disposed in the groove, the bit line contacting the second region, and the contact surface between the bit line and the second region being perpendicular to the third direction.

[0006] In some embodiments, the semiconductor further includes a substrate, the third direction being perpendicular to the substrate, the substrate and the transistor being located on different wafers, and the second region being disposed on the side of the first region facing the substrate.

[0007] In some embodiments, the surface of the bit line on the side away from the semiconductor pillar is parallel to the substrate.

[0008] In some embodiments, the semiconductor device includes a plurality of transistors arrayed along a first direction and a second direction, and a plurality of bit lines extending along the second direction, wherein second regions of transistors in the same column distributed along the second direction are connected to the same bit line, and the first direction and the second direction intersect.

[0009] In some embodiments, the insulating layer includes an insulator layer filled between the bit lines, the insulator layer including a low-K dielectric.

[0010] In some embodiments, the transistor further includes a gate electrode surrounding a sidewall of the channel region, wherein the gate electrodes of transistors in the same row distributed along the first direction are connected to form a word line.

[0011] In some embodiments, the semiconductor device further includes: a connection electrode disposed on the side of the word line near the substrate and extending in a direction perpendicular to the substrate, wherein one connection electrode is connected to one word line.

[0012] In some embodiments, the connection electrodes connecting adjacent word lines are disposed on opposite sides of the bit lines.

[0013] In some embodiments, the semiconductor device further includes: a logic circuit disposed between the substrate and the transistor, wherein the orthographic projection of the logic circuit overlaps with the orthographic projection of the transistor on a plane parallel to the substrate.

[0014] In some embodiments, the substrate includes a central region and a peripheral region surrounding the central region, the transistor is disposed in the central region, and the semiconductor device further includes a logic circuit disposed in the peripheral region, wherein the orthographic projection of the logic circuit overlaps with the orthographic projection of the transistor in a plane perpendicular to the substrate.

[0015] This disclosure provides an electronic device, including the semiconductor device described in any of the above embodiments.

[0016] This disclosure provides a method for manufacturing a semiconductor device, the semiconductor device including at least one transistor, the transistor including a semiconductor pillar, the manufacturing method including:

[0017] A first wafer is provided, and a substrate is formed thereon and a semiconductor pillar extending in a direction perpendicular to the substrate of the at least one transistor disposed on the substrate. The semiconductor pillar includes a channel region and a first region and a second region disposed on both sides of the channel region, wherein the second region is disposed on the side of the channel region away from the substrate.

[0018] An insulating layer is formed covering the semiconductor pillar, the insulating layer having a groove exposing the second region, and a bit line is formed in the groove to contact the second region, the contact surface of the bit line with the second region being parallel to the substrate;

[0019] A second wafer is provided, the first wafer is flipped, the side of the first wafer away from the substrate is bonded to the second wafer, and the substrate is etched away to expose the first region.

[0020] In some embodiments, before forming the bit line in contact with the second region, the method further includes:

[0021] A gate insulating layer and a gate electrode are sequentially formed around the sidewalls of the channel region.

[0022] In some embodiments, before bonding the first wafer to the second wafer on the side away from the substrate, the method further includes: forming logic circuitry on the second wafer.

[0023] In some embodiments, before forming the bit line in contact with the second region, the method further includes forming a logic circuit on the first wafer.

[0024] This disclosure includes a semiconductor device and its manufacturing method, and an electronic device. The semiconductor device includes: at least one transistor, an insulating layer covering the transistor, and a bit line disposed on the insulating layer away from the transistor. The transistor includes: a semiconductor pillar extending along a third direction, the semiconductor pillar including a channel region and a first region and a second region respectively disposed on both sides of the channel region; the insulating layer has a groove exposing the second region, the bit line is disposed in the groove, the bit line contacts the second region, and the contact surface between the bit line and the second region is perpendicular to the third direction. In the solution provided in this embodiment, the bit line 30 is fabricated at the top of the semiconductor pillar, and the contact surface between the bit line 30 and the second region 13 is parallel to the substrate. Compared with the process of fabricating the bit line by digging a groove at the bottom of the semiconductor pillar, the process difficulty is greatly reduced, the bit line size uniformity is improved, there are no voids, and the bit line resistance is reduced.

[0025] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description and the drawings.

[0026] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0027] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions.

[0028] Figure 1A A schematic plan view of a semiconductor device provided for an exemplary embodiment;

[0029] Figure 1B for Figure 1A A schematic diagram of the cross section along the AA' direction;

[0030] Figure 1CA schematic diagram of a semiconductor device is provided for another exemplary embodiment;

[0031] Figure 1D A schematic diagram of a semiconductor device is provided for another exemplary embodiment;

[0032] Figure 2 A perspective view of the bit line isolation groove after forming an exemplary embodiment;

[0033] Figure 3 A perspective view of the first insulating layer after its formation, provided as an exemplary embodiment;

[0034] Figure 4 A perspective view of the word line isolation groove after forming an exemplary embodiment;

[0035] Figure 5 A schematic cross-sectional view along the AA' direction after the formation of the third edge layer, provided as an exemplary embodiment;

[0036] Figure 6 A schematic cross-sectional view along the AA' direction after etching the second and third insulating layers, provided as an exemplary embodiment;

[0037] Figure 7 A schematic cross-sectional view along the AA' direction after the deposition of a gate electrode thin film, provided as an exemplary embodiment;

[0038] Figure 8 A schematic cross-sectional view along the AA' direction after the formation of the gate insulating layer and the gate electrode, provided for an exemplary embodiment;

[0039] Figure 9 A schematic cross-sectional view along the AA' direction after removing the gate electrode and gate insulating layer located at the edge of the array, provided as an exemplary embodiment;

[0040] Figure 10A A schematic cross-sectional view along the AA' direction after the formation of the fourth insulating layer, provided as an exemplary embodiment;

[0041] Figure 10B A schematic cross-sectional view along the AA' direction after the formation of the fourth insulating layer, provided for another exemplary embodiment;

[0042] Figure 11A A top view provided for an exemplary embodiment after forming a bit line;

[0043] Figure 11B A schematic cross-sectional view along the AA' direction after forming the bit line, provided for an exemplary embodiment;

[0044] Figure 12A A top view provided for an exemplary embodiment after the connection electrodes have been formed;

[0045] Figure 12B for Figure 12A A schematic diagram of the cross section along the BB' direction.

[0046] Figure 13 A top view of a first wafer and a second wafer provided for an exemplary embodiment;

[0047] Figure 14 A schematic cross-sectional view along the AA' direction after etching the substrate, provided as an exemplary embodiment;

[0048] Figure 15 A schematic cross-sectional view along the AA' direction after the connection layer is formed, provided as an exemplary embodiment;

[0049] Figure 16 A schematic cross-sectional view along the AA' direction after the capacitor is formed, provided as an exemplary embodiment;

[0050] Figure 17 A flowchart of a method for manufacturing a semiconductor device provided as an exemplary embodiment.

[0051] Explanation of reference numerals in the attached figures:

[0052] 1—Substrate; 2—First insulating layer; 3—Second insulating layer; 4—Third insulating layer; 5—Fourth insulating layer;

[0053] 10 - Semiconductor pillar; 11 - Channel region; 12 - First region; 13 - Second region; 14 - Gate insulating layer;

[0054] 20 - Word line; 21 - Gate electrode; 30 - Bit line; 40 - Connector layer; 41 - First electrode plate; 42 - Second electrode plate;

[0055] 51 - First insulator layer; 52 - Second insulator layer; 60 - Connecting electrode; 70 - Dielectric layer;

[0056] 81 - First bonding pad; 82 - Second bonding pad; 100 - First wafer; 101 - Central region;

[0057] 102 - Peripheral area; 200 - Second wafer; 210 - Logic circuit; 301 - Bonding pad. Detailed Implementation

[0058] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0059] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0060] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0061] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0062] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0063] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0064] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0065] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 81°, and therefore also includes angles of 85° or more and less than 95°.

[0066] The statement in this disclosure that "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0067] In one technical solution, bit lines are formed by trenching at the bottom of the semiconductor pillar and filling it with conductive material. This process is difficult, the resulting bit lines have poor uniformity, and voids are easily formed inside the bit lines, causing different bit lines to have different and higher resistances. In addition, it is difficult to form a reliable ohmic contact between the bit lines and the drain terminal, resulting in high contact resistance. Bit lines are isolated by deep trenches, but voids are easily generated when filling the deep trenches with insulating material, leading to leakage between the bit lines.

[0068] In this embodiment, the bit lines are fabricated by creating grooves on the top of the semiconductor pillars, which reduces the complexity of the process, improves the uniformity of the bit lines, avoids voids, reduces the bit line resistance, and facilitates the formation of reliable ohmic contacts between the bit lines and the semiconductor pillars, reducing contact resistance. Furthermore, the size and shape of different bit lines within the same memory array are easier to control, ensuring consistency in size and shape and stabilizing the bit line resistance. The insulating layer filling the spaces between the bit lines is less prone to voids, preventing leakage.

[0069] Figure 1A This is a planar schematic diagram of a semiconductor device provided in an embodiment of the present disclosure. Figure 1B for Figure 1A A schematic diagram of the cross-section along the AA' direction. (See diagram below.) Figure 1A and Figure 1B As shown, this disclosure provides a semiconductor device, which may include: at least one transistor, a fourth insulating layer 5 covering the transistor, and a bit line 30 disposed on the side of the fourth insulating layer 5 away from the transistor; the transistor may include: a semiconductor pillar 10 extending along a third direction Z, the semiconductor pillar 10 may include a channel region 11 and a first region 12 and a second region 13 respectively disposed on both sides of the channel region 11, the bit line 30 contacting the second region 13, and the contact surface between the bit line 30 and the second region 13 being perpendicular to the third direction Z. The channel region 11 can be roughly distinguished from the first region 12 and the second region 13 by the position of the gate electrode, or by the difference in conductivity between the first region 12 and the second region 13 and the channel region 11.

[0070] In the solution provided in this embodiment, the contact surface between the bit line 30 and the second region 13 is parallel to the substrate. The bit line 30 is prepared by trenching and filling the insulating layer at the top of the semiconductor pillar. That is, the bit line 30 is prepared at the top of the semiconductor pillar, which reduces the difficulty of the process, improves the uniformity of the bit line, makes it less likely to generate voids, and reduces the bit line resistance.

[0071] The first region 12 and the second region 13 can be regions of the semiconductor pillar 10 doped with impurities. In one embodiment, the conductivity type of the first region 12 and the second region 13 can be n-type or p-type. The first region 12 can be a source region and the second region 13 can be a drain region, or the first region 12 can be a drain region and the second region 13 can be a source region.

[0072] In an exemplary embodiment, the semiconductor pillar 10 extending in a direction perpendicular to the substrate 1 can be understood as extending only in a direction perpendicular to the substrate 1, and the morphology of the sidewalls of the semiconductor pillar 10 is not limited.

[0073] In one exemplary embodiment, the transistor may further include a gate electrode 21, which may surround the sidewall of the channel region 11.

[0074] In an exemplary embodiment, the transistor may further include a gate insulating layer 14 surrounding the sidewall of the semiconductor pillar 10, the gate insulating layer 14 being located between the gate electrode 21 and the semiconductor pillar 10 to insulate the gate electrode 21 from the semiconductor pillar 10.

[0075] In an exemplary embodiment, the semiconductor device further includes a substrate, the third direction being perpendicular to the substrate, the second region 13 being disposed on the side of the first region 11 facing the substrate, the substrate and the transistor being located on different wafers, i.e., the transistor is located on one wafer, which is bonded to another wafer, and the substrate of the other wafer serves as the substrate of the semiconductor device. Figure 1C and Figure 1D As shown, the transistor is located on a first wafer 100, which is disposed on a second wafer 200, and the substrate of the second wafer 200 ( Figure 1C and Figure 1D (Not shown) or a second wafer 200 as the substrate of the semiconductor device.

[0076] In an exemplary embodiment, the surface of the bit line 30 on the side away from the semiconductor pillar 10 may be parallel to the substrate. In this embodiment, both the upper and lower surfaces of the bit line 30 are parallel to the substrate, resulting in stable bit line resistance.

[0077] In one exemplary embodiment, the size and shape of the cross sections parallel to the substrate at different positions of the bit line 30 may be the same or approximately the same.

[0078] In one exemplary embodiment, the dimensions and shape of the cross-section of the channel region 11 in the direction parallel to the substrate may be approximately the same at different locations.

[0079] In one exemplary embodiment, the dimensions and shapes of the cross-section of the first region 12 in the direction parallel to the substrate may be substantially the same at different locations.

[0080] In one exemplary embodiment, the dimensions and shapes of the cross-section of the second region 13 in the direction parallel to the substrate may be substantially the same at different locations.

[0081] In one exemplary embodiment, the semiconductor device may include a memory array, which may include a plurality of vertically channeled transistors distributed along a first direction X and a second direction Y, a plurality of word lines 20 extending along the first direction X, and a plurality of bit lines 30 extending along the second direction Y. The gate electrodes 21 of transistors in the same row distributed along the first direction X are connected to form a word line 20, and the second regions 13 of transistors in the same column distributed along the second direction Y are connected to the same bit line 30. The first direction X and the second direction Y may intersect. In one exemplary embodiment, the first direction X and the second direction Y may be perpendicular.

[0082] In an exemplary embodiment, the first direction X may be parallel to the substrate, and the second direction Y may be parallel to the substrate.

[0083] In one exemplary embodiment, such as Figure 10B As shown, the fourth insulating layer may include a second insulating layer 52 filled between the bit lines 30, and the second insulating layer 52 may include a low-K dielectric. In this embodiment, compared to the method of forming trenches at the bottom of the semiconductor pillars and then filling them to form bit lines (typically, bit lines are isolated by silicon dioxide), the use of a low-K dielectric for isolation between bit lines can improve circuit delay. However, this disclosure is not limited to this; non-low-K dielectrics can be used for isolation between bit lines.

[0084] In one exemplary embodiment, the semiconductor device may further include an isolation structure filled between transistors, the isolation structure including at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0085] In one exemplary embodiment, such as Figure 12B As shown, the semiconductor device may further include: a connection electrode 60 disposed on the side of the word line 20 near the substrate and extending in a direction perpendicular to the substrate, wherein one connection electrode 60 is connected to one word line 20. Figure 12B This is a schematic diagram of the fabrication process. The actual semiconductor device will be flipped later. At this time, the connecting electrode 60 and the bit line 30 will be flipped to the bottom, that is, to the side closer to the substrate.

[0086] In one exemplary embodiment, such as Figure 12AAs shown, the connection electrodes 60 connecting adjacent word lines 20 can be disposed on opposite sides of the bit line 30. Some connection electrodes 60 are distributed on one side of the bit line 30, and some connection electrodes 60 are distributed on the other side of the bit line 30. Furthermore, the connection electrodes 60 connecting adjacent word lines 20 are disposed on different sides to avoid the connection electrodes 60 being too dense and interfering with each other.

[0087] In one exemplary embodiment, such as Figure 1C As shown, the semiconductor device may further include a logic circuit 210 disposed between the substrate and the transistor, wherein the orthographic projection of the logic circuit 210 overlaps with the orthographic projection of the transistor on a plane parallel to the substrate. In this embodiment, the logic circuit 210 is disposed below the transistor, and the logic circuit 210 and the transistor may be disposed on different wafers.

[0088] In one exemplary embodiment, such as Figure 1D As shown, the substrate may include a central region 101 and a peripheral region 102 surrounding the central region 101. The transistor may be disposed in the central region 101, and the semiconductor device may further include logic circuitry disposed in the peripheral region 102. Figure 1D (Not shown in the image), on a plane perpendicular to the substrate, the orthographic projection of the logic circuit overlaps with the orthographic projection of the transistor. In this embodiment, the logic circuit and the transistor can be fabricated on the same wafer.

[0089] In one exemplary embodiment, the semiconductor device may further include a data storage element.

[0090] In one exemplary embodiment, the data storage element is, for example, a capacitor, thus forming a 1T1C memory structure. However, the embodiments disclosed herein are not limited to this; they can be combined with other transistors to form a 2T0C memory structure, and so on.

[0091] In one exemplary embodiment, such as Figure 16 As shown, the capacitor may include a first electrode 41 and a second electrode 42, and a dielectric layer 70 disposed between the first electrode 41 and the second electrode 42. The first electrode 41 is connected to the first region 12.

[0092] Figure 1A and Figure 1B The semiconductor device structure shown is merely an example, and the embodiments disclosed herein are not limited to this; other structures may also be used.

[0093] The technical solution of this embodiment is further illustrated below through the fabrication process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process.

[0094] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0095] 101) Provide a first wafer, on which a plurality of bit line isolation trenches T1 extending along the second direction Y are formed on a substrate 1, such as Figure 2 As shown, Figure 2 This is a three-dimensional schematic diagram showing the bit line isolation grooves after they have been formed. The bit line isolation grooves T1 can be distributed at intervals along the first direction X.

[0096] In an exemplary embodiment, the substrate 1 may be a semiconductor substrate; for example, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0097] 102) A first insulating film is deposited on the substrate 1 to form a first insulating layer 2, wherein the first insulating layer 2 fills the bit line isolation groove T1, as shown in the figure. Figure 3 As shown, Figure 3 This is a three-dimensional schematic diagram after the first insulating layer has been formed.

[0098] In an exemplary embodiment, the first insulating film includes, but is not limited to, silicon oxide (SiOx), silicon nitride (SiN), etc.

[0099] After the first insulating layer 2 is formed, ion implantation, i.e. doping, can be performed according to the requirements of the first region 12, the channel region 11 and the second region 13 of the semiconductor device.

[0100] 103) Multiple word line isolation slots T2 extending along the first direction X are formed. The word line isolation slots T2 can be distributed at intervals along the second direction Y, such as... Figure 4 As shown.

[0101] At this time, multiple semiconductor pillars 10 are formed on the substrate 1 through bit line isolation trench T1 and word line isolation trench T2.

[0102] The word line isolation groove T2 and the bit line isolation groove T1 can have the same depth along the direction perpendicular to the substrate 1.

[0103] 104) Deposit a second insulating film to form a second insulating layer 3; and deposit a third insulating film to form a third insulating layer 4, wherein the second insulating layer 3 covers the semiconductor pillar 10, as shown. Figure 5 As shown, Figure 5 A schematic diagram of the cross section along the AA' direction after the formation of the third edge layer 4.

[0104] In an exemplary embodiment, the second insulating film and the third insulating film can be deposited by ALD.

[0105] In one exemplary embodiment, the second insulating film and the third insulating film may be low-K dielectric layers, that is, dielectric layers with a dielectric constant K < 3.9. For example, they may be any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC).

[0106] In one exemplary embodiment, the second insulating film may be silicon oxide.

[0107] In one exemplary embodiment, the third insulating film may be a silicon nitride.

[0108] In one exemplary embodiment, a second insulating film with a thickness of 3 nm to 8 nm can be deposited, and subsequently polished so that the thickness of the second insulating layer 3 located at the top of the semiconductor pillar 10 is less than or equal to 2 nm.

[0109] 105) Etch the second insulating layer 3 to expose the channel region 11 and the second region 13, then etch the third insulating layer 4 to expose the second region 13, as shown. Figure 6 As shown, Figure 6 This is a schematic cross-sectional view along the AA' direction after etching the second insulating layer 3 and the third insulating layer 4.

[0110] 106) Deposit gate insulating film 140 and gate electrode film 210;

[0111] The gate insulating film 140 is located between the gate electrode film 210 and the semiconductor pillar 10, insulating the gate electrode film 210 from the semiconductor pillar 10. Figure 7 As shown, Figure 7 This is a schematic cross-sectional view along the AA' direction after the deposition of the gate electrode thin film 210.

[0112] In an exemplary embodiment, the gate insulating film 140 may be a High-K dielectric material, including but not limited to at least one of the following: a single-layer or multi-layer structure of at least one of silicon oxide, aluminum oxide, silicon nitride, hafnium oxide, and silicon oxynitride.

[0113] In an exemplary embodiment, the gate electrode thin film 210 may be formed of or comprise a conductive material, and the conductive material may be, for example, one of a doped semiconductor material, a conductive metal nitride, a metal material, and a metal-semiconductor compound.

[0114] 107) Forming a gate insulating layer 14 and a gate electrode 21;

[0115] The formation of the gate insulating layer 14 and the gate electrode 21 may include: etching the gate insulating film 140 and the gate electrode film 210 to expose the second region 13, thereby forming the gate insulating layer 14 and the gate electrode 21. Figure 8 As shown, Figure 8 This is a schematic cross-sectional view along the AA' direction after the gate insulating layer 14 and gate electrode 21 are formed. The gate electrodes 21 of transistors in the same column are connected to form word lines 20.

[0116] 108) Remove the gate electrode 21 and gate insulating layer 14 located at the edge of the array;

[0117] The removal of the gate electrode 21 and gate insulating layer 14 located at the edge of the array may include: removing the gate electrode 21 and gate insulating layer 14 located on the side of the third insulating layer 4 furthest from the semiconductor pillar 10 by photolithography, such as... Figure 9 As shown, Figure 9 A schematic cross-sectional view along the AA' direction after removing the gate electrode 21 and gate insulating layer 14 located at the edge of the array.

[0118] 109) Form the fourth insulating layer 5;

[0119] The formation of the fourth insulating layer 5 may include: coating a fourth insulating film onto the substrate 1 on which the aforementioned pattern is formed to form the fourth insulating layer 5, such as... Figure 10A and Figure 10B As shown, Figure 10A This is a schematic cross-sectional view along the AA' direction after the formation of the fourth insulating layer 5, as provided in one embodiment. Figure 10B A cross-sectional schematic diagram along the AA' direction after the formation of the fourth insulating layer 5, provided for another embodiment.

[0120] In one exemplary embodiment, the fourth insulating layer 5 can be formed by depositing a fourth insulating film via spin-coated spin oxide dielectric (SOD) followed by annealing.

[0121] In one exemplary embodiment, the fourth insulating film may be an oxide of silicon, such as SiO2.

[0122] In another exemplary embodiment, the fourth insulating layer 5 may include a first insulator layer 51 and a second insulator layer 52, wherein the first insulator layer 51 is disposed on the side of the second insulator layer 52 close to the substrate 1, the first insulator layer 51 may be formed by SOD method, and the second insulator layer 52 may be formed by ALD deposition method.

[0123] In an exemplary embodiment, the first insulator layer 51 may be a silicon oxide, such as SiO2. The second insulator layer 52 may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9. For example, it may be any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC). Using a low-K dielectric layer for isolation between bit lines 30, compared to a scheme where bit lines are fabricated in bottom trenches, results in a lower dielectric constant between the isolation layers, which can improve circuit delay.

[0124] 110) Forming bit line 30;

[0125] The formation of bit line 30 may include: etching the fourth insulating layer 5 to form a groove that exposes the semiconductor pillar 10, referred to here as a bit line groove, the bit line groove may extend along the second direction Y, and the bit line groove exposes the second region 13;

[0126] A first conductive thin film is deposited in the bit line groove to form a bit line 30 extending along the second direction Y, such as... Figure 11A and Figure 11B As shown, where, Figure 11A This is a top view after bit line 30 is formed; Figure 11B This is a schematic diagram of the cross section along the AA' direction after the bit line 30 is formed. Figure 11A In the middle, the wider bonding area near the edge of the bit line 30 can be the bonding pad 301, and the subsequent bit line 30 can be connected to other devices, such as logic circuits, through the bonding pad 301.

[0127] The in-situ deposition of the first conductive thin film in the trench to form the bit line 30 may include:

[0128] A cobalt thin film is deposited, followed by a first rapid thermal annealing (RTA). The cobalt thin film is then wet-etched, and a second RTA is performed to deposit a seed layer comprising tantalum (Ta) or tantalum nitride (TaN) and copper (Cu). A copper (Cu) thin film is then formed on the seed layer via electrochemical plating (ECP). The copper thin film is then smoothed, for example by CMP, to form bit lines 30. The first conductive thin film is not limited to this and can include other conductive materials, such as tungsten. In schemes where bit lines are formed by etching trenches at the bottom, copper cannot be used as bit lines due to the difficulty of etching copper. Therefore, the scheme provided in this embodiment, when using copper to prepare bit lines, can significantly reduce resistance.

[0129] like Figure 11A As shown, multiple bit lines 30 can be formed. The number of bit lines 30 can be related to the number of columns of semiconductor pillars 10, with one bit line 30 corresponding to one column of semiconductor pillars 10.

[0130] In some embodiments, each bit line 30 may be connected to a column of semiconductor pillars 10.

[0131] 111) Form connecting electrode 60;

[0132] The forming connection electrode 60 may include:

[0133] Forming a first through hole that exposes the word line 20;

[0134] A second conductive thin film is deposited in the first via to form a connecting electrode 60. For example... Figure 12A and Figure 12B As shown, where, Figure 12A To create a top view after connecting the electrodes, Figure 12B for Figure 12A A schematic diagram of the cross section along the BB' direction.

[0135] The first through hole can correspond one-to-one with the word line 20, with each first through hole exposing one word line 20. The connecting electrode 60 can correspond one-to-one with the word line 20, with each connecting electrode 60 connecting one word line 20.

[0136] In an exemplary embodiment, the connection electrode 60 can be disposed in the boundary region. The connection electrode 60 can be divided into two groups, respectively disposed on opposite sides, and the connection electrodes of adjacent word lines 20 are respectively disposed on different sides of the bit line 30. Taking four word lines as an example, the connection electrode of the first word line is disposed on the first side of the bit line 30, the connection electrode of the second word line is disposed on the second side of the bit line 30, the connection electrode of the third word line is disposed on the first side of the bit line 30, the connection electrode of the fourth word line is disposed on the second side of the bit line 30, and so on. This is just an example, and the position of the connection electrode 60 can be changed.

[0137] In one exemplary embodiment, the deposition of the second conductive thin film may include:

[0138] A seed layer comprising tantalum (Ta) or tantalum nitride (TaN) and copper (Cu) is deposited. A copper (Cu) thin film is then formed on the seed layer via ECP, and the copper thin film is subsequently smoothed, for example, by CMP. The second conductive thin film formed here is merely an example; the second conductive thin film may include other conductive materials.

[0139] Through the above manufacturing process, a memory array comprising multiple arrayed transistors, multiple word lines 20, and multiple bit lines 30 is formed on the first wafer.

[0140] 112) A second wafer is provided, on which logic circuits are formed. The aforementioned first wafer, including the memory array, is flipped and bonded to the second wafer containing the logic circuits. The first wafer containing the memory array is positioned above, and the second wafer containing the logic circuits is positioned below. The side of the first wafer furthest from the substrate 1 is bonded to the second wafer. The second bonding pad 82 on the second wafer containing the logic circuits is mirror-symmetrical to the first bonding pad 81 on the first wafer containing the memory array. The first bonding pad 81 on the first wafer containing the memory array includes bonding pads for bit lines 30 and connecting electrodes 60, such as... Figure 13 As shown, where, Figure 13 Figure (a) on the left is a top view of the first wafer (before flipping). Figure 13 Figure (b) on the right is a top view of the second wafer. It can be seen that the second bonding pad 82 on the second wafer is mirror-symmetrical to the first bonding pad 81 on the first wafer. During bonding, the mirror-symmetrical first bonding pad 81 and second bonding pad 82 come into contact with each other to achieve electrical connection. Figure 13 The bonding pad layout shown is merely an example; electrical connections for logic circuits and memory arrays can be made in other ways.

[0141] In one exemplary embodiment, the logic circuit may include, but is not limited to, a signal sense amplifier, a decoder, a voltage converter, and so on.

[0142] 113) Etch away the substrate 1 to expose the semiconductor pillar 10, such that the height of the semiconductor pillar 10 is less than the height of the first insulating layer 2, as shown. Figure 14 As shown, Figure 14 This is a schematic diagram of a cross-section along the AA' direction after etching substrate 1, and Figure 14 Only the first wafer is shown; the second wafer is not shown.

[0143] In an exemplary embodiment, the substrate 1 can be etched to a thickness of 1 to 2 μm by CMP first, and then the substrate 1 and the semiconductor pillar 10 can be etched more precisely using tetramethylammonium hydroxide (TMAH).

[0144] In one exemplary embodiment, the height difference d between the semiconductor pillar 10 and the first insulating layer 2 is, for example, 50 angstroms to 1000 angstroms.

[0145] 114) Form a connecting layer 40;

[0146] The formation of the interconnect layer 40 may include: depositing a polycrystalline silicon thin film and then grinding it smooth to form the interconnect layer 40, such as... Figure 15 As shown, Figure 15 This is a schematic diagram of the cross-section along the AA' direction after the connection layer 40 is formed, and Figure 15 Only the first wafer is shown; the second wafer is not shown.

[0147] In one exemplary embodiment, the polycrystalline silicon thin film may be highly phosphorus-doped polycrystalline silicon. The connecting layer 40 may reduce the contact resistance between the subsequently formed first electrode plate and the first region.

[0148] 115) Forming a capacitor;

[0149] The capacitor formation may include:

[0150] A first conductor material is deposited to form a first electrode plate 41 disposed on the surface of the connecting layer 40;

[0151] The deposition medium material forms a medium layer 70;

[0152] Depositing a second conductor material to form a second electrode plate 42, such as... Figure 16 As shown, where, Figure 16 This is a schematic diagram of the cross-section along the AA' direction after the capacitor is formed, and Figure 16Only the first wafer is shown; the second wafer is not shown.

[0153] In one exemplary embodiment, the first conductor material includes, for example, TiN.

[0154] In one exemplary embodiment, the medium material may include, for example, a zirconium oxide (ZrO2) / aluminum oxide (Al2O3) / zirconium oxide (ZrO2) stacked structure, hafnium oxide, or strontium titanate.

[0155] In one exemplary embodiment, the second conductor material includes, for example, TiN.

[0156] In one exemplary embodiment, the dielectric layer 70 of the capacitors connected to the transistors in the memory array can be connected to form an integral structure.

[0157] In one exemplary embodiment, the second plates 42 of the capacitors to which the transistors in the memory array are connected can be connected to form a single, integrated structure. This integrated structure can be, for example, a full-surface electrode.

[0158] In an exemplary embodiment, the first electrode plate 41 may be U-shaped along a cross section perpendicular to the substrate.

[0159] 116) Deposit a fifth insulating film to form a sixth insulating layer covering the capacitor;

[0160] An output electrode is formed that penetrates the sixth insulating layer and the first wafer; the output electrode is connected to the logic circuit, and the output electrode can be connected to an external circuit, and a signal can be subsequently loaded to the logic circuit through the output electrode;

[0161] A bonding bump pad is formed to connect with the lead-out electrode, thus completing the fabrication of the semiconductor device.

[0162] In one exemplary embodiment, the lead electrode can be formed using through silicon via (TSV) technology. For example, a second via is formed that penetrates the sixth insulating layer, the first wafer, and exposes the logic circuit. A seed layer comprising tantalum (Ta) or tantalum nitride (TaN) and copper (Cu) is deposited within the second via. A copper (Cu) thin film is formed on the seed layer using ECP, and then the copper thin film is smoothed, for example, by CMP, to form the lead electrode.

[0163] In the above embodiments, the logic circuits and the memory array are distributed on different wafers. In other embodiments, the logic circuits and the memory array may be distributed on the same wafer. Examples are given below.

[0164] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0165] Steps 201) to 209) are the same as steps 101) to 109), a first wafer is provided, and an array of transistors is formed on the first wafer. The transistors may include, in this embodiment, a substrate 1 including a central region and a peripheral region surrounding the central region, a memory array is fabricated in the central region, and the peripheral region may be protected with photoresist.

[0166] 210) Form logic circuits in the surrounding area;

[0167] When fabricating the logic circuit, photoresist can be used to protect the memory array.

[0168] In one exemplary embodiment, the logic circuit may include, but is not limited to, a signal sense amplifier, a decoder, a voltage converter, and so on.

[0169] 211) Form bit line 30.

[0170] The bit line 30 can be formed by referring to step 110, etching the fourth insulating layer 5 to form a groove that exposes the semiconductor pillar 10, i.e., a bit line groove; and depositing a first conductive film in the bit line groove to form the bit line 30.

[0171] 212) Form connecting electrode 60;

[0172] The formation of the connection electrode 60 can be achieved by referring to step 111, forming a through hole that exposes the word line 20; and depositing a second conductive film in the through hole to form the connection electrode 60.

[0173] 213) Implement the interconnection between logic circuits and memory arrays;

[0174] 214) The first wafer, which includes the memory array and logic circuit, is flipped and bonded to a blank second wafer, with the side of the first wafer away from the substrate 1 bonded to the second wafer, the second wafer being below and the first wafer being above.

[0175] 215) to 217), same as 113) to 115), will not be repeated here.

[0176] 218) Deposit a fifth insulating film to form a sixth insulating layer covering the capacitor;

[0177] An electrode is formed that penetrates the sixth insulating layer; the electrode is connected to the logic circuit and can be connected to an external circuit, through which signals can be applied to the logic circuit.

[0178] A bonding bump is formed to connect with the lead-out electrode, thus completing the fabrication of the semiconductor device.

[0179] In an exemplary embodiment, the lead electrode can be formed using TSV technology. For example, a via is formed that penetrates the sixth insulating layer and exposes the logic circuit. A seed layer comprising tantalum (Ta) or tantalum nitride (TaN) and copper (Cu) is deposited within the via. A copper (Cu) thin film is formed on the seed layer using ECP, and then the copper thin film is smoothed, for example by CMP, to form the lead electrode.

[0180] The above embodiments are illustrated using 1T1C as an example, but the embodiments disclosed herein are not limited thereto. The transistor can be combined with other devices, such as forming a 2T0C memory structure with another transistor, etc.

[0181] In the above embodiments, instead of fabricating the bit lines in the bottom trench, the bit lines are fabricated at the top and then flipped down, which greatly reduces the difficulty of the process. The resulting bit lines have high uniformity, are less prone to voids, and have more stable contact resistance. Compared with the solution of fabricating bit lines in the bottom trench, the insulating layer filling the bit lines in the solution provided by this disclosure is less prone to voids, which can prevent leakage between bit lines. In addition, the size and shape of the bit lines are easier to control, making it easier to ensure that the size and shape of different bit lines are consistent, reducing the resistance difference between different bit lines.

[0182] This disclosure also provides an electronic device, including the semiconductor device described in the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0183] Figure 17 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 17 As shown, this disclosure provides a method for manufacturing a semiconductor device, the semiconductor device including at least one transistor, the transistor including a semiconductor pillar, the manufacturing method including:

[0184] Step 1701: Provide a first wafer, form a substrate and a semiconductor pillar extending in a direction perpendicular to the substrate for the at least one transistor disposed on the substrate, the semiconductor pillar including a channel region and a first region and a second region respectively disposed on both sides of the channel region, wherein the second region is disposed on the side of the channel region away from the substrate;

[0185] Step 1702: Form an insulating layer covering the semiconductor pillar, wherein the insulating layer has a groove exposing the second region, and a bit line is formed in the groove to contact the second region, wherein the contact surface between the bit line and the second region is parallel to the substrate;

[0186] Step 1703: Provide a second wafer, flip the first wafer, bond the side of the first wafer away from the substrate to the second wafer, and etch away the substrate to expose the first region.

[0187] The semiconductor device manufacturing method provided in this embodiment reduces the process difficulty by fabricating bit lines at the top of semiconductor pillars. This results in good bit line uniformity, avoidance of voids, low bit line resistance, and facilitates the formation of reliable ohmic contacts between the bit lines and semiconductor pillars, reducing contact resistance. Furthermore, the size and shape of different bit lines are easier to control, ensuring consistency and stable bit line resistance. The insulating layer between bit lines is less prone to voids, preventing leakage.

[0188] In one exemplary embodiment, before forming the bit line in contact with the second region, the following may also be included:

[0189] A gate insulating layer and a gate electrode are sequentially formed around the sidewalls of the channel region.

[0190] In one exemplary embodiment, before bonding the first wafer to the second wafer on the side away from the substrate, the method further includes forming logic circuitry on the second wafer.

[0191] In one exemplary implementation, before forming the bit line in contact with the second region, the method further includes forming a logic circuit on the first wafer.

[0192] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: At least one transistor, an insulating layer covering the transistor, a bit line disposed on the insulating layer on a side away from the transistor, and a substrate; the transistor includes: a semiconductor pillar extending along a third direction perpendicular to the substrate, the semiconductor pillar including a channel region and a first region and a second region respectively disposed on both sides of the channel region; the insulating layer has a groove exposing the second region, the bit line is disposed in the groove, the groove is formed by etching the insulating layer at the top of the semiconductor pillar; the bit line contacts the second region, and the contact surface between the bit line and the second region is perpendicular to the third direction; The substrate and the transistor are located on different wafers, and the second region is disposed on the side of the first region facing the substrate.

2. The semiconductor device according to claim 1, characterized in that, The surface of the bit line on the side away from the semiconductor pillar is parallel to the substrate.

3. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a plurality of transistors arrayed along a first direction and a second direction, and a plurality of bit lines extending along the second direction, wherein the second regions of transistors in the same column distributed along the second direction are connected to the same bit line, and the first direction and the second direction intersect.

4. The semiconductor device according to claim 3, characterized in that, The insulating layer includes an insulator layer filled between the bit lines, the insulator layer comprising a low-K dielectric.

5. The semiconductor device according to claim 3, characterized in that, The transistor further includes a gate electrode that surrounds the sidewall of the channel region, and the gate electrodes of transistors in the same row distributed along the first direction are connected to form a word line.

6. The semiconductor device according to claim 5, characterized in that, The semiconductor device further includes: a connection electrode disposed on the side of the word line near the substrate, extending in a direction perpendicular to the substrate, wherein one connection electrode is connected to one word line.

7. The semiconductor device according to claim 6, characterized in that, The connection electrodes connecting adjacent word lines are located on opposite sides of the bit lines.

8. The semiconductor device according to any one of claims 2 to 7, characterized in that, The semiconductor device further includes: a logic circuit disposed between the substrate and the transistor, wherein the orthographic projection of the logic circuit overlaps with the orthographic projection of the transistor on a plane parallel to the substrate.

9. The semiconductor device according to any one of claims 2 to 7, characterized in that, The substrate includes a central region and a peripheral region surrounding the central region. The transistor is disposed in the central region. The semiconductor device further includes a logic circuit disposed in the peripheral region. On a plane perpendicular to the substrate, the orthographic projection of the logic circuit overlaps with the orthographic projection of the transistor.

10. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 9.

11. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes at least one transistor, the transistor including a semiconductor pillar, and the manufacturing method includes: A first wafer is provided, a substrate is formed, and a semiconductor pillar extending in a direction perpendicular to the substrate is disposed on the substrate. The semiconductor pillar includes a channel region and a first region and a second region respectively disposed on both sides of the channel region, wherein the second region is disposed on the side of the channel region away from the substrate. An insulating layer is formed covering the semiconductor pillar, the insulating layer having a groove exposing the second region, and a bit line is formed in the groove to contact the second region, the contact surface of the bit line with the second region being parallel to the substrate; A second wafer is provided, the first wafer is flipped, the side of the first wafer away from the substrate is bonded to the second wafer, and the substrate is etched away to expose the first region.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, Before forming the bit line that contacts the second region, the method further includes: A gate insulating layer and a gate electrode are sequentially formed around the sidewalls of the channel region.

13. The method for manufacturing a semiconductor device according to claim 11, characterized in that, Before bonding the first wafer to the second wafer on the side away from the substrate, the method further includes: forming logic circuitry on the second wafer.

14. The method for manufacturing a semiconductor device according to claim 11, characterized in that, Before forming the bit line that contacts the second region, the method further includes forming a logic circuit on the first wafer.

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