Power semiconductor device, preparation method thereof and application

Abstract

A power semiconductor device and a manufacturing method thereof. The power semiconductor device includes a semiconductor layer, an alloy layer, a gate metal layer, and a gate lead-out terminal. The alloy layer, the gate metal layer, and the gate lead-out terminal are all disposed on the cathode surface of the semiconductor layer. The alloy layer is disposed between the semiconductor layer and the gate metal layer, and the thickness of the alloy layer is distributed in a gradient manner. By providing an alloy layer between the gate metal layer and the semiconductor layer and designing the thickness of the alloy layer, the present invention can achieve an optimized distribution of the metal-semiconductor contact resistance, improve the switching characteristics and current sharing effect of the device, thereby enhancing the switching safety, control flexibility, and long-term reliability of the chip.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor power devices and manufacturing, and particularly relates to a power semiconductor device, a preparation method thereof, and an application thereof. Background Art

[0002] Power semiconductor devices, also known as power electronic devices or power electronics devices, are one of the most core devices in the electronic industry chain. Power semiconductor devices can achieve electric energy conversion and circuit control, and mainly play roles such as power conversion, power amplification, power switching, circuit protection, inversion (DC to AC), and rectification (AC to DC) in a circuit.

[0003] Gate Commutated Thyristors (GCT) are semiconductor devices with extremely large power capacity in the field of power electronics. The GCT chip integrates multiple gate commutated thyristor cell units. In the GCT chip, the number and position of the gate rings are fixed, while the number of rings of the cathode comb bars is generally more than that of the gate rings. Therefore, in terms of position, the distances from the comb bars on different "cathode rings" to the gate rings are different, some are closer and some are farther. This results in an uneven resistance distribution between different GCT cells and the gate rings. This resistance imbalance causes uneven gate current distribution when the IGCT is turned on or off. Some of the GCT cells need to carry a larger current and are more likely to be damaged due to current concentration, thus affecting the overall performance of the IGCT.

[0004] In view of the above technical problems, in existing technologies such as Chinese Patent Application Publications CN2022800187754 and CN2023112244275, a lateral variable doping method is usually adopted to improve the turn-off ability of the device by changing the doping concentration at different positions in the gate region. However, the preparation process of this method is complex, and different templates are required to control the doping concentration at different positions in the gate region. The process flow is long and the preparation cost is high.

[0005] Therefore, there is an urgent need in this field to develop a power semiconductor device and a preparation method with different implementation methods to reduce the process cost while improving the turn-off ability of the device. Summary of the Invention

[0006] In view of this, the main purpose of the present invention is to provide a power semiconductor device, a preparation method thereof, and an application thereof, in order to at least partially solve the above technical problems.

[0007] To achieve the above object, as an aspect of the present invention, there is provided a power semiconductor device, including a semiconductor layer, an alloy layer, a gate metal layer, and a gate lead-out terminal. Wherein, the alloy layer, the gate metal layer, and the gate lead-out terminal are all disposed on the cathode surface of the semiconductor layer, and the alloy layer is disposed between the semiconductor layer and the gate metal layer; the thickness of the alloy layer is distributed in a gradient manner.

[0008] Preferably, the thickness of the alloy layer is distributed in a gradient manner according to its distance from the gate lead-out terminal. The farther the distance from the gate lead-out terminal, the thicker the alloy layer.

[0009] Preferably, the gate lead-out terminal is annular and concentrically arranged with the power semiconductor device. The cathode surface is further provided with a plurality of cathode rings concentric with the gate lead-out terminal. Each cathode ring includes a plurality of cathode comb bars arranged radially. The alloy layer and the cathode comb bars are arranged at intervals. The thickness of the alloy layer is distributed in the gradient manner according to the radial distance between the cathode ring region where it is located and the gate lead-out terminal, and the thickness of the alloy layer in each cathode ring region is the same.

[0010] Preferably, the thickness of the alloy layer is 5 - 50 nm; preferably, the power semiconductor device is a GCT, an IGCT, or a GTO.

[0011] As another aspect of the present invention, there is provided a method for manufacturing a power semiconductor device, including the following steps: preparing a patterned metal layer with a thickness distributed in a gradient manner in a gate region on the cathode surface of the semiconductor layer; annealing the patterned metal layer to form an alloy layer; and preparing a gate metal layer on the alloy layer.

[0012] Preferably, the manufacturing method further includes the step of forming a gate lead-out terminal region on the cathode surface before, simultaneously, or after preparing the gate metal layer. And in the step of forming the alloy layer, the patterned metal layer is distributed in a gradient manner according to the distance from its position to the preset or set gate lead-out terminal region. The farther the distance from the position of the gate lead-out terminal region, the thicker the patterned metal layer.

[0013] Preferably, the step of preparing a patterned metal layer with a thickness distributed in a gradient manner in a gate region on the cathode surface of the semiconductor layer specifically includes: preparing a first metal layer with a uniform thickness on the cathode surface; and performing a patterning process on the first metal layer to obtain the patterned metal layer with a thickness distributed in a gradient manner.

[0014] Preferably, the patterning process includes: multiple photolithography-etching processes, a metal lift-off process, and a selective etching process.

[0015] Preferably, when the patterning process is a multiple photolithography-etching process, the multiple photolithography-etching process performs photolithography and etching in batches using different photomasks according to the thickness gradient, and the number of photolithography and etching times is determined according to the thickness gradient of the patterned metal layer.

[0016] Preferably, when the patterning process is a selective etching process, the selective etching process includes an ion beam selective etching process or a high-energy laser beam selective etching process.

[0017] Preferably, the step of preparing a patterned metal layer with a gradient thickness distribution in the gate region on the cathode surface of the semiconductor layer specifically includes: preparing the patterned metal layer in the gate region by using a screen printing method or a nanoimprinting method.

[0018] Preferably, the annealing process is a single annealing process, the temperature of the single annealing process is 350 - 800 °C, and the annealing time is 0.5 - 2 h.

[0019] As another aspect of the present invention, there is provided an electronic device including the power semiconductor device of the present invention.

[0020] Thus, the power semiconductor device and its manufacturing method of the present invention, compared with the prior art, at least have one of the following beneficial effects:

[0021] By providing an alloy layer between the semiconductor layer and the gate metal layer and reasonably designing the thickness of the alloy layer, the present invention reasonably controls the contact resistance between the alloy layer and the semiconductor layer, and effectively improves the switching current sharing characteristics of the power semiconductor device.

[0022] In addition, the technical solution of the present invention can reduce the temperature rise of the device, improve the thermal stability of the device, and help optimize the design of subsequent packaging processes, extend the device life, and improve the stability and reliability of the device. Moreover, the process flow is relatively simple, the process cost is low, and it is suitable for industrial application and promotion. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic structural diagram of a power semiconductor device provided by a specific embodiment of the present invention;

[0024] Figure 2 is a schematic cross-sectional structural diagram of a power semiconductor device provided by a specific embodiment of the present invention;

[0025] Figure 3 is a schematic top-view structural diagram of a power semiconductor device provided by a specific embodiment of the present invention;

[0026] Figure 4 is a schematic flow diagram of a method for manufacturing a power semiconductor device provided by a specific embodiment of the present invention. Detailed implementation manners

[0027] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0028] The present invention provides a power semiconductor device and a manufacturing method thereof implemented in different ways, which can improve the turn-off ability of the device while reducing the process cost.

[0029] Specifically, in a specific implementation manner, the present invention provides a power semiconductor device 100, as Figure 1 shown, including a semiconductor layer 101, an alloy layer 102, a gate metal layer 103, and a gate lead 104. Among them, the alloy layer 102, the gate metal layer 103, and the gate lead 104 are all disposed on the cathode surface of the semiconductor layer 101. The alloy layer 102 is disposed between the semiconductor layer 101 and the gate metal layer 103, and the thickness of the alloy layer 102 is distributed in a gradient manner.

[0030] It should be noted that Figure 1 it is only a schematic diagram and does not limit the graphical distribution of the gate metal layer and the gate lead, as well as the thickness ratio of the alloy layer.

[0031] It can be understood that the power semiconductor device of this embodiment further includes a cathode metal layer and an anode metal layer (not shown in the figure), and may also include other layers according to actual needs, such as a dielectric layer, etc.; the semiconductor layer can be doped and designed according to actual needs, and the electrode layer (including the gate metal layer, the gate lead, the cathode metal layer, and the anode metal layer) can be graphically designed according to actual needs, which will not be specifically limited here.

[0032] The present invention provides an alloy layer between the semiconductor layer and the gate metal layer, and controls the thickness of the alloy layer to regulate the zonal distribution of the metal-semiconductor contact resistance, so as to achieve the current collection uniformity during the on and off processes of the power semiconductor device. The magnitude of the contact resistance is mainly related to the resistance of the alloy layer itself, and its resistance value can be calculated by the formula R = ρL / S, where ρ is the resistivity of the alloy layer, and L and S are respectively related to the thickness of the alloy layer and the metal-semiconductor contact area. By effectively controlling the thickness of the alloy layer at the metal-semiconductor contact position, the magnitude of the contact resistance at the corresponding position can be effectively adjusted.

[0033] Power semiconductor devices with different electrode structures have different requirements for the distribution of metal-semiconductor contact resistance, which can be designed according to actual needs. The gate commutation path resistance consists of multiple parts, including the interconnect resistance from the gate metal layer to the gate lead-out terminal and the contact resistance between the metal and semiconductor at the gate. Among them, the interconnect resistance from the gate metal layer to the gate lead-out terminal is related to the distance between them. The farther away from the gate lead-out terminal, the greater this interconnect resistance. If the contact resistances are all the same, then the gate commutation path resistances at different positions will be different, resulting in uneven commutation. To improve the problem of uneven commutation, the technical solution of the present invention adjusts the influence brought by different interconnect resistances by controlling the contact resistance between the metal and semiconductor at different positions of the gate, so that the gate commutation path resistances at different positions are kept consistent. Specifically, when the metal-semiconductor contact area is the same, the thickness of the alloy layer is distributed in a gradient according to the distance from the gate lead-out terminal. The farther away from the gate lead-out terminal, the thicker the alloy layer.

[0034] As a further preferred specific embodiment, the power semiconductor device of the present invention can be a gate-commutated thyristor chip. As Figure 2 and Figure 3 shown, the gate-commutated thyristor chip 200 includes a semiconductor layer 201, an alloy layer 202, a gate metal layer 203, a gate lead-out terminal 204, a cathode comb 205, and an anode 206. Among them, the semiconductor layer 201 includes a p+ emitter, an n+ buffer layer, an n-base region, a p-base region, and an n+ emitter. The alloy layer 202, the gate metal layer 203, the gate lead-out terminal 204, and the cathode comb 205 are all arranged on the cathode surface of the semiconductor layer 201. The alloy layer 202 is arranged between the gate metal layer 203 and the p-base region. The gate lead-out terminal 204 is arranged above the p-base region. The cathode comb 205 is arranged above the n+ emitter. The anode 206 is arranged below the p+ emitter. The gate lead-out terminal 204 is annular and is concentrically arranged with the gate-commutated thyristor chip 200. The cathode surface of the gate-commutated thyristor chip 200 includes multiple cathode rings concentric with the gate lead-out terminal 204. Each cathode ring includes multiple cathode combs 205 arranged radially. The alloy layer 202 and the cathode combs 205 are arranged at intervals. The thickness of the alloy layer 202 is distributed in a gradient according to the radial distance from its cathode ring region to the gate lead-out terminal 204. The alloy layer in the cathode ring region farther away from the gate lead-out terminal 204 is thicker, and the thickness of the alloy layer in each cathode ring region is the same.

[0035] Preferably, the thickness of the alloy layer is 5 - 50 nm, and the farther away from the gate lead-out terminal, the thicker the alloy layer.

[0036] Another embodiment of the present invention provides a method for manufacturing a power semiconductor device, which is used to manufacture the power semiconductor device of the present invention, as Figure 4As shown, it includes the following steps:

[0037] S101, prepare a patterned metal layer with a gradient thickness distribution in the gate region on the cathode surface of the semiconductor layer;

[0038] S102, anneal the patterned metal layer to form an alloy layer;

[0039] S103, prepare a gate metal layer on the alloy layer.

[0040] As described above, the technical solution of the present invention prepares a patterned metal layer with a gradient thickness distribution on the semiconductor layer to reasonably regulate the metal-semiconductor contact resistance, thereby improving the current distribution uniformity during the on and off processes of the power semiconductor device. Preferably, the patterned metal layer is distributed in a gradient according to its distance from the gate lead-out terminal region on the cathode surface. The farther the distance from the gate lead-out terminal region, the thicker the patterned metal layer.

[0041] It can be understood that the preparation of semiconductor devices is usually carried out according to the pre-designed device structure, process parameters, etc. In this embodiment, the gate region, gate lead-out terminal region, etc. on the cathode surface of the semiconductor layer can be pre-designed. During the process of preparing the gate metal layer, the gate lead-out terminal can be formed simultaneously according to needs; the gate metal layer and the gate lead-out terminal can also be prepared in different steps, and no special limitation is made here.

[0042] As a preferred embodiment, the preparation method of the power semiconductor device further includes: before step S101, perform surface treatment on the semiconductor layer.

[0043] Specifically, the surface treatment includes wet etching, ultrasonic cleaning, RCA cleaning, decontamination, drying after cleaning, etc. The main purpose of the surface treatment is to remove the oxide on the surface of the semiconductor layer and improve the adhesion of the semiconductor layer surface.

[0044] Preferably, the semiconductor layer material can be silicon, silicon carbide, III-IV compounds, and its size can be 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, 16 inches, etc. For power semiconductor devices such as IGCT, the semiconductor layer usually selects a silicon substrate with a doping effect of pnpn four-layer three-junction.

[0045] As an alternative embodiment, in step S101, a first metal layer with a uniform thickness can be prepared on the cathode surface of the semiconductor layer, and the first metal layer can be patterned to obtain the patterned metal layer with the thickness distribution.

[0046] Specifically, an evaporation process or a sputtering process can be used to prepare a first metal layer with uniform thickness on the semiconductor layer. Among them, the evaporation process can be thermal evaporation, electron beam evaporation, pulsed laser source evaporation, multi-component thin film evaporation, etc.; the sputtering process can be DC sputtering, RF sputtering, magnetron sputtering, reactive sputtering, etc. In comparison, the magnetron sputtering process has the advantages of fast deposition rate, good film formation uniformity, and stable and controllable thickness. Therefore, it is preferably to use the magnetron sputtering process to prepare the first metal layer.

[0047] When selecting the metal material, factors such as the conductivity, adhesion, purity, reliability, deposition ability of the metal, and whether it can form an alloy with the semiconductor layer should be fully considered. Metals with high conductivity, such as aluminum, titanium nickel silver, titanium copper, etc., are usually selected.

[0048] Preferably, the thickness of the first metal layer can be 1-50 nm, and the thickness of the first metal layer can be specifically determined according to the thickness of the target alloy layer and the spatial distribution of the target contact resistance.

[0049] Preferably, the preparation of the first metal layer should be carried out in a vacuum environment, generally required to be below 10 -4 Pa. The high-vacuum environment can further reduce the residual gas and pollution, ensuring the quality of the metal layer.

[0050] Optionally, the patterning process can be achieved through multiple photolithography and etching processes. The multiple photolithography and etching processes are to perform photolithography and etching in batches according to different photomasks based on the thickness gradient, and the number of photolithography and etching times is determined according to the thickness gradient.

[0051] Specifically, to achieve the controlled distribution of the metal shape and thickness through multiple photolithography and etching, a cyclic process flow such as photolithography, etching, post-etching degluing and cleaning, re-photolithography, re-etching, and post-etching degluing and cleaning again is required. The specific number of cycles of the process flow needs to be determined according to the number of different metal layer thicknesses to be formed. The metal layer patterns with the same thickness can be completed in the same photolithography, etching, and cleaning process; different photomasks are used for metal layer patterns with different thicknesses. Taking the gate turn-off thyristor as an example, the number of corresponding photolithography and etching processes should correspond to the number of cathode rings, following the rule that the first metal layer corresponding to the gate of the "cathode ring" cell farther away from the gate lead-out terminal is thicker.

[0052] Specifically, each photolithography, etching, and degluing and cleaning process steps are as follows:

[0053] (1) Lithography process: Coating, baking, exposing, and developing photoresist on the first metal layer to achieve patterning of the photoresist. Preferably, the specific steps include: a. Cleaning and treating the substrate; b. Coating the photoresist; c. Baking the photoresist; d. Exposing with a mask; e. Developing the photoresist; f. Hard baking the photoresist, thereby forming the required photoresist pattern.

[0054] Optionally, the type of photoresist can be a positive photoresist, such as Rhipley1813, AZ-703, AZ-6130, etc., or a negative photoresist, such as PMMA, RU-8, etc.

[0055] Optionally, the coating thickness of the photoresist can be 0.01 - 10 μm.

[0056] Optionally, the baking temperature of the photoresist can be 80 - 150 °C.

[0057] Optionally, the exposure wavelength of the photoresist is determined according to the specific type of photoresist and process requirements. Different photoresists have different responses and sensitivities to light sources of different wavelengths. Commonly used is ultraviolet (UV) exposure, and common wavelengths are 436 nm, 405 nm, 365 nm, 248 nm, and 193 nm.

[0058] Optionally, a developer is required for the developing process. The developers for negative photoresists are mainly xylene and butyl acetate, and the developers for positive photoresists mainly use tetramethylammonium hydroxide, etc.

[0059] (2) Etching process: Using the photoresist pattern formed in step (1) as a mask layer to protect the first metal layer below it from being etched, thereby only etching away the unprotected part of the first metal layer to form the required electrode pattern.

[0060] Optionally, the etching process for the patterned metal layer can be wet etching or dry etching. Additionally, electron beam exposure and etching, laser etching, etc. can also achieve patterning of the metal thin film.

[0061] Preferably, the commonly used gases for dry etching of metals are chlorine-based, fluorine-based, etc. gases. The specific parameter settings include the etching gas and its composition ratio, etching power, etching pressure, etching time, gas flow rate, and ambient temperature, etc. These parameters need to be optimized and adjusted according to the specific equipment and etching target. For aluminum metal etching, generally, the time required to etch a 100 nm thick aluminum film is 8 - 15 s, which can be adjusted according to parameters such as etching pressure and etching power. The etching process conditions should be kept consistent for each etching process during multiple lithography and etching processes to achieve a gradient distribution of the thickness of the first metal layer.

[0062] (3) Post-etching resist stripping and cleaning process: Post-etching resist stripping and cleaning usually adopt process flows such as soaking-rinsing-drying with organic solvents or plasma resist stripping. Optionally, the method of removing the photoresist depends on the type of photoresist used and the specific application scenario. For some photoresists that are soluble in organic solvents, corresponding solvents can be used for removal. Commonly used organic solvents include acetone, toluene, dimethylformamide (DMF), etc.

[0063] Optionally, when the thickness of the first metal layer is small, the patterning process can be achieved by multiple metal lift-off process methods. Its process steps are photolithography - metal layer deposition - resist stripping - cleaning. The number of times of the metal lift-off process should correspond to the number of cathode rings, following the rule that the first metal layer corresponding to the gate of the "cathode ring" cell farther away from the gate lead-out terminal is thicker.

[0064] Optionally, the patterning process can also be achieved by selective etching. The selective etching can adopt ion beam selective etching or high-energy laser beam selective etching. The two etching methods are similar, only the high-energy sources used are different. Hereinafter, ion beam selective etching will be taken as an example for introduction.

[0065] Ion Beam Etching (IBE) is a micro-nano processing technology that uses an ion beam to remove parts of the material surface to achieve the preparation of fine patterns and structures. The diameter of the ion beam can be adjusted to the sub-micron scale, so high-resolution processing can be achieved. In addition, ion beam selective etching can precisely control the etching depth and shape by controlling the energy and intensity of the ion beam. The main steps of ion beam selective etching include:

[0066] (1) Sample preparation and equipment evacuation: The sample needs to be placed on the chuck of the ion beam etching equipment to facilitate subsequent etching positioning. Preferably, the vacuum degree of the ion beam etching equipment is below 10 -3 Pa.

[0067] (2) Ion beam generation: Use the ion beam etching equipment to generate a high-energy ion beam. Specifically, by decomposing the inert gas argon into argon ions and accelerating them through the anode electric field to physically bombard the sample surface to achieve the etching effect. Optionally, in ion beam etching, commonly used gases include argon, nitrogen, oxygen, fluorine, etc. These gases have different functions in ion beam etching, and the gas can be selected according to the type of metal to be etched.

[0068] (3) Ion beam focusing: Focus the ion beam to an extremely small diameter through an electric field or a magnetic field to achieve high-resolution processing.

[0069] (4) Selection area control: The selection area can be scanned, or a mask or other control means can be used for selection area control. During the selection area scanning process, the etching area to be etched should be accurately positioned through the control system to ensure the accuracy of positioning. Since the size of the ion beam is small and the etching area can be accurately positioned, different thicknesses of metal can be etched even without a photoresist mask. In the embodiment of the present invention, the selection area scanning is controlled according to the thickness distribution design of the patterned metal layer.

[0070] (5) Ion beam etching: When the ion beam irradiates the surface of the sample, high-energy ions will collide with the atoms on the surface of the sample, knocking off the surface atoms to form the required structure. This process can be achieved through physical collisions or chemical reactions. The etching time needs to be determined according to the metal material to be etched and the thickness of the metal to be etched. For the etching of thin-layer thickness metals, the ion beam etching time can be selected from 1 to 600 s. By reasonably controlling the selection area scanning and the etching time, the required patterned metal layer can be obtained.

[0071] Optionally, preparing a patterned metal layer with a gradient thickness distribution in the gate region on the cathode surface of the semiconductor layer includes: preparing the patterned metal layer in the gate region by screen printing or nanoimprinting. Among them, the pattern of screen printing and the template used for nanoimprinting are reasonably designed according to the required patterned metal layer of the present invention. The process steps of preparing the metal layer are the same as those in the prior art and will not be elaborated here.

[0072] As an alternative embodiment, in step S102, the annealing treatment can be a single annealing treatment, that is, the alloying of the patterned metal layer can be achieved by a single annealing treatment to obtain the required alloy layer.

[0073] Specifically, a thermal annealing method can be adopted. By heating up, maintaining a certain duration at a certain temperature, and finally cooling slowly, the annealing process needs to be carried out in a vacuum or inert gas atmosphere to avoid metal oxidation affecting the alloying process. The specific temperature depends on the metal used and the alloying method. The present invention preferably selects an annealing temperature of 350 - 800 °C. Without exceeding the eutectic temperature of the alloy, a relatively higher annealing temperature is more conducive to the formation of the alloy layer. To enable the patterned metal layer to fully react with the semiconductor layer to form an alloy layer with a controllable thickness, the present invention preferably selects an annealing time of 0.5 - 2 h.

[0074] As another alternative embodiment, in step 102, the annealing treatment can be a segmented annealing treatment. The segmented annealing treatment determines the annealing time according to the thickness gradient. The thicker the patterned metal layer, the longer the annealing time.

[0075] Preferably, laser is used for annealing in regions. According to the thickness gradient distribution of the patterned metal layer, annealing is started in regions in sequence from the thickest to the thinnest, so as to achieve different annealing times for metal layers of different thicknesses, ensure complete alloying of the patterned metal layer, and form an alloy layer with a thickness gradient distribution.

[0076] As an alternative implementation, in step S103, an evaporation process or a sputtering process is used to prepare a gate metal layer with a uniform thickness on the alloy layer.

[0077] Preferably, the thickness of the gate metal layer can be 5 - 20 μm; the gate metal layer is prepared in a vacuum environment, generally required to be below 10 -4 Pa. A high-vacuum environment can further reduce the residual gas and contamination to ensure the quality of the metal layer.

[0078] It should be noted that the gate metal layer should be basically consistent with the pattern of the alloy layer, and a photolithography-etching method can be used to obtain the gate metal layer with the required pattern.

[0079] As a preferred implementation, the method for preparing the power semiconductor device further includes: after step S103, annealing the gate metal layer to achieve effective contact between the gate metal layer and the alloy layer, and the contact area reaches more than 95%.

[0080] Preferably, the annealing temperature of the gate metal layer is 300 - 500 °C, and the annealing time is 5 - 30 min.

[0081] Optionally, after step 103, the method for preparing the power semiconductor device further includes the preparation of a gate lead-out terminal, a cathode metal layer, and an anode metal layer. The specific preparation methods are the same as those in the prior art and will not be elaborated here.

[0082] It can be understood that the gate lead-out terminal can be prepared simultaneously with the gate metal layer, and the gate lead-out terminal and the gate metal layer are obtained through patterning. Among them, the gate metal layer is disposed above the alloy layer and is consistent with the pattern of the alloy layer. No special limitation is made here.

[0083] Another implementation of the present invention also provides an electronic device, which can be, for example, a converter, a rectifier, an electronic switch, a controller, a transformer, etc. Among them, the electronic device includes the power semiconductor device of the present invention.

[0084] It can be understood that the power semiconductor device and the electronic device of the present invention can be widely applied to power electronic systems, such as a solar power generation system, a wind power generation system, an industrial control system, an electric vehicle charging system, a network communication system, etc.

[0085] Through experimental verification, the present invention realizes precise adjustment of the contact resistance between the alloy layer and the semiconductor layer by providing an alloy layer between the semiconductor layer and the gate metal layer and reasonably designing the thickness of the alloy layer, thereby improving the switching current sharing characteristics of the power semiconductor device. At the same time, the thermal stability of the device is effectively improved and the device reliability is enhanced. Moreover, the technical solution of the present invention is simple and easy to operate, with low process cost, and is suitable for industrial application and promotion.

[0086] The specific embodiments described above further elaborate on the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A power semiconductor device, characterized in that: It comprises a semiconductor layer, an alloy layer, a gate metal layer and a gate lead-out terminal, wherein the alloy layer, the gate metal layer and the gate lead-out terminal are all arranged on the cathode surface of the semiconductor layer, and the alloy layer is arranged between the semiconductor layer and the gate metal layer; In the case where the contact area between the alloy layer and the semiconductor layer is the same, the thickness of the alloy layer is distributed in a gradient according to the distance from the gate terminal, and the farther the distance from the gate terminal, the thicker the alloy layer; or The gate lead-out terminal is annular and is arranged concentrically with the power semiconductor device. The cathode surface is also provided with a plurality of cathode rings concentric with the gate lead-out terminal. Each of the cathode rings includes a plurality of cathode comb bars arranged radially. The alloy layer and the cathode comb bars are arranged at intervals. When the contact area between the alloy layer and the semiconductor layer is the same, the thickness of the alloy layer is distributed in the gradient according to the radial distance between the cathode ring region in which it is located and the gate lead-out terminal, and the thickness of the alloy layer in each cathode ring region is the same.

2. The power semiconductor device according to claim 1, characterized in that: The thickness of the alloy layer is 5-50nm.

3. The power semiconductor device according to claim 1, characterized in that: The power semiconductor device is a GCT, an IGCT or a GTO.

4. A method for preparing a power semiconductor device, characterized in that: The following steps are involved: A patterned metal layer having a gradient thickness is prepared in the gate region on the cathode surface of the semiconductor layer; annealing the patterned metal layer to form an alloy layer; preparing a gate metal layer on the alloy layer; Before, simultaneously with or after preparing the gate metal layer, a step of forming a gate lead-out terminal region on the cathode surface is performed, and in the step of forming an alloy layer, when the contact area between the alloy layer and the semiconductor layer is the same, the patterned metal layer is distributed in a gradient according to its distance from a preset or set position of the gate lead-out terminal region, and the farther the distance from the position of the gate lead-out terminal region, the thicker the patterned metal layer.

5. The preparation method according to claim 4, characterized in that: The step of preparing a patterned metal layer with a gradient thickness distribution in the gate region on the cathode surface of the semiconductor layer specifically comprises: Preparing a first metal layer with uniform thickness on the cathode surface; The first metal layer is patterned to obtain a patterned metal layer with a gradient thickness distribution.

6. The preparation method according to claim 5, characterized in that: The graphic processing includes: multiple photolithography-etching processing, metal stripping process, and selective area etching processing.

7. The preparation method according to claim 6, characterized in that: When the patterning process is multiple photolithography-etching processes, the multiple photolithography-etching processes are to select different photomasks according to the thickness gradient to perform photolithography and etching in batches, and the number of photolithography and etching is determined according to the thickness gradient of the patterned metal layer.

8. The preparation method according to claim 7, characterized in that: When the patterning process is a selective etching process, the selective etching process includes an ion beam selective etching process or a high energy laser beam selective etching process.

9. The preparation method according to claim 4, characterized in that: The step of preparing a patterned metal layer with a gradient thickness distribution in the gate region on the cathode surface of the semiconductor layer specifically comprises: The patterned metal layer is prepared in the gate region by screen printing or nano-imprinting.

10. The preparation method according to claim 4, characterized in that: The annealing treatment is a single annealing treatment, the temperature of the single annealing treatment is 350-800° C., and the annealing time is 0.5-2 hours.

11. An electronic device, characterized in that: The electronic device comprises the power semiconductor device according to any one of claims 1 to 3.

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