Lateral Schottky diode for studying semiconductor material characteristics and preparation method thereof

Abstract

The present invention relates to a lateral Schottky diode and a preparation method for studying semiconductor material properties. The Schottky diode comprises: semiconductor material, Schottky contact electrode and ohmic contact electrode, wherein the Schottky contact electrode and the ohmic contact electrode are located on the same side surface of the semiconductor material; the ohmic contact electrode surrounds the Schottky contact electrode, and there is an optimized spacing between the ohmic contact electrode and the Schottky contact electrode; the area of ​​the ohmic contact electrode is larger than the area of ​​the Schottky contact electrode. In the study of semiconductor material properties based on capacitance measurement, the embodiment of the present invention can effectively reduce the influence of parasitic resistance, capacitance, non-intrinsic defects, etc. caused by bulk material, ohmic contact and ion implantation on the Schottky capacitance characteristics of intrinsic semiconductor materials, so that the measured capacitance value is as close as possible to the Schottky capacitance value of the intrinsic material, and the measurement result directly reflects the intrinsic characteristics of the semiconductor material, and is not limited by the carrier concentration of the semiconductor material.

Description

Technical Field

[0001] The invention belongs to semiconductors, and in particular relates to a lateral Schottky diode used for studying semiconductor material properties and a preparation method thereof. Background Art

[0002] Ultra-wide bandgap semiconductor β-Ga2O3 can be widely used in high-voltage and high-power fields. The study of the properties of gallium oxide single crystal materials, including the intrinsic crystal structure and defect types, is an important basis for the epitaxial growth of high-quality gallium oxide and the research of devices based on high-quality gallium oxide materials. At present, the research on the properties of gallium oxide single crystal materials has just started, and the model of the intrinsic crystal structure and defect types of gallium oxide single crystal materials is still incomplete.

[0003] The research methods of intrinsic crystal structure and defect types of gallium oxide single crystal materials are mainly based on optical characterization, first-principles density functional theory and electrical characterization. Optical characterization methods include X-ray diffraction (XRD), PL photoluminescence spectroscopy (PL), Raman spectroscopy (Raman), X-ray photoelectron spectroscopy (XPS), ellipsometry, etc. First-principles density functional method, based on the experimentally measured material parameters of intrinsic crystal structure and defect types of gallium oxide single crystal materials, can calculate the formation energy, transition energy level, migration barrier, energy band, state density, charge density and other properties of the corresponding defects of gallium oxide materials. Electrical characterization methods include deep-level transient spectroscopy (DLTS) based on capacitance measurement (CV), voltage-current measurement (IV), etc. The DLTS test is based on the capacitance-voltage test (CV) of the Schottky barrier diode (SBD) structure of the semiconductor material under test at different temperatures. It can analyze the defect type, defect density and energy level position of the defect in the material under test from the conduction band / valence band.

[0004] In the process of growing gallium oxide single crystal materials, impurities such as silicon are inevitably introduced, forming unintentionally doped (UID) gallium oxide single crystal materials, whose carrier concentration is usually low, within 10 15 ~10 17 cm -3CV test research on this material, such as DLTS research, cannot form Schottky contact and ohmic contact on this low-concentration UID single crystal material at the same time, that is, it is impossible to prepare a Schottky diode structure that meets the DLTS measurement requirements, and carry out DLTS measurement research based on gallium oxide UID single crystal materials, which brings serious obstacles to the study of the intrinsic crystal structure and defect types of gallium oxide materials.

[0005] Currently, the SBD structures made on gallium oxide materials for material property research include vertical and lateral types.

[0006] In the vertical SBD structure, the current flows in a direction perpendicular to the cross section of the material, usually on the epitaxial surface of the material (i.e., the doping concentration is 10 15 ~10 17 cm -3 The Schottky metal electrode is made on the epitaxial surface with a thickness of about 10 μm, and the highly doped substrate surface (i.e., the doping concentration is about 10 18 cm -3 , the thickness of the conductive substrate is about 500 μm to 650 μm) to make an ohmic metal electrode to form a vertical SBD structure. Since the carrier concentration of the unintentionally doped gallium oxide UID single crystal material is low, when a vertical SBD structure is adopted, it can form a Schottky contact with the metal contact, but it is difficult to form an ohmic contact. Although the ohmic contact can be formed by ion implantation, the body resistance corresponding to the inherent material thickness (usually ≥500 μm) will lead to the introduction of a large series resistance Rs between the Schottky contact electrode and the ohmic electrode. This will cause two problems: ① Due to the voltage-dividing effect of the series resistor Rs, the external bias voltage cannot be mostly applied to the anode Schottky junction, and the Schottky junction capacitance is the capacitance that directly reflects the characteristics of the gallium oxide UID single crystal material; ② Since the capacitance test is sensitive to phase changes, the non-negligible series resistor Rs will cause additional phase shifts between the AC voltage signal applied to the Schottky diode and the AC current flowing through it during the CV test, resulting in large errors or even mistakes in the CV test results. Therefore, it is impossible to carry out electrical property tests such as DLTS of gallium oxide UID single crystal materials based on CV measurement using the vertical SBD structure.

[0007] In the lateral SBD structure, the current flow direction is parallel to the cross section of the material. Usually, the Schottky metal electrode and the ohmic metal electrode are on the same surface of the material sheet. However, the concentration of unintentionally doped carriers in the gallium oxide UID material is extremely low, which makes it impossible to directly form an ohmic contact with the metal. Although ion implantation can be used to increase the carrier concentration in the ohmic region, ion implantation requires additional processes such as plate making, photolithography, masking, and ion implantation. The process is complicated and the cost is high. After ion implantation, the ohmic implantation area needs to be etched to select the appropriate concentration area to form an ohmic contact. However, the ion implantation process is highly discrete and the implantation area is highly random, so ideal ohmic contacts are often not obtained. More importantly, the damage to the crystal structure of the material caused by the process and other elements such as Si introduced by ion implantation will inevitably introduce non-intrinsic defects to the study of the intrinsic properties of gallium oxide materials, and the measurement results cannot reflect the actual properties of gallium oxide UID single crystal materials.

[0008] In summary, the existing vertical SBD scheme and the existing lateral SBD scheme are not suitable for the study of the intrinsic crystal structure and defect type of gallium oxide UID single crystal materials based on CV measurement. Summary of the invention

[0009] In order to solve the above problems existing in the prior art, the present invention provides a lateral Schottky diode and a preparation method for studying the characteristics of semiconductor materials. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0010] The embodiment of the present invention provides a lateral Schottky diode for studying the characteristics of semiconductor materials, comprising: semiconductor material, a Schottky contact electrode and an ohmic contact electrode, wherein:

[0011] The Schottky contact electrode and the ohmic contact electrode are located on the same side surface of the semiconductor material;

[0012] The ohmic contact electrode surrounds the Schottky contact electrode, and there is a preset distance between the ohmic contact electrode and the Schottky contact electrode;

[0013] The area of ​​the ohmic contact electrode is greater than the area of ​​the Schottky contact electrode.

[0014] In one embodiment of the present invention, the semiconductor material includes gallium oxide UID single crystal material.

[0015] In one embodiment of the present invention, the surface of the semiconductor material is formed with raised areas and recessed areas, wherein:

[0016] The recessed area is formed by etching and surrounds the raised area;

[0017] The Schottky contact electrode is located in the protruding region, the ohmic contact electrode is located in the recessed region, and a preset interval between the ohmic contact electrode and the Schottky contact electrode is formed in the protruding region.

[0018] In one embodiment of the present invention, the shape of the Schottky contact electrode includes a circle;

[0019] The outer shape of the ohmic contact electrode includes a square, and the inner shape includes a circle.

[0020] In one embodiment of the present invention, the diameter of the Schottky contact electrode is 400-1000 μm;

[0021] The distance between the ohmic contact electrode and the Schottky contact electrode is 10-500 μm.

[0022] In one embodiment of the present invention, the area of ​​the ohmic contact electrode is 10-50 times the area of ​​the Schottky contact electrode.

[0023] In one embodiment of the present invention, the capacitance of the lateral Schottky diode, the capacitance of the Schottky contact electrode, and the capacitance of the ohmic contact electrode satisfy the formula:

[0024]

[0025] Among them, C 总 is the lateral Schottky diode capacitance, C 欧姆 is the ohmic contact electrode capacitance, C 肖特基 is the Schottky contact electrode capacitance.

[0026] Another embodiment of the present invention provides a method for preparing a lateral Schottky diode for studying semiconductor material properties, comprising the steps of:

[0027] S1. Provide semiconductor materials;

[0028] S2, calculating the area of ​​the Schottky contact region according to the carrier concentration of the unintentional doping of the semiconductor material; under the constraint that the area of ​​the ohmic contact region is greater than the area of ​​the Schottky contact region, calculating the area of ​​the ohmic contact region using the area of ​​the Schottky contact region; calculating the distance between the Schottky contact region and the ohmic contact region using the body resistance of the semiconductor material (1);

[0029] S3, defining the ohmic contact region on the surface of the semiconductor material according to the area of ​​the ohmic contact region, and photolithography and etching the ohmic contact region;

[0030] S4, making an ohmic contact electrode in the etched ohmic contact area;

[0031] S5. According to the area of ​​the Schottky contact region and the preset spacing, a Schottky contact electrode is fabricated on the surface of the semiconductor material, so that the ohmic contact electrode surrounds the Schottky contact electrode, and the preset spacing requirement is met between the ohmic contact electrode and the Schottky contact electrode.

[0032] In one embodiment of the present invention, step S2 comprises:

[0033] A target capacitance value is selected within the capacitance range of the deep level transient spectrum test, and the Schottky contact area is calculated based on the unit area capacitance of the semiconductor material at a known carrier concentration and the target capacitance value:

[0034]

[0035] Where S is the area of ​​the Schottky contact region, C 阳极 is the target capacitance value, C′ is the capacitance per unit area of ​​the semiconductor material at a known carrier concentration, and R 阳极 is the radius of the Schottky contact area;

[0036] Determining the area of ​​the ohmic contact region by using the area of ​​the Schottky contact region, wherein the area of ​​the ohmic contact region is 10-50 times the area of ​​the Schottky contact region;

[0037] The bulk resistance of the semiconductor material (1) between the Schottky contact region and the ohmic contact region is calculated, wherein the following condition is satisfied when the capacitance test value of the semiconductor material (1) is equal to the actual capacitance value:

[0038]

[0039] (Required to meet R S G≤10 -4 )

[0040] When C≈C p , there is the following relationship:

[0041] ωR s C≈ωR s CP≤10 -4 ,ω=2πf

[0042] Among them, C p is the capacitance test value, C is the actual capacitance value, G is the actual conductance value corresponding to the actual capacitance value, R S is the bulk resistance of the semiconductor material between the Schottky contact region and the ohmic contact region, and f is the test frequency;

[0043] The preset distance between the Schottky contact region and the ohmic contact region is calculated using the bulk resistance of the semiconductor material, wherein the bulk resistance of the semiconductor material and the preset distance follow the following relationship:

[0044]

[0045] in, is the square resistance of the semiconductor material, and L is the preset distance between the Schottky contact area and the ohmic contact area.

[0046] In one embodiment of the present invention, etching the ohmic contact region in step S3 includes:

[0047] The ohmic contact region is etched using an ICP etching process, a plasma bombardment process or a laser etching process.

[0048] Compared with the prior art, the present invention has the following beneficial effects:

[0049] 1. In the Schottky diode of the present invention, the ohmic contact electrode surrounds the Schottky contact electrode, there is a preset distance between the ohmic contact electrode and the Schottky contact electrode, and the area of ​​the ohmic contact electrode is larger than the area of ​​the Schottky contact electrode. This structure can effectively reduce the influence of the parasitic resistance and capacitance caused by the device body material and the ohmic contact on the capacitance characteristics of the Schottky region in the study of semiconductor material characteristics, and the measurement results are directly manifested as the intrinsic characteristics of the semiconductor material; and it is not limited by the carrier concentration of the material, has a simple structure, and is easy to manufacture, which provides an effective solution for the DLTS measurement research of semiconductor materials, especially unintentionally doped and low-doping concentration semiconductor materials, the research on the electrical characteristics of devices based on semiconductor materials, and the research on the intrinsic characteristics of materials.

[0050] 2. In the device structure with optimized design of the present invention, by etching the ohmic contact area, the intrinsic dangling bonds and ohmic contact area of ​​the semiconductor material can be effectively increased, the ohmic tunneling effect can be increased, and the ohmic contact can be effectively realized while further reducing the ohmic contact resistance; and this method is not limited by the process complexity and uncertainty of ohmic contact formed by ion implantation, and avoids the influence of non-intrinsic defects brought by other elements such as Si introduced in the ion implantation process on the study of intrinsic properties of the material, and effectively expresses the intrinsic properties of the semiconductor material under study. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A top schematic diagram of a lateral Schottky diode for studying semiconductor material properties provided by an embodiment of the present invention;

[0052] Figure 2 A vertical cross-sectional schematic diagram of a lateral Schottky diode for studying semiconductor material properties provided by an embodiment of the present invention;

[0053] Figure 3 A vertical cross-sectional schematic diagram of another lateral Schottky diode for studying semiconductor material properties provided by an embodiment of the present invention;

[0054] Figure 4 A top schematic diagram of another lateral Schottky diode for studying semiconductor material properties provided by an embodiment of the present invention;

[0055] Figure 5 A schematic flow chart of a method for preparing a lateral Schottky diode for studying semiconductor material properties provided by an embodiment of the present invention;

[0056] Figure 6a-6h A schematic diagram of a process of preparing a lateral Schottky diode for studying semiconductor material properties provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0058] Embodiment 1

[0059] See also Figure 1 and Figure 2 , Figure 1 A top schematic diagram of a lateral Schottky diode for studying semiconductor material properties provided by an embodiment of the present invention, Figure 2 A vertical cross-sectional schematic diagram of a lateral Schottky diode for studying semiconductor material properties provided by an embodiment of the present invention.

[0060] The lateral Schottky diode is used for various tests to study the intrinsic characteristics of semiconductor materials, such as DLTS electrical tests based on CV measurement, and electrical tests such as voltage, current, capacitance, reverse leakage, Schottky barrier, and carrier concentration.

[0061] The lateral Schottky diode comprises: a semiconductor material 1, a Schottky contact electrode 2 and an ohmic contact electrode 3. The semiconductor material 1, the Schottky contact electrode 2 and the ohmic contact electrode 3 are located on the same side surface of the semiconductor material 1; the ohmic contact electrode 3 surrounds the Schottky contact electrode 2, and there is an optimized preset spacing between the ohmic contact electrode 3 and the Schottky contact electrode 2; the area of ​​the ohmic contact electrode 3 is greater than the area of ​​the Schottky contact electrode 2.

[0062] Specifically, the semiconductor material 1 can be a gallium oxide UID single crystal material, or other single crystal semiconductor materials, or doped semiconductor materials. It can be understood that the lateral Schottky diode structure of this embodiment is not limited by the type of semiconductor material and the carrier concentration of the semiconductor material. 17 cm -3 It is also applicable to gallium oxide materials and semiconductor materials with higher carrier concentrations.

[0063] Specifically, the surface of the semiconductor material 1 can be planar or can form other non-planar structures; for planar or non-planar semiconductor materials, the Schottky contact electrode, ohmic contact electrode and device structure design parameters must meet the above requirements.

[0064] See also Figure 3 , Figure 3 A vertical cross-sectional schematic diagram of another lateral Schottky diode for studying semiconductor material properties provided by an embodiment of the present invention. Figure 3 In the embodiment, a convex region and a concave region are formed on the surface of the semiconductor material 1, wherein the concave region is formed by etching and surrounds the convex region; the Schottky contact electrode 2 is located in the convex region, the ohmic contact electrode 3 is located in the concave region, and the spacing between the ohmic contact electrode 3 and the Schottky contact electrode 2 is formed in the convex region. Specifically, the height of the convex region relative to the concave region, that is, the etching depth is 30 to 200 nm.

[0065] In this embodiment, in order to reduce the ohmic contact resistance, the surface of the semiconductor material in the ohmic contact area can be etched. After the etching treatment, the surface roughness of the semiconductor material increases, and the intrinsic oxygen dangling bonds and ohmic contact area on the material surface are increased. Without introducing non-intrinsic defect types of semiconductor materials, the ohmic tunneling effect is effectively increased, which is conducive to the formation of ohmic contact and optimization of ohmic contact resistance, and effectively reduces the impact of ohmic contact parasitic resistance on CV testing.

[0066] Specifically, the shape of the Schottky contact electrode 2 and the shape of the ohmic contact electrode 3 can be customized, and various shapes such as circular, square, polygonal, etc. are applicable to the lateral Schottky diode of this embodiment. Exemplarily, the shape of the Schottky contact electrode 2 includes a circle; the outer shape of the ohmic contact electrode 3 includes a square, and the inner shape includes a circle to match the Schottky contact electrode 2.

[0067] Preferably, the diameter of the circular Schottky contact electrode 2 is 400-1000 μm.

[0068] Preferably, the distance L between the inner side of the ohmic contact electrode 3 and the outer side of the Schottky contact electrode 2 is 10-500 μm, but the distance L is not limited to this distance, as long as ωR sC≈ωR s C P ≤10 -4 R s The corresponding L will do.

[0069] In the lateral Schottky diode of the present embodiment, the ohmic contact electrode and the Schottky contact electrode are both on the same surface of the semiconductor material. On the basis of considering the maximum depletion region width when the anode Schottky junction is reverse biased, by setting a smaller spacing area between the Schottky contact region and the ohmic contact region (i.e., the spacing between the outer ring of the Schottky contact region and the inner ring of the ohmic contact region, L), the influence of the series resistance Rs introduced by the large resistivity of the bulk material on the CV test can be effectively reduced.

[0070] In order to improve the accuracy of CV testing, the area of ​​the ohmic contact electrode must be as large as possible as that of the Schottky contact electrode. At this time, two back-to-back series capacitors are formed between the cathode ohmic contact electrode and the anode Schottky contact electrode. When the capacitor of the anode Schottky contact electrode is reverse biased, the capacitor of the cathode ohmic contact electrode is forward biased. At this time, the reverse biased anode Schottky junction can be tested by CV. The capacitance of the lateral Schottky diode, the capacitance of the Schottky contact electrode 2, and the capacitance of the ohmic contact electrode 3 satisfy formula (1):

[0071]

[0072] Among them, C 总 is the lateral Schottky diode capacitance, C 欧姆 is the ohmic contact electrode capacitance, C 肖特基 is the Schottky contact electrode capacitance.

[0073] In formula (1), since the cathode ohmic contact electrode area is much larger than the anode Schottky contact electrode area, the cathode capacitance C 欧姆 Much larger than the anode Schottky capacitance C 肖特基 , after the formula changes to the first approximation, the C of CV measurement 总 Can be considered as approximately equal to C 肖特基 At this time, the DLTS test based on CV measurement characterizes the characteristics of the semiconductor material. Therefore, the lateral SBD structure based on etching to form an ohmic contact proposed in this embodiment provides an effective solution for the study of material properties such as crystal structure defect types of semiconductor materials (such as gallium oxide UID single crystal materials) and the study of device electrical characteristics based on semiconductor materials.

[0074] Preferably, the area of ​​the ohmic contact electrode 3 is 10-50 times the area of ​​the Schottky contact electrode 2 , but the area of ​​the ohmic contact electrode and the area of ​​the Schottky contact electrode are not limited to this multiple relationship, and any size that satisfies the relationship in formula (1) is applicable.

[0075] Furthermore, the outer side of the ohmic contact electrode 3 can extend to the edge of the semiconductor material 1 to completely cover the peripheral semiconductor material 1, such as Figure 1 It can also extend to the surface of the semiconductor material 1, partially covering the peripheral semiconductor material 1, such as Figure 4 As shown, Figure 4 A top schematic diagram of another lateral Schottky diode for studying semiconductor material properties provided by an embodiment of the present invention. This embodiment does not impose any further restrictions on the coverage area of ​​the ohmic contact electrode.

[0076] Exemplarily, the material of the cathode ohmic contact electrode includes stacked Ti and Au, and the material of the anode Schottky contact electrode includes stacked Ni and Au.

[0077] In the Schottky diode of the present embodiment, the ohmic contact electrode surrounds the Schottky contact electrode, and there is an optimized spacing between the ohmic contact electrode and the Schottky contact electrode, and the area of ​​the ohmic contact electrode is larger than the area of ​​the Schottky contact electrode, which can reduce the influence of parasitic resistance and capacitance in the device on the capacitance change of the Schottky region in the study of semiconductor material characteristics as much as possible, and the measurement results are directly expressed as the electrical properties of the intrinsic semiconductor material, effectively avoiding the problem of parasitic resistance caused by the body material and affecting the accuracy of Schottky capacitance test when measuring the capacitance of the vertical Schottky diode. This solution is not limited by the carrier concentration of the material, has a simple structure and is easy to prepare, and provides an effective solution for semiconductor materials, especially DLTS measurement research of unintentionally doped and low-doping concentration semiconductor materials, research on device electrical properties based on semiconductor materials, and research on intrinsic properties of materials.

[0078] Embodiment 2

[0079] Based on Example 1, see Figure 5 and Figure 6a-6h , Figure 5 A schematic flow chart of a method for preparing a lateral Schottky diode for studying semiconductor material characteristics provided by an embodiment of the present invention, Figure 6a-6h A schematic diagram of a process of preparing a lateral Schottky diode for studying semiconductor material properties provided by an embodiment of the present invention.

[0080] Taking gallium oxide UID single crystal material as an example, the preparation method of the lateral Schottky diode for studying the properties of semiconductor materials includes the following steps:

[0081] S1. Provide semiconductor material 1.

[0082] Specifically, select gallium oxide UID single crystal material and slice it to the target size, which is generally not less than 5mm×5mm, such as Figure 6a and 6b shown.

[0083] S2. Calculate the area of ​​the Schottky contact region based on the carrier concentration of the unintentional doping of the semiconductor material 1; calculate the area of ​​the ohmic contact region using the Schottky contact region area under the constraint that the area of ​​the ohmic contact region is greater than the area of ​​the Schottky contact region; calculate the distance between the Schottky contact region and the ohmic contact region using the body resistance of the semiconductor material 1.

[0084] Taking the shape of the Schottky contact electrode 2 as an example, the step S2 specifically includes the following steps:

[0085] S21. Select a target capacitance value within the capacitance range of the deep level transient spectrum test, and calculate the Schottky contact area based on the unit area capacitance of the semiconductor material 1 at a known carrier concentration and the target capacitance value.

[0086] Specifically, the capacitance range tested by DLTS at 0V 1MHz is usually 40pF to 2000pF. First, select the target capacitance value C within the capacitance range tested by DLTS at 0V 1MHz. 阳极 The known unit area capacitance C′ corresponding to the doping concentration of the target gallium oxide UID single crystal material is converted according to formula (2) to obtain the anode electrode radius R 阳极 .

[0087]

[0088] Where S is the area of ​​the Schottky contact region, C 阳极 is the target capacitance value, C′ is the capacitance per unit area, R 阳极 is the radius of the Schottky contact area.

[0089] S22. Determine the area of ​​the ohmic contact region using the area of ​​the Schottky contact region.

[0090] Specifically, the area of ​​the ohmic contact region can be selected to be 10 times or more of the area of ​​the Schottky contact region. For example, the area of ​​the ohmic contact region is 10-50 times the area of ​​the Schottky contact region to meet C 肖特基 < <C 欧姆 .

[0091] S23. Calculate the bulk resistance of the semiconductor material 1 between the Schottky contact region and the ohmic contact region.

[0092] Specifically, the bulk resistance R of the semiconductor material between the Schottky contact region and the ohmic contact region is calculated using the following derivation formula: S , where the following conditions are met when the capacitance test value of semiconductor material 1 is equal to the actual capacitance value:

[0093]

[0094]

[0095] When C≈C p , there is the following relationship:

[0096] ωR s C≈ωR s C P ≤10 -4 (5)

[0097] ω=2πf (6)

[0098] Among them, C p is the capacitance test value, C is the actual capacitance value, G is the actual conductance value corresponding to the actual capacitance value, R S is the bulk resistance of the semiconductor material between the Schottky contact region and the ohmic contact region, and f is the test frequency.

[0099] Consider the series resistor R S When the impact p The relationship between and C is as follows: S G≤10 -4 , so when formula (4) satisfies ωR S G≤10 -4 At this time, the test capacitor C p It is approximately equal to the actual capacitance C, see formula (5), and the capacitance test value C p is equal to the actual value of the capacitor C, so R can be solved S .

[0100] S24. Calculate the preset spacing between the Schottky contact area and the ohmic contact area for optimal design using the bulk resistance of the semiconductor material.

[0101] Specifically, the bulk resistance R of the semiconductor material between the Schottky contact region and the ohmic contact region S The calculation formula is as follows:

[0102]

[0103] in, is the square resistance of the semiconductor material, and L is the distance between the Schottky contact area and the ohmic contact area.

[0104] In formula (7), R 阳极 , R S All are known, so L can be calculated, which is the optimal design spacing between the Schottky contact area and the ohmic contact area.

[0105] This embodiment derives and calculates the appropriate Schottky contact area, ohmic contact area, and Schottky contact area / ohmic contact area spacing (the spacing between the outer circle of the Schottky contact area and the inner circle of the ohmic contact area, L) based on the intrinsic concentration of the gallium oxide UID material (i.e., the carrier concentration of the semiconductor material), so as to minimize the influence of the series resistance and capacitance in the device on the capacitance change of the Schottky area in CV measurements such as DLTS, and the measurement results directly reflect the intrinsic capacitance characteristics of the gallium oxide UID single crystal material. The lateral gallium oxide SBD structure provides an effective solution for the DLTS measurement research, intrinsic crystal structure and defect type research of gallium oxide UID single crystal materials, and the research on the electrical characteristics of devices based on this material.

[0106] S3, according to the area of ​​the ohmic contact region, define the ohmic contact region on the surface of the semiconductor material 1, and photolithograph and etch the ohmic contact region, such as Figure 6c and 6d shown.

[0107] Specifically, first, according to the area of ​​the ohmic contact region calculated in step S2, the ohmic region is exposed and developed using a photolithography process to define the ohmic contact region. Then, the ohmic contact region is etched using an ICP etching process, a plasma bombardment process, or a laser etching process, so that more intrinsic oxygen dangling bonds are formed on the surface of the gallium oxide material, thereby increasing the ohmic contact area, increasing the ohmic release tunneling effect, facilitating the formation of ohmic contact, and reducing the ohmic contact resistance.

[0108] It should be noted that this embodiment may also adopt other processes for etching the ohmic contact region to reduce the ohmic contact resistance of the gallium oxide material.

[0109] Exemplarily, the process conditions for etching the ohmic contact area using the ICP etching process are: upper / lower electrode power is 300 / 20W; etching atmosphere is BCl3 / Ar, flow rate is 10 / 30sccm; chamber pressure is 1.5Pa; etching depth is 30-200nm.

[0110] Further, after etching, a convex region and a concave region are formed on the surface of the semiconductor material 1 , the concave region surrounds the convex region, the concave region serves as an ohmic contact region, and the convex region serves as a Schottky contact region and a spacing.

[0111] S4, manufacturing an ohmic contact electrode 3 in the etched ohmic contact region.

[0112] Specifically, ohmic metal titanium Ni and gold Au are deposited by metal evaporation process, and the ohmic metal outside the etched ohmic contact area is stripped by conventional stripping process, and then annealed by ohmic annealing process to obtain ohmic contact electrode, such as Figure 6e and6f shown.

[0113] S5. According to the area of ​​the Schottky contact region and the distance between the ohmic region and the Schottky region, a Schottky contact electrode 2 is fabricated on the surface of the semiconductor material 1 so that the ohmic contact electrode 3 surrounds the Schottky contact electrode 2 and there is a distance between the ohmic contact electrode 3 and the Schottky contact electrode 2 .

[0114] Specifically, according to the area of ​​the Schottky contact region and the preset spacing, the Schottky contact region is defined by a photolithography process, and then the Schottky metal nickel Ni and gold Au are deposited by a metal evaporation process, and then the Schottky metal outside the Schottky contact region is stripped by a conventional stripping process to obtain a Schottky contact electrode, such as Figure 6g and 6h shown.

[0115] In the preparation method of this embodiment, by etching the ohmic contact area, the intrinsic dangling bonds of the semiconductor material can be effectively increased and the ohmic contact area can be increased, and no additional material defect types will be introduced, which effectively increases the tunneling effect, realizes the ohmic contact, and removes the influence of the bulk material and ohmic contact parasitic resistance of the semiconductor material in the capacitance measurement as much as possible. This method is not limited by the process complexity of ion implantation to form ohmic contact and the uncertainty of ohmic characteristics, and avoids other impurity elements such as Si introduced during the ion implantation process. The non-intrinsic defects and damage to the study of the intrinsic characteristics of the material are brought. The measurement results of this method can reflect the actual properties of the gallium oxide UID single crystal material.

[0116] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A lateral Schottky diode for studying the properties of semiconductor materials, characterized in that: include: Semiconductor material (1), Schottky contact electrode (2) and ohmic contact electrode (3), wherein: The Schottky contact electrode (2) and the ohmic contact electrode (3) are located on the same side surface of the semiconductor material (1); The ohmic contact electrode (3) surrounds the Schottky contact electrode (2), and a preset distance exists between the ohmic contact electrode (3) and the Schottky contact electrode (2); The area of ​​the ohmic contact electrode (3) is greater than the area of ​​the Schottky contact electrode (2); The capacitance of the lateral Schottky diode, the capacitance of the Schottky contact electrode (2), and the capacitance of the ohmic contact electrode (3) satisfy the formula: Among them, C 总 is the lateral Schottky diode capacitance, C 欧姆 is the ohmic contact electrode capacitance, C 肖特基 is the Schottky contact electrode capacitance.

2. The lateral Schottky diode for semiconductor material property research according to claim 1, characterized in that: The semiconductor material (1) comprises gallium oxide unintentionally doped single crystal material.

3. The lateral Schottky diode for semiconductor material property research according to claim 1, characterized in that: The surface of the semiconductor material (1) is formed with raised areas and recessed areas, wherein: The recessed area is formed by etching and surrounds the raised area; The Schottky contact electrode (2) is located in the raised area, the ohmic contact electrode (3) is located in the recessed area, and a preset distance between the ohmic contact electrode (3) and the Schottky contact electrode (2) is formed in the raised area.

4. The lateral Schottky diode for semiconductor material property research according to claim 1, characterized in that: The shape of the Schottky contact electrode (2) includes a circle; The outer shape of the ohmic contact electrode (3) includes a square, and the inner shape includes a circle.

5. The lateral Schottky diode for semiconductor material property research according to claim 4, characterized in that: The diameter of the Schottky contact electrode (2) is 400-1000 μm; The distance between the ohmic contact electrode (3) and the Schottky contact electrode (2) is 10-500 μm.

6. The lateral Schottky diode for semiconductor material property research according to claim 1, characterized in that: The area of ​​the ohmic contact electrode (3) is 10-50 times the area of ​​the Schottky contact electrode (2).

7. A method for preparing a lateral Schottky diode for studying semiconductor material properties, characterized in that: Includes steps: S1. providing semiconductor material (1); S2. Calculating the area of ​​the Schottky contact region according to the carrier concentration of the semiconductor material (1) that is not intentionally doped; and calculating the area of ​​the ohmic contact region using the area of ​​the Schottky contact region under the constraint that the area of ​​the ohmic contact region is greater than the area of ​​the Schottky contact region; Calculating a preset distance between the Schottky contact region and the ohmic contact region using the bulk resistance of the semiconductor material (1); S3, defining an ohmic contact region on the surface of the semiconductor material (1) according to the area of ​​the ohmic contact region, and photolithography and etching the ohmic contact region; S4, making an ohmic contact electrode (3) in the etched ohmic contact area; S5. According to the area of ​​the Schottky contact region and the preset spacing, a Schottky contact electrode (2) is manufactured on the surface of the semiconductor material (1), so that the ohmic contact electrode (3) surrounds the Schottky contact electrode (2), and the preset spacing requirement is met between the ohmic contact electrode (3) and the Schottky contact electrode (2).

8. The method for preparing a lateral Schottky diode for studying semiconductor material properties according to claim 7, characterized in that: Step S2 includes: A target capacitance value is selected within the capacitance range of the deep level transient spectrum test, and the Schottky contact area is calculated based on the unit area capacitance of the semiconductor material (1) at a known carrier concentration and the target capacitance value: Where S is the area of ​​the Schottky contact region, C 阳极 is the target capacitance value, C′ is the capacitance per unit area of ​​the semiconductor material at a known carrier concentration, and R 阳极 is the radius of the Schottky contact area; Determining the area of ​​the ohmic contact region by using the area of ​​the Schottky contact region, wherein the area of ​​the ohmic contact region is 10-50 times the area of ​​the Schottky contact region; The bulk resistance of the semiconductor material (1) between the Schottky contact region and the ohmic contact region is calculated, wherein the following condition is satisfied when the capacitance test value of the semiconductor material (1) is equal to the actual capacitance value: (Required to meet R S G≤10 -4 ) When C≈C p , there is the following relationship: ωR S C≈ωR S C p ≤10 -4 ,ω=2πf Among them, C p is the capacitance test value, C is the actual capacitance value, G is the actual conductance value corresponding to the actual capacitance value, f is the test frequency, R s is the volume resistance of the semiconductor material between the Schottky contact region and the ohmic contact region; the preset distance between the Schottky contact region and the ohmic contact region is calculated using the volume resistance of the semiconductor material, wherein the volume resistance of the semiconductor material and the preset distance follow the following relationship: Among them, R □ is the known sheet resistance of the semiconductor material, and L is the preset distance between the Schottky contact region and the ohmic contact region.

9. The method for preparing a lateral Schottky diode for studying semiconductor material properties according to claim 7, characterized in that: Etching the ohmic contact region in step S3 includes: The ohmic contact region is etched using an ICP etching process, a plasma bombardment process or a laser etching process.

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