Reference ripple compensation technique for SAR ADCs

Abstract

The present disclosure relates to a reference ripple compensation technique for a SAR ADC. An analog-to-digital converter (ADC) circuit includes a digital-to-analog converter (DAC) circuit, a comparator circuit, an encoder, and a compensation circuit. The DAC circuit receives a reference voltage and provides an output signal based on the reference voltage. The comparator circuit compares the output signal to an analog input signal and generates a comparison signal. A reset command is generated based on the output signal being greater than the analog input signal. The encoder splits a ripple associated with the reference voltage into a plurality of pulses in response to the reset command. The compensation circuit generates a compensation pulse to compensate for the plurality of pulses in response to the reset command.

Description

Technical Field

[0001] This specification generally relates to data communication, including, for example, a reference ripple compensation technique for a successive approximation register (SAR) analog-to-digital converter (ADC). Background Technology

[0002] Analog-to-digital converters (ADCs) come in various types, including flash ADCs, semi-flash ADCs, successive approximation register (SAR) ADCs, σ-δ ADCs, and pipelined ADCs, each with different architectures and applications. The SAR ADC of interest in this disclosure identifies the input voltage of the internal ADC by its successive approximation register and continuously compares the input voltage with the output voltage of the internal ADC, determining whether the input is above or below the midpoint of a narrowing range, and continues this process until the specified resolution is achieved.

[0003] SAR ADCs are widely used in all types of systems, especially data communication circuits and systems. Time-interleaved (TI) SAR ADCs dominate high-speed, low-power, and small-area ADC applications. High-performance TI SAR ADCs are crucial circuits in the receivers of 5G radio frequency (RF) base stations. However, performance with high signal-to-noise ratio (SNDR) and spurious-free dynamic range (SFDR) often comes at the cost of speed, power, chip area, and other metrics. Among all circuit blocks in high-resolution TI SAR, narrow-bandwidth reference buffers are used to implement the three design metrics of TI SAR: linearity, power, and chip area.

[0004] Due to correlations and trade-offs, it is fundamentally difficult to achieve all three design goals simultaneously. Furthermore, reference buffer ripple in TISAR is a significant cause of SNDR and SFDR degradation. In TISAR, the capacitive digital-to-analog converter (DAC) is charged / discharged during reset and conversion cycles, resulting in ripple (e.g., voltage fluctuations) on the reference voltage. Calibration and / or compensation are used to reduce reference ripple in high-resolution ADCs. However, process, voltage, and temperature (PVT) variations can further degrade the efficiency of calibration and / or compensation. In some extreme cases, reference voltage ripple can even increase.

[0005] The existing architecture is a reference-calibrated SAR architecture, where additional conversion cycles are used to detect and correct error bits caused by reference ripple. In this way, the SAR achieves higher resolution and significantly reduces on-chip decoupling capacitors. However, this architecture uses an error correction scheme. The error coverage of this scheme limits the resolution, and the required additional conversion cycles limit the overall speed of the SAR ADC.

[0006] Another existing reference compensation architecture includes a charge generator, which is two reference voltages Vref1 and V ref2 The required charge is provided, thus reducing reference ripple. This architecture offers perfect timing matching for reference charge compensation, but changes to the PVT degrade the architecture. This architecture compensates for reference ripple only in flash ADCs, not TI-SAR. The timing of flash ADCs and SAR ADCs differs significantly, resulting in different characteristics of their reference voltage ripple. In time-interleaved ADCs, the ripple constitutes a significant portion of the reference voltage, which this architecture cannot compensate for. Summary of the Invention

[0007] In one aspect, this disclosure relates to an analog-to-digital converter (ADC) circuit comprising: a digital-to-analog converter (DAC) circuit configured to receive a reference voltage and provide an output signal based on the reference voltage; a comparator circuit configured to compare the output signal with an analog input signal and generate a comparison signal, wherein a reset command is generated based on the output signal being greater than the analog input signal; an encoder configured to compensate for the ripple associated with the reference voltage by splitting it into a plurality of pulses in response to the reset command; and a compensation circuit configured to generate compensation pulses in response to the reset command to compensate for the plurality of pulses.

[0008] In another aspect, this disclosure relates to an integrated circuit comprising: a controller configured to generate a reset command; an encoder configured to split a ripple associated with a reference voltage of a digital-to-analog converter (DAC) circuit into a plurality of pulses in response to the reset command; and a compensation circuit configured to generate compensation pulses in response to the reset command, wherein: the reset command is generated based on the output signal of the DAC circuit being greater than the analog input signal, and the compensation pulses are configured to compensate for the plurality of pulses associated with the ripple.

[0009] In another aspect, this disclosure relates to an apparatus comprising: an encoder configured to receive a reset command from a controller circuit and, in response to the reset command, split a ripple associated with a reference voltage of a digital-to-analog converter (DAC) circuit of an analog-to-digital converter (ADC) circuit into a plurality of pulses; and a compensation circuit configured to receive the reset command from the controller circuit and, in response to the reset command, generate compensation pulses to compensate for the plurality of pulses, wherein the generation of the reset command is based on the output signal of the DAC circuit being greater than the analog input signal of the ADC circuit. Attached Figure Description

[0010] Specific features of the present technology are set forth in the appended claims. However, for illustrative purposes, several aspects of the present technology are depicted in the following figures.

[0011] Figure 1 This is a block diagram illustrating an example of a device for representing an analog-to-digital converter (ADC), within which some aspects of the present technology are implemented.

[0012] Figure 2 This is a diagram illustrating examples of ripple in the reference voltage of an ADC before and after compensation, according to various aspects of this technology.

[0013] Figure 3 This is a schematic diagram illustrating an exemplary implementation of a reference charge compensation (RCC) circuit according to various aspects of the present technology.

[0014] Figure 4 This is a diagram illustrating various aspects of this technology. Figure 3 A diagram illustrating an example of clock pulses used in a time-controlled charging circuit.

[0015] Figure 5 This is a flowchart illustrating an example of a method for reference ripple compensation for a SAR ADC according to various aspects of this technology.

[0016] Figure 6 This is a block diagram illustrating an exemplary electronic device in which various aspects of the present technology are implemented. Detailed Implementation

[0017] The detailed description below is intended to illustrate various configurations of the present technology and is not intended to represent only the configurations in which the present technology can be practiced. The accompanying drawings are incorporated herein and form part of the detailed description. For the purpose of providing a thorough understanding of the present technology, the detailed description includes specific details. However, the present technology is not limited to the specific details set forth herein and can be practiced using one or more embodiments. In one or more examples, structures and components are shown in block diagram form to avoid obscuring the concept of the present technology.

[0018] According to several aspects, this technology relates to a reference ripple compensation device and technique for an analog-to-digital converter (ADC), such as a SAR ADC including a time-interleaved (TI) successive approximation register (SAR) ADC circuit. The disclosed reference ripple compensation technique overcomes limitations caused by process, voltage, and temperature (PVT) variations by using a reference charge compensation (RCC) circuit with multi-pulse compensation. This technique compensates for the large peak charge of ripple (e.g., reset ripple) by splitting it into dual half-peak charges. Ripple is a significant voltage component of the ADC's reference voltage and is compensated by this disclosure. The width of the reset time window is doubled, allowing for tolerance to more timing variations and significantly reducing any compensation overshoot.

[0019] The disclosed technology produces many advantageous features at the circuit, system, and product levels.

[0020] At the circuit level, the disclosed architecture achieves enhanced signal-to-noise ratio (SNDR) and spurious-free dynamic range (SFDR) compared to time-interleaved SAR ADCs without reference ripple compensation. Since the reference ripple is compensated within each SAR and neighboring SARs are unaffected, greater design freedom is available to improve the SAR performance of high-resolution time-interleaved ADCs. In some embodiments, SFDR exceeding 90 dB can be achieved using only reference ripple spurs. Furthermore, the reference compensation technique of this technology reduces the decoupling capacitor area, a significant portion of the SAR area. Additionally, each SAR cell is designed compactly, and the SAR spacing is reduced. Therefore, the overall TI SAR area efficiency is significantly improved without increasing spurious signal power or sacrificing SAR speed. In some embodiments, the overall TI SAR area efficiency can be improved by approximately 10% to 15%. Moreover, the disclosed architecture well tolerates the PVT changes that reduce the effectiveness of existing reference ripple compensation circuits without sacrificing other metrics.

[0021] At the system level, the area of ​​the SAR ADC can be further reduced by applying the disclosed techniques. For example, for a 5nm, 400MS / s, 11-bit CMOS SAR ADC prototype, the overall SAR ADC area can be reduced by approximately 10%. Since the SAR ADC contributes approximately one-third to the total SFDR, the entire receiver can be freed from the linearity requirements of the analog front-end (AFE) and tracking hold due to the disclosed architecture.

[0022] At the product level, this technology provides one of the key and unique enabling technologies to achieve extremely high SFDR for a particular receiver. In some embodiments, the reference ripple spurious can be below approximately -100 dBFS. Furthermore, this technology can result in a significant area reduction (e.g., approximately 10% to 15%) while maintaining high resolution across a wide range of products involving time-interleaved ADCs, including 5G radio frequency (RF) base station receivers, optical links, serializer-deserializer (SERDES) chips, and other products. Implementing the disclosed technology can bring competitive area and power advantages to the market for products based on high-resolution, high-speed ADCs.

[0023] Figure 1This is a block diagram illustrating an example of a device representing an ADC 100, within which some aspects of the present technology are implemented. In some embodiments, the device is an integrated circuit. In some embodiments, the ADC 100 is a SAR ADC. The ADC 100 includes a digital-to-analog converter (DAC) circuit 110, a comparator circuit 120, a controller circuit 130, an encoder circuit 140, a compensation circuit 150, a bootstrap circuit 160, and switches S1 and S2. In some embodiments, the DAC circuit 110 is a circuit that receives a reference voltage Vref and generates a DAC output signal 112 based on Vref. In some embodiments, the reference voltage is provided by a power supply and determines the highest value of the input analog signal that the ADC can convert. For example, if the input analog signal varies in the range between 0V and 5V, then the reference voltage may be 5V. The accuracy and stability of the reference voltage are important factors for precise analog-to-digital conversion. Ripple (e.g., reset ripple) associated with the reference voltage must be compensated for to reduce conversion errors. In some embodiments, the DAC circuit 110 uses the reference voltage to generate an accurate analog output voltage corresponding to the input digital signal of the DAC circuit 110. Ripple associated with a reference voltage is an unwanted variation superimposed on the reference voltage, which is typically a constant voltage. For example, noise, electromagnetic interference, and the charging and discharging of parasitic capacitances can all cause ripple.

[0024] In some embodiments, comparator circuit 120 is a circuit that compares DAC output signal 112 with analog input signal Vin applied to positive input terminal IP and negative input terminal IN and generates comparison signal 122. In some embodiments, comparison signal 122 includes the result of the comparison. In one or more embodiments, controller circuit 130 is a circuit that receives comparison signal 122, generates a reset command 134 based on comparison signal 122, and then provides reset command 134 to encoder circuit 140 and compensation circuit 150. In some embodiments, controller circuit 130 also provides control signal 132 to comparator circuit 120 to control its operation. In some embodiments, controller circuit 130 may be a finite state machine (FSM) circuit that generates reset command 134 based on the comparison and provides reset command 134 to encoder circuit 140 and compensation circuit 150.

[0025] In some implementations, encoder circuit 140 is a most significant bit (MSB) encoder. In some embodiments, the encoder is a circuit capable of splitting ripple into multiple pulses (e.g., bi-peak ripple) in response to a reset command (e.g., reset command 134). In some embodiments, the reset command is provided by controller circuit 130 based on comparison signal 122. For example, if the comparison result is positive, i.e., the DAC output signal is greater than the analog input signal Vin, a reset command is generated when the comparison is performed. In some embodiments, a reset ripple is generated on the reference voltage by charging and discharging the capacitors of DAC circuit 110 during the reset cycle. Similarly, MSB ripple and least significant bit (LSB) ripple are generated during the transition cycle. The magnitude of the reset ripple can be larger than the magnitude of the MSB ripple (e.g., twice as large) and dominates the reference voltage. This technology provides a technique for overcoming reset ripple as well as MSB and LSB ripple. To split the reset ripple into two pulses, encoder circuit 140 extends the reset window by splitting the MSB ripple and LSB ripple in the time domain. For multiple pulses, encoder circuit 140 can further split the LSB into MSB-1 and other LSBs.

[0026] In some embodiments, compensation circuit 150 is a reference charge compensation (RCC) circuit that generates compensation pulses. In some embodiments, the two compensation pulses are two reference charge pulses used to compensate for ripple. In some embodiments, compensating for reset ripple involves adjusting the width and magnitude of the two compensation pulses to cancel out multiple pulses so that the amplitude of the multiple pulses is reduced to a level within a specified range defined by design specifications. In some embodiments, the terms “compensate,” “compensating,” or “compensated” refer to the cancellation of a value (e.g., voltage), which may include a reduction in amplitude or the complete elimination or cancellation of the value. In some embodiments, for dual-pulse compensation, reference voltage ripple may be reduced by approximately 70%. In some embodiments, compensation circuit 150 generates further compensation pulses to compensate for MSB and LSB ripple in each conversion cycle. In some embodiments, compensation circuit 150 generates compensation pulses by providing (e.g., injecting) charge into the reference voltage port of the DAC circuit, as discussed in more detail herein. In some embodiments, the generation of compensation pulses occurs before the DAC circuit 110 receives a subsequent reference voltage.

[0027] In some embodiments, reset command 134 is also received by DAC circuit 110 to initiate a reset cycle. During the reset cycle, switch S1 is closed by reset command 134 to disable (shorten) input signal Vin. In some embodiments, switch S2 is a sampling switch and can be controlled by bootstrap circuit 160 to sample input signal Vin based on clock signal 172 (clk_in).

[0028] Figure 2 This is a graph 200 illustrating examples of the ripple of a reference voltage for an ADC (e.g., a SAR ADC) before and after compensation, according to various aspects of the present technology. In some embodiments, the reference voltage sets the highest value of the input signal to be measured by the DAC circuitry of the SAR ADC. Graph 200 includes curves 210, 220, and 230. Curve 210 shows the ripple 212 within the reset cycle or window, the MSB ripple 214 during the transition cycle (Tconv), and the LSB ripple 216. Ripple 212 is the dominant ripple and cannot be canceled by a single compensation pulse 215 provided by existing architectures.

[0029] Curve 220 illustrates two pulses 222, which in some embodiments are achieved by using... Figure 1 The encoder circuit 140 splits the ripple 212 to form the signal. In some embodiments, the width W2 of the two pulses 222 is twice the width W1 of the ripple 212. The two compensation pulses 225 are formed by... Figure 1 The compensation circuit 150 generates the pulses. The magnitude and width of the two compensation pulses 225 are adjusted to reduce or cancel the plurality of pulses 222. In some embodiments, canceling the plurality of pulses 222, according to design specifications, can reduce the amplitude of the plurality of pulses 222 to a level within a specified range. In some embodiments, the reset ripple amplitude is reduced to approximately 10% of the value of the ripple 212.

[0030] Curve 230 illustrates the compensation results of compensation circuit 150 for ripple 212 and MSB ripple 214. In some embodiments, MSB ripple compensation is achieved by cancellation by a single compensation pulse. In some embodiments, LSB ripple 216 can also be compensated similarly.

[0031] Figure 3This is a schematic diagram illustrating an exemplary embodiment 300 of an RCC circuit according to various aspects of the present technology. The exemplary embodiment 300 of the RCC circuit includes, but is not limited to, a buffer circuit 310 and a charging circuit 320. The buffer circuit 310 provides a reference voltage Vref from an input reference voltage Vref_in. The buffer circuit 310 includes an operational amplifier (op-amp) 312, a transistor Q, and a current source Is, which is biased by supplier voltages VDDH and VSS. The transistor Q and the current source Is are responsible for providing current to the reference voltage Vref through the supplier voltages VDDH and VSS.

[0032] In some embodiments, the charging circuit 320 consists of two clock signals. and A time-controlled charging circuit is included. The charging circuit 320 comprises a capacitor C and transistors (switches) T1, T2, T3, and T4. In some embodiments, the charging circuit 320 provides charge pulses by injecting charge into the reference voltage port of the DAC circuit 110. Transistors T1, T2, T3, and T4 are controlled by two clock signals that serve as complementary clock signals. and Control. Clock signal and They are called complementary because when one (e.g., When the connection is made, the other party (e.g., It will disconnect, and vice versa. For example, when the clock signal... When it has a positive value, the clock signal It has a negative value. When the clock signal At zero volts, transistors T1 and T2 are active (ON), which allows capacitor C to be charged through the Vcharge source, and when the clock signal... When the value changes to positive, transistors T1 and T2 are turned off. When the clock signal... When the value is negative, transistor T3 is turned on to allow capacitor C to discharge to Vref, thus generating Figure 2 The compensation pulse is 225.

[0033] Figure 4 This is a diagram illustrating various aspects of this technology. Figure 3 Figure 400 shows an example of the clock signals used by the timing circuit 320. Figure 400 includes multiple sets of clock signals 410 and 420 shown in a single SAR cycle. The set of clock signals 410 is used to cancel (during T1) MSB ripple and is used to cancel (during T2)... Figure 2The second peak of the multiple pulses 222 (generated by ripple 212). The set of clock signals 420 is used to cancel (during T3) the first peak of the multiple pulses, which has a different timing from the second peak of the multiple pulses compensated by the set of clock signals 410.

[0034] Figure 5 This is a diagram illustrating the various aspects of the application of this technology. Figure 1 A flowchart illustrating an example of a method 500 for reference ripple compensation of an ADC 100. Method 500 includes: generating (e.g., by...) Figure 1 130) reset command (e.g., Figure 1 (134)(510); and in response to a reset command, via the encoder (e.g., Figure 1 (140) will be used with the DAC circuit of the SAR ADC (e.g., Figure 1 The reference voltage of 110) (e.g., Figure 1 The ripple associated with Vref (e.g., Figure 2 212) is split into multiple pulses (e.g., Figure 1 (222)(520). Method 500 further includes, in response to a reset command, a compensation circuit (e.g., Figure 1 150) generates a compensation pulse (e.g., Figure 2 (225) to compensate for ripple (530). The reset command is generated based on the DAC output signal (e.g., Figure 1 (112) and the analog input signal of the SAR ADC (e.g., Figure 1 A comparison of Vin.

[0035] Figure 6 This is a block diagram illustrating an exemplary electronic device 600 in which various aspects of the present technology are implemented. Examples of electronic device 600 include communication systems, such as Ethernet switches for Ethernet (e.g., private networks including data center networks, enterprise networks, or other private networks), which may benefit from the ripple compensation techniques of the present technology. Electronic device 600 includes multiple ingress (input) ports IP1 to IPn and multiple egress (output) ports EP1 to EPm. In one or more embodiments, one or more of the ingress ports IP1 to IPn may receive data packets from another switch or endpoint device in the network. Electronic device 600 further includes hardware components such as an application-specific integrated circuit (ASIC) 610 (which may be implemented as a field-programmable array (FPGA) in some embodiments), a buffer 620, a processor 630, a memory 640, and a software module 650.

[0036] In some implementations, ASIC 610 may include suitable logic, circuitry, interface, and / or code operable to perform the functionality of the PHY circuitry. Buffer 620 includes suitable logic, circuitry, interface, and / or code operable to receive, store, and / or delay data blocks transmitted through one or more output ports EP1 to EPM. Processor 630 includes suitable logic, circuitry, and / or code operable to process data and / or control the operation of electronic device 600. In this respect, processor 630 is capable of providing control signals to various other parts of electronic device 600. Processor 630 also controls data transfers between various parts of electronic device 600. Additionally, processor 630 may enable the implementation of an operating system or other code execution to manage the operation of electronic device 600. In some implementations, ASIC 610 may include a SAR ADC with reference ripple compensation, such as... Figure 1 SAR ADC.

[0037] Memory 640 includes suitable logic, circuitry, and / or code that enables the storage of various types of information (e.g., received data, generated data, code, and / or configuration information). Memory 640 includes, for example, RAM, ROM, flash memory, and / or magnetic storage devices. In various embodiments of this technology, memory 640 may include RAM, DRAM, SRAM, T-RAM, Z-RAM, TTRAM, or any other storage medium. Memory 640 may include software module 650, which, when executed by a processor (e.g., processor 630), performs some or all of the functionality of ASIC 610. In some embodiments, software module 650 includes code that, when executed by a processor, performs, for example, the functionality of configuring electronic device 600.

[0038] The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will readily become apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to limit the aspects presented herein, but should be given the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” (unless specifically stated so), but rather “one or more.” Unless specifically stated otherwise, the term “some” means one or more. Male pronouns (e.g., his) include female and gender-neutral pronouns (e.g., her and its), and vice versa. Headings and subheadings, if present, are for convenience only and do not limit this disclosure.

[0039] The predicates “configured to,” “operable to,” and “programmed to” do not imply any specific tangible or intangible modification of the subject, but are intended to be used interchangeably. For example, a processor configured to monitor and control the operation of a component can also mean a processor programmed to monitor and control said operation or a processor operable to monitor and control said operation. Similarly, a processor configured to execute code can be constructed to be a processor programmed to execute code or operable to execute code.

[0040] For example, the phrase "aspect" does not imply that this aspect is essential to the technology or that this aspect applies to all configurations of the technology. Disclosures relating to an aspect may apply to all configurations or one or more configurations. For example, the phrase "aspect" may refer to one or more aspects, and vice versa. For example, the phrase "configuration" does not imply that this configuration is essential to the technology or that this configuration applies to all configurations of the technology. Disclosures relating to configuration may apply to all configurations or one or more configurations. For example, the phrase "configuration" may refer to one or more configurations, and vice versa.

[0041] The term “example” is used in this document to mean “used as an example or illustration.” Any aspect or design described as an “example” in this document is not necessarily to be construed as superior to other aspects or designs or as preferred or advantageous.

[0042] All structural and functional equivalents of the various aspects of the elements described throughout this disclosure that are known or subsequently learned by those skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be public, regardless of whether the disclosure is expressly stated in the claims. No claim element will be construed in accordance with 35 U.S.SC §112(f) unless the element is expressly stated using the phrase “component for…” or, in the case of a method claim, the element is stated using the phrase “step for…”. Moreover, with regard to the use of the terms “comprising,” “having,” etc., in the detailed description or claims, such terms are intended to be inclusive in a manner similar to how the term “comprising” is interpreted when “comprising” is used as a transitional word in a claim.

[0043] Those skilled in the art will understand that the various illustrative blocks, modules, elements, components, methods, and algorithms described herein can be implemented as electronic hardware, computer software, or a combination of both. To illustrate this interchangeability between hardware and software, the various illustrative blocks, modules, elements, components, methods, and algorithms have generally been described above in terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in varying ways for each specific application. Various components and blocks can be arranged in different ways (e.g., in different orders or divided in different ways), all without departing from the scope of this art.

Claims

1. An analog-to-digital converter (ADC) circuit, comprising: A digital-to-analog converter (DAC) circuit is configured to receive a reference voltage and provide an output signal based on the reference voltage; A comparator circuit is configured to compare the output signal with an analog input signal and generate a comparison signal, wherein a reset command is generated based on the output signal being greater than the analog input signal. An encoder is configured to compensate for the reset ripple by splitting the reset ripple associated with the reference voltage into multiple pulses during the reset cycle of the ADC circuit in response to the reset command. and A compensation circuit is configured to generate compensation pulses in response to the reset command to compensate for the plurality of pulses.

2. The ADC circuit of claim 1, further comprising a controller circuit configured to receive the comparison signal and generate the reset command.

3. The ADC circuit of claim 2, wherein the controller circuit includes a finite state machine (FSM) circuit configured to provide the reset command to the encoder and the compensation circuit.

4. The ADC circuit of claim 1, wherein the compensation circuit includes a reference charge compensation RCC circuit, the RCC circuit being configured to generate two compensation pulses to compensate the plurality of pulses.

5. The ADC circuit according to claim 4, wherein the two compensation pulses compensate the plurality of pulses to reduce the amplitude of the plurality of pulses to a specified range.

6. The ADC circuit according to claim 5, wherein the width and magnitude of the two compensation pulses are adjustable to cancel out the plurality of pulses.

7. The ADC circuit of claim 1, wherein the compensation circuit is further configured to generate a second set of compensation pulses to compensate for MSB ripple generated based on the reference voltage during the conversion cycle of the ADC circuit.

8. The ADC circuit of claim 1, wherein the compensation circuit is further configured to generate the compensation pulse before the DAC circuit receives a subsequent reference voltage.

9. The ADC circuit of claim 1, wherein the compensation circuit is further configured to generate the compensation pulse by providing charge to a reference voltage port of the DAC circuit.

10. The ADC circuit of claim 9, wherein the compensation circuit includes a charging circuit configured to provide a charge pulse to the reference voltage port.

11. An integrated circuit, comprising: The controller is configured to generate a reset command; An encoder configured to split a reset ripple associated with a reference voltage of a digital-to-analog converter (DAC) circuit into multiple pulses during a reset cycle in response to the reset command; and A compensation circuit is configured to generate a compensation pulse in response to the reset command. in: The reset command is generated based on the fact that the output signal of the DAC circuit is greater than the analog input signal. The compensation pulse is configured to compensate for the plurality of pulses associated with the reset ripple.

12. The integrated circuit of claim 11, wherein the controller includes a finite state machine (FSM) circuit configured to generate the reset command and provide the reset command to the encoder and the compensation circuit.

13. The integrated circuit of claim 11, wherein the encoder is further configured to double the size of the reset window by splitting the MSB ripple and the least significant bit LSB ripple in the time domain.

14. The integrated circuit of claim 11, wherein the compensation circuit includes a reference charge compensation RCC circuit, wherein the RCC circuit is configured to generate two compensation pulses to compensate the plurality of pulses, wherein the width and magnitude of the two compensation pulses are adjusted to cancel the plurality of pulses to reduce the amplitude of the plurality of pulses to a level within a specified range, and wherein the plurality of pulses includes bimodal ripple.

15. The integrated circuit of claim 11, wherein the compensation circuit is configured to generate the compensation pulse by injecting charge into a reference voltage port of the DAC circuit.

16. The integrated circuit of claim 15, further comprising a charging circuit, wherein the charging circuit is controlled by two clock signals and configured to provide charge pulses for injection into the reference voltage port.

17. An apparatus comprising: An encoder configured to receive a reset command from a controller circuit and, in response to the reset command, split a reset ripple associated with a reference voltage of a digital-to-analog converter (DAC) circuit into multiple pulses during a reset cycle of the analog-to-digital converter (ADC) circuit, wherein the ADC circuit includes the DAC circuit. and A compensation circuit is configured to receive the reset command from the controller circuit and, in response to the reset command, generate compensation pulses to compensate for the plurality of pulses. The reset command is generated based on the fact that the output signal of the DAC circuit is greater than the analog input signal of the ADC circuit.

18. The device of claim 17, wherein the encoder is configured to split the most significant bit (MSB) ripple and the least significant bit (LSB) ripple in the time domain.

19. The device according to claim 17, wherein; The compensation circuit includes a reference charge compensation RCC circuit, and The RCC circuit is configured to generate two compensation pulses by injecting charge into the reference voltage port of the DAC circuit.

20. The apparatus according to claim 19, wherein: The width and magnitude of the two compensation pulses are adjusted to compensate for the plurality of pulses, so as to reduce the amplitude of the plurality of pulses to a level within a specified range. The multiple pulses include bi-peak ripple.

Images