Power semiconductor device chip, its manufacturing method, corresponding device and electronic device

Abstract

A power semiconductor device chip, a preparation method thereof, a corresponding device and an electronic device belong to the technical field of semiconductor design and manufacturing. The power semiconductor device chip includes a gate contact ring formed on a base region and cathode comb bars arranged in a ring shape. A wavy junction is formed between each cathode comb bar and the corresponding base region; among them, the wavy junction farthest from the gate contact ring has the largest width and / or junction depth relative to the wavy junctions in other regions. By adjusting the wavy junction implantation mask of the IGCT cells in different cathode rings, the present invention optimizes the wavy junction morphology of the IGCT cells in the cathode ring far from the gate contact ring, making the dynamic avalanche position during IGCT turn-off farther from the cathode region, not easily causing cathode re-triggering failure, and enhancing the device current turn-off ability; the method of the present invention has a simple process, only requires modifying the ion implantation mask, and does not add additional process steps.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor design and manufacturing, and particularly to a power semiconductor device chip, a preparation method thereof, a power semiconductor device using the same, and an electronic device. Background Art

[0002] In 1957, General Electric (GE) Company in the United States invented the first thyristor (Silicon Controlled Rectifier, SCR; also known as Thyristor) for industrial power conversion and control. By applying a certain positive voltage between the gate and the cathode, the device can be turned on. The thyristor can control a large power with a small current, marking the entry of the transformation, transmission, and application of electric energy into a new era of technological development. Power electronic conversion devices began to be widely used in various fields such as industry, transportation, and energy, achieving the control of strong electricity by weak electricity and fulfilling the purpose of controlling high-power electric energy. The power electronics technology has developed rapidly, and thyristors of the 4kA / 8kV level have entered mass production at the beginning of this century.

[0003] In order to overcome the weakness that the thyristor cannot be turned off through the gate, the Gate Turn-off Thyristor (GTO) was introduced in 1960. Through structural and technological optimizations such as surrounding the gate with discrete cathodes in parallel and reducing the saturation depth during conduction, gate turn-off control was achieved, greatly simplifying the complex supporting circuit and improving the reliability. However, due to the large gate drive power, complex drive circuit of the GTO, and the non-uniformity of the current in the turn-off device, a huge buffer circuit is required, and these disadvantages limit the application of the GTO.

[0004] Integrated Gate-Commutated Thyristor (IGCT) is a device that integrates an improved GTO chip with a gate drive circuit. Essentially belonging to the thyristor class of devices, it has a strong conductivity modulation effect during conduction to ensure low on-state voltage drop and high current-carrying capacity. At the same time, due to the introduction of a transparent anode, a field-stop layer, and hard drive technology, it has fast and reliable switching characteristics and can be used without a snubber circuit during application. The design concept of IGCT was first proposed by ABB of Switzerland in 1996, and it was then called a hard-driven transparent anode GTO (HD-GTO). It was officially named IGCT in 1997. Compared with Insulated Gate Bipolar Transistor (IGBT), IGCT has a lower switching frequency (<1 kHz), but has advantages such as higher voltage withstand, larger current-carrying capacity, lower on-state voltage drop, higher reliability, and lower manufacturing cost. In fact, compared with applications in AC power grids, key equipment such as medium-voltage and high-capacity AC-DC converters, DC transformers, and DC circuit breakers in DC power grids have many new characteristics. For example, the switching frequency of modular multilevel AC-DC converters is very low, dual-active full-bridge DC transformers have soft-switching capabilities, and DC circuit breakers only require single operation. These characteristics largely avoid the disadvantage of the relatively low operating frequency of IGCT and bring opportunities for the application of IGCT in DC power grids.

[0005] Although IGCT has excellent performance, in practical applications, many factors restrict the further expansion of the Safe Operating Area (SOA) of IGCT, and the reliability of IGCT still needs to be improved. In particular, the turn-off process of IGCT is often accompanied by turn-off failures and even device damage. When IGCT is turned off under high voltage and large current conditions, due to the influence of excess carriers in the base region, the device is prone to dynamic avalanche at a voltage much lower than the static blocking voltage, resulting in turn-off failure of the device and even irreversible electrothermal breakdown.

[0006] In 2005, ABB studied the failure mechanism of large-area IGCT devices during turn-off and pointed out that the regions near and far from the gate contact in IGCT always have slightly different gate impedances. Therefore, there will be a slight time offset between each IGCT cathode ring during current turn-off, which will lead to current redistribution during the turn-off process, and current crowding occurs in the region far from the gate contact, resulting in failure.

[0007] In 2007, ABB first proposed the concept of Corrugated p-base IGCT, as Figure 1As shown, the test results indicate that the wavy-junction p-base IGCT can effectively improve the current turn-off ability of the device, especially at room temperature. At 25 °C, the current turn-off ability of the wavy-junction p-base IGCT is increased from 5 kA to 7.2 kA; however, at 125 °C, the improvement in the current turn-off ability of the wavy-junction p-base IGCT is not obvious, increasing from 6 kA to about 6.7 kA.

[0008] In 2013, as Figure 2A , 2B shown, researchers from the University of Cambridge in the UK and ABB compared the turn-off abilities of traditional-structured IGCTs and wavy-junction p-base IGCTs and analyzed the reasons why the wavy-junction p-base IGCT structure has excellent turn-off ability. This is because the lateral electric field component in the wavy-junction p-base IGCT design redirects the hole current to the gate metal contact point, preventing holes from reaching near the cathode junction. This more preferred current path can prevent the dynamic avalanche current from triggering the current gain mechanism of the transistor-transistor.

[0009] In summary, although the wavy-junction p-base IGCT can effectively improve the current turn-off ability of the unit cell IGCT, due to the fact that the regions near and far from the gate contact in the IGCT always have slightly different gate impedances, there will be a slight time offset between the cathode rings of each IGCT during current turn-off, which will lead to a redistribution of current during the turn-off process. The cathode rings of the IGCTs far from the gate contact are still prone to current crowding and thus failure.

[0010] The current solution is mainly to improve the current non-uniformity phenomenon during the turn-off process of large-size IGCT chips through local lifetime control.

[0011] In 2005, as Figure 3 shown, ABB carried out lateral local lifetime control on the cathode rings in the region far from the gate contact, adjusted the current density distribution during the conduction stage, thereby alleviating the SOA degradation phenomenon caused by uneven impedance distribution, and by cooperating with the switch self-clamping technology, the current turn-off ability of the 4.5 kV asymmetric IGCT device was increased by more than 30%.

[0012] In 2012, Zhuzhou CSR Times Electric Co., Ltd. adopted the method of lateral non-uniform electron irradiation to achieve local minority carrier lifetime control of the IGCT chip through the two-irradiation technology. By reducing the minority carrier lifetime of the cathode rings in the region far from the gate contact, the redistribution effect of current during the turn-off of the IGCT was reduced, and the turn-off uniformity was improved, thereby improving the overall safe operating area of the IGCT chip (patent authorization announcement number CN103065950B). This patent mainly protects the process implementation method of lateral non-uniform irradiation, as Figure 4As shown in the figure, non-uniform irradiation is achieved by different thicknesses of the baffle.

[0013] However, the above-mentioned several methods still have defects such as complex processing technology and high processing costs more or less. The inventor of the present invention has found a new way and developed a new power semiconductor device with a variable-size wavy base region and a preparation method thereof, which better solves the defects and deficiencies of the prior art. Summary of the Invention

[0014] In view of this, the main object of the present invention is to provide a power semiconductor device chip, a preparation method thereof, a power semiconductor device using the same, and an electronic device, in order to at least partially solve the above technical problems.

[0015] To achieve the above object, as the first aspect of the present invention, a power semiconductor device chip is proposed, which includes a gate contact ring formed on a base region and cathode comb bars arranged in a ring shape. A wavy junction is formed between each cathode comb bar and the corresponding base region; among them, the wavy junction farthest from the gate contact ring has the largest width and / or junction depth compared with the wavy junctions in other regions.

[0016] As the second aspect of the present invention, a manufacturing method of a power semiconductor device chip is also proposed, including the following steps:

[0017] Form a base region on a semiconductor substrate;

[0018] Form a wavy junction between the cathode comb bar of the power semiconductor device chip and the corresponding base region on the base region by ion implantation; among them, the ion implantation mask used for preparing the wavy junction farthest from the gate contact ring has the largest lateral dimension compared with the ion implantation masks used for preparing the wavy junctions in other regions, or, the wavy junction farthest from the gate contact ring has the longest push-junction time compared with the wavy junctions in other regions.

[0019] As the third aspect of the present invention, a power semiconductor device including the power semiconductor device chip as described above is also proposed.

[0020] As the fourth aspect of the present invention, an electronic device using the power semiconductor device as described above is also proposed.

[0021] Based on the above technical solutions, the power semiconductor device chip of the present invention and its preparation method have at least one of the following beneficial effects compared with the prior art:

[0022] 1. By adjusting the wave junction implantation mask of IGCT cells in different cathode rings, the present invention optimizes the wave junction morphology of IGCT cells in the cathode ring far from the gate contact ring, making the dynamic avalanche position during IGCT turn-off further away from the cathode region. During the large-current turn-off process of IGCT, even if current crowding occurs in the IGCT cathode ring far from the gate contact, the dynamic avalanche position of this cathode ring is further away from the cathode region, and it is not easy to occur cathode re-triggering failure, thus enhancing the current turn-off ability of the entire IGCT device;

[0023] 2. The manufacturing method of the present invention has the advantages of simple process and easy implementation. This manufacturing method only needs to modify the photolithography mask for wave junction implantation without adding additional process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments.

[0025] Figure 1 is a cross-sectional structure schematic diagram of a wave junction p-base region IGCT of the prior art;

[0026] Figure 2 is a comparison diagram of the electric field distribution when two IGCT structures of the prior art are turned off, where Figure 2A is the wave junction p-base region IGCT, Figure 2B is the traditional structure IGCT;

[0027] Figure 3 is the radius-V relationship broken line diagram under the IGCT lateral local lifetime control proposed by ABB; T relationship broken line diagram;

[0028] Figure 4 is a schematic diagram of the process implementation method of lateral non-uniform irradiation in the prior art;

[0029] Figure 5 is a top view of a typical active region layout of an IGCT chip in the prior art;

[0030] Figure 6 is a top view of the layout of the cathode comb bars in the cathode ring in the prior art;

[0031] Figure 7 is a cross-sectional schematic diagram including a mask when ion implantation is performed on the IGCT wave junction of the present invention;

[0032] Figure 8 is a schematic diagram of ion implantation of cells at different positions of the IGCT of the present invention under masks of different sizes;

[0033] Figure 9 is a cross-sectional schematic diagram of the first push junction after ion implantation of cells at different positions of the IGCT of the present invention;

[0034] Figure 10 It is a cross-sectional schematic diagram of the p2 region formed after the first push knot in the p1 region of the present invention.

[0035] Figure 11 It is a cross-sectional schematic diagram of the wavy knot p-base region finally formed after the second push knot of the p1 region and the p2 region of the present invention.

[0036] Figure 12 It is a cross-sectional schematic diagram of an asymmetric IGCT chip structure according to an embodiment of the present invention.

[0037] Figure 13 It is a cross-sectional schematic diagram of a reverse-blocking IGCT chip structure according to another embodiment of the present invention.

[0038] Figure 14A It is the overall circuit of the IGCT switch circuit of the present invention.

[0039] Figure 14B It is the local circuit details of specifically connecting the GCT1 and GCT2 thyristor cells in the IGCT switch circuit of the present invention.

[0040] Figure 15 It is a waveform comparison diagram when the traditional IGCT chip structure and the IGCT chip structure of the present invention are turned off.

[0041] Figure 16A 、 Figure 16B respectively are Figure 15 The comparison diagram of the electric field distribution of GCT2 in the traditional IGCT and the IGCT of the present invention at time t1 in (the simulated IGCT is a half-cell structure);

[0042] Figure 17A 、 Figure 17B respectively are Figure 15 The comparison diagram of the current density distribution of GCT2 in the traditional IGCT and the IGCT of the present invention at time t1 in (the simulated IGCT is a half-cell structure).

[0043] In the above-mentioned drawings, the meanings of the reference numerals are as follows:

[0044] 01, 02, and 04 are respectively gate contact rings at different positions in the cell structure;

[0045] 03 is the cathode comb bar;

[0046] 11, 12, and 13 are respectively cathode comb bars at different positions in the cell structure;

[0047] 101 is the n-base region; 102 is the mask for the wavy junction ion implantation; 103 is the p1 region formed by the wavy junction ion implantation; 104 is the p2 region formed by diffusion or ion implantation; 105 is the wavy junction p-base region; 106 is the p+ base region; 107 is the n+ cathode region (also known as the cathode comb bar); 108 is the n-type buffer layer; 109 is the p+ anode region; 110 is the p-type anode region on the back. Detailed implementation manners

[0048] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0049] In this article, the meanings of some terms are as follows:

[0050] A thyristor, also known as a silicon-controlled rectifier, is a semiconductor device with the characteristics of a silicon rectifier device and can operate under high voltage and large current conditions. Its basic use is controllable rectification, and its working process can be controlled, having the advantages of small size, light weight, low power consumption, high efficiency, and rapid switching.

[0051] IGCT is the abbreviation of Integrated Gate-Commutated Thyristor, that is, an integrated gate-commutated thyristor. It is a power semiconductor device used for current switching in industrial equipment. It has the advantages of stable turn-off ability and low on-state loss. In the conduction stage, it exhibits the performance of a thyristor; in the turn-off stage, it presents the characteristics of a transistor.

[0052] A GCT cell (or an IGCT cell) is the basic structure that composes an IGCT. The longitudinal structure of each cell from the cathode to the anode is an n+ emitter, a p-base region, an n-base region, an n+ buffer layer, and a p+ emitter, with a total of three PN junctions J1, J2, and J3. The layout, geometric shape and size, and cell density of the GCT cell determine the on-state voltage drop of the IGCT.

[0053] GTO is the abbreviation of Gate-Turn-Off Thyristor, which is a gate-turn-off thyristor. When a positive voltage is applied to the anode and a positive trigger current is applied to the gate, the GTO conducts. In the conducting state, when a sufficiently large reverse trigger pulse current is applied to the gate, the GTO turns from conduction to blocking. The GTO has the self-turn-off ability and thyristor characteristics, is resistant to high voltage, has a large current capacity, and has a strong surge withstand ability. Therefore, it has gradually replaced the ordinary thyristor and become the main switching device in large and medium-capacity converter devices.

[0054] Integrated Gate-Commutated Thyristor (IGCT) is a device that integrates an improved GTO chip with a gate drive circuit. Essentially, it belongs to the thyristor type of devices. When conducting, it has a strong conductivity modulation effect to ensure low on-state voltage drop and high current-carrying capacity. At the same time, due to the introduction of a transparent anode, a field-stop layer, and a hard drive technology, it has fast and reliable switching characteristics, and a buffer circuit can be dispensed with during application. Figure 5 Fig. Figure 5 is a top view of a typical active region layout of an Integrated Gate-Commutated Thyristor (IGCT) chip. Among them, 02 is the gate contact ring of the IGCT, and the gate signal is given through the gate contact ring to control the triggering conduction and commutation turn-off of the entire device. What is shown as 03 is the cathode comb bar, that is, corresponding to the cell structure of an IGCT. Each IGCT device may include at least several hundred to at most tens of thousands of cathode comb bar structures according to the chip area and chip design. It should be noted that Figure 5 What is shown is a typical layout method of the active region of an IGCT, but the position of the gate contact ring is not fixed. According to different designs, the position of the gate contact ring of the IGCT can also be located at position 01 (the central region of the chip active region) or position 04 (the peripheral region of the chip active region). Or the gate contact ring of the IGCT can also be any combination among 01, 02, and 04. The present invention does not make any limitation on the position of the gate contact ring of the IGCT.

[0055] Among at least several hundred to at most tens of thousands of cathode comb bars of the IGCT, some cathode comb bars (IGCT cells) are closer to the gate contact ring, and some cathode comb bars (IGCT cells) are farther from the gate contact ring. The cathode comb bars at the same distance from the gate contact ring form a cathode ring, and the cathode comb bars within the cathode ring are usually arranged in a circular shape with the same radius. As Figure 6 shown, the cathode comb bar (IGCT cell) at position 11 is very close to the gate contact ring 02, and the gate impedance is small; while the cathode comb bars (IGCT cells) at positions 12 and 13 are farther from the gate contact ring. During the transmission of the gate signal, the gate signal has to pass through the cells closer to the gate contact ring before flowing through, and relatively large gate impedance will surely be generated. Therefore, there will be a slight time offset between each IGCT cathode ring during the current turn-off period, which will lead to a redistribution of the current during the turn-off process. The cells within the IGCT cathode ring far from the gate contact are prone to current crowding and thus failure.

[0056] In view of the deficiencies in the prior art, through in-depth research, the inventor of the present invention has proposed the following specific solutions:

[0057] (1) A chip structure of an integrated gate-commutated thyristor is proposed. According to the different distances from the gate contact ring, the IGCT cells at different positions have different wavy junction p-base region morphologies. The wavy junction p-base region of the IGCT cell far from the gate contact is farther from the center of the n+ cathode region. During the large-current turn-off process of the IGCT, even if current crowding occurs in the cathode ring of the IGCT far from the gate contact, the dynamic avalanche position of this cathode ring is farther from the cathode region and is not prone to cathode retriggering failure, thereby enhancing the current turn-off ability of the entire IGCT device.

[0058] (2) A manufacturing method of an integrated gate-commutated thyristor chip is proposed. The wavy junction injection masks of the cells in different cathode rings of the integrated gate-commutated thyristor chip are variable. The size of the wavy junction injection mask of the cells in the cathode ring far from the IGCT gate contact ring is larger than that of the cells in other regions.

[0059] (3) There are two specific implementation schemes for the lithography mask design of the wavy junction p-base region in the manufacturing method: A. The size of the wavy junction injection mask of the cells in the cathode ring far from the IGCT gate contact ring is larger than that of the cells in other regions, and the sizes of the wavy junction injection masks of the cells in other regions are the same; B. The size of the wavy junction injection mask of the IGCT cells in different cathode rings is adjusted according to the distance from the gate contact ring. As the distance from the gate contact ring increases, the sizes of the wavy junction injection masks of the IGCT cells in each cathode ring increase.

[0060] Specifically, the present invention proposes a power semiconductor device chip, which includes a gate contact ring formed on the base region and cathode comb bars arranged in a ring shape. A wavy junction is formed between each cathode comb bar and the corresponding base region. It is characterized in that the wavy junction farthest from the gate contact ring has the largest width and / or junction depth relative to the wavy junctions in other regions.

[0061] Wherein, the width of the wavy junction refers to the width of the wavy junction region in the cross-sectional view, that is, the width at the position where the wavy junction width is the largest.

[0062] Wherein, for the case of having multiple gate contact rings, regardless of the position of the gate contact ring, the distance from the gate contact ring is determined according to the distance to the nearest gate contact ring because the current follows the shortest path principle.

[0063] Wherein, the width and / or junction depth of the wavy junction change in a gradient manner with the distance from the gate contact ring; or, except for the wavy junction farthest from the gate contact ring, the widths and / or junction depths of the wavy junctions in other regions are the same.

[0064] Wherein, the junction depth of the wavy junction is, for example, 100 - 180 μm.

[0065] In a preferred embodiment, in the IGCT cell closest to the gate contact ring, the width of the wavy junction region accounts for 40%-80% of the total width of the cell where it is located; in the IGCT cell farthest from the gate contact ring, the width of the wavy junction region accounts for 20%-50% of the total width of the cell where it is located. Preferably, in the IGCT cell closest to the gate contact ring, the width of the wavy junction region accounts for 60%-70% of the total width of the cell where it is located; in the IGCT cell farthest from the gate contact ring, the width of the wavy junction region accounts for 30%-40% of the total width of the cell where it is located, and the ratio of the two is approximately 2:1.

[0066] Among them, the junction depth range, that is, the distance from the interface of the wavy junction p-base region to the cathode surface is 100-180 μm.

[0067] Among them, the cathode ring includes a number of cells, and each cell includes a cathode comb bar.

[0068] Among them, the power semiconductor device chip is a chip including a number of cells, and the power semiconductor device chip is a GCT, IGCT or GTO chip.

[0069] Among them, the power semiconductor device chip is, for example, an asymmetric IGCT chip or a reverse blocking IGCT chip.

[0070] The present invention also provides a manufacturing method of a power semiconductor chip, including the following steps:

[0071] Form a base region on a semiconductor substrate;

[0072] Form a wavy junction between the cathode comb bar of the power semiconductor device chip and the corresponding base region on the base region by ion implantation; among them, the ion implantation mask used for preparing the wavy junction farthest from the gate contact ring has the largest lateral dimension relative to the ion implantation mask used for preparing the wavy junctions in other regions, or, the wavy junction farthest from the gate contact ring has the longest pushing junction time relative to the wavy junctions in other regions.

[0073] Among them, the ion implantation mask of the ion implantation method can be realized in two ways: (1) directly use photoresist as a mask for ion implantation; (2) use photoresist as a mask to etch the oxide layer, transfer the pattern of the photoresist to the oxide layer, and then use the oxide layer as an ion implantation mask (also called a hard mask, Hard mask) to perform ion implantation. Both of these implementation methods are applicable to the present invention.

[0074] Thus, the ion implantation mask can be photoresist, silicon dioxide or other hard masks.

[0075] When the ion implantation mask is formed of photoresist, the developed photoresist pattern is directly used as the ion implantation mask.

[0076] Among them, the ion implantation mask used satisfies any of the following conditions: (1) The size of the wavy junction ion implantation mask of the cells in the cathode ring far from the gate contact ring is larger than that of the cells in other regions, and the sizes of the wavy junction ion implantation masks of the cells in other regions are the same; (2) Adjust the size of the wavy junction ion implantation mask of the cells in different cathode rings according to the distance from the gate contact ring. As the distance from the gate contact ring increases, the sizes of the wavy junction ion implantation masks of the cells in each cathode ring increase.

[0077] When the ion implantation mask is silicon dioxide or other hard masks, it is formed by patterning on an oxide layer such as silicon dioxide or other hard masks, and then the remaining part is used as the ion implantation mask.

[0078] Among them, for the push - junction time, the push - junction process can be realized by multiple doping and push - junction in partitions to achieve different push - junction depths (junction depths) in different regions. If technological progress enables local control of the push - junction, it is also included within the scope of the present invention.

[0079] In a preferred embodiment, in the IGCT cells closest to the gate contact ring, the width of the wavy - junction region accounts for 40% - 80% of the total width of the cell where it is located. In the IGCT cells farthest from the gate contact ring, the width of the wavy - junction region accounts for 20% - 50% of the total width of the cell where it is located. Preferably, in the IGCT cells closest to the gate contact ring, the width of the wavy - junction region accounts for 60 - 70% of the total width of the cell where it is located. In the IGCT cells farthest from the gate contact ring, the width of the wavy - junction region accounts for 30 - 40% of the total width of the cell where it is located, and the ratio of the two is approximately 2:1.

[0080] Among them, the steps of forming the wavy junction specifically include:

[0081] Forming the wavy junction by ion implantation;

[0082] Performing the first push - junction by thermal diffusion;

[0083] Performing the second push - junction by diffusion or ion implantation.

[0084] Among them, the impurity elements implanted when forming the wavy junction are, for example, N - type doping or P - type doping elements, preferably boron element or aluminum element, and further preferably aluminum element; generally, the ion implantation dose range is 1E12 - 1E14 cm -2 , and the implantation energy range is 30 - 200 keV.

[0085] Among them, the first push-junction forms the p1 region, and the junction depth range of the p1 region is 30 - 100 μm.

[0086] Among them, the process conditions of the first push-junction are related to the impurity elements and the push-junction depth. Optionally, for Al doping, it can be carried out at 1250 °C for 500 - 1300 min. If at 1150 °C or other lower temperatures, a longer push-junction time is required.

[0087] Among them, the second push-junction forms the p2 region, and the junction depth range of the p2 region, that is, the distance from the interface of the wavy-junction p-base region to the cathode surface, is 100 - 180 μm.

[0088] Among them, the impurity elements diffused or ion-implanted during the second push-junction are generally boron or aluminum elements, preferably aluminum element; the equivalent dose range for forming the p2 region by diffusion or ion implantation is 1E12 - 1E14 cm -2 . Generally speaking, the impurity dose in the p2 region should be equivalent to or slightly lower than that in the p1 region.

[0089] The present invention also discloses a power semiconductor chip prepared by a manufacturing method based on the above power semiconductor chip.

[0090] The present invention also discloses a power semiconductor device including the above power semiconductor chip, and the power semiconductor device is, for example, GCT, IGCT, GTO, etc.

[0091] The present invention also discloses an electronic device using the above power semiconductor device, and the electronic device is, for example, a rectifier, an inverter, an inverter, a power switch, a switching circuit device, etc.

[0092] In a preferred embodiment, the present invention also discloses a specific manufacturing method for a key structure of IGCT - the wavy-junction p-base region, including the following steps:

[0093] Figure 7 Schematic diagram of the mask for IGCT wavy-junction ion implantation, where 101 is the n - base region, generally composed of an n-type substrate. According to different voltage levels, the n - base region can be designed with different doping concentrations and thicknesses. 102 is the mask for IGCT wavy-junction ion implantation, which can be photoresist, or silicon dioxide or other hard mask materials. Here, the material of the implantation mask is not limited. As Figure 7 shown in, according to the distance from the gate contact ring, different positions of IGCT cells have different mask sizes L1 and L2, and L2 is greater than L1, that is, the IGCT cells farther from the gate contact ring have a larger mask size for wavy-junction implantation.

[0094] Figure 8Schematic diagram of ion implantation for cells at different positions of IGCT under different-sized masks. Among them, 103 is the p1 region formed by wavy junction ion implantation. Due to different masks, the IGCT cells at different positions have different lateral dimensions of the p region. The IGCT cells far from the gate contact ring have smaller lateral dimensions of the p1 region. The impurity element for ion implantation is generally boron or aluminum, preferably aluminum. Generally, the ion implantation dose range is 1E12 - 1E14 cm -2 , and the implantation energy range is 30 - 200 keV.

[0095] Figure 9 Schematic diagram of the first push-junction after ion implantation for cells at different positions of IGCT. Among them, the p1 region 103 formed by wavy junction ion implantation thus becomes the p1 region formed after the first push-junction (thermal diffusion). Due to different masks and ion implantation regions, the IGCT cells at different positions have different lateral dimensions of the p1 region. The IGCT cells far from the gate contact ring have smaller lateral dimensions of the p1 region. The final junction depth range of the p1 region formed after the first push-junction is 30 - 100 μm.

[0096] Figure 10 Schematic diagram of the formation of the p2 region after the first push-junction of the p1 region. Among them, 104 is the p2 region formed by diffusion or ion implantation. The impurity element for forming the p2 region by diffusion or ion implantation is generally boron or aluminum, preferably aluminum. The equivalent dose range for forming the p2 region by diffusion or ion implantation is 1E12 - 1E14 cm -2 . Generally speaking, the impurity dose of the p2 region should be equivalent to or slightly lower than that of the p1 region.

[0097] Figure 11 Schematic diagram of the finally formed wavy p-base region after the second push-junction of the p1 region and the p2 region. Among them, 105 is Figure 10 the wavy p-base region formed by the second push-junction (thermal diffusion) of 103 and 104 in -3 . The peak doping concentration range of the finally formed wavy p-base region is 1E14 - 1E16 cm

[0098] Figure 12An asymmetric IGCT chip structure proposed by the present invention, which is also Example 1. Among them, 101 is the n-base region, 105 is the wavy-junction p-base region, 106 is the p+-base region, 107 is the n+-cathode region (also known as the cathode comb bar), 108 is the n-type buffer layer, and 109 is the p+-anode region. According to the different distances from the gate contact ring, the IGCT cells at different positions have different morphologies of the wavy-junction p-base region. The wavy-junction p-base region of the IGCT cell far from the gate contact is farther from the center of the n+-cathode region. Except for the wavy-junction p-base region, the IGCT chip structure and process proposed by the present invention are the same as those of the traditional IGCT. Therefore, the manufacturing methods of other regions of the IGCT structure of the present invention will not be described in detail.

[0099] Figure 13 A reverse-blocking IGCT chip structure proposed by the present invention, which is also Example 2. Among them, 101 is the n-base region, 105 is the wavy-junction p-base region, 106 is the p+-base region, 107 is the n+-cathode region (also known as the cathode comb bar), 109 is the p+-anode region, and 110 is the p-type anode region on the back. According to the different distances from the gate contact ring, the IGCT cells at different positions have different morphologies of the wavy-junction p-base region. The wavy-junction p-base region of the IGCT cell far from the gate contact is farther from the center of the n+-cathode region.

[0100] There are two embodiments for the lithography mask design of the wavy-junction p-base region in the manufacturing method: 1. The size of the wavy-junction injection mask of the cells in the cathode ring far from the IGCT gate contact ring is larger than that of the cells in other regions, and the sizes of the wavy-junction injection masks of the cells in other regions are the same; 2. Adjust the sizes of the wavy-junction injection masks of the IGCT cells in different cathode rings according to the distance from the gate contact ring. As the distance from the gate contact ring increases, the sizes of the wavy-junction injection masks of the IGCT cells in each cathode ring increase.

[0101] Establish the switching circuit of the IGCT and simulate and study the advantages of the structure of the present invention. The IGCT switching circuit established in the present invention includes a current-limiting inductor and an RCD buffer circuit, as Figure 14A shown, where DUT is the IGCT device under test. The IGCT device contains two GCT chips, as Figure 14B shown, named GCT1 and GCT2 respectively. GCT2 represents the gate-commutated thyristor cell far from the gate contact ring, and GCT1 represents the gate-commutated thyristor cells in other regions. GCT2 has additional gate inductance R diff and gate inductance L diff compared with GCT1. As shown in Figure 5On the shown IGCT active region, the area ratio of GCT1 to GCT2 is 83:17. That is, for example, the IGCT active region includes 10,000 IGCT cells, among which, for example, 8,300 are designed according to GCT1 and 1,700 are designed according to GCT2.

[0102] The IGCT device for simulation study is an 8.5 kV reverse-blocking IGCT device. The conditions for the switching test are: the bus voltage VDC = 1,700 V, and the total anode current during turn-off is 6,000 A.

[0103] Figure 15 Shown is the waveform comparison during turn-off between the traditional IGCT chip structure and the IGCT chip structure of the present invention. The cell size of both chips is 500 μm. In the traditional structure, the ion implantation mask width of the wavy junction p-base region of GCT1 and GCT2 is uniformly 180 μm; while in the structure of the present invention, the ion implantation mask width of the wavy junction p-base region of GCT1 is 120 μm, and the ion implantation mask width of the wavy junction p-base region of GCT2 is 240 μm.

[0104] As mentioned above, since the regions near and far from the gate contact in the IGCT always have slightly different gate impedances, during the current turn-off period, there will be a slight time offset between each IGCT cathode ring, which will lead to current redistribution during the turn-off process. The IGCT cathode ring far from the gate contact (i.e., GCT2) is prone to current crowding and thus failure. For easy comparison, Figure 15 only shows the cathode current of GCT2 in the traditional IGCT chip and the IGCT chip of the present invention during the turn-off process. When the cathode-to-gate commutation is completed during the IGCT turn-off process, if the cathode current exceeds 10% of its conduction current, it can be determined as cathode re-triggering failure. From Figure 15 it can be seen that the cathode current of GCT2 in the traditional structure increases significantly. At time t1, the cathode current reaches 217 A, which is determined as cathode re-triggering failure. While the cathode current of GCT in the structure of the present invention does not increase significantly and turns off normally.

[0105] Figure 16A 、 16B Shown is Figure 15 the comparison of the electric field distribution of GCT2 in the traditional IGCT and the IGCT of the present invention at time t1 in Figure 16A 、 16B it can be seen that the position of the wavy junction of the cathode p-base region of the IGCT of the present invention is farther from the cathode center. During dynamic avalanche, the position of the avalanche point is farther from the cathode, and it is less likely to occur cathode re-triggering failure; while the traditional structure is the opposite. In addition, the peak value of the electric field intensity of the IGCT of the present invention at this moment is slightly lower than that of the traditional IGCT structure.

[0106] Figure 17A , 17B shows Figure 15 the comparison of the current density distributions of the traditional IGCT and GCT2 in the IGCT of the present invention at time t1 in Figure 17A , 17B which. It can be seen from Figure 17A , 17B that in the traditional IGCT, the cathode center of GCT2 conducts current again at this moment (cathode retriggering), while the current distribution of GCT2 in the IGCT of the present invention is normal at this moment, and the current is still conducted by the gate.

[0107] The above are only the preferred embodiments of the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the embodiments of the present invention shall be included within the scope of protection of the embodiments of the present invention.

Claims

1. A power semiconductor device chip, comprising a gate contact ring formed on a base region and cathode comb bars arranged in a ring shape, wherein a wavy junction is formed between each cathode comb bar and the corresponding base region, characterized in that: The wavy junction farthest from the gate contact ring has the largest width and / or junction depth relative to the wavy junctions in other areas; The width and / or depth of the wavy junction varies gradually with the distance from the gate contact ring; or Except for the wavy junction farthest from the gate contact ring, the width and / or junction depth of the wavy junctions in other areas are the same.

2. The power semiconductor device chip according to claim 1, characterized in that: The knot depth of the wavy knot is 100-180 μm; and / or The power semiconductor device chip is a GCT, IGCT or GTO chip; and / or For the wave knot closest to the gate contact ring, the width of the wave knot accounts for 40%-80% of the total width of the cell; for the wave knot farthest from the gate contact ring, the width of the wave knot accounts for 20%-50% of the total width of the cell.

3. The power semiconductor device chip according to claim 2, characterized in that: The width of the wavy knot closest to the gate contact ring accounts for 60%-70% of the total width of the cell; the width of the wavy knot farthest from the gate contact ring accounts for 30%-40% of the total width of the cell; and / or The power semiconductor device chip is an asymmetric IGCT chip or a reverse resistance IGCT chip.

4. A method for manufacturing a power semiconductor device chip, characterized in that: The following steps are involved: forming a base region on a semiconductor substrate; A wavy junction is formed between the cathode comb bar of the power semiconductor device chip and the corresponding base region on the base region by ion implantation; wherein the ion implantation mask used to prepare the wavy junction farthest from the gate contact ring has the largest lateral dimension relative to the ion implantation mask used to prepare the wavy junction in other regions, or the wavy junction farthest from the gate contact ring has the longest push-in time relative to the wavy junctions in other regions; The width and / or depth of the wavy junction varies gradually with the distance from the gate contact ring; or Except for the wavy junction farthest from the gate contact ring, the width and / or junction depth of the wavy junctions in other areas are the same.

5. The manufacturing method according to claim 4, characterized in that The ion implantation mask is formed by photoresist, and the developed photoresist pattern is directly used as the ion implantation mask; and / or The ion implantation mask is silicon dioxide or other hard mask, and a pattern is formed on it through a graphic process and then the remaining part is used as an ion implantation mask; and / or The power semiconductor device chip is a GCT, IGCT or GTO chip; and / or The steps of forming the wave knot specifically include: forming the wavy knot by ion implantation; The first push-in is done by thermal diffusion; The second junction is pushed through by diffusion or ion implantation.

6. The manufacturing method according to claim 5, characterized in that The ion implantation mask satisfies one of the following conditions: (1) when preparing a wavy knot far away from the gate contact ring, the size of the ion implantation mask is larger than the size of the ion implantation mask for preparing other areas, and the sizes of the ion implantation masks for preparing other areas are the same; (2) the size of the ion implantation mask is adjusted according to the distance from the gate contact ring, and as the distance from the gate contact ring increases, the size of each ion implantation mask increases.

7. The manufacturing method according to claim 5, characterized in that: The impurity element ion-implanted when forming the wavy junction is boron or aluminum; the dose range of the ion implantation is 1E12-1E14 cm -2 , implantation energy range is 30-200keV; and / or The first push-knot has a junction depth ranging from 30 to 100 μm; and / or The second push-in junction depth ranges from 100-180 μm; and / or The impurity element diffused or ion-implanted during the second push-up is boron or aluminum; the equivalent dose range of diffusion or ion implantation is 1E12-1E14 cm -2 .

8. A power semiconductor device comprising the power semiconductor device chip according to any one of claims 1 to 3.

9. An electronic device using the power semiconductor device according to claim 8.

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